DDR output driver circuit and DDR chip

Abstract

This disclosure relates to a DDR output driver circuit and a DDR chip. The circuit includes: a first delay module for receiving a data signal to be transmitted and delaying it to obtain a first delayed signal; a second delay module for receiving the data signal to be transmitted and delaying it to obtain a second delayed signal; a first output drive module coupled to the first delay module for receiving the first delayed signal, driving it to obtain and output a first delayed drive signal; and a second output drive module coupled to the second delay module for receiving the second delayed signal, driving it to obtain and output a second delayed drive signal. The output terminals of the first and second output drive modules are coupled, such that the first and second delayed drive signals are coupled to obtain an emphasized output data signal. This disclosure achieves impedance matching and also implements output data signal emphasis processing, which is beneficial for combating high-frequency losses in transmission lines.

Description

Technical Field

[0001] This disclosure relates to the field of chips, and in particular to a DDR (Double Data Rate) output driver circuit and a DDR chip. Background Technology

[0002] In a DDR memory system, the TX (Transmitter) circuit is located in the memory controller and is responsible for sending data (write operations) to the DRAM (Dynamic Random-Access Memory) chips. Its core function is to ensure the reliability of high-speed data writing through precise timing control, signal shaping, and data synchronization.

[0003] High-speed circuit modules of the DDR type use ZQ (Zone Qualifier) ​​calibration to set the drive capability or characteristic impedance of the TX circuit. The calibration level obtained after ZQ calibration is matched with the number of output drivers (TX DRV) in the output driver array that are turned on to achieve the required drive strength or impedance matching under the required hardware conditions.

[0004] To achieve the required drive strength or impedance matching under the necessary hardware conditions, the number of output drivers must be sufficiently redundant. A small number of output drivers may not be enough to achieve the required drive strength or impedance matching. Therefore, with redundant output drivers, some will inevitably be in a disabled state. Output drivers in a disabled state have no function for the DDR system, and for DDR to operate stably for a long time, these disabled output drivers may never be used, thus wasting hardware resources. Summary of the Invention

[0005] In view of this, this disclosure provides a DDR output driver circuit and a DDR chip, which realizes the effective use of the output driver and, under the premise of achieving the required drive strength or impedance matching under the required hardware conditions, further realizes the emphasis processing of the output data signal.

[0006] According to one aspect of the present disclosure, a DDR output driver circuit is provided, comprising:

[0007] The first delay module is used to receive the data signal to be transmitted and perform a first delay on the data signal to be transmitted to obtain a first delayed signal.

[0008] The second delay module is used to receive the data signal to be transmitted and perform a second delay on the data signal to be transmitted to obtain a second delayed signal.

[0009] A first output driving module, coupled to the first delay module, is used to receive the first delay signal and drive the first delay signal to obtain and output a first delay driving signal;

[0010] The second output driving module is coupled to the second delay module and is used to receive the second delay signal, drive the second delay signal to obtain and output the second delay driving signal;

[0011] The output terminals of the first output driving module and the second output driving module are coupled together, so that the first delay driving signal and the second delay driving signal are coupled to obtain an emphasized output data signal.

[0012] In one possible implementation, the DDR output driver circuit further includes:

[0013] The delay setting module, coupled to the second delay module, is used to set the delay degree of the second delay signal relative to the first delay signal.

[0014] In one possible implementation, the first output driving module includes a first number of output drivers, the input terminals of the first number of output drivers are coupled to the first delay module to receive the first delay signal, and the output terminals of the first number of output drivers are coupled to each other to obtain the first delay driving signal.

[0015] The second output driving module includes a second number of output drivers, the input terminals of the second number of output drivers are coupled to the second delay module to receive the second delay signal, and the output terminals of the second number of output drivers are coupled to each other to obtain the second delay driving signal;

[0016] The first quantity and the second quantity are determined by ZQ calibration.

[0017] In one possible implementation, the first number of output drivers and the second number of output drivers constitute an output driver array consisting of a preset number of output drivers;

[0018] Wherein, the sum of the first quantity and the second quantity is the preset quantity;

[0019] In the DDR output driver circuit, the preset quantity remains constant.

[0020] In one possible implementation, the output driver is an impedance-adjustable driver.

[0021] In one possible implementation, the impedance-adjustable driver is an impedance-adjustable inverter.

[0022] In one possible implementation, the output driver includes:

[0023] PMOS, wherein the source of the PMOS is coupled to the power supply voltage;

[0024] A first adjustable resistor, one end of which is coupled to the drain of the PMOS;

[0025] NMOS, wherein the source of the NMOS is connected to the reference ground;

[0026] A second adjustable resistor, one end of which is coupled to the drain of the NMOS;

[0027] The gate of the PMOS and the gate of the NMOS are coupled to each other as the input terminal of the output driver, and the other end of the first adjustable resistor and the other end of the second adjustable resistor are coupled to each other as the output terminal of the output driver.

[0028] The resistance values ​​of the first adjustable resistor and the second adjustable resistor are determined by ZQ calibration.

[0029] In one possible implementation, the first delay signal is a pre-emphasis control signal, the second delay signal is the main signal, and the output data signal is the equalized data signal after pre-emphasis.

[0030] In one possible implementation, the pulse of the first delayed signal is time-correlated with the transition edge of the second delayed signal, and the pulse of the first delayed signal leads the transition edge of the second delayed signal.

[0031] In one possible implementation, the first delayed signal is the main signal, the second delayed signal is the de-emphasis control signal, and the output data signal is the de-emphasis equalized data signal.

[0032] In one possible implementation, the effective level of the second delayed signal is time-correlated with the steady-state portion of the first delayed signal, and the transition edge of the second delayed signal has a defined delay relative to the transition edge of the first delayed signal.

[0033] According to another aspect of the present disclosure, a DDR chip is provided, including the DDR output driver circuit as described in any of the preceding claims.

[0034] As can be seen from the above scheme, the DDR output driver circuit and DDR chip disclosed herein, based on the impedance matching of related technologies, reuse the originally redundant and unused output driver to realize the pre-emphasis and de-emphasis processing of the output data signal. This is beneficial for combating high-frequency loss of the transmission line, ensuring the steepness of the signal edge, reducing inter-symbol interference, preventing the energy of the previous bit of the transmitted data from interfering with the next bit, expanding the signal eye diagram, and thus improving the data sampling margin at the receiving end and reducing the bit error rate. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the output driver array section in the DDR transmitter circuit of related technologies;

[0036] Figure 2 This is a schematic diagram of a DDR output driver circuit structure according to an illustrative embodiment;

[0037] Figure 3 This is a schematic diagram of an application scenario structure of a DDR output driver circuit according to an illustrative embodiment;

[0038] Figure 4 This is a schematic diagram of the circuit structure of an output driver according to an illustrative embodiment.

[0039] In the attached diagram, the component names represented by each number are as follows:

[0040] 100. Output driver array

[0041] 11. Output driver 1_1

[0042] 12. Output drivers 1 and 2

[0043] 1N, the 1_Nth output driver,

[0044] 201. First Delay Module

[0045] 202. Second Delay Module

[0046] 203. First output driver module,

[0047] 21. Output driver 2_1

[0048] 22. Output driver 2_2

[0049] 2M, the 2_M output driver,

[0050] 204. Second output driver module,

[0051] 31. Output driver #3_1

[0052] 32. Output driver #3_2

[0053] 3P, the third output driver,

[0054] 205. Delay setting module,

[0055] MP1, PMOS,

[0056] RV1, the first adjustable resistor,

[0057] MN1, NMOS,

[0058] RV2, the second adjustable resistor,

[0059] VDD, power supply voltage

[0060] VSS, Reference Site. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided with reference to the accompanying drawings and embodiments.

[0062] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0063] As used in the specification and claims of this disclosure, “coupled (or connected)” may refer to any direct or indirect means of connection. For example, if a first device is coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection.

[0064] Figure 1 This is a schematic diagram of the output driver array section in the DDR transmitter circuit of related technologies, such as... Figure 1 As shown, the output driver array 100 in the DDR transmitter circuit includes multiple output drivers, such as... Figure 1The output drivers shown as 1_1 (11), 1_2 (12), ..., 1_N (1N) are only distinguished by their naming conventions. Each output driver can be a CMOS (Complementary Metal-Oxide-Semiconductor) circuit composed of PMOS (P-channel Metal-Oxide-Semiconductor) and NMOS (N-channel Metal-Oxide-Semiconductor) sensors, along with an impedance-adjustable inverter consisting of two variable resistors. Multiple output drivers can be connected in parallel (e.g., ...). Figure 1 The output drivers 11, 12, ..., 1N shown are connected in parallel, simultaneously receiving the data signal to be transmitted and generating a data output signal. The function of the output driver array 100 is to convert the data signal to be transmitted, after serial-to-parallel conversion and level shifting, into a level signal conforming to relevant standards, based on a programmable drive strength code (used to set the resistance value of the variable resistor and determine the number of output drivers that are effectively enabled). This signal drives the external transmission line with controllable rising and falling slopes, achieving impedance matching, reducing reflections, and ensuring the integrity of the double data rate signal.

[0065] In related technologies, after ZQ calibration is completed, a portion of the output drivers in the output driver array 100 are turned off. To ensure a sufficient calibration range, these output drivers cannot be removed; they must remain in the circuit even if they are never used, thus wasting hardware resources. Furthermore, with the development of DDR technology, transmission rates are constantly increasing, and the requirements for signal integrity are becoming increasingly stringent. Pre-emphasis and de-emphasis can be used for signal shaping in high-speed signal transmission, combating high-frequency losses and improving the signal-to-noise ratio (SNR), thereby improving signal integrity. Although it may not be necessary now, there is a potential need for pre-emphasis and de-emphasis in future DDR technology.

[0066] In view of this, the present disclosure provides a DDR output driver circuit and a DDR chip to achieve effective utilization of the output driver, solve the problem of wasted hardware resources, and further enhance the output data signal to improve signal integrity, provided that the required drive strength or impedance matching is achieved under the required hardware conditions.

[0067] Figure 2This is a schematic diagram of a DDR output driver circuit structure according to an illustrative embodiment, such as... Figure 2 As shown, the DDR output driver circuit mainly includes a first delay module 201, a second delay module 202, a first output drive module 203, and a second output drive module 204. The first delay module 201 receives the data signal to be transmitted and applies a first delay to the data signal to be transmitted to obtain a first delayed signal. The second delay module 202 receives the data signal to be transmitted and applies a second delay to the data signal to be transmitted to obtain a second delayed signal. The first output drive module 203 is coupled to the first delay module 201 and receives the first delayed signal, drives the first delayed signal to obtain and outputs a first delayed drive signal. The second output drive module 204 is coupled to the second delay module 202 and receives the second delayed signal, drives the second delayed signal to obtain and outputs a second delayed drive signal. The output terminals of the first output drive module 203 and the second output drive module 204 are coupled, so that the first delayed drive signal and the second delayed drive signal are coupled to obtain an emphasized output data signal.

[0068] In the illustrative embodiment, both the first delayed signal and the second delayed signal originate from the data signal to be transmitted. Therefore, the first delayed signal and the second delayed signal are related but not completely synchronized. There is a phase difference between the first delayed signal and the second delayed signal to achieve signal emphasis processing. Even after being driven by different output driving modules (the first delayed signal is driven by the first output driving module 203, and the second delayed signal is driven by the second output driving module 204), this phase difference still exists. Consequently, after coupling, the two are related and there is a phase difference to achieve signal emphasis processing, thus producing a signal emphasis effect. This makes the output data signal an emphasized output data signal, thereby achieving the purpose of emphasizing the output data signal.

[0069] In an illustrative embodiment, the DDR output driver circuit of this disclosure can be located in the memory controller of the DDR. Based on this scenario, the data signal to be transmitted can be one of a data signal or a control signal. The data signal to be transmitted is a data signal that has been processed by the memory controller and / or forwarded by the memory controller, and has not yet been processed by the TX circuit or the DDR output driver circuit of this disclosure.

[0070] like Figure 2 As shown in the illustrative embodiment, the DDR output driver circuit of this disclosure further includes a delay setting module 205. The delay setting module 205 is coupled to the second delay module 202 and is used to set the delay degree of the second delay signal relative to the first delay signal.

[0071] Emphasis processing includes two cases: pre-emphasis and de-emphasis. The phase relationship and amplitude difference between the emphasis control signal and the main signal used in pre-emphasis and de-emphasis are different, so the expected effects of pre-emphasis and de-emphasis are different. Based on the different phase relationship between the emphasis control signal and the main signal, the delay of the corresponding emphasis control signal is not the same when pre-emphasis processing and de-emphasis processing are required. Therefore, the DDR output driver circuit of this embodiment sets the delay degree of the second delay signal relative to the first delay signal through the delay setting module 205, thereby realizing the adaptive requirements for different emphasis processing of pre-emphasis and de-emphasis.

[0072] Figure 3 This is a schematic diagram illustrating an application scenario structure of a DDR output driver circuit according to an illustrative embodiment. For example... Figure 3 and combined Figure 2 As shown, in an illustrative embodiment, the first output driving module 203 includes a first number of output drivers, for example... Figure 3 The second output driver 21, the second output driver 22, ..., the second-M output driver 2M shown, with a first quantity of, for example, M, have their input terminals coupled to the first delay module 201 to receive a first delay signal. The output terminals of the first quantity of output drivers (the second-1 output driver 21, the second-2 output driver 22, ..., the second-M output driver 2M) are mutually coupled to obtain the first delay drive signal. The second output drive module 204 includes a second quantity of output drivers, for example... Figure 3 The output drivers shown are designated 3_1 (31), 3_2 (32), ..., 3_P (3P). The second number of output drivers (e.g., P) is connected to the second delay module 202 to receive the second delayed signal. The outputs of these second number of output drivers are also connected to each other to obtain the second delayed drive signal. The first and second numbers are determined by ZQ calibration. It should be noted that the differences between the output drivers 2_1 (21), 2_2 (22), ..., 2_M (2M), 3_1 (31), 3_2 (32), ..., 3_P (3P) are only in naming; the structures of all output drivers are identical.

[0073] In high-speed digital circuits, such as DDR circuits, signal integrity is paramount. To minimize signal reflections on transmission lines, it is essential to ensure that the driver's output impedance matches the characteristic impedance of the transmission line, while the terminating resistor at the receiving end also requires precise matching. However, the on-resistance of transistors in integrated circuits drifts significantly with process variations, operating voltage fluctuations, and temperature changes, making it extremely challenging to maintain stable impedance matching. ZQ calibration is a calibration method specifically designed to address this issue. The core of ZQ calibration lies in providing a stable external reference that is unaffected by PVT (process, voltage, temperature) factors. The purpose of ZQ calibration is to calibrate the output driver array 100, which consists of all the on-die terminations (ODTs) within the DRAM and the output drivers connected in parallel with the TX circuit, to the specified resistance values ​​(e.g., the nominal resistance values ​​specified by JEDEC (Joint Electron Device Engineering Council, including 240Ω, 120Ω, 48Ω, 34Ω, etc.) to compensate for process, voltage, and temperature drift. In summary, ZQ calibration uses an externally connected resistor with a set resistance value (e.g., 240Ω) as a benchmark, allowing the DRAM to align all its internal "variable resistors" at once, ensuring high-speed signal integrity and minimizing reflections without external intervention.

[0074] In an illustrative embodiment, in the DDR output driver circuit of this disclosure, the first output driver module 203 and the second output driver module 204 can be implemented by an output driver array 100 of the related art. Based on this, in the illustrative embodiment, a first number of output drivers and a second number of output drivers constitute an output driver array 100 composed of a preset number of output drivers. The sum of the first number and the second number is the preset number, for example, the preset number is... Figure 1 In the related technologies shown, N has two quantities: M and P, where M + P = N. In the DDR output driver circuit, the preset quantity is fixed, i.e., N remains constant. The output driver array 100 is a parallel binary weighted driver array, whose basic unit is a CMOS inverter. As a whole, the main function of this driver array is not to implement logic inversion, but rather to serve as a linear output driver stage with precisely controlled digital signals and programmable impedance.

[0075] Therefore, the DDR output driver circuit of this embodiment can fully utilize all the output drivers in the output driver array 100, and further achieve the purpose of emphasizing the output data signal while meeting the required drive strength or impedance matching under the necessary hardware conditions. For example, in conjunction with related technologies, the preset number is the total number of output drivers included in the output driver array 100. After the DDR design and manufacturing are completed, the total number of output drivers included in the output driver array 100 is fixed. According to the relevant JEDEC specifications for DDR, the output driver array 100 typically needs to have at least 6 to 10 output drivers to meet the relevant configuration requirements and ensure sufficient redundancy.

[0076] In an illustrative embodiment, in the DDR output driver circuit of this disclosure, the first quantity may be the number of output drivers that are turned on after ZQ calibration, and the second quantity may be the number of output drivers that should have been turned off after ZQ calibration.

[0077] In an illustrative embodiment, in the DDR output driver circuit of this disclosure, the second quantity may be the number of output drivers that are turned on after ZQ calibration, and the first quantity may be the number of output drivers that should have been turned off after ZQ calibration.

[0078] To achieve impedance matching, in this illustrative embodiment, the output driver is an impedance-adjustable driver.

[0079] In an illustrative embodiment, the impedance-adjustable driver is an impedance-adjustable inverter.

[0080] Figure 4 This is a schematic diagram of the circuit structure of the output driver according to an illustrative embodiment, such as... Figure 4As shown, in the illustrative embodiment, the output driver includes a PMOS MP1, a first adjustable resistor RV1, an NMOS MN1, and a second adjustable resistor RV2. The source of the PMOS MP1 is coupled to the power supply voltage VDD. One end of the first adjustable resistor RV1 is coupled to the drain of the PMOS MP1. The source of the NMOS MN1 is connected to reference ground VSS. One end of the second adjustable resistor RV2 is coupled to the drain of the NMOS MN1. The gates of the PMOS MP1 and the NMOS MN1 are coupled together as the input terminal of the output driver, and the other ends of the first and second adjustable resistors RV1 and RV2 are coupled together as the output terminal of the output driver. In the illustrative embodiment, the resistance values ​​of the first and second adjustable resistors RV1 and RV2 are determined by ZQ calibration. By adjusting the resistance values ​​of the first and second adjustable resistors RV1 and RV2, the pull-up and pull-down capabilities of the output driver can be adjusted. This approach enables the DDR output driver circuit of the present disclosure embodiments to be directly compatible with the relevant DDR protocol standards, which helps the present disclosure embodiments to be compatible with existing DDR technologies.

[0081] The DDR output driver circuit of this disclosure, through the cooperation of the first delay module 201, the second delay module 202, the first output drive module 203 (a first number of output drivers), and the second output drive module 204 (a second number of output drivers), achieves impedance matching in related technologies and reuses previously redundant and unused output drivers to realize the emphasis processing of the output data signal. According to the emphasis processing requirements, the DDR output driver circuit of this disclosure can realize pre-emphasis and de-emphasis.

[0082] In the illustrative embodiment, the first delay module 201 and the second delay module 202 have the same basic structure, both consisting of several basic delay units (such as buffers) connected in series. In the illustrative embodiment, the number of basic delay units in the first delay module 201 that delay the data signal to be transmitted is fixed, that is, the delay amount of the data signal to be transmitted in the first delay module 201 is not adjustable. Relative to the data signal to be transmitted in the second delay module 202, the delay of the data signal to be transmitted in the first delay module 201 can be called the intrinsic delay, and the first delayed signal can also be called the intrinsic delay signal. In an illustrative embodiment, the number of basic delay units in the second delay module 202 used to delay the data signal to be transmitted can be adjusted as needed. That is, the delay amount of the data signal to be transmitted in the second delay module 202 can be adjusted. The selection of the second delayed signal by the second delay module 202 can be realized by a multiplexer (MUX) and related registers. The registers are used to control which basic delay units the multiplexer passes through in the second delay module 202 before outputting the second delayed signal. The information in the registers can be configured by the delay setting module 205 to realize the relevant settings of the delay degree of the second delayed signal relative to the first delayed signal.

[0083] In an illustrative embodiment, when pre-emphasizing the output data signal, the first delay signal is the pre-emphasization control signal, the second delay signal is the main signal, and the output data signal is the equalized data signal after pre-emphasization.

[0084] In an illustrative embodiment, when the output data signal is pre-emphasized, the pulse of the first delayed signal is time-correlated with the transition edge of the second delayed signal, and the pulse of the first delayed signal leads the transition edge of the second delayed signal.

[0085] In the case of pre-emphasis of the output data signal, by configuring the second delay module 202, the transition of the second delay signal lags slightly behind the pulse of the first delay signal. That is, the pulse of the first delay signal leads the transition of the second delay signal, thereby establishing a relationship between the first and second delay signals as a pre-emphasis control signal and the main signal. Then, through the pre-emphasis processing of the first output drive module 203 and the second output drive module 204 (i.e., the output driver array 100 with all output drivers enabled), the pre-emphasized equalized data signal is obtained. At this time, the first output drive module 203 and the second output drive module 204 (i.e., the output driver array 100 with all output drivers enabled) not only perform impedance matching but also pre-emphasize the output data signal, thus realizing the pre-emphasis function of the output data signal.

[0086] In an illustrative embodiment, when de-emphasis is implemented on the output data signal, the first delay signal is the main signal, the second delay signal is the de-emphasis control signal, and the output data signal is the de-emphasis equalized data signal.

[0087] In an illustrative embodiment, when de-emphasis is implemented on the output data signal, the effective level of the second delayed signal is temporally correlated with the steady-state portion of the first delayed signal, and the transition edge of the second delayed signal has a defined delay relative to the transition edge of the first delayed signal.

[0088] In the process of de-emphasing the output data signal, the second delay module 202 is configured such that the transition edge of the second delayed signal has a certain delay relative to the transition edge of the first delayed signal. That is, the transition edge of the second delayed signal lags behind the transition edge of the first delayed signal, thereby establishing a relationship between the first and second delayed signals: a main signal and a de-emphasis control signal. The de-emphasis-equipped equalized data signal is then obtained through the de-emphasis processing of the first output drive module 203 and the second output drive module 204 (i.e., the output driver array 100 with all output drivers enabled). At this time, the first output drive module 203 and the second output drive module 204 (i.e., the output driver array 100 with all output drivers enabled) not only perform impedance matching but also de-emphasize the output data signal, thus realizing the de-emphasis function of the output data signal.

[0089] The configuration process of the DDR output driver circuit in this embodiment is as follows:

[0090] Step 1: Perform ZQ calibration to set the resistance value of the adjustable resistor in each output driver in the output driver array 100, as well as the number of output drivers turned on corresponding to the main signal, to complete impedance matching.

[0091] Step 2: According to the signal emphasis requirements, one of the first output driving module 203 and the second output driving module 204 is determined as the main path corresponding to the main signal, and the other of the first output driving module 203 and the second output driving module 204 is determined as the emphasis path corresponding to the emphasis signal. The number of output drivers in the main path is the number of output drivers that are turned on corresponding to the main signal.

[0092] Step 3: Set the delay degree of the second delay module 202 according to the signal emphasis requirements.

[0093] Step 2 is divided into the following two cases:

[0094] Scenario 1, Pre-aggravation:

[0095] In the case of pre-emphasis requirement, the first output driving module 203 is determined as the pre-emphasis path corresponding to the pre-emphasis signal, and the second output driving module 204 is determined as the main path. The number of output drivers in the second output driving module 204 is the number of output drivers turned on corresponding to the main signal. The second output driving module 204 can be used for impedance matching.

[0096] Scenario 2, to aggravate:

[0097] In the case of deemphasis requirement, the second output drive module 204 is determined as the preemphasis path corresponding to the deemphasis signal, and the first output drive module 203 is determined as the main path. The number of output drivers in the first output drive module 203 is the number of output drivers turned on corresponding to the main signal. The first output drive module 203 can be used for impedance matching.

[0098] Step 3 is divided into the following two cases:

[0099] Scenario 1, Pre-aggravation:

[0100] In the case of pre-emphasis requirements, the delay degree of the second delay module 202 is set so that the pulse of the first delay signal leads the transition of the second delay signal, thereby enabling the output data signal to generate an "overshoot" waveform when the second delay signal, which is the main signal, transitions, thus compensating for the attenuation of the high-frequency transition edge of the signal transmission line.

[0101] Scenario 2, to aggravate:

[0102] In the case of reducing the demand, the delay of the second delay module 202 is set so that the transition edge of the second delay signal has a certain delay relative to the transition edge of the first delay signal. This delay is a delay with a phase of more than 180 degrees, so that the effective level of the second delay signal is temporally correlated with the steady-state part of the first delay signal, and the phase of the second delay signal is opposite to the phase of the first delay signal. Thus, during the non-transition period of the first delay signal, which is the main signal, the signal amplitude of the output data signal is weakened, thereby highlighting the transition of the output data signal.

[0103] The DDR output driver circuit of this disclosure, based on impedance matching of related technologies, reuses the originally redundant and unused output driver to achieve pre-emphasis and de-emphasis processing of the output data signal. This is beneficial for combating high-frequency loss of the transmission line, ensuring steep signal edges, reducing inter-symbol interference, preventing the energy of the previous bit of transmitted data from interfering with the next bit, expanding the signal eye diagram, and thus improving the data sampling margin at the receiving end and reducing the bit error rate.

[0104] The purpose of impedance matching is to eliminate the influence of signal reflection, ensuring that signal energy is efficiently and without reflection transmitted from the driving source to the transmission line, thereby obtaining a clean and complete signal waveform. This is already accomplished during ZQ calibration. The emphasis processing disclosed herein is equivalent to changing the current driving intensity of the main signal at fixed time points in the signal time domain to achieve pre-emphasis or de-emphasis, which does not conflict with impedance matching.

[0105] Meanwhile, the DDR output driver circuit of this embodiment does not affect the load of subsequent circuits, including bump pads, and achieves the goal of emphasis processing without adding an additional output driver. Furthermore, the emphasis position of the main signal can be flexibly adjusted by changing the delay of the second delay module 202 relative to the first delay signal. The DDR output driver circuit of this embodiment utilizes a delay line added to the data path to transmit pre-emphasis or de-emphasis control signals using an output driver not used after ZQ calibration, thereby optimizing the signal eye diagram.

[0106] In illustrative embodiments, depending on the design, at least one of the first delay module 201, the second delay module 202, the first output driver module 203, the second output driver module 204, and the delay setting module 205 can be implemented as a combination of multiple hardware, firmware, and software (i.e., programs).

[0107] In terms of hardware, at least one of the first delay module 201, the second delay module 202, the first output driver module 203, the second output driver module 204, and the delay setting module 205 can be implemented as logic circuits on an integrated circuit. For example, the related functions of at least one of the first delay module 201, the second delay module 202, the first output driver module 203, the second output driver module 204, and the delay setting module 205 can be implemented in various logic blocks, modules, and circuits in one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), or other processing units. The relevant functions of at least one of the first delay module 201, the second delay module 202, the first output driver module 203, the second output driver module 204, and the delay setting module 205 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages.

[0108] In software or firmware form, the relevant functions of at least one of the first delay module 201, the second delay module 202, the first output driver module 203, the second output driver module 204, and the delay setting module 205 can be implemented as programming codes. For example, at least one of the first delay module 201, the second delay module 202, the first output driver module 203, the second output driver module 204, and the delay setting module 205 can be implemented using general programming languages ​​(such as C, C++, or assembly language) or other suitable programming languages. The programming code can be recorded and stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or a storage device. Electronic devices (such as CPUs, hardware controllers, microcontrollers, hardware processors, or microprocessors) can read and execute programming code from a non-transient machine-readable storage medium to achieve at least one of the related functions of the first delay module 201, the second delay module 202, the first output driver module 203, the second output driver module 204, and the delay setting module 205.

[0109] In the illustrative embodiments, the DDR output driver circuit of this disclosure is applicable to SoC chips, etc., wherein the SoC chip can be any one of CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural network Processing Unit), DPU (Deep learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Unit).

[0110] In an illustrative embodiment, a DDR chip is also provided, which includes the DDR output driver circuitry as described in any of the preceding embodiments.

[0111] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A DDR output driver circuit, characterized in that, include: The first delay module is used to receive the data signal to be transmitted and perform a first delay on the data signal to be transmitted to obtain a first delayed signal. The second delay module is used to receive the data signal to be transmitted and perform a second delay on the data signal to be transmitted to obtain a second delayed signal. A first output driving module, coupled to the first delay module, is used to receive the first delay signal and drive the first delay signal to obtain and output a first delay driving signal; The second output driving module is coupled to the second delay module and is used to receive the second delay signal, drive the second delay signal to obtain and output the second delay driving signal; The output terminals of the first output driving module and the second output driving module are coupled together, so that the first delay driving signal and the second delay driving signal are coupled to obtain an emphasized output data signal. The first output driving module includes a first number of output drivers, and the second output driving module includes a second number of output drivers. The first number of output drivers and the second number of output drivers form an output driver array composed of a preset number of output drivers.

2. The DDR output driver circuit according to claim 1, characterized in that, The DDR output driver circuit also includes: The delay setting module, coupled to the second delay module, is used to set the delay degree of the second delay signal relative to the first delay signal.

3. The DDR output driver circuit according to claim 1, characterized in that: The input terminals of the first number of output drivers are coupled to the first delay module to receive the first delay signal, and the output terminals of the first number of output drivers are coupled to each other to obtain the first delay drive signal; The input terminals of the second number of output drivers are coupled to the second delay module to receive the second delay signal, and the output terminals of the second number of output drivers are coupled to each other to obtain the second delay drive signal; The first quantity and the second quantity are determined by ZQ calibration.

4. The DDR output driver circuit according to claim 3, characterized in that: The sum of the first quantity and the second quantity is the preset quantity; In the DDR output driver circuit, the preset quantity remains constant.

5. The DDR output driver circuit according to claim 3, characterized in that: The output driver is an impedance-adjustable driver.

6. The DDR output driver circuit according to claim 5, characterized in that: The impedance-adjustable driver is an impedance-adjustable inverter.

7. The DDR output driver circuit according to claim 3, characterized in that, The output driver includes: PMOS, wherein the source of the PMOS is coupled to the power supply voltage; A first adjustable resistor, one end of which is coupled to the drain of the PMOS; NMOS, wherein the source of the NMOS is connected to the reference ground; A second adjustable resistor, one end of which is coupled to the drain of the NMOS; The gate of the PMOS and the gate of the NMOS are coupled to each other as the input terminal of the output driver, and the other end of the first adjustable resistor and the other end of the second adjustable resistor are coupled to each other as the output terminal of the output driver. The resistance values ​​of the first adjustable resistor and the second adjustable resistor are determined by ZQ calibration.

8. The DDR output driver circuit according to claim 1, characterized in that: The first delay signal is a pre-emphasis control signal, the second delay signal is the main signal, and the output data signal is the equalized data signal after pre-emphasis.

9. The DDR output driver circuit according to claim 1, characterized in that: The pulse of the first delayed signal is time-correlated with the transition edge of the second delayed signal, and the pulse of the first delayed signal leads the transition edge of the second delayed signal.

10. The DDR output driver circuit according to claim 1, characterized in that: The first delayed signal is the main signal, the second delayed signal is the de-emphasis control signal, and the output data signal is the de-emphasis equalized data signal.

11. The DDR output driver circuit according to claim 1, characterized in that: The effective level of the second delayed signal is time-correlated with the steady-state portion of the first delayed signal, and the transition edge of the second delayed signal has a defined delay relative to the transition edge of the first delayed signal.

12. A DDR chip, characterized in that, Includes the DDR output driver circuit as described in any one of claims 1 to 11.

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