Mixed-polarity rm logic area-power trade-off analysis system and method thereof

Abstract

The application provides a mixed polarity RM logic area-power consumption trade-off analysis system and method, which is applied to the field of integrated circuit design and comprises a logic library database, a mixed polarity synthesizer, a logic synthesizer, a power consumption calculator, a constraint converter and a layout analyzer. The mixed polarity synthesizer is a core innovative module, which comprises a circuit topology mapping engine, a multi-level homomorphism decision engine, a spectrum feature cooperative optimization engine and an optimization strategy adjustment unit. The application innovatively maps the circuit structure into a weighted directed graph and converts the polarity distribution problem into an optimization problem on the graph. The multi-level topology homomorphism model is adopted to realize the macroscopic, mesoscopic and microscopic representation of the circuit, thereby effectively reducing the optimization complexity. The spectrum graph theory is introduced to analyze the circuit structure, and the optimal trade-off between area and power consumption is realized through spectrum segmentation and cooperative optimization. Compared with the prior art, the search space is reduced by more than 80%, and the optimization speed is increased by 3-5 times.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and in particular to a mixed-polarity RM (Reed-Muller) logic area-power tradeoff analysis system and method, for automatically searching for area-power tradeoff points for mixed-polarity CMOS integrated circuits and obtaining area-power tradeoff curves. Background Technology

[0002] With the development of integrated circuit technology and the diversification of application requirements, low-power design has become an important goal in integrated circuit design. Hybrid polarity Reed-Muller (RM) logic, as a novel logic design method, has significant advantages in low-power applications. However, the polarity allocation of hybrid polarity RM logic directly affects the circuit's area and power consumption performance; a reasonable polarity allocation is key to achieving the optimal trade-off between area and power consumption.

[0003] Traditional polarity optimization methods primarily employ heuristic search or exhaustive methods. When dealing with large-scale circuits, these methods suffer from exponential growth of the search space, resulting in low optimization efficiency and a tendency to get trapped in local optima. Furthermore, existing methods often treat area and power consumption as independent objectives, making it difficult to find the optimal trade-off.

[0004] Currently, there is no existing technology that can comprehensively consider the characteristics of circuit topology and achieve synergistic optimization of area and power consumption for mixed-polarity RM logic area-power tradeoff analysis. Therefore, developing an efficient mixed-polarity RM logic area-power tradeoff analysis system is of great significance for improving the design efficiency and performance of mixed-polarity CMOS integrated circuits. Summary of the Invention

[0005] The purpose of this invention is to provide a mixed-polarity RM logic area-power tradeoff analysis system and method. By introducing graph topology optimization technology, it realizes intelligent decision-making for circuit polarity allocation, efficiently obtains area-power tradeoff curves, and provides strong support for mixed-polarity CMOS integrated circuit design.

[0006] This invention proposes a hybrid polarity RM logic area-power tradeoff analysis system and method, including:

[0007] A logic library database used to store basic circuit unit libraries of different polarities;

[0008] A mixed-polarity synthesizer, connected to the logic library database, is used to perform mixed-polarity conversion on the input circuit layout, wherein the mixed-polarity synthesizer includes:

[0009] A circuit topology mapping engine is used to map circuit structures into weighted directed graphs, which include nodes representing logic gates and edges representing connection relationships.

[0010] A multi-level homomorphic decision engine, connected to the circuit topology mapping engine, is used to construct a three-level topology model of the circuit, consisting of macroscopic, mesoscopic, and microscopic layers, and to make polarity decisions at each level based on topological homomorphism theory.

[0011] A spectral feature collaborative optimization engine, connected to the multi-level homomorphic decision engine, is used to perform spectral segmentation of the circuit using spectral theory and achieve area-power consumption collaborative optimization.

[0012] A logic synthesizer, connected to the mixed-polarity synthesizer, is used to provide process libraries of different polarities to the mixed-polarity synthesizer and receive the final synthesis result from the mixed-polarity synthesizer;

[0013] A power consumption calculator, connected to the logic synthesizer, is used to provide an area-power consumption tradeoff calculation method, calculate the power consumption value based on the synthesis result of the logic synthesizer, and obtain the area-power consumption tradeoff curve;

[0014] A constraint converter, connected to the logic synthesizer, is used to convert the user constraint list into a format suitable for the power consumption calculator.

[0015] A layout analyzer, connected to the logic synthesizer, is used to generate circuit layout during the circuit synthesis stage.

[0016] Preferably, the circuit topology mapping engine includes:

[0017] The netlist parsing unit is used to read the circuit netlist description and identify different types of logic gates and their connections.

[0018] A node construction unit, connected to the netlist parsing unit, is used to map each logic gate to a node in the graph and mark the node type and initial polarity state.

[0019] An edge relationship construction unit, connected to the node construction unit, is used to establish directed edges based on signal flow direction and calculate the weight attributes of the edges;

[0020] The topology feature extraction unit, connected to the edge relationship construction unit, is used to calculate global topology features and identify functional sub-units and critical paths.

[0021] Preferably, the multi-level homomorphic decision engine includes:

[0022] Hierarchical model building units are used to construct three-layer topological models: macroscopic, mesoscopic, and microscopic.

[0023] The homomorphic mapping unit, connected to the hierarchical model construction unit, is used to define structure preservation rules, attribute transformation rules, and constraint transfer rules, and to establish inter-layer mapping relationships.

[0024] The hierarchical decision-making unit, connected to the homomorphic mapping unit, is used to make polarity decisions starting from the macro level, pass the decisions to the lower levels through homomorphic mapping, and handle inter-level conflicts and feedback adjustments.

[0025] Preferably, the spectral feature collaborative optimization engine includes:

[0026] The spectral representation building unit is used to construct a weighted Laplacian matrix based on the circuit topology diagram, and to calculate the eigenvalue spectrum and key eigenvectors.

[0027] A spectrum segmentation unit, connected to the spectrum representation construction unit, is used to divide the circuit into sub-regions with high polarity correlation using feature vectors;

[0028] The collaborative optimization unit, connected to the spectrum segmentation unit, is used to define an area-power-weighted objective function, perform polarity optimization in each region, and coordinate consistency between regions.

[0029] Preferably, the weighted directed graph includes a node table and an edge table. The node table stores node ID, gate type, polarity state, fan-in list, fan-out list, and topology attributes. The edge table stores edge ID, source node, target node, signal type, and weight attributes.

[0030] The gate types of the nodes include combinational logic gates, sequential logic gates, and mixed logic gates;

[0031] The polarity states include positive polarity, negative polarity, and variable polarity.

[0032] Preferably, the processing flow of the hierarchical decision-making unit includes:

[0033] At the macro level, global polarity initialization is performed based on functional modules;

[0034] The meso-level receives the decision results from the macro-level, refines the polarity within the functional units, and resolves polarity conflicts at the interfaces between units.

[0035] The decision constraints mapped from the meso-level are received at the micro-level, and precise polarity assignment is performed on each logic gate;

[0036] Through the inter-layer feedback adjustment mechanism, the actual results of the lower layer are fed back to the upper layer, and the upper layer adjusts its decision-making strategy based on the feedback.

[0037] Preferably, the collaborative optimization unit adopts:

[0038] Adaptive spectrum segmentation technology dynamically adjusts the segmentation granularity based on circuit characteristics, balancing the size of subproblems and inter-region dependencies.

[0039] Multi-level spectral filtering technology filters out non-critical spectral features to reduce computation while retaining structurally sensitive critical features.

[0040] Boundary node processing technology identifies key boundary nodes between regions and designs special boundary processing strategies to ensure optimized coordination and consistency between regions.

[0041] Preferably, the hybrid polarity synthesizer further includes an optimization strategy adjustment unit, connected to the spectral feature co-optimization engine, for:

[0042] The area-power consumption weights are dynamically adjusted based on the optimization progress.

[0043] Resource allocation that balances local optimization and global coordination;

[0044] Simultaneously maintain multiple candidate solution spaces for parallel exploration;

[0045] Adjust the search strategy based on the feedback.

[0046] Preferably, the hybrid polarity synthesizer further includes a circuit decomposition model, which decomposes the circuit into basic units in the circuit basic unit library. All gates in the entire circuit that contain only combinational logic are selected as candidate gates with variable polarity; all gates in the entire circuit that contain sequential logic and gates that contain both combinational and sequential logic are selected as fixed gates with immutable polarity; and an iterative strategy is used to find the optimal polarity during the polarity decomposition process, wherein the iterative strategy stops the polarity decomposition when an increase in area or power consumption occurs.

[0047] A mixed-polarity RM logic area-power tradeoff analysis method, applied to the aforementioned system, is characterized by comprising the following steps:

[0048] Input circuit, define global polarity and circuit constraints;

[0049] Decompose the circuit into basic units from the basic circuit unit library;

[0050] The circuit topology mapping engine maps the circuit structure into a weighted directed graph.

[0051] The multi-level homomorphic decision engine is used to construct a three-level topological model and perform polarity decisions at each level.

[0052] The circuit is spectrally segmented and area-power consumption is optimized through the spectral feature collaborative optimization engine.

[0053] The area-power consumption weight and search strategy are dynamically adjusted through the optimization strategy adjustment unit.

[0054] The final polarity decision result is output to the logic synthesizer;

[0055] The power consumption calculator is used to calculate the power consumption value and obtain the area-power consumption trade-off curve.

[0056] The layout analyzer generates the circuit layout.

[0057] The beneficial effects of this invention include:

[0058] 1. By introducing graph theory and topology optimization theory into the field of polarity optimization, the circuit structure is innovatively mapped as a weighted directed graph, and the polarity assignment problem is transformed into an optimization problem on the graph, thereby improving the quality of decision-making from a mechanistic perspective.

[0059] 2. By adopting a multi-level topological homomorphic model, the macroscopic, mesoscopic and microscopic layers of the circuit are represented, which effectively reduces the optimization complexity, reduces the search space by more than 80%, and improves the optimization speed by 3-5 times.

[0060] 3. By introducing spectral theory to analyze the circuit structure, and through spectral segmentation and collaborative optimization, the power consumption is reduced by an average of 15-25% under the same area constraint; and the area is reduced by an average of 10-20% under the same power consumption constraint.

[0061] 4. It has good scalability, supports optimization of circuits with millions of gates, adapts to different scale requirements, significantly reduces design costs, and shortens the design cycle. Attached Figure Description

[0062] Figure 1 This is the overall architecture diagram of the hybrid polarity RM logic area-power tradeoff analysis system of the present invention;

[0063] Figure 2 This is a diagram showing the internal structure of the hybrid polarity synthesizer of the present invention;

[0064] Figure 3 This is a flowchart illustrating the workflow of the circuit topology mapping engine of this invention.

[0065] Figure 4 This is a flowchart illustrating the workflow of the multi-level homomorphic decision engine of this invention.

[0066] Figure 5 This is a flowchart illustrating the workflow of the spectral feature collaborative optimization engine of this invention.

[0067] Figure 6 This is a flowchart of the mixed polarity RM logic area-power tradeoff analysis method of the present invention. Detailed Implementation

[0068] Please refer to Figures 1-6 The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0069] like Figure 1As shown, the present invention provides a mixed polarity RM logic area-power tradeoff analysis system, including: a logic library database 1, a mixed polarity synthesizer 2, a logic synthesizer 3, a power consumption calculator 4, a constraint converter 5, and a layout analyzer 6.

[0070] Logic library database 1 is used to store basic circuit cell libraries of different polarities. In practical applications, logic library database 1 can contain basic logic cells with positive and negative polarities, such as AND gates, OR gates, NOT gates, NAND gates, NOR gates, etc., as well as various composite logic cells. Preferably, logic library database 1 can also store the area and power consumption parameters of each basic cell, providing basic data for subsequent area-power consumption tradeoff analysis. For example, for a standard cell library under a certain process node, the area of ​​a positive NAND gate may be 2.5 μm², the static power consumption is 0.03 μW, and the dynamic power consumption is 0.5 μW at a 1 MHz operating frequency; while the area of ​​a negative NAND gate may be 2.2 μm², the static power consumption is 0.035 μW, and the dynamic power consumption is 0.48 μW under the same conditions.

[0071] The hybrid polarity synthesizer 2 is connected to the logic library database 1 and is used to perform hybrid polarity conversion on the input circuit layout. As the core innovative module of this invention, the hybrid polarity synthesizer 2 employs a graph topology optimization method to achieve efficient polarity allocation decisions. For example... Figure 2 As shown, the hybrid polarity synthesizer 2 includes a circuit topology mapping engine 21, a multi-level homomorphic decision engine 22, a spectral feature collaborative optimization engine 23, and an optimization strategy adjustment unit 24. Furthermore, the hybrid polarity synthesizer 2 also includes a circuit decomposition model 25, used to decompose the circuit into basic units from a circuit basic unit library.

[0072] The circuit topology mapping engine 21 is used to map the circuit structure into a weighted directed graph, which includes nodes representing logic gates and edges representing connection relationships. Specifically, the circuit topology mapping engine 21 includes a netlist parsing unit 211, a node construction unit 212, an edge relationship construction unit 213, and a topology feature extraction unit 214.

[0073] The netlist parsing unit 211 is used to read the circuit netlist description and identify different types of logic gates and their connections. In one embodiment of the present invention, the netlist parsing unit 211 can handle various common netlist formats, such as Verilog and SPICE, and extract circuit structure information through syntax analysis. For example, for an 8-bit adder circuit, the netlist parsing unit 211 can identify approximately 100 basic logic gates, including AND gates, OR gates, NOT gates, etc., and their connections.

[0074] Node construction unit 212 is connected to netlist resolution unit 211 and is used to map each logic gate to a node in the graph, and to mark the node type and initial polarity state. In this invention, node types include combinational logic gates, sequential logic gates, and hybrid logic gates; polarity states include positive polarity, negative polarity, and variable polarity. It is worth noting that only combinational logic gates are marked as variable polarity, while sequential logic gates and hybrid logic gates are marked as immutable polarity. This distinction is crucial for ensuring the correctness of circuit function. In practical applications, for the aforementioned 8-bit adder, node construction unit 212 may identify 85 combinational logic gates (candidate gates) and 15 sequential logic gates (fixed gates).

[0075] Edge relationship construction unit 213 is connected to node construction unit 212 and is used to establish directed edges based on signal flow direction and calculate the weight attributes of the edges. In this invention, the weight attributes of the edges include signal delay, load capacitance, power consumption influence factor, etc. For example, the power consumption influence factor of the edge can be calculated by the following formula:

[0076] ,

[0077] in, Here, α is the power consumption influence factor (in μW), and α is the activity factor (dimensionless, representing the probability of signal switching, ranging from 0 to 1). Load capacitance (in pF) This refers to the supply voltage (in volts). This refers to the operating frequency (in MHz). In practical applications, Estimation can be made based on the application scenario of the circuit, for example, for high-activity data paths. 0.5 can be used; for control logic, A value of 0.2 can be used; for clock networks, It can range from 0.8 to 1.0. For an 8-bit adder at the 65nm process node, a typical... The value may be between 0.01 pF and 0.05 pF. It is 1.2V. It is 500MHz, therefore It is approximately between 3 μW and 15 μW.

[0078] The topology feature extraction unit 214 is connected to the edge relationship construction unit 213 and is used to calculate global topology features and identify functional sub-units and critical paths. Global topology features include graph connectivity, diameter, etc.; functional sub-units refer to circuit modules with specific functions, such as adders and multipliers; critical paths refer to paths in the circuit that have a decisive impact on timing performance. Preferably, the topology feature extraction unit 214 can also calculate the topology importance index of each node, such as centrality, which helps in the subsequent polarity decision-making process. In the example of an 8-bit adder, the topology feature extraction unit 214 may identify carry propagation chains as critical paths and mark the logic gates in the carry propagation chains as high-priority nodes.

[0079] The multi-level homomorphic decision engine 22 is connected to the circuit topology mapping engine 21 and is used to construct a three-layer topology model of the circuit, namely the macroscopic layer, the mesoscopic layer, and the microscopic layer, and to make polarity decisions at each layer based on topological homomorphism theory. The multi-level homomorphic decision engine 22 includes a hierarchical model construction unit 221, a homomorphic mapping unit 222, and a hierarchical decision unit 223.

[0080] The hierarchical model building unit 221 is used to construct a three-layer topology model: macroscopic, mesoscopic, and microscopic. The macroscopic layer corresponds to the functional block level, with nodes representing functional modules and edges representing interfaces between modules. The mesoscopic layer corresponds to the sub-circuit level, with nodes representing logic sub-circuits and edges representing signal flows. The microscopic layer corresponds to the gate-level circuit, with nodes representing logic gates and edges representing actual connections. This multi-layered representation effectively reduces optimization complexity, making the optimization of large-scale circuits feasible. In the example of an 8-bit adder, the macroscopic layer may contain only one node (the entire adder); the mesoscopic layer may contain eight nodes (eight 1-bit full adders); and the microscopic layer may contain approximately 100 nodes (all logic gates).

[0081] Homomorphic mapping unit 222 is connected to hierarchical model building unit 221 and is used to define structure preservation rules, attribute transformation rules, and constraint propagation rules to establish inter-layer mapping relationships. Structure preservation rules ensure that the topology of the critical path remains unchanged, maintaining control dependencies and functional equivalence; attribute transformation rules define how the attributes of higher-level nodes are aggregated from the attributes of the corresponding lower-level node sets; constraint propagation rules ensure that timing constraints, area constraints, and power constraints are reasonably propagated during inter-layer mapping. For example, in an 8-bit adder, if a 2ns timing constraint is set at the macroscopic layer, homomorphic mapping unit 222 will allocate this constraint to the mesoscopic layer according to the proportion of each 1-bit full adder on the critical path. The possible result is that a 1-bit full adder on the carry chain is allocated a 0.2ns constraint, instead of a constraint on the non-carry chain allocated a 0.3ns constraint.

[0082] The hierarchical decision-making unit 223 is connected to the homomorphic mapping unit 222 and is used to make polarity decisions starting from the macro level, pass the decisions to the lower levels through homomorphic mapping, and handle inter-level conflicts and feedback adjustments. In one embodiment of the present invention, the processing flow of the hierarchical decision-making unit 223 includes: performing initial global polarity allocation based on functional modules at the macro level; receiving the macro level decision results at the meso level, refining the polarity within the functional units, and resolving polarity conflicts at the interfaces between units; receiving the decision constraints mapped by the meso level at the micro level, and performing precise polarity allocation for each logic gate; and through the inter-level feedback adjustment mechanism, feeding back the actual results from the lower levels to the upper levels, and adjusting the decision strategy based on the feedback. This hierarchical decision-making method can improve optimization efficiency while ensuring global optimality. In the example of an 8-bit adder, the hierarchical decision unit 223 may first decide that the entire adder adopts positive polarity (macro-level decision), then decide that the first 4 bits adopt positive polarity and the last 4 bits adopt negative polarity according to the characteristics of each 1-bit full adder (meso-level decision), and finally perform precise polarity allocation for each logic gate (micro-level decision).

[0083] The spectral feature collaborative optimization engine 23 is connected to the multi-level homomorphic decision engine 22, and is used to perform spectral segmentation of the circuit using spectral theory and achieve area-power collaborative optimization. The spectral feature collaborative optimization engine 23 includes a spectral representation construction unit 231, a spectral segmentation unit 232, and a collaborative optimization unit 233.

[0084] The spectral representation construction unit 231 is used to construct a weighted Laplacian matrix based on the circuit topology diagram, and to calculate the eigenvalue spectrum and key eigenvectors. The construction of the weighted Laplacian matrix L can be achieved through the following steps:

[0085] First, construct the adjacency matrix. ,in Represents a node and nodes The connection weights between nodes. If nodes and nodes If there is no connection between them, then .in, It is an adjacency matrix. For matrix The Line number Column elements (representing nodes) To the node (connection weights).

[0086] Next, construct the degree matrix. This is a diagonal matrix, where , represents a node The weighted degree. Among them, For degree matrix, For matrix The Line number Column elements (representing nodes) (weighted degree) Indicates all The value is summed and the node is about to be The connection weights are added together with those of all other nodes.

[0087] Finally, calculate the Laplace matrix. .in, Let be the Laplace matrix, representing the topological properties of the graph.

[0088] The eigenvalues ​​and eigenvectors of the Laplacian matrix contain important information about the graph structure. In particular, the second smallest eigenvalue (algebraic connectivity) and its corresponding eigenvector (Fiedler vector) are especially useful for graph partitioning. In practical applications, for a circuit graph with 100 nodes, the Laplacian matrix L is a 100×100 matrix, and calculating its eigenvalues ​​and eigenvectors may require numerical methods such as power iteration or QR decomposition.

[0089] The spectrum segmentation unit 232 is connected to the spectrum representation construction unit 231 and is used to divide the circuit into sub-regions with high polarity correlation using feature vectors. Specifically, the spectrum segmentation unit 232 sorts the nodes using the values ​​in the Fiedler vector and then divides the nodes into different sub-regions according to a certain threshold. In one embodiment of the present invention, the median of the Fiedler vector can be selected as the threshold to divide the circuit into two sub-regions; or multiple thresholds can be used to achieve multi-region division based on the distribution characteristics of the Fiedler vector. For example, in an 8-bit adder circuit, if the value range of the Fiedler vector is [-0.2, 0.3], the median may be around 0.05, then 0.05 can be used as the threshold to divide the circuit into two sub-regions.

[0090] The collaborative optimization unit 233 is connected to the spectrum segmentation unit 232 and is used to define an area-power-weighted objective function, perform polarity optimization in each region, and coordinate consistency between regions. In this invention, the collaborative optimization unit 233 employs adaptive spectrum segmentation technology, multi-level spectrum filtering technology, and boundary node processing technology.

[0091] The area-power weighted objective function can be expressed as:

[0092] ,

[0093] in, The weighted objective function value (dimensionless). This is the area weighting coefficient (dimensionless, ranging from 0 to 1). For normalized area (dimensionless), Normalized power consumption (dimensionless). Normalized area and power consumption are ratios relative to a reference value, typically taken as the area and power consumption of the initial design. , ,in This is the actual area. Base area This represents the actual power consumption. This is the baseline power consumption. In practical applications, The value can be dynamically adjusted according to design requirements. For example, if the area constraint is stricter, it can be set to... If power consumption constraints are stricter, you can set... .

[0094] Adaptive spectral segmentation technology dynamically adjusts the segmentation granularity based on circuit characteristics, balancing the size of subproblems and inter-region dependencies. For example, a larger segmentation granularity can be used for structurally uniform circuit parts, while a smaller segmentation granularity can be used for structurally complex parts. In practical applications, the appropriate segmentation point can be determined by the spectral gap (the difference between adjacent eigenvalues); the larger the spectral gap, the better the segmentation effect. For an 8-bit adder, if the spectral gap between the 2nd and 3rd eigenvalues ​​is large (e.g., the difference is greater than 0.1), while the difference between the 3rd and 4th eigenvalues ​​is small (e.g., less than 0.02), then the eigenvector corresponding to the 2nd eigenvalue can be used for binary segmentation.

[0095] Multi-level spectral filtering techniques are used to filter out non-critical spectral features to reduce computational load while retaining structurally sensitive key features. In practical applications, only a few eigenvalues ​​and their corresponding eigenvectors closest to the algebraic connectivity can be retained. These eigenvectors typically contain the most critical information about the graph structure. For example, for a 100-node circuit graph, it may only be necessary to compute the 10 smallest eigenvalues ​​and their eigenvectors, instead of all 100.

[0096] Boundary node processing technology is used to identify critical boundary nodes between regions and design special boundary processing strategies to ensure consistent optimization between regions. Boundary nodes are nodes connecting different sub-regions, and the polarity decisions for these nodes need to consider the influence of multiple sub-regions. In this invention, boundary nodes can be given higher priority or special decision rules can be adopted. For example, between two sub-regions of an 8-bit adder, there may be five boundary nodes. The polarity decisions for these nodes can be set to prioritize minimizing the critical path delay while satisfying the constraints of both sub-regions.

[0097] The optimization strategy adjustment unit 24 is connected to the spectral feature collaborative optimization engine 23, and is used to dynamically adjust the area-power consumption weights according to the optimization progress; balance the resource allocation between local optimization and global coordination; simultaneously maintain multiple candidate solution spaces for parallel exploration; and adjust the search strategy based on feedback results. In practical applications, the optimization strategy adjustment unit 24 can dynamically adjust the area and power consumption trends during the optimization process. Value. For example, if the area is already close to the upper limit of the constraint, but there is still a lot of room for optimization in power consumption, it can be... The value was adjusted from the initial 0.5 to 0.3, increasing the weight of power consumption optimization.

[0098] Circuit decomposition model 25 decomposes the circuit into basic units in a basic circuit unit library. All gates in the entire circuit containing only combinational logic are designated as candidate gates with variable polarity; all gates in the entire circuit containing sequential logic, and gates containing both combinational and sequential logic, are designated as fixed gates with immutable polarity. An iterative strategy is used to find the optimal polarity during the polarity decomposition process. This iterative strategy stops the polarity decomposition if an increase in area or power consumption occurs. In the example of an 8-bit adder, circuit decomposition model 25 might mark 85 combinational logic gates as candidate gates and 15 sequential logic gates as fixed gates. Then, during the polarity optimization process, if a change in the polarity of a candidate gate results in an increase in area exceeding 5% or an increase in power consumption exceeding 3%, the polarity decomposition of that gate will be stopped.

[0099] Logic synthesizer 3 is connected to mixed-polarity synthesizer 2, providing various technology libraries of different polarities to mixed-polarity synthesizer 2 and receiving the final synthesis result from mixed-polarity synthesizer 2. In this invention, logic synthesizer 3 can be a commercially available logic synthesis tool, such as Synopsys' DesignCompiler or Cadence's Genus. For an 8-bit adder, logic synthesizer 3 may receive the polarity assignment result output by mixed-polarity synthesizer 2, and then perform synthesis using the corresponding technology library to generate an optimized netlist.

[0100] The power consumption calculator 4 is connected to the logic synthesizer 3 to provide an area-power tradeoff calculation method. It calculates the power consumption value based on the synthesis results from the logic synthesizer 3 and obtains the area-power tradeoff curve. The power consumption calculation can consider both static and dynamic power consumption.

[0101] ,

[0102] in, Total power consumption (in mW). This refers to static power consumption (in mW). This represents dynamic power consumption (in mW). Static power consumption is mainly caused by leakage current and can be estimated using the following formula:

[0103] ,

[0104] in, Leakage current (unit: mA). This refers to the supply voltage (in volts). Dynamic power consumption is mainly caused by charging / discharging and short-circuit current, and can be estimated using the following formula:

[0105] ,

[0106] in, The activity factor (dimensionless, with a value range of 0 to 1). This is the load capacitance (in pF). This refers to the power supply voltage (in volts). This refers to the operating frequency (in MHz). In practical applications, for an 8-bit adder using a 65nm process node, It's likely between 0.1mW and 0.5mW. At an operating frequency of 500MHz, the power consumption may be between 3mW and 10mW. It ranges from approximately 3.1mW to 10.5mW.

[0107] The constraint converter 5 is connected to the logic synthesizer 3 and is used to convert the user constraint list into a format suitable for the power consumption calculator 4. User constraints typically include area constraints, power consumption constraints, timing constraints, etc. The constraint converter 5 converts these constraints into a format that the system can process internally. For example, the user may specify that the area of ​​an 8-bit adder does not exceed 0.05 mm², the power consumption does not exceed 15 mW, and the timing delay does not exceed 2 ns. The constraint converter 5 will convert these constraints into a normalized representation or a specific format for the system's internal processing.

[0108] Layout analyzer 6 is connected to logic synthesizer 3 and is used to generate circuit layout during the circuit synthesis stage. Layout analyzer 6 can utilize existing layout tools, such as Cadence's Innovus or Synopsys' ICCompiler. For an 8-bit adder, layout analyzer 6 generates a physical layout based on the optimized netlist, calculates the actual area and power consumption, and feeds this information back to the system for evaluation.

[0109] This invention also provides a mixed-polarity RM logic area-power tradeoff analysis method, applicable to the above-mentioned system, such as... Figure 6 As shown, it includes the following steps:

[0110] Step S1: Input Circuit, Define Global Polarity and Circuit Constraints. In this step, the user inputs the netlist of the circuit to be optimized. The system defines the initial global polarity (usually all positive or all negative) and sets conditions such as area constraints, power constraints, and timing constraints. For example, the user might input a Verilog description of a 16-bit multiplier, setting the initial polarity to all positive, the area constraint to 0.2 mm², the power constraint to 50 mW, and the timing constraint to 5 ns.

[0111] Step S2: Decompose the circuit into basic units from the circuit basic unit library. Specifically, circuit decomposition model 25 decomposes the circuit into combinational logic gates (candidate gates, variable polarity) and sequential / mixed logic gates (fixed gates, immutable polarity). For a 16-bit multiplier, approximately 2000 combinational logic gates and 300 sequential logic gates may be identified.

[0112] Step S3: The circuit structure is mapped into a weighted directed graph using the circuit topology mapping engine 21. As mentioned earlier, this process includes netlist parsing, node construction, edge relationship construction, and topology feature extraction. For a 16-bit multiplier, a weighted directed graph with approximately 2300 nodes and 6000 edges will be constructed.

[0113] Step S4: Construct a three-layer topology model using the multi-level homomorphic decision engine 22 and perform polarity decisions at each level. This process includes steps such as hierarchical model construction, homomorphic mapping, and hierarchical decision-making. For a 16-bit multiplier, the macroscopic layer may contain 1 node (the entire multiplier), the mesoscopic layer may contain 16 nodes (partial product generation and accumulation units), and the microscopic layer contains approximately 2300 nodes (all logic gates).

[0114] Step S5: The circuit is spectrally segmented and area-power consumption is co-optimized using the spectral feature co-optimization engine 23. This process includes steps such as spectral representation construction, spectral segmentation, and co-optimization. For a 16-bit multiplier, the circuit may be divided into 8 sub-regions, each containing approximately 300 nodes.

[0115] Step S6: The area-power weights and search strategy are dynamically adjusted by the optimization strategy adjustment unit 24. Based on the optimization progress and feedback results, the system can adjust the area and power weights, and change the search direction and strategy. For example, for a 16-bit multiplier, the initial settings may be... =0.5, during the optimization process, if the area is found to be close to the upper limit of the constraint, it may be reduced. Adjusted to 0.7, increasing the weight of area optimization.

[0116] Step S7: Output the final polarity decision results to the logic synthesizer 3. These results include the polarity assignment scheme for each logic gate. For example, for a 16-bit multiplier, it may be decided that 1500 combinational logic gates will be positive polarity, 500 will be negative polarity, and all sequential logic gates will retain their original polarity.

[0117] Step S8: Calculate the power consumption value and obtain the area-power consumption tradeoff curve using the power consumption calculator 4. The system can generate a series of optimization results based on different area-power consumption weight settings, forming the area-power consumption tradeoff curve. For example, for a 16-bit multiplier, five tradeoff points may be generated, with an area range of 0.15mm² to 0.19mm² and a power consumption range of 40mW to 46mW.

[0118] Step S9: Generate the circuit layout using layout analyzer 6. Finally, the system outputs the optimized circuit layout and related performance report. For a 16-bit multiplier, the layout size is likely 0.17 mm², power consumption is 43 mW, and timing delay is 4.5 ns, satisfying all design constraints.

[0119] In practical applications, the above steps may require multiple iterations until a satisfactory optimization result is achieved or a preset termination condition is met. For example, the system may be set to a maximum of 10 iterations, or terminate when the objective function improves by no more than 1% in three consecutive iterations.

[0120] The hybrid polarity RM logic area-power tradeoff analysis system and method of this invention can be applied to various integrated circuit design scenarios, especially in application areas with strict requirements on area and power consumption, such as IoT devices, wearable devices, and mobile devices. The working process of this invention is illustrated below with a specific application example.

[0121] Suppose an IoT sensor node's digital processing circuit contains approximately 100,000 logic gates, with strict limitations on power consumption and area. The design goal is to minimize power consumption while meeting specific area constraints (e.g., no more than 2 mm²).

[0122] First, the designer inputs the circuit netlist into the system, sets the initial global polarity to positive, and defines the area constraint as 2 mm² and the power consumption constraint as low as possible.

[0123] The system decomposes the circuit into basic units, identifying approximately 80,000 combinational logic gates (candidate gates) and 20,000 sequential / mixed logic gates (fixed gates).

[0124] The circuit topology mapping engine maps the circuit structure into a weighted directed graph containing approximately 100,000 nodes and 300,000 edges. The topology feature extraction unit identifies critical paths and functional modules in the circuit, such as data processing units, control units, and storage units.

[0125] The multi-level homomorphic decision engine constructs a three-layer topology model: the macro layer contains 10 functional modules, the meso layer contains approximately 100 functional units, and the micro layer contains approximately 100,000 logic gates. The hierarchical decision units begin polarity decisions from the macro layer and pass the decisions to the lower layers through homomorphic mapping.

[0126] The spectral feature co-optimization engine constructs a weighted Laplacian matrix and calculates the eigenvalue spectrum and key eigenvectors. The spectral segmentation unit divides the circuit into 20 sub-regions, and the co-optimization unit performs polarity optimization within each sub-region and coordinates the consistency between regions.

[0127] The optimization strategy adjustment unit dynamically adjusts the area-power consumption weights based on the area constraint (2mm²), initially setting the area weight to 0.7 and the power consumption weight to 0.3. As optimization progresses, once the area constraint is met, the system gradually increases the power consumption weight, eventually setting it to an area weight of 0.3 and a power consumption weight of 0.7.

[0128] After multiple iterations and optimizations, the system found a polarity allocation scheme that satisfies the area constraint (1.95 mm²) and minimizes power consumption (approximately 20 mW). Compared to the initial all-positive polarity scheme, power consumption was reduced by approximately 22%, while the area increased by approximately 8%, but both remained within the constraints.

[0129] Finally, the system outputs optimized circuit netlists, layouts, and performance reports for designers to further analyze and integrate.

[0130] This example demonstrates that the hybrid polarity RM logic area-power tradeoff analysis system and method of the present invention can effectively handle the polarity optimization problem of large-scale circuits, achieving the optimal tradeoff between area and power consumption while meeting design constraints.

[0131] In summary, the mixed-polarity RM logic area-power tradeoff analysis system and method provided by this invention achieves efficient and accurate polarity allocation decisions through innovative topology optimization technology, providing a powerful optimization tool for mixed-polarity CMOS integrated circuit design, and has significant theoretical and practical value.

[0132] The embodiments described above are merely illustrative of specific implementations of the present invention, and while the descriptions are detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A mixed-polarity RM logic area-power trade-off analysis system, characterized by, include: A logic library database used to store basic circuit unit libraries of different polarities; A mixed-polarity synthesizer, connected to the logic library database, is used to perform mixed-polarity conversion on the input circuit layout, wherein the mixed-polarity synthesizer includes: A circuit topology mapping engine is used to map circuit structures into weighted directed graphs, which include nodes representing logic gates and edges representing connection relationships. A multi-level homomorphic decision engine, connected to the circuit topology mapping engine, is used to construct a three-level topology model of the circuit, consisting of macroscopic, mesoscopic, and microscopic layers, and to make polarity decisions at each level based on topological homomorphism theory. A spectral feature collaborative optimization engine, connected to the multi-level homomorphic decision engine, is used to perform spectral segmentation of the circuit using spectral theory and achieve area-power consumption collaborative optimization. A logic synthesizer, connected to the mixed-polarity synthesizer, is used to provide process libraries of different polarities to the mixed-polarity synthesizer and receive the final synthesis result from the mixed-polarity synthesizer; A power consumption calculator, connected to the logic synthesizer, is used to provide an area-power consumption tradeoff calculation method, calculate the power consumption value based on the synthesis result of the logic synthesizer, and obtain the area-power consumption tradeoff curve; A constraint converter, connected to the logic synthesizer, is used to convert the user constraint list into a format suitable for the power consumption calculator. A layout analyzer, connected to the logic synthesizer, is used to generate a circuit layout during the circuit synthesis stage. The spectral feature collaborative optimization engine includes: The spectral representation building unit is used to construct a weighted Laplacian matrix based on the circuit topology diagram, and to calculate the eigenvalue spectrum and key eigenvectors. A spectrum segmentation unit, connected to the spectrum representation construction unit, is used to divide the circuit into sub-regions with high polarity correlation using feature vectors; A collaborative optimization unit, connected to the spectrum segmentation unit, is used to define an area-power-weighted objective function, perform polarity optimization in each region, and coordinate consistency between regions. The collaborative optimization unit adopts: Adaptive spectrum segmentation technology dynamically adjusts the segmentation granularity based on circuit characteristics, balancing the size of subproblems and inter-region dependencies. Multi-level spectral filtering technology filters out non-critical spectral features to reduce computation while retaining structurally sensitive critical features. Boundary node processing technology identifies key boundary nodes between regions and designs special boundary processing strategies to ensure optimized coordination and consistency between regions.

2. The hybrid polarity RM logic area-power tradeoff analysis system according to claim 1, characterized in that, The circuit topology mapping engine includes: The netlist parsing unit is used to read the circuit netlist description and identify different types of logic gates and their connections. A node construction unit, connected to the netlist parsing unit, is used to map each logic gate to a node in the graph and mark the node type and initial polarity state. An edge relationship construction unit, connected to the node construction unit, is used to establish directed edges based on signal flow direction and calculate the weight attributes of the edges; The topology feature extraction unit, connected to the edge relationship construction unit, is used to calculate global topology features and identify functional sub-units and critical paths.

3. The hybrid polarity RM logic area-power tradeoff analysis system according to claim 1, characterized in that, The multi-level homomorphic decision engine includes: Hierarchical model building units are used to construct three-layer topological models: macroscopic, mesoscopic, and microscopic. The homomorphic mapping unit, connected to the hierarchical model construction unit, is used to define structure preservation rules, attribute transformation rules, and constraint transfer rules, and to establish inter-layer mapping relationships. The hierarchical decision-making unit, connected to the homomorphic mapping unit, is used to make polarity decisions starting from the macro level, pass the decisions to the lower levels through homomorphic mapping, and handle inter-level conflicts and feedback adjustments.

4. The hybrid polarity RM logic area-power tradeoff analysis system according to claim 1, characterized in that: The weighted directed graph includes a node table and an edge table. The node table stores node ID, gate type, polarity state, fan-in list, fan-out list, and topology attributes. The edge table stores edge ID, source node, target node, signal type, and weight attributes. The gate types of the nodes include combinational logic gates, sequential logic gates, and mixed logic gates; The polarity states include positive polarity, negative polarity, and variable polarity.

5. The hybrid polarity RM logic area-power tradeoff analysis system according to claim 3, characterized in that, The processing flow of the hierarchical decision-making unit includes: At the macro level, global polarity initialization is performed based on functional modules; The meso-level receives the decision results from the macro-level, refines the polarity within the functional units, and resolves polarity conflicts at the interfaces between units. The decision constraints mapped from the meso-level are received at the micro-level, and precise polarity assignment is performed on each logic gate; Through the inter-layer feedback adjustment mechanism, the actual results of the lower layer are fed back to the upper layer, and the upper layer adjusts its decision-making strategy based on the feedback.

6. The hybrid polarity RM logic area-power tradeoff analysis system according to claim 1, characterized in that, The hybrid polarity synthesizer further includes an optimization strategy adjustment unit, connected to the spectral feature co-optimization engine, for: The area-power consumption weights are dynamically adjusted based on the optimization progress. Resource allocation that balances local optimization and global coordination; Simultaneously maintain multiple candidate solution spaces for parallel exploration; Adjust the search strategy based on the feedback.

7. The hybrid polarity RM logic area-power tradeoff analysis system according to claim 6, characterized in that, The hybrid polarity synthesizer also includes a circuit decomposition model, which decomposes the circuit into basic units in the basic unit library of the circuit, and selects all gates in the entire circuit that contain only combinational logic as candidate gates, with variable polarity. All gates in the entire circuit that contain sequential logic, as well as gates that contain both combinational and sequential logic, are treated as fixed gates with immutable polarity. An iterative strategy is used to find the optimal polarity during the polarity decomposition process, wherein the iterative strategy stops the polarity decomposition when an increase in area or power consumption occurs.

8. A method for analyzing the area-power tradeoff of hybrid polarity RM logic, applied to the hybrid polarity RM logic area-power tradeoff analysis system described in claim 7, characterized in that, Includes the following steps: Input circuit, define global polarity and circuit constraints; Decompose the circuit into basic units from the basic circuit unit library; The circuit topology mapping engine maps the circuit structure into a weighted directed graph. The multi-level homomorphic decision engine is used to construct a three-level topological model and perform polarity decisions at each level. The circuit is spectrally segmented and area-power consumption is optimized through the spectral feature collaborative optimization engine. The area-power consumption weight and search strategy are dynamically adjusted through the optimization strategy adjustment unit. The final polarity decision result is output to the logic synthesizer; The power consumption calculator is used to calculate the power consumption value and obtain the area-power consumption trade-off curve. The layout analyzer generates the circuit layout.

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