A low-power error calibration circuit and chip for high-precision ADCs

Abstract

The application discloses a kind of low-power error calibration circuit and chip for high-precision ADC, it is related to analog-digital conversion technical field.The calibration circuit includes ADC core unit, error extraction unit, compensation control unit, analog compensation unit and error evaluation unit.The method is by dividing capacitor array into low bit and high bit redundant capacitor group, using the segmented calibration sequence from low bit to high bit, the mismatch information of each capacitor group is extracted in turn and the compensation weight is updated;During calibration, the relative size of capacitor is detected using charge redistribution principle and comparator, the mismatch rate is calculated, and the weight correction is carried out through analog compensation unit;Error evaluation unit monitors the error after calibration, to ensure that it is within the allowable range;The application simplifies the control logic by segmented calibration, avoids error accumulation, and significantly improves the overall calibration accuracy when calibrating high-bit capacitors based on calibrated low-bit capacitors.

Description

TECHNICAL FIELD

[0001] The present application relates to analog-to-digital conversion technology, and in particular to a low-power error calibration circuit and chip for high-precision ADCs. BACKGROUND

[0002] In the field of analog-to-digital converters (ADCs), especially in high-precision successive approximation ADCs, the mismatch error of the capacitor array is a key factor affecting conversion accuracy and linearity. Due to the inherent bias of semiconductor manufacturing processes, there is a small difference between the actual value and the ideal value of the capacitor, which causes non-linear error in the ADC output code and seriously restricts the performance improvement of high-precision ADCs.

[0003] Prior art, such as Chinese patent application publication CN105811979A, proposes a successive approximation analog-to-digital converter with correction and a correction method thereof. In the patent, a redundant switching is inserted before the normal switching of the capacitor to be corrected. During the redundant switching, the capacitor to be corrected remains connected to the common-mode voltage, while all lower capacitors are simultaneously switched to the same reference voltage as the normal switching direction of the capacitor to be corrected.

[0004] The two results of the comparator after comparing the redundant switching and the normal switching are compared to determine whether the actual weight of the capacitor to be corrected is greater than or less than the sum of the weights of all lower capacitors.

[0005] According to the comparison result, the digital correction code word of the capacitor is updated with a fixed step. After the correction code words of all high capacitors are accumulated, an additional correction DAC is used to convert the analog compensation voltage, which is injected into the main DAC through a coupling capacitor to real-time correct the effective weight of the capacitor in the current conversion.

[0006] Among them, when calibrating the current bit, all lower capacitors are used as the reference for comparison. However, the low capacitors themselves have not been calibrated or are being calibrated, and there is a mismatch error in themselves. This will cause the accumulation and transmission of calibration errors, limiting the final overall calibration accuracy.

[0007] Also, as proposed in Chinese Patent Application Publication No. CN116707527A, a SAR ADC capacitor array calibration method and circuit. In this patent, in calibration mode, let the high-bit capacitor sample the reference voltage, then use all low-bit capacitors to form a sub-AD to accurately quantify this sampled voltage. Through the quantization result of the low-bit capacitor, the error between the actual weight and the ideal weight of the high-bit capacitor is accurately calculated. The weight error of all high-bit capacitors is stored as an error compensation code. In normal working mode, according to the switching state of each capacitor during the conversion process, the error compensation code of the corresponding bit is taken out and summed, and finally added to the original output result of the ADC in the digital domain to obtain the calibrated digital code. Through multiple comparisons and statistics of "0" / "1" probability, combined with the fine quantization weight-probability lookup table, sub-LSB level weight error measurement can be realized.

[0008] It needs to establish a fine quantization lookup table for each high-bit capacitor and perform multiple comparisons, and the calibration period is relatively long.

[0009] Therefore, the prior art needs further improvement. SUMMARY

[0010] Based on the above technical problems, the present application provides a low-power error calibration circuit and chip for high-precision ADC.

[0011] The technical solution of the present application is as follows:

[0012] A low-power error calibration chip for high-precision ADC, comprising:

[0013] Step 1: When any calibration trigger condition is detected, enter calibration state; wherein the capacitor group of the high-precision ADC chip includes a low-bit redundant capacitor group and a high-bit redundant capacitor group;

[0014] Step 2: Extract the mismatch information of each capacitor group of the high-precision ADC chip from low to high, wherein the capacitor array of the low-bit redundant capacitor group is 0 to n / 2 bits, and the capacitor array of the high-bit redundant capacitor group is (n / 2)+1 to n bits;

[0015] Wherein, when performing low-bit redundant capacitor group calibration, use the reference capacitor as the reference reference, and when performing high-bit redundant capacitor group calibration, use the calibrated low-bit redundant capacitor group as the reference reference or the reference capacitor as the reference reference;

[0016] Step 3: Determine whether the calibration weight error is within the maximum allowed error, if yes, go to Step 4; if not, return to Step 2;

[0017] Step 4: The high-precision ADC chip exits the calibration state and enters the working state.

[0018] In the present application, the Step2 includes:

[0019] Step2.1: activate the low-bit redundant capacitor group, measure the actual capacitance value of each capacitor unit of the low-bit redundant capacitor group by alternately switching the capacitor network, and calculate the first capacitance mismatch rate;

[0020] Step2.2: calculate the low-bit compensation weight and update the low-bit calibration state;

[0021] Step2.3: activate the high-bit redundant capacitor group, measure the actual capacitance value of each capacitor unit of the high-bit redundant capacitor group by alternately switching the capacitor network, and calculate the second capacitance mismatch rate;

[0022] Step2.4: calculate the high-bit compensation weight and update the high-bit calibration state;

[0023] According to the number i of bits, the compensation process is executed when i≤n / 2 for low-bit compensation, and when i>n / 2 for high-bit compensation, wherein the first capacitance mismatch rate or the second capacitance mismatch rate The calculation formula is:

[0024] ;

[0025] In the formula, is the actual measured value of the i-bit unit capacitance; is the ideal value of the reference capacitance, represents the relative mismatch rate of the i-bit capacitance calculated;

[0026] According to the first capacitance mismatch rate and the second capacitance mismatch rate, the calculation formula of the low-bit compensation weight and the high-bit compensation weight is:

[0027] ;

[0028] The calculated capacitance mismatch rate is added to the original weight value, represents the initial weight; represents the updated weight.

[0029] A low-power error calibration circuit for a high-precision ADC includes a low-power error calibration method for a high-precision ADC chip, and the low-power error calibration circuit includes:

[0030] An ADC core unit includes a capacitor DAC and a comparator, the capacitor DAC is used to realize accurate allocation and redistribution of electric charge through a capacitor switch network, and convert digital code into corresponding analog voltage value;

[0031] An error extraction unit is used to extract mismatch information of the capacitor array, which includes a low-order redundant capacitor group and a high-order redundant capacitor group.

[0032] The compensation control unit is used to control the calibration process and activate the low-order redundant capacitor group and the high-order redundant capacitor group in segments according to the order from low to high.

[0033] A simulation compensation unit is used to update the capacitor weights based on the mismatch information;

[0034] The error assessment unit is used to assess whether the error after calibration is within the maximum permissible error.

[0035] In this invention, the error extraction unit includes a low-order redundant capacitor, a high-order redundant capacitor, and a mismatch calculator.

[0036] Wherein, the low-order redundant capacitor is from capacitor C0 to capacitor C0. The high-level redundant capacitor is composed of capacitors. to composition.

[0037] In this invention, the capacitor C0 to the capacitor Set up separate switches To switch It is used to switch the connection to the charge detection circuit during error extraction.

[0038] In this invention, the error extraction unit determines the relative size of the capacitance using the charge redistribution principle and a comparator, specifically including:

[0039] Select the capacitor to be measured and reference capacitor ;

[0040] Charge the capacitor under test and the reference capacitor;

[0041] The two capacitors are switched by a switch to share charge, and the voltage after sharing is detected by a comparator.

[0042] The capacitor mismatch rate is calculated based on the shared voltage.

[0043] In this invention, the compensation control unit controls the calibration process according to the state machine sequence, first activating the low-level redundant capacitor bank for error extraction, and then activating the high-level redundant capacitor bank for error extraction.

[0044] In this invention, the error assessment unit calculates the total residual error E to assess the calibration quality. The formula for calculating the total residual error E is:

[0045] ,

[0046] wherein Y t represents an ideal output value, Y c represents an average digital output code converted from multiple sampling of the standard reference voltage under the current compensation weight.

[0047] In the present application, the error evaluation unit compares the total residual error E with a preset maximum allowable error If the comparison result is E , the calibration quality is up to standard, and the calibration state is exited; if the comparison result is E , the calibration quality is not up to standard, and the calibration state is re-entered.

[0048] In the present application, the ADC core unit switches from the working mode to the calibration mode at 0 us, exits the calibration state and re-enters the working state at 251 us,

[0049] wherein,

[0050] During the calibration process, the compensation control unit starts the calibration process at 1 us, the error extraction unit detects the mismatch of the low-bit redundant capacitor group during 25 us to 125 us, and detects the mismatch of the high-bit redundant capacitor group during 126 us to 250 us.

[0051] The low-power error calibration circuit and chip for high-precision ADC implemented by the present application has the following beneficial effects:

[0052] The capacitor array is divided into a low-bit redundant capacitor group and a high-bit redundant capacitor group, and a segmented calibration sequence from low bit to high bit is adopted. When the high-bit capacitor is calibrated, the error of the low-bit capacitor has been preliminarily corrected, thereby providing a more accurate reference for high-bit calibration, and significantly improving the overall calibration precision.

[0053] Compared with the complex control logic of simultaneously calibrating all capacitors, the segmented calibration only processes part of the capacitor groups each time, thereby simplifying the state machine design and timing control. BRIEF DESCRIPTION OF DRAWINGS

[0054] Fig. 1 is a flowchart of the low-power error calibration chip of the present application;

[0055] Fig. 2 is a logic diagram of the low-power error calibration chip of the present application;

[0056] Fig. 3 is a structure diagram of the low-power error calibration circuit of the present application;

[0057] Fig. 4 is a structure diagram of the low-power error calibration circuit of the present application;

[0058] Fig. 5The structural block diagram of the low-power error calibration circuit of the application;

[0059] Fig. 6 The logic block diagram of the low-power error calibration circuit of the application.

[0060] The reference signs are as follows: ADC core unit 10, error extraction unit 20, compensation control unit 30, analog compensation unit 40, and error evaluation unit 50. DETAILED DESCRIPTION

[0061] The technical solutions in the embodiments of the application will be clearly and completely described in the embodiments of the application in combination with the accompanying drawings. Embodiment one

[0062] After the high-precision ADC chip is powered on, initialization operation is performed, and each default parameter is set. The high-precision ADC chip has a working state and a calibration state. The conditions for triggering the calibration state include but are not limited to: the environmental temperature changes by more than a preset threshold; the voltage fluctuation is more than a preset range; the high-precision ADC chip is started or reset to automatically trigger the calibration request; and the calibration request is manually triggered.

[0063] Referring to Figs. 1-2 The first embodiment of the application proposes a low-power error calibration chip for a high-precision ADC, including the following steps:

[0064] Step 1: When any calibration trigger condition is detected, the calibration state is entered; wherein the capacitor group of the high-precision ADC chip includes a low-bit redundant capacitor group and a high-bit redundant capacitor group.

[0065] After the calibration state is entered, dedicated timing resources are allocated for the calibration process, the high-precision ADC chip keeps normal working, and data conversion continues to ensure that the main data flow of the high-precision ADC chip is not affected during the calibration. The calibration period is set to 250 , the calibration period of the low-bit redundant capacitor group is 125 , and the calibration period of the high-bit redundant capacitor group is 125 .

[0066] Step 2: The mismatch information of each capacitor group of the high-precision ADC chip is extracted in segments from low bits to high bits, wherein the capacitor array of the low-bit redundant capacitor group is 0 to n / 2 bits, and the capacitor array of the high-bit redundant capacitor group is (n / 2)+1 to n bits.

[0067] Step 2.1: The low-bit redundant capacitor group is activated, the actual capacitance value of each capacitor unit of the low-bit redundant capacitor group is measured by alternately switching the capacitor network, and the capacitance mismatch rate is calculated;

[0068] Step 2.2: Calculate low-bit compensation weight, update low-bit calibration state;

[0069] Step 2.3: Activate high-bit redundant capacitor group, measure the actual capacitance value of each capacitor unit in the high-bit redundant capacitor group by alternating switching capacitor network, and calculate the capacitance mismatch rate;

[0070] Step 2.4: Calculate high-bit compensation weight, update high-bit calibration state.

[0071] According to the bit number i, the compensation process is controlled. When i≤n / 2, low-bit compensation is performed; when i>n / 2, high-bit compensation is performed, wherein the capacitance mismatch rate The calculation formula is:

[0072] ;

[0073] In the formula, is the actual measured value of the i-bit unit capacitance; is the ideal value of the reference capacitance, which is generally the nominal value. represents the relative mismatch rate of the i-bit capacitance calculated; a positive value indicates that the actual capacitance is larger, and a negative value indicates that the actual capacitance is smaller.

[0074] Due to fluctuations in the semiconductor manufacturing process, the actual value of each capacitor will have a slight deviation from the ideal value, resulting in a decrease in the linearity of high-precision ADC chips and affecting accuracy. If is larger, it means that when using this capacitor for conversion, it will contribute more charge, resulting in a larger value of the output code. If is smaller, the opposite is true, so the weight needs to be increased or decreased to make the final output closer to the ideal value.

[0075] In summary, the calculation formula of low-bit compensation weight and high-bit compensation weight is:

[0076] ;

[0077] The formula represents the full iteration update process, and the calculated capacitance mismatch rate is added to the original weight value, represents the initial weight; represents the updated weight.

[0078] Step 3: Determine whether the error after calibration weight is within the maximum allowed error. If yes, go to Step 4; if no, return to Step 2;

[0079] Step 4: High-precision ADC chip exits calibration state and enters working state.

[0080] In the embodiment, the multi-bit capacitor array is divided into a low-bit redundant capacitor group and a high-bit redundant capacitor group for independent calibration, which is simpler than simultaneously calibrating all capacitors.

[0081] Meanwhile, the weight of the high-bit redundant capacitor group is much larger than that of the low-bit. If the high-bit redundant capacitor group is calibrated first, the mismatch of the low-bit high-bit redundant capacitor group may be disturbed during the calibration of the high-bit.

[0082] In the embodiment, the low-bit to high-bit segmented calibration is adopted, which ensures that the low-bit error is preliminarily corrected when the high-bit is calibrated, thereby providing an accurate reference for the high-bit calibration and improving the overall calibration accuracy.

[0083] Embodiment Two

[0084] Referring to Figs. 3-4 The second embodiment of the present application proposes a low-power error calibration circuit for a high-precision ADC, including an ADC core unit 10, an error extraction unit 20, a compensation control unit 30, an analog compensation unit 40, and an error evaluation unit 50.

[0085] The ADC core unit 10 includes a capacitor DAC and a comparator, and the capacitor DAC is used to realize accurate distribution and redistribution of electric charges through a capacitor switch network, to convert digital codes into corresponding analog voltage values.

[0086] In the embodiment, when the calibration is triggered, the ADC core unit 10 enters the calibration state, and at 0 μs, the ADC core unit 10 switches from the working mode to the calibration mode.

[0087] At 1 μs, the compensation control unit 30 is started, and the calibration process is started.

[0088] The compensation control unit 30 activates the low-bit redundant capacitor group in sequence according to the state machine to perform error extraction.

[0089] From 25 μs to 125 μs, the error extraction unit 20 detects the mismatch of the low-bit redundant capacitor group, calculates the capacitor mismatch rate of each capacitor, and judges whether it is within the allowed range.

[0090] The analog compensation unit 40 updates the weight compensation of the low-bit redundant capacitor group according to the capacitor mismatch rate.

[0091] At 125 μs, the calibration of the low-bit redundant capacitor group is completed, and the state machine switches to the error extraction of the high-bit redundant capacitor group.

[0092] The external error extraction of the high-level redundant capacitor bank is performed from 126μs to 250μs, following the same procedure as the high-level redundant capacitor bank. At 250μs, the calibration of the high-level redundant capacitor bank is completed.

[0093] Error assessment unit 50 monitors the error throughout the calibration process to ensure that the error after calibration is within ±0.5%.

[0094] At 251μs, the ADC core unit 10 exits the calibration state and re-enters the working state.

[0095] Furthermore, in this embodiment, referring to Fig. 5 As shown, the error extraction unit 20 includes a low-order redundant capacitor, a high-order redundant capacitor, and a mismatch calculator.

[0096] Low-order redundant capacitors include capacitors C0, C1, ..., C n / 2 Composition; the high-level redundant capacitor consists of capacitor C n / 2+1 Capacitor C n / 2+2 ..., Capacitor C n Composition. Among them, capacitor C0, capacitor C1, ..., capacitor C n Each switch S0, switch S1, ..., switch S is set independently. n .

[0097] In this embodiment, both the counter and the status register are set to the initial state during error extraction. The capacitance in the capacitor array is then measured, and the relative magnitude of the capacitance is determined using the charge redistribution principle and a comparator.

[0098] Select the capacitor to be measured, Cm, and the reference capacitor, Cn. The reference capacitor is usually a capacitor with a known precise value. Switch S i Connect the selected capacitor to the charge detection circuit. Charge the capacitor under test and the reference capacitor. Connect one end of the capacitor to the reference voltage and the other end to ground or virtual ground; then switch the two capacitors to share charge, and detect the voltage after sharing using a comparator; the comparator output is read, and the relative ratio of the two capacitors is accurately determined through multiple measurements.

[0099] C m C is the actual value of the capacitor being measured. n The theoretical (or known) value of the reference capacitance. Calculated... This is the relative error.

[0100] Specific examples are provided:

[0101] Step 1: Select capacitor C0 and reference capacitor C n ;

[0102] Step 2: Test capacitor C0 and reference capacitor Cn Charging to reference voltage Vref and GND;

[0103] For example, the capacitor C0

[0104] The upper plate is connected to the reference voltage Vref, and the lower plate is connected to GND; the reference capacitor C n The upper plate is connected to GND, and the lower plate is connected to the reference voltage Vref, and then the upper plates of the two capacitors are connected and the lower plates are connected through the switch S0 to share the charge;

[0105] Step 3: The comparator detects the shared voltage Vs, where the shared voltage is Vs = Vref * (C0 / (C0+ C n ), and the value of C0 can be deduced from the shared voltage Vs;

[0106] Step 4: Calculate the capacitance mismatch rate through the voltage after charge sharing and store it to the state register;

[0107] Step 5: Select the next capacitor and repeat steps 2-4 until all low-redundancy capacitor groups are measured.

[0108] Further, in this embodiment, the low-redundancy capacitor group error has been preliminarily corrected. When the high-redundancy capacitor group is measured, it can be based on a more accurate reference. Specifically, the measurement of the high-redundancy capacitor group no longer completely depends on the theoretical value of the reference capacitor, but uses the low-redundancy capacitor group that has been calibrated as a reference standard. In the high-redundancy group calibration process, the low-redundancy capacitor group that has been calibrated is combined with the low-redundancy capacitor group for group measurement, and the mismatch error of the high-redundancy capacitor is accurately extracted through voltage comparison of the charge sharing node.

[0109] In this embodiment, referring to Fig. 6 After the preliminary compensation of the capacitance mismatch is completed, the error evaluation unit 50 performs overall conversion precision evaluation to determine whether it is within the maximum allowed error.

[0110] The total residual error E is calculated as follows:

[0111] ;

[0112] In the formula, Y t represents the ideal output value, that is, the digital output code that should be obtained in theory when the input is a known standard reference voltage, where the standard reference voltage is usually generated by a high-stability bandgap reference source inside the chip. Y c represents the current compensation weight Next, the digital output code is obtained by taking average of the digital codes obtained by sampling and converting the same standard reference voltage for multiple times, wherein the taking average aims to reduce the influence of random noise.

[0113] The calculated total residual error E is compared with the preset maximum allowed error E max . If E≤E max , the calibration quality is up to standard, and the calibration state is exited and the working state is entered. If E>E max , the calibration quality is not up to standard, and the calibration state is entered again.

[0114] The above merely describes the preferred embodiments of the present application and is not used to limit the present application. Any modification, equivalent replacement and improvement within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A low-power error calibration chip for high-precision ADC, characterized in that, Comprise: Step1: When any calibration trigger condition is detected, enter the calibration state; wherein the capacitor group of the high-precision ADC chip includes a low-bit redundant capacitor group and a high-bit redundant capacitor group; Step2: Extract the mismatch information of each capacitor group of the high-precision ADC chip from low to high segment, wherein the capacitor array of the low-bit redundant capacitor group is 0 to n / 2 bits, and the capacitor array of the high-bit redundant capacitor group is (n / 2)+1 to n bits; Wherein, when performing low-bit redundant capacitor group calibration, using the reference capacitor as the reference reference, when performing high-bit redundant capacitor group calibration, using the calibrated low-bit redundant capacitor group as the reference reference or the reference capacitor as the reference reference; Step3: Determine whether the calibration weight error is within the maximum allowable error, if yes, go to Step4; if not, return to Step2; Step4: The high-precision ADC chip exits the calibration state and enters the working state, Wherein, the Step2 includes: Step2.1: Activate the low-bit redundant capacitor group, measure the actual capacitance value of each capacitor unit of the low-bit redundant capacitor group by alternately switching the capacitor network, and calculate the first capacitor mismatch rate; Step2.2: Calculate the low-bit compensation weight and update the low-bit calibration state; Step2.3: Activate the high-bit redundant capacitor group, measure the actual capacitance value of each capacitor unit of the high-bit redundant capacitor group by alternately switching the capacitor network, and calculate the second capacitor mismatch rate; Step2.4: Calculate the high-bit compensation weight and update the high-bit calibration state; The compensation process is controlled according to the bit number i, low-bit compensation is performed when i≤n / 2, and high-bit compensation is performed when i>n / 2, wherein the first capacitance mismatch rate or the second capacitance mismatch rate The calculation formula is: ； In the formula, is the value of the i-th bit unit capacitance actually measured; is the ideal value of the reference capacitance, represents the relative mismatch rate of the i-th bit capacitance calculated; The calculation formula of the low-bit compensation weight and the high-bit compensation weight is respectively calculated according to the first capacitor mismatch rate and the second capacitor mismatch rate: ； The calculated capacitance mismatch rate is added to the original weight value, represents an initial weight; represents an updated weight.

2. A low-power error calibration circuit for a high-precision ADC, comprising a low-power error calibration chip of the high-precision ADC chip of claim 1, characterized in that, The low-power error calibration circuit comprises: An ADC core unit comprising a capacitor DAC and a comparator, the capacitor DAC being used to realize accurate allocation and redistribution of electric charges through a capacitor switch network, and convert digital codes into corresponding analog voltage values; An error extraction unit for extracting mismatch information of a capacitor array, the capacitor array comprising a low-bit redundant capacitor group and a high-bit redundant capacitor group; A compensation control unit for controlling the calibration process and activating the low-bit redundant capacitor group and the high-bit redundant capacitor group in order from low to high; An analog compensation unit for updating the capacitor weight according to the mismatch information; An error evaluation unit for evaluating whether the error after calibration is within the maximum allowable error.

3. The low power error correction circuit of claim 2, wherein, The error extraction unit comprises a low-bit redundant capacitor, a high-bit redundant capacitor, and a mismatch calculator, Wherein, the low bit redundant capacitor is composed of capacitors to capacitor The high bit redundant capacitor is composed of capacitors to capacitor .

4. The low power error correction circuit of claim 3, wherein, The capacitance To the capacitance Respectively independently set switch To the switch For switching the connection charge detection circuit through the switch when error extraction.

5. The low power error correction circuit of claim 4, wherein, The error extraction unit judges the relative size of the capacitor through the principle of charge redistribution and the comparator, specifically including: selecting the measured capacitance and the reference capacitance ; Charge the measured capacitor and the reference capacitor; Switch the two capacitors through the switch to share the electric charges, and detect the shared voltage through the comparator; Calculate the capacitor mismatch rate based on the shared voltage.

6. The low power error correction circuit of claim 2, wherein, The compensation control unit controls the calibration process in sequence according to the state machine, first activates the low-bit redundant capacitor group for error extraction, and then activates the high-bit redundant capacitor group for error extraction.

7. The low power error correction circuit of claim 2, wherein, The error evaluation unit calculates a total residual error E to evaluate the calibration quality, and the total residual error E is calculated according to the following formula: ; wherein, represents an ideal output value, represents an average digital output code converted from multiple sampling of the standard reference voltage under the current compensation weight.

8. The low power error correction circuit of claim 7, wherein, The error evaluation unit compares the total residual error E with a preset maximum allowable error If the calibration quality is up to standard, and the calibration state is exited; if the calibration quality is not up to standard, and the calibration state is reentered.

9. The low power error correction circuit of claim 2, wherein, The ADC core unit switches from working mode to calibration mode at 0us, and exits the calibration state and reenters the working state at 251us, In the calibration process, the compensation control unit starts the calibration process at 1 μs, and the error extraction unit detects the mismatch of the low-redundancy-capacitor group during 25 μs to 125 μs, and detects the mismatch of the high-redundancy-capacitor group during 126 μs to 250 μs.

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