Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel is located on a substrate in the wiring area, a data line set and a shielding piece, the data line set comprises a plurality of first data lines and a plurality of second data lines which are arranged around the function additional area, the first data lines and the second data lines are arranged on different layers, and the shielding piece is arranged between the first data lines and the second data lines. The orthographic projection of at least one of the first data line and the second data line on the substrate is located in the orthographic projection of the shielding piece on the substrate; the shielding piece is arranged between the first data line and the second data line which are arranged in different layers around the function additional area, so that the coupling capacitance between the first data line and the second data line is reduced, the problem that data signals input into the sub-pixels are abnormal is solved, and under the condition that the narrow frame design is achieved, the data transmission efficiency is improved. And the display stability of the display panel is considered.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In current display panels, there is a functional supplementary area. The data cables on the display panel are usually arranged around the functional supplementary area. When the area of ​​the functional supplementary area is large, the length of the data cable is long, which occupies a large space between the display area and the functional supplementary area. If the spacing between the data cables is reduced, the coupling capacitance between the data cables is increased, making it impossible to achieve both the display effect and the narrow bezel design of the display panel. Summary of the Invention

[0003] This application provides a display panel and display device to improve the technical problem that existing display panels cannot simultaneously achieve both display effect and narrow bezel design.

[0004] This application provides a display panel including a functional additional area, a display area, and a wiring area located between the functional additional area and the display area; wherein, the wiring area is provided with:

[0005] Substrate;

[0006] A data line group is disposed on the substrate, the data line group including a plurality of first data lines and a plurality of second data lines disposed around the functional additional area, the first data lines and the second data lines being disposed in different layers;

[0007] A shielding element is disposed on the substrate, and in the thickness direction of the display panel, the shielding element is disposed between the first data line and the second data line;

[0008] Wherein, at least one of the first data line and the second data line has its orthographic projection on the substrate located within the orthographic projection of the shielding member on the substrate.

[0009] Optionally, the shielding component includes a first shielding layer, and the orthographic projections of the first data line and the second data line on the substrate are both located within the orthographic projection of the shielding component on the substrate.

[0010] Optionally, the first shielding layer is laid entirely within the area where the data line is located.

[0011] Optionally, the shielding element includes:

[0012] The first shielding layer includes multiple spaced first shielding lines;

[0013] A second shielding layer is disposed between the first shielding layer and the plurality of second data lines, the second shielding layer comprising a plurality of spaced second shielding lines;

[0014] The first shielding line overlaps with the second data line, and the second shielding line overlaps with the first data line.

[0015] Optionally, the orthographic projections of a plurality of first shielding lines and a plurality of second shielding lines on the substrate are alternately arranged;

[0016] Wherein, the first shielding line and the second data line and the first data line all have overlapping portions; the second shielding line and the first data line and the second data line all have overlapping portions.

[0017] Alternatively, the first shielding line overlaps with the second data line, and the second shielding line overlaps with the first data line.

[0018] Optionally, the line width of the first data line is smaller than the line width of the second data line.

[0019] Optionally, the spacing between two adjacent first data lines is greater than the spacing between two adjacent second data lines.

[0020] Optionally, the orthographic projections of a plurality of first data lines on the substrate and the orthographic projections of a plurality of second data lines on the substrate are alternately arranged.

[0021] Optionally, the wiring area may further include:

[0022] A scan line group is located on the side of the data line group away from the functional supplementary area, and the scan line group includes a plurality of scan control lines arranged around the functional supplementary area;

[0023] Multiple data transmission lines, one of which is connected to a first data line or a second data line;

[0024] The multiple data transmission lines and the multiple scan control lines have overlapping portions.

[0025] Optionally, the display panel further includes:

[0026] Multiple compensation capacitors are disposed on the side of the scan line group away from the functional additional area, and the compensation capacitors are electrically connected to at least one of the multiple scan control lines.

[0027] Optionally, at least a portion of the plurality of compensation capacitors are located within the wiring area.

[0028] Optionally, the display area is provided with a pixel driving circuit, the pixel driving circuit including a switching transistor and a driving transistor electrically connected to the switching transistor, and the input terminal of the switching transistor is electrically connected to the data transmission line;

[0029] The plurality of scan control lines include a plurality of switch control lines, the switch control lines being electrically connected to the gate of the switch transistor, and the switch control lines being electrically connected to the compensation capacitor.

[0030] Optionally, the display panel further includes a first binding area disposed on one side of the display area, the first binding area being provided with a plurality of first binding terminals, the display area being provided with a plurality of data transmission lines, and one of the data transmission lines being connected to a first data line or a second data line;

[0031] The display panel further includes multiple multiplexing circuits, one end of which is electrically connected to a first bonding terminal, and the other end of which is electrically connected to at least two data transmission lines.

[0032] Optionally, the display panel includes a display layer, the display layer including a first body, a second body and a curved portion connecting the first body and the second body, the second body and the first body being disposed opposite to each other, and the first body including the display area;

[0033] The multiple multiplexed circuits are disposed on the first body, and the multiple multiplexed circuits are located between the display area and the curved portion.

[0034] Meanwhile, embodiments of this application provide a display device, which includes the display panel as described above.

[0035] Optionally, the display device includes a first display screen and a second display screen, which are disposed on opposite sides of the display device;

[0036] The area of ​​the first display screen is larger than the area of ​​the second display screen, and the second display screen is the display panel.

[0037] Other features and advantages of this application will be described in detail in the following detailed description section.

[0038] This application reduces the coupling capacitance between the first and second data lines by placing a shield between them in the surrounding functional additional area, thereby improving the problem of abnormal data signals input to the sub-pixel and enhancing the display stability of the display panel while achieving a narrow bezel design. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0041] Figure 1 This is a schematic diagram of the front and back of the display device of this application.

[0042] Figure 2 This is a top view of the display panel of this application.

[0043] Figure 3 This is a first cross-sectional view of the display panel of this application.

[0044] Figure 4 This is a second cross-sectional view of the display panel of this application.

[0045] Figure 5 This is a circuit diagram of the pixel driving circuit in the display panel of this application.

[0046] Figure 6 This is a film layer diagram of the display layer in the display panel of this application.

[0047] Figure 7 for Figure 2 A magnified view of the central region AA.

[0048] Figure 8 for Figure 2 A magnified view of the central region BB.

[0049] Figure 9 This is a first structural diagram of the multiplexing circuit in the display panel of this application.

[0050] Figure 10 This is a second structural diagram of the multiplexing circuit in the display panel of this application.

[0051] Figure 11 for Figure 7 The first type of cross-sectional view of the mid-section MM.

[0052] Figure 12 for Figure 7 The second cross-sectional view of the midsection MM.

[0053] Figure 13 for Figure 7 The third type of cross-section of section MM.

[0054] Figure 14 for Figure 7 A magnified view of the central region CC.

[0055] Figure 15 for Figure 7 A magnified view of the middle region DD. Detailed Implementation

[0056] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0057] Please see Figures 1 to 15 This application proposes a display panel 100, which includes a functional additional area DA, a display area AA, and a wiring area DB located between the functional additional area DA and the display area AA.

[0058] In this embodiment, the wiring area DB is provided with a substrate 110 and a data line group DL and a shield 40 disposed on the substrate 110. The data line group DL includes a plurality of first data lines 531 and a plurality of second data lines 532 disposed around the functional additional area DA. The first data lines 531 and the second data lines 532 are disposed in different layers.

[0059] In this embodiment, the shielding member 40 is disposed between the first data line 531 and the second data line 532 in the thickness direction of the display panel 100.

[0060] In this embodiment, at least one of the first data line 531 and the second data line 532 has its orthographic projection on the substrate 110 located within the orthographic projection of the shielding member 40 on the substrate 110.

[0061] This application improves the problem of abnormal data signals input to sub-pixels by setting a shield 40 between the first data line 531 and the second data line 532 in the surrounding functional additional area DA, thereby reducing the coupling capacitance between the first data line 531 and the second data line 532. This achieves a narrow bezel design while also ensuring the display stability of the display panel 100.

[0062] Please see Figure 1 , Figure 1This is a schematic diagram of the front and back of the display device 200 of this application. The front of the display device 200 is provided with a first display screen A1 (also called the main screen), and the back of the display device 200 is provided with a second display screen A2 (also called the secondary screen) and a rear camera. The size of the second display screen A2 can be smaller than the size of the first display screen A1. The resolution of the second display screen A2 can be less than or equal to the resolution of the first display screen A1. In some scenarios, a high-efficiency 2D graphics subsystem is sufficient to meet the requirements.

[0063] In this embodiment, the size of the first display screen A1 is larger than the size of the second display screen A2.

[0064] In this embodiment, the display performance of the first display screen A1 is higher than that of the second display screen A2. For example, the resolution of the first display screen A1 is greater than or equal to the resolution of the second display screen A2. In some scenarios, a high-efficiency 2D graphics subsystem is sufficient to meet the requirements.

[0065] In this embodiment, the power consumption of the second display screen A2 is lower than that of the first display screen A1.

[0066] In this embodiment, the first display screen A1 and / or the second display screen A2 include a touch layer to support touch functionality.

[0067] In this embodiment, the second display screen A2 can support always-on display and can also customize the display time, notification messages, or custom wallpapers. The camera function can be activated on the second display screen A2, allowing for selfies using the rear camera which offers better image quality.

[0068] In this embodiment, when the first display screen A1 is off, the rear-mounted second display screen A2 can display various push messages from the application; optionally, users can also select the song to listen to by performing a swipe up or down operation on the second display screen A2 while listening to music; optionally, different wallpapers can also be set for the second display screen A2.

[0069] In this embodiment, for an electronic device with dual screens and dual processors, in addition to the first processor controlling the first display screen A1 and the second processor controlling the second display screen A2, the device can also switch between the first processor and the second processor (or between the main operating system and the lightweight operating system) and between the first display screen A1 and the second display screen A2, depending on the specific application scenario. For example, the first processor may run the first application and control the first display screen A1 to display the first application, while the device switches to the second processor running the first application and controlling the second display screen A2 to display the second application, or vice versa, to reduce power consumption.

[0070] In this embodiment, the first processor can be the main processor and the second processor can be the coprocessor; or, the second processor can be independent of the first processor, for example, the first processor and the second processor are implemented by different chips; or, the second processor and the first processor are both integrated on the SoC chip.

[0071] It should be noted that the display panel 100 of this application can be at least one of the first display screen A1 or the second display screen A2. The following description will take the second display screen A2 as an example.

[0072] It should be noted that the structure within the functional supplementary area DA is not limited in the embodiments of this application. The functional supplementary area DA may be normally displayed or not displayed. The film layer within the functional supplementary area DA may be hollowed out or partially hollowed out, or the film layer within the functional supplementary area DA may not be hollowed out. When the functional supplementary area DA can be normally displayed, the pixel arrangement within the functional supplementary area DA may be the same as or different from the pixel arrangement within the display area AA, and the pixel density within the functional supplementary area DA may be the same as or different from the pixel density within the display area AA. When the functional supplementary area DA is not displayed, the functional supplementary area DA may be set to correspond to the corresponding sensor, or embedded in the hole within the functional supplementary area DA.

[0073] In this embodiment, the sensor may include a fingerprint recognition sensor, a camera, a structured light sensor, a time-of-flight sensor, a distance sensor, a light sensor, etc., so that the sensor can collect signals through the functional additional area DA, thereby enabling the display device 200 to realize under-display fingerprint recognition, under-display camera, under-display facial recognition, under-display distance sensing and other under-display sensing solutions.

[0074] In this embodiment, the sensor can be a camera, and the number of functional additional areas (DA) is one or more; for example, please refer to... Figure 2 The display panel 100 may include two additional functional areas DA, namely, two sensors are provided on the second display screen A2.

[0075] It should be noted that, since the second display screen A2 of this application is a secondary screen, the functional additional area DA on the second display screen A2 is used to house the rear camera of the display device 200. At the same time, the area of ​​the second display screen A2 is usually small, while the area of ​​the rear camera is larger than that of a conventional camera, meaning that the rear camera occupies a large area of ​​the second display screen A2. Therefore, the length of the first data line 531 and the second data line 532 surrounding the functional additional area DA is relatively long, resulting in a large coupling capacitance between the first data line 531 and the second data line 532, which causes abnormalities in the data signal input to the sub-pixel. This application improves the problem of abnormal data signals input to the sub-pixel by setting a shield 40 between the first data line 531 and the second data line 532 around the functional additional area DA, thereby reducing the coupling capacitance between the first data line 531 and the second data line 532 and improving the display stability of the display panel 100.

[0076] It should be noted that the display device 200 of this application can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0077] The technical solution of this application is described below with reference to specific embodiments.

[0078] Please see Figure 2 The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. The display area AA contains multiple rows of sub-pixels. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is the area within the display panel 100 used for display functions, and it contains multiple display units that implement its display functions. The non-display area NA may be a border area of ​​the display panel 100, and it may contain functional components that assist the display units within the display area AA in displaying information.

[0079] Please see Figure 2 The first bonding area BD1 is provided with a first bonding terminal, which can be connected to an external circuit. The first bonding terminal TM transmits the signal input from the external circuit to the data trace, thereby driving the display panel 100 to display the image. For example, the first bonding terminal TM can be bonded to a chip, a flip-chip film, or a flexible circuit board to provide power and drive signals to the display panel 100.

[0080] Please see Figure 2When the non-display area NA also includes a second bonding area located on the side of the first bonding area BD1 away from the display area AA, the second bonding area is provided with a second bonding terminal; the first bonding terminal in the first bonding area BD1 can be bonded to the driver chip, and the bonding terminal in the second bonding area can be bonded to the flexible circuit board.

[0081] Please see Figure 3 and Figure 4 The display panel 100 includes a display layer 10, which may include a first body 11, a second body 12, and a curved portion 13 connecting the first body 11 and the second body 12. The second body 12 is bent to the back side of the first body 11. The first body 11 has the display area AA, and the second body 12 has the first binding area BD1 and the second binding area.

[0082] In this embodiment, multiple light-emitting devices (LEDs) and pixel driving circuits (PCs) for driving the LEDs can be arrayed within the display area AA. The pixel driving circuit PC can be mTnC, where m and n are both positive integers, such as 6T1C, 7T1C, 7T2C, 8T2C, 8T3C, 8T4C, etc. This application does not impose specific limitations. The following description uses an 8T2C pixel driving circuit PC as an example.

[0083] Please see Figure 5 The pixel driving circuit PC may include a switching transistor T2A, a driving transistor T1A, a compensation transistor T3A, a first reset transistor T4A, a second reset transistor T7A, a third reset transistor T8A, a first light-emitting transistor T5A, a second light-emitting transistor T6A, a boost capacitor Cboost, and a storage capacitor Cst.

[0084] Please see Figure 5The first electrode of switching transistor T2A is connected to the data transmission line Data, and the second electrode of switching transistor T2A is connected to the first node Aa. The gate of switching transistor T2A receives the switching control signal PscanA. The first electrode of driving transistor T1A is connected to the control node Aa, the second electrode of driving transistor T1A is connected to the control node Ba, and the gate of driving transistor T1A is connected to the control node Qa. The first electrode of compensation transistor T3A is connected to the control node Qa, the second electrode of compensation transistor T3A is connected to the control node Ba, and the gate of compensation transistor T3A receives the compensation control signal NscanA. The first electrode of the first reset transistor T4A receives the first reset signal Vi1, the second electrode of the first reset transistor T4A is connected to the control node Qa, and the gate of the first reset transistor T4A receives the first reset control signal NscanB. The first electrode of the second reset transistor T7A is connected to the second reset signal Vi2, and the second electrode of the second reset transistor T7A is connected to the anode of the light-emitting device. The gate of the third reset transistor T8A receives the second reset control signal PscanB; the first electrode of the third reset transistor T8A receives the third reset signal Vi3, the second electrode of the third reset transistor T8A is connected to the control node Aa, and the gate of the third reset transistor T8A receives the third reset control signal Vi3; the first electrode of the first light-emitting transistor T5A is connected to the high-level source VDD, the second electrode of the first light-emitting transistor T5A is connected to the control node Aa, and the gate of the first light-emitting transistor T5A receives the light-emitting control signal EM; the first electrode of the second light-emitting transistor T6A is connected to the second node Ba, the second electrode of the second light-emitting transistor T6A is connected to the anode of the light-emitting device, and the gate of the second light-emitting transistor T6A receives the light-emitting control signal EM; one end of the boost capacitor Cboost is connected to the control node Qa, and the other end of the boost capacitor Cboost is connected to the gate of the switching transistor T2A; one end of the storage capacitor Cst is connected to the control node Qa, and the other end of the storage capacitor Cst is connected to the high-level source VDD; the cathode of the light-emitting device is connected to the low-level source VSS.

[0085] In this embodiment, the high-level source VDD is used to provide a constant high voltage to the pixel driving circuit PC, and the low-level source VSS is used to provide a constant low voltage to the pixel driving circuit PC.

[0086] In this embodiment, the switching transistor T2A, driving transistor T1A, second reset transistor T7A, third reset transistor T8A, first light-emitting transistor T5A, and second light-emitting transistor T6A can be either P-type transistors or N-type transistors, and the compensation transistor T3A and first reset transistor T4A can be either P-type transistors or N-type transistors. This application uses the example of switching transistor T2A, driving transistor T1A, second reset transistor T7A, third reset transistor T8A, first light-emitting transistor T5A, and second light-emitting transistor T6A being P-type transistors, and compensation transistor T3A and first reset transistor T4A being N-type transistors for illustration.

[0087] In this embodiment, the capacitance of the boost capacitor Cboost is smaller than the capacitance of the storage capacitor Cst. In this embodiment, the storage capacitor Cst is mainly used to maintain the stability of the potential of the third node Qa; therefore, the capacitance of the storage capacitor Cst is relatively large.

[0088] In this embodiment, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain.

[0089] The following is about Figures 3 to 5 The structure of the film layer of the display panel 100 of this application is described.

[0090] Please see Figure 6 The display panel 100 may have a substrate 110 and an array driving layer 120 disposed on the substrate 110 in the display area AA and the non-display area NA. Within the display area AA, the display panel 100 may also have a pixel definition layer (PDL) disposed on the array driving layer 120, a light-emitting device layer disposed on the same layer as the pixel definition layer (PDL), and an encapsulation layer (TFE) disposed on the pixel definition layer (PDL). The film structure within the display area AA is described below.

[0091] In this embodiment, the substrate 110 supports various layers disposed on the substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque substrate, as well as a transparent substrate, can be used.

[0092] In this embodiment, the substrate 110 is used to support the various film layers disposed on the substrate 110. The substrate 110 may be made of an insulating material such as glass, quartz, or polymer resin. The substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials used for flexible substrates include, but are not limited to, polyimide (PI).

[0093] In this embodiment, the substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 stacked together. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material, such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0094] In this embodiment, the first flexible substrate 111 is formed by coating a polymeric material onto a support substrate (not shown) and then curing the polymeric material. The second flexible substrate 113 is formed by coating the first flexible substrate 111 with the same material and then curing the material. The second flexible substrate 113 is formed by the same method as that used to form the first flexible substrate 111. Each of the first flexible substrate 111 and the second flexible substrate 113 may be formed to have a thickness of about 8 μm to about 12 μm. Furthermore, when the substrate 110 is formed from the first flexible substrate 111 and the second flexible substrate 113, pinholes, cracks, etc., formed during the manufacturing of the first flexible substrate 111 are covered by the second flexible substrate 113, thereby removing the aforementioned defects.

[0095] Please see Figure 6 The array driving layer 120 may include multiple thin-film transistors (TFTs). These TFTs may be etch-block type, back-channel etch type, or classified according to the position of the gate and active layer as bottom-gate TFTs, top-gate TFTs, etc., or according to their performance as N-type TFTs, P-type TFTs; among them, Figure 6 The thin-film transistors in the diagram do not represent the structure of any transistor in the display panel 100, but are only schematic diagrams of the various film layers of the display panel 100 in this application.

[0096] Please see Figure 6The array driving layer 120 may include a light-shielding layer 121 disposed on the substrate 110, a buffer layer 122 disposed on the light-shielding layer 121, a first active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, a third gate insulating layer 128 disposed on the second gate layer 127, and a second active layer 128 disposed on the third gate insulating layer 128. 9. A fourth gate insulating layer 130 disposed on the second active layer 129, a third gate layer 131 disposed on the fourth gate insulating layer 130, an inter-insulating layer 132 disposed on the third gate layer 131, a first source-drain layer 133 disposed on the inter-insulating layer 132, a first planarization layer 134 disposed on the first source-drain layer 133, a second source-drain layer 135 disposed on the first planarization layer 134, a second planarization layer 136 disposed on the second source-drain layer 135, a third source-drain layer 137 disposed on the second planarization layer 136, and a third planarization layer 138 disposed on the third source-drain layer 137.

[0097] Please see Figure 6 The light-shielding layer 121 is disposed on the second barrier layer 114. The light-shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The material of the light-shielding layer 121 can be made of black light-shielding material, such as black light-shielding metal or black organic material.

[0098] Please see Figure 6 A buffer layer 122 is disposed on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may be composed of a compound consisting of nitrogen, silicon and oxygen elements, such as a single layer of silicon oxide film or a stacked structure of silicon oxide and silicon nitride.

[0099] Please see Figure 6 The first active layer 123 is disposed on the buffer layer 122, and the second active layer 129 can be disposed on the third gate insulating layer 128. The materials of the first active layer 123 and the second active layer 129 can be one of silicon semiconductor transistors or oxide semiconductor transistors, such as metal oxide semiconductor, amorphous silicon or low temperature polycrystalline silicon. For example, in this application, the material of the first active layer 123 can be low temperature polycrystalline silicon, and the material of the second active layer 129 can be indium gallium zinc oxide semiconductor.

[0100] Please see Figure 6The first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, and the interlayer insulating layer 132 are respectively disposed on the corresponding metal layer or semiconductor layer, and are disposed separately as different metal layers or semiconductor layers; the materials of the first gate insulating layer 124, the second gate insulating layer 126, the interlayer insulating layer 132, the third gate insulating layer 128, the fourth gate insulating layer 130, and the first planarization layer 134 can be inorganic materials composed of silicon oxynitride or organic materials with planarity, or stacked structures such as silicon oxide, silicon nitride, and aluminum oxide.

[0101] Please see Figure 6 The first gate layer 125, the second gate layer 127, and the third gate layer 131 are respectively disposed on the corresponding insulating layers. The materials of the first gate layer 125, the second gate layer 127, and the third gate layer 131 may include metals such as Cr, W, Ti, Ta, Mo, Al, and Cu, or single-layer or multi-layer metal structures composed of at least two of the above metals. For example, the materials may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0102] Please see Figure 6 The first source-drain layer 133 is disposed on the inter-insulating layer 132, the second source-drain layer 135 is disposed on the first planarization layer 134, and the third source-drain layer 137 is disposed on the first planarization layer 136. The materials of the first source-drain layer 133, the second source-drain layer 135, and the third source-drain layer 137 may include metals such as Cr, W, Ti, Ta, Mo, Al, and Cu, or single-layer or multi-layer metal structures composed of at least two of the above metals. For example, the materials may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0103] Please see Figure 6 The first planarization layer 134, the second planarization layer 136, and the second planarization layer 138 are laid in their entirety, or only in the display area AA and part of the non-display area NA, to ensure the flatness of the film layer of the array driving layer 120. The materials of the first planarization layer 134, the second planarization layer 136, and the second planarization layer 138 can be inorganic materials composed of silicon oxynitride or organic materials with flatness, such as flexible materials such as polytetrafluoroethylene.

[0104] Please see Figure 6The light-emitting device layer may further include an anode layer AN disposed on the planarization layer 158, a light-emitting layer EL disposed on the anode layer AN, and a cathode layer CA disposed on the light-emitting layer EL. The anode layer AN includes multiple anodes, the pixel definition layer PDL includes multiple pixel openings corresponding one-to-one with the multiple anodes, and each pixel opening exposes the upper surface of an anode. The light-emitting layer EL may include multiple light-emitting pixels corresponding one-to-one with the multiple anodes.

[0105] It should be noted that the number of gate layers and source / drain layers in this application can be adjusted according to the specific type of pixel driving circuit and gate driving circuit. For example, the number of gate layers and source / drain layers can both be 1 to 3; in this application, the number of gate layers and source / drain layers is 3.

[0106] It should be noted that, Figure 6 The film structure is a combination of low-temperature polycrystalline silicon semiconductor and oxide semiconductor. If only one of the low-temperature polycrystalline silicon semiconductor and oxide semiconductor exists in the pixel driving circuit, the corresponding active layer and insulating layer can be removed.

[0107] Please see Figure 3 The display panel 100 also includes a polarizer 310, a cover layer 320, and an optical adhesive layer 330 disposed between the polarizer 310 and the cover layer 320. The cover layer 320 is bonded to the polarizer 310 layer through the optical adhesive layer 330.

[0108] In this embodiment, a ring of ink layer 340 may be provided on the side of the cover plate layer 320 near the optical adhesive layer 330. The ink layer 340 can be used to cover the peripheral area of ​​the display panel 100, so the ink layer 340 can define the edge area of ​​the display panel 100.

[0109] Please see Figure 3 The display panel 100 also includes a composite support layer 20 disposed between the first body 11 and the second body 12. The composite support layer 20 includes a first back plate 21, a second back plate 22 and a functional support layer 23 disposed between the first back plate 21 and the second back plate 22. The first back plate 21 is in contact with the first body 11 and the second back plate 22 is in contact with the second body 12.

[0110] In this embodiment, the materials of the first back plate 21 and the second back plate 22 may include polyethylene terephthalate, etc.

[0111] In this embodiment, the functional support layer 23 may include a heat dissipation buffer layer 231 (Super Clean Foam, SCF) and a filler adhesive layer 232 (Stiffener, STF). The filler adhesive layer 232 is disposed between the second back plate 22 and the heat dissipation buffer layer 231. The heat dissipation buffer layer 231 may include a mesh adhesive layer, a foam layer and a metal layer stacked in sequence, or a mesh adhesive layer, a foam layer, a polyimide layer and a metal layer stacked in sequence.

[0112] Please see Figure 4 For foldable display devices, the functional support layer 23 may include a stacked structure of a buffer layer, a rigid layer and a filling adhesive layer. The material of the buffer layer may be foam or polyimide, and the material of the rigid layer may be stainless steel, titanium metal or carbon fiber, etc. At the same time, a heat dissipation material such as graphite or copper may be provided on the side of the rigid layer away from the first back plate.

[0113] In this embodiment, the boundary of the heat dissipation buffer layer 231 near the bend 13 is recessed relative to the boundary of the first back plate 21 near the bend 13, and the boundary of the filling adhesive layer 232 near the bend 13 is recessed relative to the boundary of the second back plate 22 near the bend 13.

[0114] In this embodiment, the display panel 100 further includes a protective adhesive layer 350 disposed on the display layer 10, the protective adhesive layer 350 covering the curved portion 13 and part of the first body 11 and part of the second body 12.

[0115] In this embodiment, the material of the protective adhesive layer 350 can be a UV-curable adhesive.

[0116] It should be noted that the technical solution of this application is applicable to both non-foldable display devices and foldable display devices; for non-foldable display devices, such as those described in this application... Figure 3 The middle cover layer 320 can be a rigid cover, for foldable display devices, such as... Figure 4 The cover layer 320 can be ultra-thin glass UTG and a protective layer PW with built-in optical adhesive.

[0117] It should be noted that, in Figure 3 and Figure 4 In the structure, the driver chip IC can be directly bonded to the second body 12 of the display layer 10, and the end of the second body 12 away from the bending part 13 is bonded to the flexible circuit board FPC. The flexible circuit board FPC can be connected to the heat dissipation buffer layer 231 or the rigid layer in the composite support layer 20 through pressure-sensitive adhesive PSA.

[0118] It should be noted that this application uses the aforementioned display panel as an example. Figure 3 The structure in the example will be used for illustration.

[0119] Please see Figure 7 The display panel 100 has multiple data transmission lines 50 and multiple scan control lines SLa arranged in a crisscross pattern in the display area AA. Due to the setting of the functional supplementary area DA, the data transmission lines 50 and the scan control lines SLa need to be arranged around the functional supplementary area DA.

[0120] Please see Figure 8 The display panel 100 also includes a plurality of multiplexing circuits MUX, which are disposed between the display area AA and the first binding area BD1. One end of each multiplexing circuit MUX is electrically connected to a first binding terminal, and the other end of each multiplexing circuit MUX is electrically connected to at least two data transmission lines 50.

[0121] It should be noted that the display panel 100 is a smaller sub-screen in the display device 200. In order to ensure that the display panel 100 has a certain resolution, the display panel 100 needs to be equipped with a large number of data lines. However, the smaller sub-screen cannot accommodate a larger driver chip IC, resulting in the number of first bonding terminals in the first bonding area BD1 being less than the number of data transmission lines 50. The multiplexing circuit MUX of this application can enable one first bonding terminal to be adapted to at least two data transmission lines 50, thus meeting the requirements of the data transmission lines 50 even with a small number of terminals.

[0122] Please see Figure 9 The multiplexing circuit MUX includes a first multiplexing transistor TX1 and a second multiplexing transistor TX2. The first electrode of the first multiplexing transistor TX1 is electrically connected to the first data line 531, and the first electrode of the second multiplexing transistor TX2 is electrically connected to the second data line 532. The second electrodes of both the first multiplexing transistor TX1 and the second multiplexing transistor TX2 are connected to the data line.

[0123] It should be noted that the first electrode and the second electrode can be different from each other, which are the source or drain of the transistor.

[0124] Please see Figure 9 The gates of the first multiplexed transistor TX1 and the second multiplexed transistor TX2 are both connected to the multiplexing control line CTL; and the first multiplexed transistor TX1 and the second multiplexed transistor TX2 are either N-type transistors or P-type transistors, which are different from each other.

[0125] For example, in Figure 9In the structure, the first multiplexed transistor TX1 is an N-type transistor, and the second multiplexed transistor TX2 is a P-type transistor. When the multiplexing control line CTL outputs a high level, the first multiplexed transistor TX1 is turned on, and the second multiplexed transistor TX2 is turned off, and the first bonding terminal transmits a data signal to the first data line 531; when the multiplexing control line CTL outputs a low level, the first multiplexed transistor TX1 is turned off, and the second multiplexed transistor TX2 is turned on, and the first bonding terminal transmits a data signal to the second data line 532.

[0126] Please see Figure 10 The gates of the first multiplexed transistor TX1 and the second multiplexed transistor TX2 are connected to two different multiplexing control lines CTL, and the first multiplexed transistor TX1 and the second multiplexed transistor TX2 are either N-type transistors or P-type transistors.

[0127] For example, the gate of the first multiplexed transistor TX1 is connected to the first multiplexing control line CTL1, and the gate of the second multiplexing transistor TX2 is connected to the second multiplexing control line CTL2. Both the first multiplexing transistor TX1 and the second multiplexing transistor TX2 are N-type transistors. When the first multiplexing control line CTL1 outputs a high level and the second multiplexing control line CTL2 outputs a low level, the first multiplexing transistor TX1 is turned on, and the second multiplexing transistor TX2 is turned off, and the first bonding terminal transmits a data signal to the first data line 531. When the first multiplexing control line CTL1 outputs a low level and the second multiplexing control line CTL2 outputs a high level, the first multiplexing transistor TX1 is turned off, and the second multiplexing transistor TX2 is turned on, and the first bonding terminal transmits a data signal to the second data line 532.

[0128] Please see Figure 8 Due to the limitations of the space wiring and narrow bezel of the display panel 100, the multiple multiplexing circuits MUX of this application are disposed on the first body 11, and the multiple multiplexing circuits MUX are located between the display area AA and the curved portion 13.

[0129] In this embodiment, since multiple signal lines transmitting different signals are provided between the multiple multiplexing circuits MUX and the display area AA, the wiring space for the first data line 531 and the second data line 532 connected to the multiplexing circuits MUX is small. This application allows the first data line 531 and the second data line 532 located between the multiple multiplexing circuits MUX and the display area AA to be disposed on different layers. For example, the first data line 531 can be made of at least one of the materials of the first gate layer 125, the second gate layer 127, or the third gate layer 131, and the second data line 532 can be made of at least one of the materials of the first source-drain layer 133, the second source-drain layer 135, or the third source-drain layer 137.

[0130] In this embodiment, for the area between the multiple multiplexed circuits MUX and the display area AA, the first data line 531 can be made of the material of the first gate layer 125, and the second data line 532 can be made of the material of the third source-drain layer 137.

[0131] In this embodiment, due to the limitation of the narrow bezel, one of the data transmission lines 50 of this application may include a first fan-out line 510, a second fan-out line 520, and a data connection line 530. The first fan-out line 510 extends along a first direction X, and the second fan-out line 520 and the data connection line 530 both extend along a second direction Y. The first fan-out line 510 and the second fan-out line 520 are located within the display area AA. A portion of the data connection line 530 is located within the display area AA, and another portion of the data connection line 530 is located within the wiring area DB and the non-display area NA. The data connection line 530 is electrically connected to a pixel driving circuit PC arranged along the second direction Y.

[0132] This application moves the first fan-out line 510 and the second fan-out line 520, which were originally located in the non-display area NA, to the display area AA, thereby reducing the space occupied by the first fan-out line 510 and the second fan-out line 520 in the non-display area NA and realizing the narrow bezel design of the display panel 100.

[0133] In this embodiment, the first fan-out line 510 can be made of the material of the second source-drain layer 135, and the second fan-out line 520 and the data connection line 530 can be made of the material of the third source-drain layer 137.

[0134] In this embodiment, the first data line 531 and the second data line 532 located between the multiple multiplex circuits MUX and the display area AA can both be connected to a second fan-out line 520. That is, in this application, the first data line 531 in this area needs to be switched from the first gate layer 125 to the second fan-out line 520 of the third source-drain layer 137, and then switched from the third source-drain layer 137 to the first fan-out line 510 of the second source-drain layer 135 in the display area AA, and finally switched from the second source-drain layer 135 to the data connection line 530 of the third source-drain layer 137.

[0135] In this embodiment, the first data line 531 and the second data line 532 located in the wiring area DB are part of the data connection line 530. That is, in order to achieve a narrow bezel design, this application replaces part of the data connection line 530 located in the third source-drain layer 137 with the lower metal layer. For example, the first data line 531 located in the wiring area DB can be made of at least one of the materials of the first gate layer 125, the second gate layer 127 or the third gate layer 131.

[0136] In this embodiment, within the wiring region DB, the first data line 531 can be made of the material of the first gate layer 125, and the second data line 532 can be made of the material of the third source-drain layer 137.

[0137] Please see Figures 11 to 13 , Figures 11 to 13 for Figure 7 Different cross-sectional views of the mid-section MM.

[0138] Please see Figure 11 The orthographic projections of multiple first data lines 531 on the substrate 110 and multiple second data lines 532 on the substrate 110 are alternately arranged, that is, the multiple first data lines 531 and multiple second data lines 532 located in the wiring area DB of this application can be arranged non-overlappingly.

[0139] Since the coupling capacitance between the first data line 531 and the second data line 532 is positively correlated with the area of ​​the first data line 531 and the second data line 532 facing each other, in order to reduce the coupling capacitance between them, this application arranges the plurality of first data lines 531 and the plurality of second data lines 532 to be non-overlapping.

[0140] In this embodiment, the linewidth of the first data line 531 is smaller than the linewidth of the second data line 532. The first data line 531 can be fabricated from the material of the first gate layer 125, and the second data line 532 can be fabricated from the material of the third source / drain layer 137. The material of the first gate layer 125 is typically molybdenum, and the material of the third source / drain layer 137 is typically titanium-aluminum-titanium. Therefore, the first data line 531 can be fabricated as a signal line with a smaller linewidth, and the second data line 532 can be fabricated as a signal line with a larger linewidth.

[0141] In this embodiment, since the line width of the first data line 531 is smaller than the line width of the second data line 532, the spacing between two adjacent first data lines 531 is greater than the spacing between two adjacent second data lines 532.

[0142] Please see Figure 11 The shielding member 40 includes a first shielding layer 410, and the orthographic projections of the first data line 531 and the second data line 532 on the substrate 110 are both located within the orthographic projection of the shielding member 40 on the substrate 110.

[0143] In this embodiment, the first shielding layer 410 may be made of the material of the first source-drain layer 133.

[0144] In this embodiment, within the area where the data line is located, the first shielding layer 410 may include a plurality of spaced first shielding lines 411, and two adjacent first shielding lines 411 may overlap with the first data line 531 and the second data line 532, respectively.

[0145] Please see Figure 11 In the area where the data line is located, the first shielding layer 410 is laid out in its entirety to completely isolate the first data line 531 and the second data line 532.

[0146] In this embodiment, the first shielding layer 410 may also be made of the material of the second source-drain layer 135, and the first shielding layer 410 is laid in the entire wiring area DB.

[0147] Please see Figure 12 and Figure 13 , Figure 12 and Figure 13 and Figure 11Similar to or identical to each other, but differing in that: the shielding element 40 may include a first shielding layer 410 and a second shielding layer 420, the second shielding layer 420 being disposed between the first shielding layer 410 and a plurality of second data lines 532, the first shielding layer 410 including a plurality of spaced first shielding lines 411, the second shielding layer 420 including a plurality of spaced second shielding lines 421, the first shielding lines 411 having overlapping portions with the second data lines 532, and the second shielding lines 421 having overlapping portions with the first data lines 531.

[0148] In this embodiment, the first shielding layer 410 may be made of the material of the first source-drain layer 133, and the second shielding layer 420 may be made of the material of the second source-drain layer 135.

[0149] In this embodiment, the orthographic projections of a plurality of first shielding lines 411 and a plurality of second shielding lines 421 on the substrate 110 are alternately arranged. Since the thickness of the first source-drain layer 133 and the second source-drain layer 135 is relatively large, if the first shielding lines 411 and the second shielding lines 421 are overlapped, the planarization layer will not be able to level the source-drain layer. In order to ensure the flatness of the film layer, this application allows the plurality of first shielding lines 411 and the plurality of second shielding lines 421 to be arranged without overlap.

[0150] For example, please see Figure 12 The first shielding line 411 overlaps with the second data line 532, and the second shielding line 421 overlaps with the first data line 531. The arrangement of the first shielding line 411 and the second shielding line 421 can reduce the coupling capacitance between the first data line 531 and the second data line 532, improve the problem of abnormal data signals input to the sub-pixel, improve the accuracy of the data signals received by the pixel driving circuit PC, and further improve the display stability of the display panel 100.

[0151] It should be noted that, due to the large thickness of the first source-drain layer 133 and the second source-drain layer 135, if the first shielding line 411 and the second shielding line 421 are overlapped, the planarization layer cannot level the source-drain layer. Therefore, this application makes the first shielding line 411 located in the first source-drain layer 133 overlap with the second data line 532, and the second shielding line 421 located in the second source-drain layer 135 overlap with the first data line 531. That is, the first shielding line 411 and the second data line 532 have a first planarization layer 134 and a second planarization layer 136. The double planarization layer ensures the planarization of the film layer in the area corresponding to the first shielding line 411.

[0152] For example, please see Figure 13The first shielding line 411 and the second data line 532 and the first data line 531 all have overlapping portions, and the second shielding line 421 and the first data line 531 and the second data line 532 all have overlapping portions.

[0153] In this embodiment, since there is a partial oblique capacitance between the first data line 531 and the second data line 532, this application can shift the first shielding line 411 to the area between two adjacent first data lines 531 and the second shielding line 421 to the area between two adjacent second data lines 532.

[0154] Please see Figure 14 A first adapter electrode 610, a second adapter electrode 620, a third adapter electrode 630, and a fourth adapter electrode 640 are provided on the side of the data line group DL near the scan line group SL. One end of the first adapter electrode 610 is electrically connected to the first data line 531, and the other end of the first adapter electrode 610 is electrically connected to a data connection line 530. One end of the second adapter electrode 620 is electrically connected to the first shielding line 411, and the other end of the second adapter electrode 620 is electrically connected to a high potential line VDD. One end of the third adapter electrode 630 is electrically connected to the second shielding line 421, and the other end of the third adapter electrode 630 is electrically connected to another high potential line VDD. One end of the fourth adapter electrode 640 is electrically connected to the second data line 532, and the other end of the fourth adapter electrode 640 is electrically connected to another data connection line 530.

[0155] In this embodiment, both the data connection line 530 and the high potential line VDD are made of the material of the second source-drain layer 135.

[0156] In this embodiment, this application Figures 11 to 13 The multiple first shielding lines 411 and multiple second shielding lines 421 can be electrically connected to the high potential line VDD that transmits high potential signals, so as to shield the first data line 531 and the second data line 532.

[0157] Please see Figure 7 The wiring area DB is provided with a data line group DL and a scan line group SL. The data line group DL is located close to the functional supplementary area DA, and the scan line group SL is located on the side of the data line group DL away from the functional supplementary area DA.

[0158] In this embodiment, the scan line group SL includes a plurality of scan control lines SLa arranged around the functional additional area DA, and the plurality of data connection lines 530 and the plurality of scan control lines SLa have overlapping portions.

[0159] Because the data connection line 530 overlaps with the scan control line SLa, there is a coupling capacitance between the data connection line 530 and the scan control line SLa, which causes the scan control signal transmitted by the scan control line SLa to be affected to a certain extent.

[0160] Please see Figure 15 The display panel 100 also includes a plurality of compensation capacitors 70 disposed on the side of the scan line group SL away from the functional additional area DA, and the compensation capacitors 70 are electrically connected to at least one of the plurality of scan control lines SLa.

[0161] In this embodiment, one end of the compensation capacitor 70 is electrically connected to the scan control line SLa, and the other end of the compensation capacitor 70 can be connected to the high potential line VDD. The capacitance in the compensation capacitor 70 can compensate for the control signal transmitted by the scan control line SLa, so as to maintain the stability of the control signal transmitted by the scan control line SLa.

[0162] In this embodiment, at least a portion of the plurality of compensation capacitors 70 are located within the wiring area DB. For example, see [link to documentation]. Figure 7 A portion of the plurality of compensation capacitors 70 is located within the wiring area DB, and another portion of the plurality of compensation capacitors 70 is located within the display area AA. That is, the plurality of compensation capacitors 70 can be located in the area near the boundary between the wiring area DB and the display area AA.

[0163] In this embodiment, the plurality of scan control lines SLa include a plurality of switch control lines Pscan1, the switch control lines Pscan1 are electrically connected to the gate of the switch transistor T2A, and the switch control lines Pscan1 are electrically connected to the compensation capacitor 70.

[0164] Please see Figure 5 The switch control line Pscan1 is used to transmit the switch control signal PscanA, and the input terminal of the switch transistor T2A is electrically connected to the data connection line 530. That is, the data signal transmitted by the data connection line 530 needs to be transmitted to the pixel driving circuit PC through the switch transistor T2A. This application maintains the stability of the switch control signal PscanA transmitted by the switch control line Pscan1 by electrically connecting the switch control line Pscan1 and the compensation capacitor 70, thus ensuring the accuracy of the data signal received by the first node A.

[0165] Please see Figure 15The first gate layer 125 includes a second reset control line Pscan2, a light emission control line EM1, a first electrode 701 of the compensation capacitor 70, and a switch control line Pscan1 arranged at intervals along the second direction Y. The first gate layer 125 also includes a first compensation connection line 710 connecting two adjacent first electrodes 701. The first compensation connection line 710 extends along the first direction X and is disposed between the light emission control line EM1 and the switch control line Pscan1.

[0166] Please see Figure 15 The second gate layer 127 includes the second electrode 702 of the compensation capacitor 70. The second electrode 702 is disposed opposite to the first electrode 701, and a connection hole HL is provided on the second electrode 702.

[0167] Please see Figure 15 The first source-drain layer 133 includes a second compensation connection line 720 and a third compensation connection line 730. The second compensation connection line 720 extends along a first direction X, and the third compensation connection line 730 extends along a second direction Y. Two adjacent second plates 702 are electrically connected through the second compensation connection line 720, and the second plates 702 can be electrically connected to the high potential line VDD in the second source-drain layer 135. One end of the third compensation connection line 730 is connected to the switch control line Pscan1, and the other end of the third compensation connection line 730 passes through the connection hole HL and is connected to the first plate 701.

[0168] This application utilizes the first plate of the storage capacitor in the original pixel driving circuit PC to set the first plate 701 of the compensation capacitor 70, and the second plate of the storage capacitor in the original pixel driving circuit PC to set the second plate 702 of the compensation capacitor 70. A third compensation connection line 730 connecting the switch control line Pscan1 and the first plate 701 is prepared by the first source-drain layer 133 material, so that the first plate 701 of the compensation capacitor 70 is electrically connected to the switch control line Pscan1, and the second plate 702 of the compensation capacitor 70 is electrically connected to the high potential line VDD. This maintains the stability of the switch control signal PscanA transmitted by the switch control line Pscan1, ensures the accuracy of the data signal received by the first node A, and improves the display stability of the display panel 100.

[0169] This application provides a display panel and a display device. The display panel includes a substrate, a data line group, and a shielding member located within a wiring area. The data line group includes a plurality of first data lines and a plurality of second data lines arranged around a functional additional area. The first data lines and second data lines are arranged in different layers. The shielding member is disposed between the first data lines and the second data lines. The orthographic projection of at least one of the first data lines and the second data lines on the substrate is located within the orthographic projection of the shielding member on the substrate. By providing a shielding member between the first data lines and the second data lines arranged around the functional additional area, this application reduces the coupling capacitance between the first data lines and the second data lines, improves the problem of abnormal data signals input to the sub-pixels, and enhances the display stability of the display panel.

[0170] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0171] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0172] In the above embodiments, the structures shown in the accompanying drawings are only schematic diagrams, and the specific structure of the display panel of this application is based on the description in the specification.

[0173] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0174] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized by, The display panel comprises a functional additional area, a display area, and a wiring area located between the functional additional area and the display area; wherein the wiring area is provided with: a substrate substrate; a data line group provided on the substrate substrate, the data line group comprising a plurality of first data lines and a plurality of second data lines arranged around the functional additional area, the first data lines and the second data lines being arranged in different layers; a shielding member provided on the substrate substrate, the shielding member being arranged between the first data lines and the second data lines in the thickness direction of the display panel; wherein the orthographic projection of at least one of the first data lines and the second data lines on the substrate substrate is located within the orthographic projection of the shielding member on the substrate substrate.

2. The display panel of claim 1, wherein, The shielding member comprises a first shielding layer, and the orthographic projection of at least one of the first data lines and the second data lines on the substrate substrate is located within the orthographic projection of the shielding member on the substrate substrate.

3. The display panel of claim 2, wherein, The first shielding layer is laid in the entire area of the data lines.

4. The display panel of claim 1, wherein, The shielding member comprises: a first shielding layer comprising a plurality of first shielding lines arranged at intervals; a second shielding layer arranged between the first shielding layer and the plurality of second data lines, the second shielding layer comprising a plurality of second shielding lines arranged at intervals; wherein the first shielding lines and the second data lines have overlapping portions, and the second shielding lines and the first data lines have overlapping portions.

5. The display panel of claim 4, wherein, The orthographic projections of the plurality of first shielding lines and the plurality of second shielding lines on the substrate substrate are arranged alternately; wherein the first shielding lines and the second data lines and the first data lines all have overlapping portions, and the second shielding lines and the first data lines and the second data lines all have overlapping portions; alternatively, the first shielding lines overlap the second data lines, and the second shielding lines overlap the first data lines.

6. The display panel of any one of claims 1 to 5, wherein, The line width of the first data lines is smaller than the line width of the second data lines.

7. The display panel of claim 6, wherein, The distance between two adjacent first data lines is greater than the distance between two adjacent second data lines.

8. The display panel of any one of claims 1 to 5, wherein, The orthographic projections of the plurality of first data lines on the substrate substrate and the orthographic projections of the plurality of second data lines on the substrate substrate are arranged alternately.

9. The display panel of any one of claims 1 to 5, wherein, The wiring area is further provided with: a scan line group provided on the side of the data line group away from the functional additional area, the scan line group comprising a plurality of scan control lines arranged around the functional additional area; a plurality of data transmission lines, one data transmission line being connected to one first data line or one second data line; wherein the plurality of data transmission lines and the plurality of scan control lines have overlapping portions.

10. The display panel of claim 9, wherein, The display panel further comprises: a plurality of compensation capacitors provided on the side of the scan line group away from the functional additional area, the compensation capacitors being electrically connected to at least one of the plurality of scan control lines.

11. The display panel of claim 10, wherein, At least part of the plurality of compensation capacitors is located in the wiring area.

12. The display panel of claim 10, wherein, The display area is provided with a pixel driving circuit, the pixel driving circuit comprising a switching transistor and a driving transistor electrically connected to the switching transistor, the input end of the switching transistor being electrically connected to the data transmission line; The plurality of scanning control lines include a plurality of switch control lines, the switch control lines are electrically connected with the gate of the switch transistor, and the switch control lines are electrically connected with the compensation capacitor.

13. The display panel of any one of claims 1 to 5, wherein, The display panel further comprises a first binding area on one side of the display area, a plurality of first binding terminals are arranged in the first binding area, a plurality of data transmission lines are arranged in the display area, and one data transmission line is connected with one first data line or one second data line. The display panel further comprises a plurality of multiplexing circuits, one end of the multiplexing circuit is electrically connected with one first binding terminal, and the other end of the multiplexing circuit is electrically connected with at least two data transmission lines.

14. The display panel of claim 13, wherein, The display panel comprises a display layer, the display layer comprises a first body, a second body and a bending part connecting the first body and the second body, the second body and the first body are oppositely arranged, and the first body comprises the display area. The plurality of multiplexing circuits are arranged on the first body, and the plurality of multiplexing circuits are located between the display area and the bending part.

15. A display device comprising: The display device comprises a first display screen and a second display screen, the first display screen and the second display screen are arranged on opposite sides of the display device.

16. The display device of claim 15, wherein, The area of the first display screen is larger than the area of the second display screen, and the second display screen is the display panel. ​

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