Detection system for power switches

Abstract

The application discloses a detection system for a power switch. The detection system comprises a bias circuit, an operational amplifier, a sampling MOSFET, a capacitor and a current mirror circuit. The detection system does not need to use a single integrated or customized power tube, and accurately provides a current proportional to the current flowing through the power switch to be detected, so that the system can perform sampling, protection and other functions.

Description

Technical Field

[0001] This invention relates to electronic circuits, and more specifically to a detection system for power switches. Background Technology

[0002] A smart power switch is an integrated circuit that integrates power devices, internal drive and protection circuits, etc., onto a single chip. It has important applications in industrial control, automotive electronics, and avionics, and is significant for the miniaturization and intelligentization of related equipment. In some applications of smart power switches, there is a need to detect the current flowing through the switch to understand the overall operating status of the device; therefore, current detection is an important function of smart power switches in certain applications.

[0003] Figure 1 This is a schematic diagram of the circuit structure of a common current detection circuit 50. Figure 1 As shown, the prior art uses a small portion of the cells 52 of the main power transistor 51 to be detected as a sampling transistor. A certain gate voltage is applied to the sampling transistor 53 through the negative feedback clamping effect of the operational amplifier 53, so that its drain voltage is equal to the drain voltage of the main power transistor 51, thereby outputting a detection current Imon that is proportional to the main power transistor.

[0004] This current sensing circuit boasts advantages such as high output accuracy, good linearity, and simple circuit structure. However, it is only suitable for applications requiring monolithic integration or custom power transistors. Monolithic integration refers to integrating the main power transistor, sampling transistor, and operational amplifier control circuitry onto a single chip, where current sensing is implemented from the chip design stage. This current sensing method requires stringent conditions to achieve its function, and it has limitations for high-side power switches where monolithic integration or custom power transistors are not feasible. Summary of the Invention

[0005] To address the aforementioned problems, this invention proposes an improved detection system.

[0006] A detection system for a power switch, used to detect the current flowing through the power switch, wherein a first terminal of the power switch is coupled to a power rail and a second terminal is coupled to a load, the detection system comprising: a bias circuit coupled between the power rail and a reference ground to provide a bias voltage; an operational amplifier having a non-inverting input, an inverting input, and an output, the non-inverting input being coupled to the second terminal of the power switch to receive the voltage at the second terminal of the power switch, and the inverting input being coupled to the power rail through a sampling resistor; a sampling MOSFET having a gate, a source, and a drain, the source being coupled to the inverting input of the operational amplifier, and the gate being coupled to the output of the operational amplifier; a capacitor coupled between the output of the operational amplifier and the bias voltage; and a current mirror circuit having a current flow... The system comprises an input section and a current-outflow section. The current-inflow section is coupled between the drain of the sampling MOSFET and the bias circuit to receive the current flowing through the sampling MOSFET and the sampling resistor. The current-outflow section is coupled between the power rail and the output terminal of the detection system to provide the detection current. The power rail provides a positive reference voltage to the operational amplifier, and the bias voltage provides a negative reference voltage to the operational amplifier. The bias circuit includes: a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first capacitor, a first NPN transistor, a second NPN transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a first P-type laterally diffused MOS transistor.

[0007] The aforementioned detection system for power switches according to various aspects of the present invention does not require the use of monolithic integrated circuits or custom power transistors. It can accurately provide a current proportional to the current flowing through the power switch to be detected, so that the system can perform sampling, protection and other functions. At the same time, the detection system uses a bias voltage generated based on the power rail as the DC operating point of the operational amplifier and the current mirror circuit, which makes the detection system highly independent and ensures that the detection system does not interfere with the control circuit of the power switch under test. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the existing current detection circuit 50.

[0009] Figure 2 A circuit structure diagram of a detection system 200 for a power switch according to an embodiment of the present invention is shown;

[0010] Figure 3 A circuit structure diagram of a detection system 300 for a power switch according to an embodiment of the present invention is shown.

[0011] Figure 4 A schematic diagram of the transistor-level circuit structure of a detection system 400 for a power switch according to an embodiment of the present invention is shown. Detailed Implementation

[0012] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0013] Throughout this specification, references to “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment,” “in an embodiment,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an element is referred to as “coupled to” or “connected to” another element, it can be directly coupled to or coupled to the other element, or there may be intermediate elements. Conversely, when an element is referred to as “directly coupled to” or “directly connected to” another element, there are no intermediate elements. The same reference numerals indicate the same elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0014] like Figure 2 The diagram shown is a circuit structure schematic of a detection system 200 for a power switch according to an embodiment of the present invention. Figure 2 As shown, the detection system 200 is used to detect the current I flowing through the power switch 101. 101 The power switch 101 has its first terminal coupled to the power rail VDD and its second terminal coupled to the load 120. The detection system 200 includes a bias circuit 102 coupled between the power rail VDD and a reference ground, providing a bias voltage V. F Operational amplifier 103 has a non-inverting input terminal 31, an inverting input terminal 32, and an output terminal 33. Its non-inverting input terminal 31 is coupled to the second terminal of power switch 101 to receive the voltage V at the second terminal of power switch. SIts inverting input terminal 32 is coupled to the power rail VDD through sampling resistor 104; the sampling MOSFET (metal-oxide-semiconductor field-effect transistor) 105 has a gate, source, and drain, its source is coupled to the inverting input terminal 32 of the operational amplifier 103, and its gate is coupled to the output terminal 33 of the operational amplifier 103; capacitor 106 is coupled to the output terminal 33 of the operational amplifier 103 and the bias voltage VDD. F Between; the current mirror circuit 107 has a current inflow portion 71 and a current outflow portion 72, the current inflow portion 71 being coupled to the drain of the sampling MOSFET 105 and the bias circuit V. F Between the sampling MOSFET 105 and the sampling resistor 104, the current flowing out 72 is coupled between the power rail VDD and the output terminal 130 of the detection system 200 to provide the detection current Imon. The power rail VDD provides a positive reference voltage to the operational amplifier 103, and the bias voltage V... F Provide a negative reference voltage to operational amplifier 103.

[0015] In one embodiment of the present invention, the sampling MOSFET 105 is P-type doped.

[0016] The working principle of this invention is as follows:

[0017] After the detection system 200 is powered on, a bias voltage V relative to the power rail VDD is provided through the bias circuit 102. F The bias voltage V F The DC operating points of operational amplifier 103 and current mirror circuit 107 were determined. The non-inverting input of operational amplifier 103 receives the voltage V from the second terminal of power switch 101. S Based on the operating principle of virtual short and virtual open at the non-inverting and inverting input terminals of the operational amplifier, the voltage at the inverting input terminal of the operational amplifier 103 is also V. S That is, the voltage at one end of the sampling resistor 104 is V. S The voltage at the other end is the power rail VDD. Therefore, the voltage across sampling resistor 104 is equal to the voltage across power switch 101. The current I flowing through sampling resistor 104 is... 104 for:

[0018] (1).

[0019] Where R 104 R is the resistance value of the second resistor. dson This is the on-resistance of power switch 101.

[0020] From the above expression (1), it can be seen that the current I flowing through the sampling resistor 104 is 104With the current I flowing through power switch 101 101 Proportional.

[0021] Because the current I flowing through the sampling resistor 104 104 Simultaneously, the current flowing through the current inflow portion 71 of the current mirror circuit 107, and the current flowing out of the current mirror circuit 107 (i.e., the detection current Imon) are related to I... 104 The current Imon is proportional to the current I flowing through the power switch 101. 101 It is also directly proportional. That is to say, the detected current Imon reflects the current I flowing through the power switch 101. 101 The detection system 200 implements current detection of the power switch. This detected current, Imon, can be output to an external resistor to provide the system with a detection voltage characterizing the power switch current, thereby enabling the system to perform control and protection functions.

[0022] Figure 3 A schematic diagram of the circuit structure of a detection system 300 for a power switch according to an embodiment of the present invention is shown. Figure 3 The detection system 300 shown is Figure 2 The detection system 200 shown is similar to, and Figure 2 The difference is that, in Figure 3 In the illustrated embodiment, the detection system 300 further includes a high-voltage P-type MOSFET 108, having a gate, a drain, and a source, with its gate coupled to a clamping voltage V. F Its source is coupled to the current output portion 72 of the current mirror circuit 107, and its drain is coupled to the output terminal 130 of the detection system 300 to provide the detection current Imon. The high-voltage P-type MOSFET 108 is a high-voltage resistant transistor, such as one with a withstand voltage of tens of volts, hundreds of volts, or even one hundred volts. When the power rail VDD has a relatively high voltage value, the high-voltage P-type MOSFET 108 provides protection for the current output portion 72 of the current mirror circuit 107.

[0023] In one embodiment of the present invention, the high-voltage P-type MOSFET 108 comprises a laterally diffused metal-oxide semiconductor (LDMOS).

[0024] Figure 4 A schematic diagram of the transistor-level circuit structure of a detection system 400 for a power switch according to an embodiment of the present invention is shown. Figure 4As shown, the bias circuit 102 includes: a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a first capacitor C1, a first NPN transistor Q1, a second NPN transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a first P-type lateral diffusion MOS transistor PLD1. The gate of the first NMOS transistor N1 is coupled to the gate and drain of the second NMOS transistor N2 and the drain of the first PMOS transistor P1; the drain of the first NMOS transistor N1 is coupled to the power rail VDD; the source of the first NMOS transistor N1 is coupled to the source of the second NMOS transistor N2, one end of the first resistor R1, one end of the fourth resistor R4, one end of the fifth resistor R5, and the gate of the first P-type laterally diffused MOS transistor PLD1; the gate of the first PMOS transistor P1 is coupled to the drain of the second PMOS transistor P2, the collector of the first NPN transistor Q1, and one end of the first capacitor C1; the source of the first PMOS transistor P1 is coupled to the power rail VDD; the gate of the second PMOS transistor P2 is coupled to the gate and drain of the third PMOS transistor P3 and the collector of the second NPN transistor Q2; the source of the second PMOS transistor P2 is coupled to the power rail VDD; the base of the first NPN transistor Q1 is coupled to the second NPN transistor Q2. The base of the first NPN transistor Q1 is connected to one end of the first resistor R1 and one end of the second resistor R2; the emitter of the second NPN transistor Q2 is connected to the other end of the second resistor R2; the other end of the third resistor R3 is connected to the power rail VDD; the other end of the fifth resistor R5 is connected to the reference ground; the drain of the first P-type laterally diffused MOSFET PLD1 is connected to the reference ground; the source of the first P-type laterally diffused MOSFET PLD1 provides the bias voltage VDD. F .

[0025] The operational amplifier 103 includes: a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, and a sixth resistor R6. The gate of the third NMOS transistor N3 is coupled to the gates of the fifth NMOS transistor N5, the seventh NMOS transistor N7, the eleventh NMOS transistor N11, the thirteenth NMOS transistor N13, the drain of the fourth PMOS transistor P4, and one end of the sixth resistor R6; the drain of the third NMOS transistor N3 is coupled to the gates of the fourth NMOS transistor N4, the sixth NMOS transistor N6, the eighth NMOS transistor N8, the twelfth NMOS transistor N12, the fourteenth NMOS transistor N14, and the other end of the sixth resistor R6; the source of the third NMOS transistor N3 is coupled to the drain of the fourth NMOS transistor N4; and the source of the fourth NMOS transistor N4 is coupled to the bias voltage V. F The source of the sixth NMOS transistor N6, the source of the eighth NMOS transistor N8, the source of the twelfth NMOS transistor N12, and the source of the fourteenth NMOS transistor N14; the drain of the fifth NMOS transistor is coupled to the gate and drain of the sixth PMOS transistor P6, the gate of the ninth PMOS transistor P9, and the gate of the tenth PMOS transistor P10; the source of the fifth NMOS transistor N5 is coupled to the drain of the sixth NMOS transistor N6; the drain of the seventh NMOS transistor N7 is coupled to the source of the ninth NMOS transistor N9 and the source of the tenth NMOS transistor N10; the source of the seventh NMOS transistor N7 is coupled to the drain of the eighth NMOS transistor N8; the gate of the ninth NMOS transistor N9 serves as the non-inverting input terminal 31 of the operational amplifier 103 and is coupled to the second terminal of the power switch 101 to receive the voltage V at the second terminal of the power switch. SThe drain of the ninth NMOS transistor N9 is coupled to the drain of the seventh PMOS transistor P7 and the source of the ninth PMOS transistor P9; the gate of the tenth NMOS transistor N10 is coupled to the sampling MOSFET. The source of 105 is connected to one end of the sampling resistor 104; the drain of the tenth NMOS transistor N10 is coupled to the drain of the eighth PMOS transistor P8 and the source of the tenth PMOS transistor P10; the drain of the eleventh NMOS transistor N11 is coupled to the gate of the seventh PMOS transistor P7, the gate of the eighth PMOS transistor P8, and the drain of the ninth PMOS transistor P9; the source of the eleventh NMOS transistor N11 is coupled to the drain of the twelfth NMOS transistor N12; the drain of the thirteenth NMOS transistor N13 is coupled to the drain of the tenth PMOS transistor P10 and the gate of the eleventh PMOS transistor P11, and serves as the output terminal of the operational amplifier 103, coupled to the other end of the capacitor 106; the source of the thirteenth NMOS transistor N13 is coupled to the drain of the fourteenth NMOS transistor N14.

[0026] The current inflow section 71 of the current mirror circuit 107 includes: the fifteenth NMOS transistor N15, the sixteenth NMOS transistor N16, the seventeenth NMOS transistor N17, and the eighteenth NMOS transistor N18; the current outflow section 72 includes: the nineteenth NMOS transistor N19, the twentieth NMOS transistor N20, the twelfth PMOS transistor P12, the thirteenth PMOS transistor P13, the fourteenth PMOS transistor P14, and the fifteenth PMOS transistor P15. The gate and drain of the fifteenth NMOS transistor N15 are coupled to the gates of the seventeenth NMOS transistor N17, the nineteenth NMOS transistor N19, and the sampling MOSFET. The drain of NMOS transistor N15 is coupled to the gate and drain of NMOS transistor N16, the gate of NMOS transistor N18, and the gate of NMOS transistor N20; the drain of NMOS transistor N17 is coupled to the gate and drain of PMOS transistor P12; the drain of NMOS transistor N19 is coupled to the gate and drain of PMOS transistor P13 and the gate of PMOS transistor P15; the drain of NMOS transistor N19 is coupled to the gate and drain of PMOS transistor P13 and the gate of PMOS transistor P15; The source of the twentieth NMOS transistor N20 is coupled to the drain of the twelfth PMOS transistor P12; the source of the thirteenth PMOS transistor P13 is coupled to the power rail VDD; the drain of the fourteenth PMOS transistor P14 is coupled to the source of the fifteenth PMOS transistor P15; the source of the fourteenth PMOS transistor P14 is coupled to the power rail VDD; the drain of the fifteenth PMOS transistor P15 serves as the output terminal 130 of the detection system 200, or is coupled to the output terminal 130 of the detection system 200 via a high-voltage P-type MOSFET 108 to provide the detection current Imon.

[0027] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A detection system for a power switch for detecting a current flowing through the power switch, a first terminal of the power switch being coupled to a power supply rail and a second terminal of the power switch being coupled to a load, characterized in that, The detection system comprises: a bias circuit coupled between a power supply rail and a reference ground to provide a bias voltage; an operational amplifier having a non-inverting input, an inverting input and an output, the non-inverting input of the operational amplifier being coupled to a second terminal of the power switch to receive a voltage at the second terminal of the power switch, the inverting input of the operational amplifier being coupled to the power supply rail through a sampling resistor; a sampling MOSFET having a gate, a source and a drain, the source of the sampling MOSFET being coupled to the inverting input of the operational amplifier, the gate of the sampling MOSFET being coupled to the output of the operational amplifier; a capacitor coupled between the output of the operational amplifier and the bias voltage; a current mirror circuit having a current flow-in portion and a current flow-out portion, the current flow-in portion of the current mirror circuit being coupled between the drain of the sampling MOSFET and the bias circuit to receive a current flowing through the sampling MOSFET and the sampling resistor, the current flow-out portion of the current mirror circuit being coupled between the power supply rail and an output of the detection system to provide a detection current; wherein: the power supply rail provides a positive reference voltage for the operational amplifier, and the bias voltage provides a negative reference voltage for the operational amplifier; the bias circuit comprises: a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first capacitor, a first NPN transistor, a second NPN transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a first P-type lateral diffusion MOS transistor; wherein: a gate of the first NMOS transistor is coupled to a gate and a drain of the second NMOS transistor and a drain of the first PMOS transistor; a drain of the first NMOS transistor is coupled to the power supply rail; a source of the first NMOS transistor is coupled to a source of the second NMOS transistor, one end of the first resistor, one end of the fourth resistor, one end of the fifth resistor, and a gate of the first P-type lateral diffusion MOS transistor; a gate of the first PMOS transistor is coupled to a drain of the second PMOS transistor, a collector of the first NPN transistor, and one end of the first capacitor; a source of the first PMOS transistor is coupled to the power supply rail; a gate of the second PMOS transistor is coupled to a gate and a drain of the third PMOS transistor and a collector of the second NPN transistor; a source of the second PMOS transistor is coupled to the power supply rail; a base of the first NPN transistor is coupled to a base of the second NPN transistor, one end of the third resistor, and the other end of the fourth resistor; an emitter of the first NPN transistor is coupled to the other end of the first resistor and one end of the second resistor; an emitter of the second NPN transistor is coupled to the other end of the second resistor; the other end of the third resistor is coupled to the power supply rail; the other end of the fifth resistor is coupled to the reference ground; a drain of the first P-type lateral diffusion MOS transistor is coupled to the reference ground; a source of the first P-type lateral diffusion MOS transistor provides the bias voltage.

2. The detection system of claim 1, wherein, The sampling MOSFET is of a P-type.

3. The detection system of claim 1, wherein, Further comprising: a high-voltage P-type MOSFET having a gate, a drain and a source, the gate of the high-voltage P-type MOSFET being coupled to the bias voltage, the source of the high-voltage P-type MOSFET being coupled to the current flow-out portion of the current mirror circuit, and the drain of the high-voltage P-type MOSFET being coupled to the output of the detection system to provide the detection current.

4. The detection system of claim 3, wherein, The high-voltage P-type MOSFET is a high-voltage resistant transistor.

5. The detection system of claim 1, wherein, The operation amplifier comprises: The third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube, the thirteenth NMOS tube, the fourteenth NMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube, the tenth PMOS tube and the sixth resistor.

6. The detection system of claim 5, wherein, The gate of the third NMOS tube is coupled to the gate of the fifth NMOS tube, the gate of the seventh NMOS tube, the gate of the eleventh NMOS tube, the gate of the thirteenth NMOS tube, the drain of the fourth PMOS tube and one end of the sixth resistor; The drain of the third NMOS tube is coupled to the gate of the fourth NMOS tube, the gate of the sixth NMOS tube, the gate of the eighth NMOS tube, the gate of the twelfth NMOS tube, the gate of the fourteenth NMOS tube and the other end of the sixth resistor; The source of the third NMOS tube is coupled to the drain of the fourth NMOS tube; The source of the fourth NMOS tube is coupled to a bias voltage, the source of the sixth NMOS tube, the source of the eighth NMOS tube, the source of the twelfth NMOS tube and the source of the fourteenth NMOS tube; The drain of the fifth NMOS tube is coupled to the gate and the drain of the sixth PMOS tube, the gate of the ninth PMOS tube and the gate of the tenth PMOS tube; The source of the fifth NMOS tube is coupled to the drain of the sixth NMOS tube; The drain of the seventh NMOS tube is coupled to the source of the ninth NMOS tube and the source of the tenth NMOS tube; The source of the seventh NMOS tube is coupled to the drain of the eighth NMOS tube; The gate of the ninth NMOS tube is coupled to the second end of the power switch as the non-inverting input terminal of the operation amplifier to receive the voltage of the second end of the power switch; The drain of the ninth NMOS tube is coupled to the drain of the seventh PMOS tube and the source of the ninth PMOS tube; The gate of the tenth NMOS tube is coupled to the source of the sampling MOSFET and one end of the sampling resistor; The drain of the tenth NMOS tube is coupled to the drain of the eighth PMOS tube and the source of the tenth PMOS tube; The drain of the eleventh NMOS tube is coupled to the gate of the seventh PMOS tube, the gate of the eighth PMOS tube and the drain of the ninth PMOS tube; The source of the eleventh NMOS tube is coupled to the drain of the twelfth NMOS tube; The drain of the thirteenth NMOS tube is coupled to the drain of the tenth PMOS tube, the gate of the eleventh PMOS tube and the other end of the capacitor as the output terminal of the operation amplifier; The source of the thirteenth NMOS tube is coupled to the drain of the fourteenth NMOS tube. The current flowing into part of the current mirror circuit comprises: the fifteenth NMOS tube, the sixteenth NMOS tube, the seventeenth NMOS tube and the eighteenth NMOS tube; 7. The detection system of claim 5, wherein, The current flowing out part comprises: the nineteenth NMOS tube, the twentieth NMOS tube, the twelfth PMOS tube, the thirteenth PMOS tube, the fourteenth PMOS tube and the fifteenth PMOS tube. The current flowing into part of the current mirror circuit comprises: the fifteenth NMOS tube, the sixteenth NMOS tube, the seventeenth NMOS tube and the eighteenth NMOS tube; ​ 8. The detection system of claim 7, wherein, ​ a gate and a drain of the fifteenth NMOS are coupled to a gate of the seventeenth NMOS, a gate of the nineteenth NMOS, and a drain of the sampling MOSFET; a source of the fifteenth NMOS is coupled to a gate and a drain of the sixteenth NMOS, a gate of the eighteenth NMOS, and a gate of the twentieth NMOS; a drain of the seventeenth NMOS is coupled to a gate and a drain of the twelfth PMOS; a drain of the nineteenth NMOS is coupled to a gate, a drain of the thirteenth PMOS, and a gate of the fifteenth PMOS; a source of the nineteenth NMOS is coupled to a drain of the twentieth NMOS; a source of the twelfth PMOS is coupled to a power supply rail; a source of the thirteenth PMOS is coupled to a power supply rail; a drain of the fourteenth PMOS is coupled to a source of the fifteenth PMOS; a source of the fourteenth PMOS is coupled to a power supply rail; a drain of the fifteenth PMOS is coupled to an output of the detection system to provide the detection current.

9. The detection system of claim 7, wherein, wherein: a gate and a drain of the fifteenth NMOS are coupled to a gate of the seventeenth NMOS, a gate of the nineteenth NMOS, and a drain of the sampling MOSFET; a source of the fifteenth NMOS is coupled to a gate and a drain of the sixteenth NMOS, a gate of the eighteenth NMOS, and a gate of the twentieth NMOS; a drain of the seventeenth NMOS is coupled to a gate and a drain of the twelfth PMOS; a drain of the nineteenth NMOS is coupled to a gate, a drain of the thirteenth PMOS, and a gate of the fifteenth PMOS; a source of the nineteenth NMOS is coupled to a drain of the twentieth NMOS; a source of the twelfth PMOS is coupled to a power supply rail; a source of the thirteenth PMOS is coupled to a power supply rail; a drain of the fourteenth PMOS is coupled to a source of the fifteenth PMOS; a source of the fourteenth PMOS is coupled to a power supply rail; a drain of the fifteenth PMOS is coupled to an output of the detection system to provide the detection current.

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