Chip code integration method, electronic equipment and medium

Abstract

The invention relates to the technical field of chips, in particular to a chip code integration method, electronic equipment and a medium, and the method comprises the following steps: performing self-inspection on codes generated by each chip IP in each stage, and sequencing to generate a queue to be submitted after self-inspection; and performing chip system testing on the code generated by each chip IP according to the sequence in the queue to be submitted, performing chip system environment self-inspection after the testing is passed, and integrating the code generated by the chip IP into a chip system after the chip system environment self-inspection is passed. The chip code integration efficiency and accuracy are improved.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a chip code integration method, electronic device, and medium. Background Technology

[0002] Chip development is a phased process, with each phase requiring the integration of code from all intellectual property (IP) units. Integration can only proceed if the code from all IP units meets the development requirements of the current phase. Due to the large number of IP units and their often diverse team composition, current technologies cannot accurately and quickly ensure the accuracy of code submissions for each IP unit. Furthermore, errors in the code of a single IP unit can block the integration process, resulting in low efficiency and inaccuracy, thus impacting chip development progress. Therefore, improving the efficiency and accuracy of chip code integration is a pressing technical challenge. Summary of the Invention

[0003] The purpose of this invention is to provide a chip code integration method, electronic device, and medium that improve the efficiency and accuracy of chip code integration.

[0004] According to a first aspect of the present invention, a chip code integration method is provided, comprising: Step S1: Obtain the chip IP set {IP1, IP2, ..., IP...} m IP M IP m Let m be the m-th chip IP, where m ranges from 1 to M, and M is the total number of chip IPs in the chip system. Initially, the current chip development stage identifier n=1. Step S2: Obtain IP m The corresponding code A for the nth chip development stage n m , will A n m After the chip IP undergoes self-testing, it is added to the submission queue, which is updated in real time. The value of n ranges from 1 to N, where N is the total number of chip development stages. Step S3: Select A to be processed from the current queue of submissions. n m and will process A n m Remove from the pending queue, based on pending A. n m Perform chip system testing. If the chip system test passes, proceed to step S4; otherwise, proceed to step S6.

[0005] Step S4: Process A nm Submit the chip system environment to the system for self-test. If the chip system environment self-test passes, proceed to step S5; otherwise, discard the pending A chip system. n m Proceed to step S6; Step S5: Process A n m Integrate into the chip system and proceed to step S7; Step S6: Based on the A to be processed n m Generate a prompt message and return to step S3; Step S7: If all IPs in the nth chip development stage... m If all the code is integrated into the chip system, then proceed to step S8; otherwise, return to step S3. Step S8: If n=N, then end the process; otherwise, set n=n+1 and return to step S2.

[0006] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the first aspect of the present invention.

[0007] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions for performing the method described in the first aspect of the present invention.

[0008] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the chip code integration method, electronic device, and medium provided by this invention achieve considerable technological advancement and practicality, and have broad industrial application value. It has at least the following beneficial effects: This invention first performs a self-check on the code generated by each chip IP at each stage, and then sorts and generates a queue to be submitted. The code generated by each chip IP is then subjected to chip system testing according to the order in the queue. After passing the test, a chip system environment self-check is performed. Only after the chip system environment self-check passes is the code generated by the chip IP integrated into the chip system, thus improving the efficiency and accuracy of chip code integration. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A flowchart illustrating the chip code integration method provided in an embodiment of the present invention. Detailed Implementation

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0012] According to a first aspect of the present invention, a chip code integration method is provided, such as... Figure 1 As shown, it includes: Step S1: Obtain the chip IP set {IP1, IP2, ..., IP...} m IP M IP m Let m be the m-th chip IP, where m ranges from 1 to M, and M is the total number of chip IPs in the chip system. Initially, the current chip development stage identifier n=1.

[0013] It should be noted that the chip system includes M chip IPs, and the code for each chip IP is developed independently.

[0014] Step S2: Obtain IP m The corresponding code A for the nth chip development stage n m , will A n m After the chip IP passes the self-test, it is added to the submission queue. The submission queue is updated in real time. The value of n ranges from 1 to N, where N is the total number of chip development stages.

[0015] It should be noted that each IP address m In each stage of chip development, code must be successfully integrated into the chip system before the next stage of development can proceed. During integration, various problems may arise; therefore, some IP... m In a chip development phase, multiple submissions may be required for successful integration. This is because each IP... m Integrating code into a chip system requires a certain process and time. To improve code integration efficiency, after submitting to the IP... m Before being submitted to the queue, a chip IP self-test is performed to detect problems earlier. New A chips are continuously added to the submission queue. n m Submissions are being made, and A's are constantly being added. n mSubmitted, and A in the queue to be submitted. n m The order of these processes directly affects the efficiency of chip code integration; therefore, the queue to be submitted is updated in real time.

[0016] As one example, N=4, which includes 4 chip development stages. Specifically, the first chip development stage is used to realize chip comprehensive area evaluation, the second chip development stage is used to realize power group timing analysis, the third chip development stage is used to generate back-end layout diagram, and the fourth chip development stage is used to generate final netlist.

[0017] Step S3: Select A to be processed from the current queue of submissions. n m and will process A n m Remove from the pending queue, based on pending A. n m Perform chip system testing. If the chip system test passes, proceed to step S4; otherwise, proceed to step S6.

[0018] It should be noted that A in the pending submission queue n m All are A-type chips awaiting submission to the chip system. n m Therefore, when A n m Selected as pending A n m After performing chip system testing, the chip to be processed (A) will be... n m Remove from the queue of pending submissions.

[0019] Step S4: Process A n m Submit the chip system environment to the system for self-test. If the chip system environment self-test passes, proceed to step S5; otherwise, discard the pending A chip system. n m Proceed to step S6.

[0020] It should be noted that, in order to further improve the efficiency and accuracy of chip code integration, when the A to be processed... n m After passing the chip system test, it cannot be directly integrated into the chip system; the A to be processed still needs to be... n m The chip system environment is submitted to the system for self-testing. Only after the chip system environment self-test passes can the chip be processed. n m Integrated into the chip system to avoid issues caused by unprocessed A nm It corrupts the entire chip system code.

[0021] Step S5: Process A n m Integrate into the chip system and proceed to step S7.

[0022] Step S6: Based on the A to be processed n m Generate a prompt message and return to step S3.

[0023] It should be noted that, based on the A to be processed n m After generating the prompt message, you need to modify the pending A again. n m The modified A also needs to be... n m Processed in the pending submission queue until integration is successful at the current stage.

[0024] Step S7: If all IPs in the nth chip development stage... m If all the code is integrated into the chip system, then proceed to step S8; otherwise, return to step S3.

[0025] It should be noted that all IPs must be guaranteed at each stage of chip development. m The code must be integrated into the chip system before the next stage of chip development can proceed.

[0026] Step S8: If n=N, then end the process; otherwise, set n=n+1 and return to step S2.

[0027] As one embodiment, step S2 includes: Step S21, if IP m No code A has been submitted during the development phase of the nth chip. n m Or the code A for the nth chip development phase has already been submitted. n m And received based on A n m When generating the prompt message, obtain the IP address. m The corresponding code A for the nth chip development stage n m .

[0028] It should be noted that each IP address m Code needs to be integrated into the chip system at every stage of chip development, but not necessarily for every IP. m All integrations were successful on the first attempt. If problems occurred during integration, they would be resolved based on A. n m Generate a prompt message. Therefore, if the IP address...m No code A has been submitted during the development phase of the nth chip. n m Or the code A for the nth chip development phase has already been submitted. n m And received based on A n m IP address must be obtained when generating notification messages. m The corresponding code A for the nth chip development stage n m .

[0029] Step S22, based on A n m Running IP m The corresponding self-testing test case set B m Generate the corresponding pass rate P n m and functional coverage Q n m .

[0030] It should be noted that each IP address m Each IP address has a corresponding set of self-testing test cases. m The corresponding set of self-testing test cases is the same at each stage of chip development.

[0031] Step S23, if P n m Higher than IP m The yield threshold PX corresponding to the nth chip development stage n m And Q n m Higher than IP m The functional coverage threshold QX corresponding to the nth chip development stage n m Then A n m If the chip IP self-test is performed, proceed to step S24; otherwise, based on A... n m Generate a prompt message and return to step S21.

[0032] Where, given a fixed value of m, P n m The size of Q is directly proportional to the value of n. n m The magnitude of P is directly proportional to the value of n; that is, given a fixed value of m, the larger the value of n, the greater the magnitude of P. n m The larger the value of Q, the better. n m The larger the value, the better.

[0033] Step S24, place A n m Add to the pending submission queue, which is updated in real time.

[0034] It should be noted that A is in the queue to be submitted. n m The sorting will affect A n m The order in which A is integrated affects the efficiency of chip code integration. Therefore, how to properly handle A in the submission queue is crucial. n m The order is also extremely important. As one embodiment, step S24 includes: Step S241: Obtain A for each queue to be added to the submission queue. n m The corresponding current weight value C m : C m =D m -E m ×α-F m ×β, Among them, D m For IP m The corresponding initial weight value, E m For IP m The corresponding number of times the chip system failed the test, F m For IP m The corresponding number of times the chip system environment self-test failed, where α is the loss weight for failing the chip system test and β is the loss weight for failing the chip system environment self-test, and α < β.

[0035] It should be noted that if the IP address is... m For shared IPs, such as bus IPs, the initial weight value is greater than that of ordinary IPs. The specific initial weight data is set according to the specific application requirements. m For IP m The cumulative value of F across all chip development stages. m For IP m The cumulative value across all chip development stages. Since the loss caused by a failed chip system environment self-test to chip code integration is greater than the loss caused by a failed chip system test, α < β is set.

[0036] Step S242: Based on A to be added to the submission queue n m A, which is to be added to the pending submission queue n m Add it to the queue to be submitted, so that A in the queue to be submitted... n mArranged in descending order of their current weight values.

[0037] It should be noted that through the processing in steps S241-S242, the A in the queue to be submitted can be... n m A more rational sorting process is likely to reduce wasted time in chip code integration and greatly improve chip code integration efficiency.

[0038] As one embodiment, in step S3, the process of selecting A to be processed from the current queue of submissions is described. n m ,include: Step S31: If the first A in the current submission queue... n m Dependency A exists n m If the result is positive, proceed to step S32; otherwise, directly add the first A in the current submission queue. n m As A to be processed n m .

[0039] Step S32, if dependent on A n m If there is also an A in the pending submission queue, then the first A in the previous pending submission queue will be selected. n m And dependent on A n m All are treated as pending A n m Otherwise, proceed to step S33.

[0040] It should be noted that when A n m Dependency A exists n m At that time, it is necessary to depend on A. n m Simultaneously, chip system testing is performed.

[0041] Step S33: Add the next A in the current queue to be submitted. n m As the first A n m Return to step S31.

[0042] As one embodiment, in step S3, based on the A to be processed n m Perform chip system testing, including: Step B31, based on the A to be processed n mPerform system test case set G corresponding to the nth chip development stage. n .

[0043] Step B32, if G n If all test cases in the code pass the test, then process A is complete. n m The corresponding chip system test passed; otherwise, process A. n m The corresponding chip system test failed.

[0044] To further improve the processing efficiency of A n m The processing efficiency for chip system testing, in step S3, is based on the A to be processed. n m Perform chip system testing, including: Step C31: Obtain the A to be processed n m System testing window H n m .

[0045] Step C32, based on the A to be processed n m Perform system test case set G corresponding to the nth chip development stage. n If in H n m Inner and G n If all test cases in the code pass the test, then process A is complete. n m The corresponding chip system passed the test. If in H n m And G exists n If the test cases fail, proceed to step C33. If H has been reached... n m And G n If not all test cases in the process have passed, then pending process A will be executed. n m The corresponding chip system test failed.

[0046] Step C33: Update pending process A. n m It also performs a self-check, and updates pending A based on the self-check results. n m Return to step C32.

[0047] It should be noted that by setting a window period, one can provide options for fine-tuning pending A processes. n mIt provides an opportunity for quick modifications while avoiding some pending issues. n m By not passing system tests for an extended period, the chip code integration process is blocked, thus improving the efficiency of chip code integration.

[0048] As a method that works smoothly, the method also includes: Step S10: Real-time display of the current chip system code integration status information, including the current pending submission queue, the chip system test currently being executed, or the system environment self-test. n m A, already integrated into the chip system n m .

[0049] It should be noted that by displaying the current code integration status information of the chip system in real time, the code integration status can be accurately and intuitively displayed. If the current submission queue is empty, there is currently no chip system test or system environment self-check being performed. n m And there is no A that has been integrated into the chip system. n m Simply set the current chip system's code integration status to "ready".

[0050] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.

[0051] This invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in this invention.

[0052] This invention also provides a computer-readable storage medium storing computer-executable instructions for performing the methods described in this invention.

[0053] In this embodiment of the invention, the code generated by each chip IP is first self-checked at each stage, and then sorted to form a queue to be submitted. Chip system testing is performed on the code generated by each chip IP according to the order in the queue. After the test passes, a chip system environment self-check is performed. Only after the chip system environment self-check passes is the code generated by the chip IP integrated into the chip system, thus improving the efficiency and accuracy of chip code integration.

[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A chip code integration method, comprising: Step S1, obtaining a chip IP set {IP1, IP2,..., IP m ,...,IP M}, IP m is the mth chip IP, the value range of m is 1 to M, M is the total number of chip IPs contained in the chip system, and the initial setting is that the current chip development stage identifier n = 1; Step S2, acquiring IP m Corresponding nth chip development stage code A n m A n m After self-checking of the chip IP, it is added into a to-be-submitted queue, the to-be-submitted queue is updated in real time, the value range of n is 1 to N, and N is the total number of chip development stages. Step S3, selecting a to-be-processed A from the current to-be-submitted queue n m and deleting the to-be-processed A from the to-be-submitted queue n m based on the to-be-processed A n m performing a chip system test, if the chip system test passes, executing step S4, otherwise, executing step S6; Step S4, the to-be-processed A n m The system is submitted to the chip system environment self-checking, if the chip system environment self-checking passes, then step S5 is executed, otherwise, the to-be-processed A in the chip system is discarded n m Step S6 is executed; Step S5, the to-be-processed A n m integrated into a chip system, step S7 is performed; Step S6, based on the to-be-processed A n m generate the prompt information, and return to step S3; Step S7: If all IPs in the nth chip development stage... m If all the code is integrated into the chip system, then proceed to step S8; otherwise, return to step S3. Step S8, if n=N, ending the flow, otherwise, setting n=n+1, and returning to execute step S2. 2.The method of claim 1, wherein, the step S2 comprises: Step S21, if IP m has not been submitted to the n-th chip development stage code A n m or has been submitted to the n-th chip development stage code A n m and has received the A-based n m When generating the prompt information, acquire the IP m corresponding to the n-th chip development stage code A n m ; Step S22, based on A n m Running IP m Corresponding self-test test case set B m , generate the corresponding pass rate P n m And the functional coverage Q n m ; Step S23, if P n m Higher than IP m The pass rate threshold PX corresponding to the nth chip development stage n m And Q n m Higher than IP m The functional coverage threshold QX corresponding to the nth chip development stage n m Then A n m Through chip IP self-checking, step S24 is executed, otherwise, based on A n m Generate prompt information and return to step S21; Step S24, A n m Join the to-be-committed queue, which is updated in real time. 3.The method of claim 2, wherein, P n m The size of Q n m The size of Q 4.The method of claim 2, wherein, the step S24 comprises: Step S241, obtaining A n m corresponding current weight value C m : C m =D m -E m ×α-F m ×β, wherein, D m is the IP m corresponding to the initial weight value, E m is the IP m corresponding to the number of times of failing the chip system test, F m is the IP m corresponding to the number of times of failing the chip system environment self-checking, a is the loss weight of failing the chip system test, β is the loss weight of failing the chip system environment self-checking, and a < β. Step S242, according to the A n m The A to be added to the pending submission queue is added to the pending submission queue, so that the A in the pending submission queue is n m added to the pending submission queue, so that the A in the pending submission queue is n m arranged in descending order of the current weight value. 5.The method of claim 1, wherein, In the step S3, the A to be processed is selected from the current queue to be submitted n m , comprising: Step S31, if the first A in the current to-be-committed queue is A n m There is a dependency A n m Step S32 is performed, otherwise, the first A in the current to-be-committed queue is directly committed n m as a to-be-processed A n m ; Step S32, if dependent A n m is in the current pending queue, then the first A n m and dependent A n m are all treated as pending A n m , otherwise, step S33 is executed; Step S33, the next A n m as the first A n m Step S31 is returned to. 6.The method of claim 1, wherein, In the step S3, based on the A n m performing chip system test, comprising: Step B31, based on the A n m Performing the system test case set G corresponding to the n-th chip development stage of the chip system n ; Step B32, if all test cases in G n pass, then process A n m the corresponding chip system passes, otherwise, process A n m the corresponding chip system fails. 7.The method of claim 1, wherein, In the step S3, based on the A n m Performing chip system test, comprising: Step C31, obtaining A to be processed n m Window period H for system testing n m ; Step C32, based on the A n m The chip system in the n-th chip development phase corresponding to the system test case set G n , if all test cases in H n and G m pass, the A n to be processed n m The corresponding chip system passes the test, if there is a test case in H n m and G n does not pass, step C33 is executed, if H n m and G n has been reached and all test cases in G n still do not pass, the A m to be processed corresponding chip system fails the test; Step C33, then update the to-be-processed A n m and perform self-checking, and update the to-be-processed A based on the self-checking passing n m Return to execute step C32. 8.The method of claim 1, wherein, the method further comprises: Step S10, presenting the code integration status information of the current chip system in real time, the code integration status information including the current to-be-submitted queue, the A n m , which has been integrated into the chip system n m .

9. An electronic device, comprising: comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executed by the at least one processor, the instructions being configured to perform the method of any one of the preceding claims 1-8.

10. A computer-readable storage medium, characterized in that, computer executable instructions for performing the method of any one of the preceding claims 1-8.

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