Chip code integration method, electronic device, and medium

Abstract

The application relates to the chip technical field, in particular to a chip code integration method, an electronic device and a medium, which comprises the following steps: in each stage, first, self-checking is performed on the code generated by each chip IP; after the self-checking, the code is sorted to generate a to-be-submitted queue; according to the order in the to-be-submitted queue, the code generated by each chip IP is subjected to chip system testing; after the testing, chip system environment self-checking is performed; and after the chip system environment self-checking, the code generated by the chip IP is integrated into the chip system. The application improves the chip code integration efficiency and accuracy.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip, and particularly to a chip code integration method, an electronic device and a medium. BACKGROUND

[0002] The chip development process needs to be carried out in stages, and all chip IP (Intellectual Property) codes need to be integrated in each stage to ensure that all chip IP codes meet the development requirements of the current stage, and then the integration can be carried out. Since the number of chip IPs is large and is usually responsible by different teams, the existing technology cannot accurately and quickly ensure the accuracy of the code submitted by each chip IP, and a certain chip IP code error may block the chip code integration process, thereby reducing the chip code integration efficiency and accuracy and affecting the progress of chip development. Therefore, how to improve the chip code integration efficiency and accuracy has become a technical problem to be solved. SUMMARY

[0003] The present application aims to provide a chip code integration method, an electronic device and a medium, which improve the chip code integration efficiency and accuracy.

[0004] According to the first aspect of the present application, a chip code integration method is provided, comprising:

[0005] Step S1, obtaining a chip IP set {IP1, IP2,..., IP m ,...,IP M}, IP m is the mthchip IP, the value range of m is 1 to M, M is the total number of chip IPs contained in the chip system, and the initial setting of the current chip development stage identifier n=1;

[0006] Step S2, obtaining IP m corresponding to the nthchip development stage code A n m , A n m After self-checking of the chip IP, the chip IP is added to the to-be-submitted queue, the to-be-submitted queue is updated in real time, the value range of n is 1 to N, N is the total number of chip development stages;

[0007] Step S3, selecting a to-be-processed A n m from the current to-be-submitted queue, and deleting the to-be-processed A n m from the to-be-submitted queue, based on the to-be-processed A n m carrying out chip system test, if the chip system test is passed, executing step S4, otherwise, executing step S6.

[0008] Step S4, the to-be-processed A n m The chip system is submitted to the system for chip system environment self-checking, if the chip system environment self-checking is passed, step S5 is executed, otherwise, the to-be-processed A in the chip system is discarded n m Step S6 is executed;

[0009] Step S5, the to-be-processed A n m Integrated into the chip system, step S7 is executed;

[0010] Step S6, based on the to-be-processed A n m The prompt information is generated, and step S3 is returned;

[0011] Step S7, if all the IP m Code of the n-th chip development stage is integrated into the chip system, step S8 is executed, otherwise, step S3 is returned;

[0012] Step S8, if n=N, the process is ended, otherwise, n=n+1 is set, and step S2 is returned.

[0013] According to the second aspect of the application, an electronic device is provided, comprising: at least one processor; and a memory in communication connection with the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are arranged to execute the method of the first aspect of the application.

[0014] According to the third aspect of the application, a computer readable storage medium is provided, which stores computer executable instructions, and the computer instructions are used to execute the method of the first aspect of the application.

[0015] Compared with the prior art, the chip code integration method, the electronic device and the medium provided by the application have obvious advantages and beneficial effects. By the above technical scheme, the chip code integration method, the electronic device and the medium provided by the application can achieve considerable technical progress and practicality, and have wide industrial utilization value. At least the following beneficial effects are achieved:

[0016] In each stage, the code generated by each chip IP is first self-checked, and the to-be-submitted queue is generated after sorting. The code generated by each chip IP is tested according to the order in the to-be-submitted queue, and then the chip system environment self-checking is performed after the test is passed. The code generated by the chip IP is integrated into the chip system after the chip system environment self-checking is passed, which improves the chip code integration efficiency and accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to make the technical solutions in the embodiments of the present application clearer, the accompanying drawings needed in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only represent some of the embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0018] Figure 1 The chip code integration method flow chart provided by the embodiments of the present application is shown in the figure. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments only represent some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without any creative effort belong to the protection scope of the present application.

[0020] According to the first aspect of the present application, a chip code integration method is provided, as shown in the figure, comprising: Figure 1

[0021] Step S1, obtaining a chip IP set {IP1, IP2,..., IP m ,...,IP M}, IP m is the mth chip IP, the value range of m is 1 to M, M is the total number of chip IPs included in the chip system, and the initial setting of the current chip development stage identifier n = 1.

[0022] It should be noted that the chip system includes M chip IPs, and the code of each chip IP is developed independently.

[0023] Step S2, obtaining the IP m corresponding to the nth chip development stage code A n m , and adding A n m to the to-be-submitted queue after self-checking of the chip IP, the to-be-submitted queue is updated in real time, and the value range of n is 1 to N, N is the total number of chip development stages.

[0024] It should be noted that each IP m needs to be successfully integrated into the chip system in each chip development stage, and then the next chip development stage can be executed. During the integration process, various problems may be encountered, so some IP m may need to be submitted multiple times in a chip development stage to be successfully integrated. Since each IP m ​It needs certain process and time to integrate the code into the chip system. In order to improve the code integration efficiency, the IP m Before the submission queue, the chip IP self-check is carried out, so that the problem can be found earlier. New A n m is submitted, and A n m is submitted, and A n m in the submission queue is constantly updated in real time. The order of A n m in the submission queue directly affects the chip code integration efficiency, so the submission queue is updated in real time.

[0025] As an embodiment, N=4, that is, four chip development stages are included. Specifically, the first chip development stage is used to realize chip synthesis area evaluation, the second chip development stage is used to realize power consumption group timing analysis, the third chip development stage is used to generate a back-end layout, and the fourth chip development stage is used to generate a final netlist.

[0026] Step S3, selecting a to-be-processed A n m from the current submission queue, and deleting the to-be-processed A n m from the submission queue based on the to-be-processed A n m carries out chip system test, if the chip system test passes, step S4 is executed, otherwise, step S6 is executed.

[0027] It should be noted that A n m in the submission queue is A n m waiting to be submitted to the chip system, so when A n m is selected as the to-be-processed A n m , after the chip system test, the to-be-processed A n m is deleted from the submission queue.

[0028] Step S4, submitting the to-be-processed A n m to the system to carry out chip system environment self-check, if the chip system environment self-check passes, step S5 is executed, otherwise, the to-be-processed A n m in the chip system is discarded, and step S6 is executed.

[0029] It should be noted that in order to further improve the efficiency and accuracy of chip code integration, when the to-be-processed A n mAfter the chip system test, the A n m to be processed A n m is integrated into the chip system, avoiding the destruction of the entire chip system code. n m

[0030] to be processed A n m is integrated into the chip system, and step S7 is executed.

[0031] to be processed A n m generates a prompt information and returns to step S3.

[0032] to be processed A n m After generating the prompt information, the A n m to be processed A n m is processed in the submission queue until the integration is successful at the current stage.

[0033] Step S7: If all IP m codes of the nth chip development stage are integrated into the chip system, step S8 is executed, otherwise, step S3 is returned.

[0034] It should be noted that each chip development stage needs to ensure that all IP m codes are integrated into the chip system before proceeding to the next chip development stage.

[0035] Step S8: If n=N, the process ends, otherwise, set n=n+1 and return to step S2.

[0036] As an embodiment, the step S2 includes:

[0037] Step S21: If the IP m has not submitted the nth chip development stage code A n m or has submitted the nth chip development stage code A n m and received a prompt information based on A n m , the corresponding nth chip development stage code A m is obtained. n ​m .

[0038] It should be noted that each IP address m Code needs to be integrated into the chip system at every stage of chip development, but not necessarily for every IP. m All integrations were successful on the first attempt. If problems occurred during integration, they would be resolved based on A. n m Generate a prompt message. Therefore, if the IP address... m No code A has been submitted during the development phase of the nth chip. n m Or the code A for the nth chip development phase has already been submitted. n m And received based on A n m IP address must be obtained when generating notification messages. m The corresponding code A for the nth chip development stage n m .

[0039] Step S22, based on A n m Running IP m The corresponding self-testing test case set B m Generate the corresponding pass rate P n m and functional coverage Q n m .

[0040] It should be noted that each IP address m Each IP address has a corresponding set of self-testing test cases. m The corresponding set of self-testing test cases is the same at each stage of chip development.

[0041] Step S23, if P n m Higher than IP m The yield threshold PX corresponding to the nth chip development stage n m And Q n m Higher than IP m The functional coverage threshold QX corresponding to the nth chip development stage n m Then A n m If the chip IP self-test is performed, proceed to step S24; otherwise, based on A... n m Generate a prompt message and return to step S21.

[0042] Where, given a fixed value for m, Pn m The size of Q is proportional to the value of n, and the value of P n m The size of Q is proportional to the value of n, and the value of P n m The size of Q is proportional to the value of n, and the value of P n m The size of Q is proportional to the value of n, and the value of P

[0043] Step S24, adding A n m to the to-be-submitted queue, which is updated in real time.

[0044] It should be noted that the order of A n m in the to-be-submitted queue will affect the integrated processing order of A n m and the processing efficiency of chip code integration. Therefore, how to reasonably order A n m in the to-be-submitted queue is also extremely important. As an embodiment, the step S24 comprises:

[0045] Step S241, obtaining a current weight value C n m corresponding to each A m to be added to the to-be-submitted queue:

[0046] C m =D m -E m ×α-F m ×β,

[0047] wherein D m is an initial weight value of the IP m , E m is a number of times of failing the chip system test of the IP m , F m is a number of times of failing the chip system environment self-check of the IP m , α is a loss weight of failing the chip system test, and β is a loss weight of failing the chip system environment self-check, and α<β.

[0048] It should be noted that if the IP m is a shared IP, for example, a bus IP, the corresponding initial weight value is greater than that of an ordinary IP, and the specific data of the initial weight is set according to the specific application requirement. E m is a cumulative value of the IP m in all chip development stages, and F m is a cumulative value of the IP mThe cumulative value of all the chip development stages experienced. Since the loss caused by chip system environment self-check failure is higher than the loss caused by chip system test failure, α<β is set.

[0049] Step S242, according to A n m to be added to the pending queue, A n m is added to the pending queue, so that A n m is arranged in descending order according to the current weight value.

[0050] It should be noted that through the processing of steps S241-S242, A n m in the pending queue can be arranged more reasonably, which can greatly reduce the waste of time in chip code integration and greatly improve the efficiency of chip code integration.

[0051] As an embodiment, in step S3, A n m to be processed is selected from the current pending queue, including:

[0052] Step S31, if the first A n m in the current pending queue depends on A n m , step S32 is executed, otherwise, the first A n m in the current pending queue is directly selected as A n m to be processed.

[0053] Step S32, if the dependent A n m also exists in the pending queue, the first A n m in the pending queue and the dependent A n m are both selected as A n m to be processed, otherwise, step S33 is executed.

[0054] It should be noted that when A n m depends on A n m , chip system testing needs to be performed simultaneously with the dependent A n m .

[0055] Step S33: Add the next A in the current queue to be submitted. n m As the first A n m Return to step S31.

[0056] As one embodiment, in step S3, based on the A to be processed n m Perform chip system testing, including:

[0057] Step B31, based on the A to be processed n m Perform system test case set G corresponding to the nth chip development stage. n .

[0058] Step B32, if G n If all test cases in the code pass the test, then process A is complete. n m The corresponding chip system test passed; otherwise, process A. n m The corresponding chip system test failed.

[0059] To further improve the processing efficiency of A n m The processing efficiency for chip system testing, in step S3, is based on the A to be processed. n m Perform chip system testing, including:

[0060] Step C31: Obtain the A to be processed n m System testing window H n m .

[0061] Step C32, based on the A to be processed n m Perform system test case set G corresponding to the nth chip development stage. n If in H n m Inner and G n If all test cases in the code pass the test, then process A is complete. n m The corresponding chip system passed the test. If in H n m And G exists n If the test cases fail, proceed to step C33. If H has been reached... n m And G nIf the test case in the test case queue has not passed all the tests, then execute the pending A n m The corresponding chip system test fails.

[0062] Step C33, then update the pending A n m and perform a self-check, and based on the self-check passing, update the pending A n m Return to execute step C32.

[0063] It should be noted that by setting the window period, it is possible to provide an opportunity for quick modification for the pending A n m that need to be fine-tuned, and to avoid the situation where some pending A n m are blocked for a long time from passing system tests, thereby improving the efficiency of chip code integration.

[0064] As a time goes very smoothly, the method further comprises:

[0065] Step S10, present the current chip system code integration status information in real time, the code integration status information including the current pending submission queue, the current A n m that are being executed for chip system tests or system environment self-checks, and the A n m that have been integrated into the chip system.

[0066] It should be noted that by presenting the current chip system code integration status information in real time, it is possible to accurately and intuitively present the code integration status. If the current pending submission queue is empty, there is no A n m being executed for chip system tests or system environment self-checks, and there is no A n m that have been integrated into the chip system, it is possible to present the current chip system code integration status as a preparation state.

[0067] It should be noted that some example embodiments are described as a process or method depicted as a flowchart. Although each step of the flowchart is described as occurring sequentially, many of the steps can be performed in parallel, concurrently or at the same time. In addition, the order of the steps can be re-arranged. The process can be terminated when its operations are completed, but could also have additional steps not included in the figure. A process can correspond to a method, function, routine, subroutine, or the like.

[0068] The embodiment of the present application further provides an electronic device, comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executed by the at least one processor, and the instructions are arranged to execute the method of the embodiment of the present application.

[0069] The embodiment of the present application further provides a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are used to execute the method of the embodiment of the present application.

[0070] The embodiment of the present application performs self-checking on the code generated by each chip IP at each stage, and generates a to-be-submitted queue after the sorting. The code generated by each chip IP is tested in the chip system according to the order in the to-be-submitted queue, and then the chip system environment is self-checked after the test. The code generated by the chip IP is integrated into the chip system after the chip system environment self-checking, thereby improving the chip code integration efficiency and accuracy.

[0071] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as above, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content without departing from the technical solution of the present application, and the equivalent embodiments with equivalent changes are equivalent to the above. Any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the present application are still within the scope of the technical solution of the present application.

Claims

1. A chip code integration method, comprising: Step S1: Obtain the chip IP set {IP1, IP2, ..., IP...} m IP M IP m Let m be the m-th chip IP, where m ranges from 1 to M, and M is the total number of chip IPs in the chip system. Initially, the current chip development stage identifier n=1. Step S2: Obtain IP m The corresponding code A for the nth chip development stage n m , will A n m After the chip IP undergoes self-testing, it is added to the submission queue, which is updated in real time. The value of n ranges from 1 to N, where N is the total number of chip development stages. Step S2 includes: Step S21, if IP m No code A has been submitted during the development phase of the nth chip. n m Or the code A for the nth chip development phase has already been submitted. n m And received based on A n m When generating the prompt message, obtain the IP address. m The corresponding code A for the nth chip development stage n m ; Step S22, based on A n m Running IP m The corresponding self-testing test case set B m Generate the corresponding pass rate P n m and functional coverage Q n m ; Step S23, if P n m Higher than IP m The yield threshold PX corresponding to the nth chip development stage n m And Q n m Higher than IP m The functional coverage threshold QX corresponding to the nth chip development stage n m Then A n m If the chip IP performs a self-test, proceed to step S24; otherwise, based on A... n m Generate a prompt message and return to step S21; Step S24, place A n m Add to the pending submission queue, which is updated in real time; Step S24 includes: Step S241: Obtain A for each queue to be added to the submission queue. n m The corresponding current weight value C m : C m =D m -E m ×α-F m ×β, Among them, D m For IP m The corresponding initial weight value, E m For IP m The corresponding number of times the chip system failed the test, F m For IP m The corresponding number of times the chip system environment self-test failed, α is the loss weight for failing the chip system test, β is the loss weight for failing the chip system environment self-test, and α < β; Step S242: Based on A to be added to the submission queue n m Add A to the pending submission queue n m Add it to the queue to be submitted, so that A in the queue to be submitted... n m Arranged in descending order of current weight values; Step S3: Select A to be processed from the current queue of submissions. n m and will process A n m Remove from the pending queue, based on pending A. n m Perform chip system testing. If the chip system test passes, proceed to step S4; otherwise, proceed to step S6. Step S4: Process A n m Submit the chip system environment to the system for self-test. If the chip system environment self-test passes, proceed to step S5; otherwise, discard the pending A chip system. n m Proceed to step S6; Step S5: Process A n m Integrate into the chip system and proceed to step S7; Step S6: Based on the A to be processed n m Generate a prompt message and return to step S3; Step S7: If all IPs in the nth chip development stage... m If all the code is integrated into the chip system, then proceed to step S8; otherwise, return to step S3. Step S8: If n=N, then end the process; otherwise, set n=n+1 and return to step S2.

2. The method according to claim 1, characterized in that, Given a fixed value for m, P n m The size of Q is directly proportional to the value of n. n m The size of the value is directly proportional to the value of n.

3. The method according to claim 1, characterized in that, In step S3, select A to be processed from the current queue of pending submissions. n m ,include: Step S31: If the first A in the current submission queue... n m Dependency A exists n m If the result is positive, proceed to step S32; otherwise, directly add the first A in the current submission queue. n m As A to be processed n m ; Step S32, if dependent on A n m If there is also an A in the pending submission queue, then the first A in the previous pending submission queue will be selected. n m And dependent on A n m All are treated as pending A n m Otherwise, proceed to step S33; Step S33: Add the next A in the current queue to be submitted. n m As the first A n m Return to step S31.

4. The method according to claim 1, characterized in that, In step S3, based on the A to be processed n m Perform chip system testing, including: Step B31, based on the A to be processed n m Perform system test case set G corresponding to the nth chip development stage. n ; Step B32, if G n If all test cases in the code pass the test, then process A is complete. n m The corresponding chip system test passed; otherwise, process A. n m The corresponding chip system test failed.

5. The method according to claim 1, characterized in that, In step S3, based on the A to be processed n m Perform chip system testing, including: Step C31: Obtain the A to be processed n m System testing window H n m ; Step C32, based on the A to be processed n m Perform system test case set G corresponding to the nth chip development stage. n If in H n m Inner and G n If all test cases in the code pass the test, then process A is complete. n m The corresponding chip system passed the test. If in H n m And G exists n If the test cases fail, proceed to step C33. If H has been reached... n m And G n If not all test cases in the process have passed, then pending process A will be executed. n m The corresponding chip system test failed; Step C33: Update pending process A. n m It then performs a self-check, and updates pending process A based on the self-check's success. n m Return to step C32.

6. The method according to claim 1, characterized in that, The method further includes: Step S10: Real-time display of the current chip system code integration status information, including the current pending submission queue, the chip system test currently being executed, or the system environment self-test. n m A, already integrated into the chip system n m .

7. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores instructions that are executed by the at least one processor, the instructions being configured to perform the method of any one of claims 1-6.

8. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for performing the method of any one of claims 1-6.

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