Codeless clock management unit design system and method

Abstract

The invention relates to a system and a method for designing a clock management unit in a code-free mode, which can be used for testing a clock component and generating a test clock based on a functional clock path. The system includes a memory to store instructions, and a processor to execute the instructions. The instructions include generating a clock instance including a clock source block, a clock control signal block, and a test multiplexer block; generating a test mode controller instance containing the test data register block; setting connection between the two; and instructions to generate hardware code.

Description

Technical Field

[0001] This invention relates to a system and method for designing a clock management unit for a system-on-a-chip, and more specifically, to a system and method for designing a clock management unit in a no-code manner, which can test the clock components constituting the clock management unit and generate a test clock according to a functional clock generation path. Background Technology

[0002] A system-on-chip (SoC) is a technology that integrates multiple function blocks, such as a central processing unit (CPU), memory, interface, digital signal processing circuits, and analog signal processing circuits, onto a single semiconductor integrated circuit, or an integrated circuit (IC) based on this technology, to realize a computer system or other electronic system. SoCs are evolving into more complex systems that include processors, multimedia, graphics, interfaces, and security functions.

[0003] The system-on-a-chip can be driven in test mode to detect defects and confirm whether the system-on-a-chip is working properly during the design and manufacturing process, and can be driven in functional mode when it passes the test and is running normally.

[0004] Typically, power supply and clock design are extremely important in on-chip systems. The power supply and clock design process for an on-chip system may include the following steps: power / clock diagram drawing, Verilog coding and scripting, initial documentation, generation of Unified Power Format / Standard Design Constraint (UPF / SDC) documents, implementation layout design, secondary documentation, Design for Testability (DFT) controller insertion, hardware system analysis, and software optimization.

[0005] The power / clock diagram drawing step visually represents the power and clock structure, creating a block diagram to represent the power and clock tree. In this step, clock components and their connections are shown graphically only. The Verilog coding and scripting step creates the Verilog code and scripts used to define and implement the functions of the on-chip system to execute the hardware's register transfer level (RTL) design. That is, based on the power / clock diagram artifacts, developers manually generate the register transfer level (RTL) code.

[0006] The first textualization step is to document the design intent and structure at the beginning of the project, creating various texts such as requirement details, architecture design, power / clock diagrams, etc., required by multiple stakeholders such as the validation team and software development team.

[0007] The Unified Power Format / Standard Design Constraint file generation step involves generating Unified Power Format (UPF) and Standard Design Constraint (SDC) files for controlling power management and timing constraints, thus generating the inputs required for hardware synthesis.

[0008] The implementation layout design step involves designing and configuring the actual system-on-chip (SoC) layout at the gate level. The second documentation step involves updating and refining various documents to reflect design and implementation changes. The design-testable controller insertion step involves designing and integrating the design-testable controller and logic circuits for testing and debugging into the SoC. The hardware system analysis step involves verifying and analyzing the software's operation through simulation and verification to confirm the design's accuracy and effectiveness. The software optimization step involves analyzing and optimizing the software code running on the SoC to optimize software performance.

[0009] In the power supply / clock diagram drawing step, the path for the functional clock operating in functional mode is designed, and in the design-for-test-controller insertion step, the path for the test clock operating in test mode is designed. That is, previously, the functional clock design step and the test clock design step were separate and executed independently. Therefore, the clock management unit is designed to provide the functional clock to the IP block via the functional clock path in functional mode, and to provide the test clock to the IP block via a test clock path different from the functional clock path in test mode.

[0010] The clock management unit designed in this way will not drive its internal clock component in the on-chip system test mode, so it is impossible to test whether the clock component is working properly.

[0011] Furthermore, the functional clock path and the test clock path are different. Therefore, the frequency of the test clock provided to the IP block in test mode and the frequency of the functional clock provided to the IP block in functional mode may be different. As a result, there is a difference between the voltage margin in test mode and the voltage margin in functional mode. Due to this difference in voltage margin, there will be problems such as increased defect rate and decreased chip yield during mass production. Summary of the Invention

[0012] The purpose of this invention is to provide a system and method for designing a clock management unit in a no-code manner, wherein in test mode, a test clock generated by the same path as the functional clock path is provided to the IP block, which can test the various clock components constituting the clock management unit.

[0013] The present invention can be implemented in a variety of ways, including apparatus (system), method, computer program stored in a computer-readable medium, or computer-readable medium storing a computer program.

[0014] A no-code clock management unit design system according to an embodiment of the present invention includes: a memory for storing at least one instruction; a clock component repository for storing clock component information constituting the clock management unit; a hardware code logic repository for storing hardware code logic for generating hardware code of the designed clock management unit; and at least one processor for executing at least one instruction stored in the memory. The at least one instruction includes: an instruction for generating a clock instance including a clock source block, a clock control signal block, and a test multiplexer block based on the clock component information; an instruction for generating a test mode controller instance including a test mode test data register (TDR) block and a test control test data register block corresponding to the test multiplexer block; an instruction for setting the connection point between the test multiplexer block and the test mode controller instance; and an instruction for generating hardware code based on the clock instance, the test mode controller instance, the connection point information, and the hardware code logic.

[0015] Preferably, at least one instruction includes: an instruction for generating a scan controller instance corresponding to the clock control signal block; an instruction for setting the connection point between the clock control signal block and the scan controller instance; and an instruction for generating hardware code based on the scan controller instance, connection point information, and hardware code logic.

[0016] Preferably, the test mode controller instance is implemented based on the built-in IEEE1687 standard.

[0017] Preferably, the test mode test data register block is activated or deactivated, and the test control test data register block generates a test clock control signal in the test mode.

[0018] More preferably, the test control test data register block is composed of a number of flip-flops equal to the number of control bits of the clock source block.

[0019] Preferably, the test mode test data register block and the test control test data register block are set through the Internal Joint Test Action Group (IJTAG) interface.

[0020] Preferably, the clock component is one of a phase-locked loop controller component, a clock divider component, a clock multiplexer component, and a clock gating component.

[0021] A no-code clock management unit design method according to an embodiment of the present invention is executed by at least one processor in a computer system including a clock component repository and a hardware code logic repository. The clock component repository stores clock component information constituting the clock management unit, and the hardware code logic repository stores hardware code logic for generating hardware code from the designed clock management unit. The no-code clock management unit design method includes the following steps: generating a clock instance including a clock source block, a clock control signal block, and a test multiplexer block based on the clock component information; generating a test mode controller instance including a test mode test data register block and a test control test data register block corresponding to the test multiplexer block; setting the connection point between the test multiplexer block and the test mode controller instance; and generating hardware code based on the clock instance, the test mode controller instance, the connection point information, and the hardware code logic.

[0022] Preferably, the method further includes the following steps: generating a scan controller instance corresponding to the clock control signal block; setting the connection point between the clock control signal block and the scan controller instance; and generating hardware code based on the scan controller instance, connection point information, and hardware code logic.

[0023] Preferably, the test mode controller instance is implemented based on the built-in IEEE1687 standard.

[0024] Preferably, the test mode test data register block is activated or deactivated, and the test control test data register block generates a test clock control signal in the test mode.

[0025] More preferably, the test control test data register block is composed of a number of flip-flops equal to the number of control bits of the clock source block.

[0026] Preferably, the test mode test data register block and the test control test data register block are set through the internal joint test action group interface.

[0027] Preferably, the clock component is one of a phase-locked loop controller component, a clock divider component, a clock multiplexer component, and a clock gating component.

[0028] One embodiment of the present invention provides a computer program stored in a computer-readable medium for performing the method in a computer.

[0029] According to the present invention, the present invention has the following effects.

[0030] According to the present invention, when designing the path of the functional clock operating in the functional mode in the power supply / clock diagram drawing step, the path of the test clock operating in the test mode can be designed automatically at the same time.

[0031] According to the present invention, the testability design controller insertion step can be omitted, thereby reducing the resources required for the design of the clock management unit and effectively improving the efficiency of the design process.

[0032] According to the present invention, even if the staff has no coding knowledge or clock operation knowledge, they can design a test mode control system that controls the clock management unit in test mode in a no-code manner.

[0033] According to the present invention, a clock management unit can be designed to generate a test clock with the same path as the functional clock path. Therefore, it is possible to test whether multiple clock components constituting the functional clock path are working properly in test mode.

[0034] According to the present invention, the clock component is divided into a low-speed domain and a high-speed domain. The low-speed domain can be tested using a scan chain reference clock for on-chip system logic testing, while the high-speed domain can use the same circuit as the functional clock path and be tested using a test clock with the same frequency as the functional clock.

[0035] In the clock management unit designed according to the present invention, when the on-chip system device is driven in test mode, a test clock can be provided to the IP block to enable the IP block test to be executed smoothly.

[0036] In the clock management unit designed according to the present invention, the clock management unit generates a test clock through the same path as the functional clock path. Therefore, the frequency of the test clock is the same as the frequency of the functional clock used in the functional mode, so the voltage margin in the test mode is the same as the voltage margin in the functional mode, thereby reducing the defect rate and improving the chip yield during mass production.

[0037] The effects of this invention are not limited to those mentioned above. Those skilled in the art to which this invention pertains (referred to as "skilled persons") can clearly understand other effects not mentioned from the description of the scope of protection of the invention. Attached Figure Description

[0038] Embodiments of the present invention will be described with reference to the accompanying drawings, wherein similar reference numerals denote similar structural elements, but are not limited thereto.

[0039] Figure 1 This is a block diagram illustrating a typical System-on-Chip (SoC).

[0040] Figure 2 for Figure 1 The detailed block diagram of the clock management unit 200 included in the system-on-a-chip.

[0041] Figure 3 for Figure 2 A detailed diagram of a portion of the clock management unit.

[0042] Figure 4 This is a detailed view of a clock management unit designed based on the present invention.

[0043] Figure 5 The structural diagram of the no-code clock management unit design system of the present invention is shown.

[0044] Figure 6 An example diagram illustrating the display screen of the clock management unit design system of the present invention in a code-free manner.

[0045] Figure 7 This is a flowchart illustrating the no-code clock management unit design method of the present invention.

[0046] Figure 8 An exemplary computing device is shown for performing the methods and / or embodiments, etc.

[0047] Explanation of reference numerals in the attached figures

[0048] 510: Screen Window Processing Unit 511: Command Window Processing Unit

[0049] 512: Content Window Processing Department 513: Design Window Processing Department

[0050] 514: Setting Window Processing Unit; 520: Clock Management Unit Processing Unit

[0051] 521: Clock Instance Generation Unit 522: Scan Controller Instance Generation Unit

[0052] 523: Test Mode Controller Instance Generation Department

[0053] 530: Data repository 531: Clock component repository

[0054] 532: Content Repository; 533: Clock Management Unit Repository

[0055] 534: Hardware code logic repository; 540: Hardware code processing department.

[0056] 541: Clock Hardware Code Generation Department

[0057] 542: Scan Controller Hardware Code Generation Department

[0058] 543: Test Mode Controller Hardware Code Generation Department Detailed Implementation

[0059] Hereinafter, with reference to the accompanying drawings, the specific contents for implementing the present invention will be described in detail. However, in the following description, specific descriptions of known functions or structures will be omitted where there is a concern that this may unnecessarily obscure the spirit of the invention.

[0060] In the accompanying drawings, the same or corresponding structural elements are given the same reference numerals. Furthermore, in describing the following embodiments, repeated descriptions of the same or corresponding structural elements may be omitted. However, even if descriptions related to structural elements are omitted, it does not mean that such structural elements are not included in any embodiment.

[0061] The advantages, features, and methods of implementing the embodiments described in this specification will be referenced in the appendix. Figure 1 The invention becomes clearer from the embodiments described below. However, the invention is not limited to the embodiments disclosed below, but can be embodied in many different forms. These embodiments are provided only to fully inform those skilled in the art of the scope of the invention.

[0062] The terminology used in this specification is briefly explained, and the disclosed embodiments are described in detail. The terminology used in this specification takes into account its function in the invention and, where possible, selects generally widely used terms. However, this may be changed according to the intentions of those skilled in the art, conventions, or the emergence of new technologies. Furthermore, in certain cases, there may be an intention by the applicant to arbitrarily choose terms; in such cases, their meanings are described in detail in the description of the corresponding invention. Therefore, the terminology used in this invention is not simply a name, but should be defined based on the meaning of the term and the overall content of the invention.

[0063] Unless explicitly specified in the context as singular, singular expressions in this specification include plural expressions. And unless explicitly specified in the context as plural, plural expressions include singular expressions. Throughout this specification, when a section includes a structural element, unless otherwise stated, it implies the inclusion of other structural elements, and not the exclusion of other structural elements.

[0064] In this invention, terms such as "comprising" and "including" can indicate the presence of features, steps, actions, elements and / or structural elements, and such terms do not exclude the addition of more than one other function, step, action, element, structural element and / or combination of these.

[0065] In this invention, when referring to a specific structural element being "combined," "combined," "connected," "related," or "reacting" with other structural elements, the specific structural element may be directly combined, combined, connected, and / or related or reacting with other structural elements, but is not limited thereto. For example, at least one intermediate structural element may exist between the specific structural element and other structural elements. Furthermore, in this invention, "and / or" may include a combination of each of the at least one listed item or at least a portion of at least one item.

[0066] In this invention, terms such as "first" and "second" are used to distinguish specific structural elements from other structural elements, and the structural elements are not limited to such terms. For example, a "first" structural element can be used to represent an element with the same or similar form as a "second" structural element.

[0067] In embodiments of the present invention, the "clock component" can be a clock tool that can be used in the design of a clock management unit. The clock component may include a phase-locked loop controller component, a clock divider component, a clock multiplexer component, and a clock gating component. In this invention, the clock component can be displayed as an icon in the clock component window.

[0068] In embodiments of the present invention, a "clock instance" can be a clock component added to the design window through user operation. That is, a clock instance can be a clock component included in the clock management unit design. If a user drags and drops any clock component icon from the clock component window into the design window area, a clock instance corresponding to the corresponding clock component can be generated. If a clock instance is generated, the basic register of the corresponding clock instance can be automatically generated, and extended registers can be selectively generated. The field values ​​constituting the basic register and the selectively generated extended register can be preset or changed by user input.

[0069] The clock management unit can include multiple clock instances for each type of clock component. A clock instance generated based on a phase-locked loop controller component is called a phase-locked loop controller instance; a clock instance generated based on a clock divider component is called a clock divider instance; a clock instance generated based on a clock multiplexer component is called a clock multiplexer instance; and a clock instance generated based on a clock gating component is called a clock gating instance.

[0070] In an embodiment of the present invention, the clock element is a module that implements hardware code based on a completed clock instance, which can constitute a clock management unit.

[0071] In summary, a clock component can be the material used to design a clock management unit, a clock instance is the node included in the design of the clock management unit, and a clock element is a module implemented in hardware code based on the completed clock instance and capable of operating in the clock management unit.

[0072] In this invention, the clock instance is a node included in the design of the clock management unit, which may include a clock source block, a clock control signal block, and a test multiplexer block. The clock source block, clock control signal block, and test multiplexer block are implemented in hardware code and function as the clock source, clock control signal, and test multiplexer, respectively.

[0073] In this invention, the test mode controller instance is a node included at design time, which may include a test mode test data register block and a test control test data register block. The test mode controller instance, the test mode test data register block, and the test control test data register block are implemented in hardware code and function as the test mode controller, the test mode test data register, and the test control test data register, respectively.

[0074] In this invention, the scan controller instance is a node included in the design of the clock management unit, implemented in hardware code and functioning as a scan controller.

[0075] Figure 1 This is a block diagram illustrating a typical System-on-Chip (SoC).

[0076] The System-on-a-Chip (SoC) may include an input / output board 110, a clock management unit 120 (CMU), a power management unit 130 (PMU), and at least one IP block 140, 150, or 160 (intellectual property). When the SoC is operating in a working mode, the clock management unit 120 can generate function clocks for the first IP block 140, the second IP block 150, and the third IP block 160, respectively. For example, the clock management unit 120 can generate a first function clock CLK1, a second function clock CLK2, and a third function clock CLK3.

[0077] The first IP block 140, the second IP block 150, and the third IP block 160 can be connected to the system bus and communicate with each other through the system bus. The first IP block 140, the second IP block 150, and the third IP block 160 can each include a processor, a graphics processor, a memory controller, an input and output interface block, etc.

[0078] When the first IP block 140 is operational, the clock management unit 120 can provide a first functional clock CLK1 to the first IP block 140; when the second IP block 150 is operational, it can provide a second functional clock CLK2 to the second IP block 150; and when the third IP block 160 is operational, it can provide a third functional clock CLK3 to the third IP block 160. The power management unit 130 controls the power supply to the system-on-chip. For example, when the system-on-chip device enters a standby mode, the power management unit 130 can disconnect the power supply to the system-on-chip to reduce power consumption.

[0079] Figure 2 for Figure 1 A detailed structural diagram of the clock management unit 200 included in the system-on-a-chip. Figure 2 The clock management unit 200 can execute in the normal functional mode of the on-chip system. The clock management unit 200 can provide... Figure 1 Clock management unit 120.

[0080] Reference Figure 2The clock management unit 200 includes multiple clock elements 202, 204, 206, 208, 210, 212, and 214, and a clock management unit controller (CMUController) 216. The multiple clock elements 202, 204, 206, 208, 210, 212, and 214 can generate function clocks to be provided to IP blocks. The frequencies of the multiple function clocks provided to each IP block can be different. The clock management unit controller 216 can control the multiple clock elements 202, 204, 206, 208, 210, 212, and 214 to generate function clocks with the frequencies required in each IP block.

[0081] Clock components may include phase-locked loop (PLL) controllers 202 and 204, clock dividers 206 and 210, clock multiplexers 208, and clock gates 212 and 214. Each clock component may include a clock source for processing the clock and a clock control circuit for controlling the clock source CS. For example, the clock source CS may include multiplexing circuits, frequency divider circuits, and gate circuits.

[0082] The phase-locked loop controllers 202 and 204 do not include a clock source internally, and can control the phase-locked loop located outside the clock management unit 200.

[0083] Clock dividers 206 and 210 each include a divider circuit as a clock source CS, and clock control circuits CC of clock dividers 206 and 210 control the divider circuits respectively. The divider circuits divide the input clock and output it, and the clock control circuit CC can control the division ratio of the divider circuits, etc.

[0084] Clock multiplexer 208 includes a multiplexing circuit as a clock source CS, and a clock control circuit CC controls the multiplexing circuit. The multiplexing circuit selectively outputs one of the multiple input clocks. The clock control circuit CC can instruct the multiplexing circuit which input clock to selectively output.

[0085] Clock gates 212 and 214 each include a gate circuit as a clock source CS, and clock control circuits CC of clock gates 212 and 214 control the gate circuits respectively. The gate circuit activates the clock and provides a functional clock to the IP block only when the IP block needs to operate; otherwise, it disconnects the clock to control unnecessary clocking. The clock control circuit CC can stop or activate the functional clock of the gate circuit.

[0086] The clock management unit controller 216 includes registers that record information required to control and set the operation of the clock management unit 200 in register-transfer-level RTL code. Register-transfer-level RTL code describing the operation of the clock control circuitry for each clock element is created in the registers of the clock management unit controller 216. This register-transfer-level RTL code can be implemented using hardware design tools for the actual clock management unit hardware.

[0087] Figure 2 The clock management unit executes in the normal functional mode of the on-chip system and provides the functional clock to the IP block.

[0088] Figure 3 for Figure 2 A detailed diagram of a portion of the clock management unit.

[0089] The clock management unit may include multiple clock elements 310 and 320. The clock elements may include a phase-locked loop controller, a clock multiplexer, a clock divider, and a clock gating. Figure 3 The diagram illustrates an example of the connection between clock multiplexer 310 and clock divider 320. Any clock element can be added to the front end of clock multiplexer 310 and the rear end of clock divider 320. The clock element may include a clock source for processing the clock and clock control circuitry for controlling the clock source. The clock source may include multiplexing circuitry, divider circuitry, and gating circuitry, etc.

[0090] For example, clock multiplexer 310 may include multiplexing circuit 311 for processing clock and clock control circuit 312 for controlling multiplexing circuit 311, and clock divider 320 may include divider circuit 321 for processing clock and clock control circuit 322 for controlling divider circuit 321.

[0091] The multiplexing circuit 311 receives two or more input clocks CLKIN1 and CLKIN2 from two or more front-end clock elements, and receives a multiplexer selection signal from the clock control circuit 312 to select one of the two or more input clocks CLKIN1 and CLKIN2 as the output clock CLKOUT1 and provide it to the back-end clock elements. The clock control circuit 312 receives multiplexer selection information from the register 330 and outputs a multiplexer selection signal to the multiplexing circuit 311.

[0092] Frequency divider circuit 321 receives the output clock of the front-end clock element as the input clock CLKIN3, and provides the back-end clock element with the output clock CLKOUT2, which is obtained from the clock control circuit 322 and divided according to the clock division ratio of the input clock CLKIN3. The clock control circuit 322 receives the clock division ratio information from register 330 and provides it to frequency divider circuit 321.

[0093] The clock control circuits 312 and 322 of the multiple clock elements are typically combined with and driven by a reference clock of around tens of MHz. On the other hand, the multiple clock sources 311 and 321 of the clock elements handle high-speed clocks ranging from hundreds of MHz to several GHz.

[0094] The clock element of the clock management unit can be separated into a low-speed domain 340 composed of clock control circuits 312 and 322 and a high-speed domain 350 composed of clock sources 311 and 321.

[0095] The structural elements of the low-speed domain 340 of the clock management unit, the operating clock frequency of the low-speed domain 340 when testing the high-speed domain 350, and the operating clock frequency of the high-speed domain 350 are different. Therefore, it is necessary to design to separate the testing of the low-speed domain 340 and the high-speed domain 350 to perform different test methods separately.

[0096] On the other hand, during the manufacturing process of a system-on-a-chip, it is necessary to test whether the IP blocks are working properly, and in test mode, a test clock needs to be provided to the IP blocks.

[0097] Figure 4 This is a detailed view of a clock management unit designed based on the present invention.

[0098] The clock management unit of the present invention may include multiple clock elements 410 and 420. The clock elements may include a phase-locked loop controller, a clock multiplexer, a clock divider, and a clock gating. Figure 4 The diagram illustrates an example of the connection between clock multiplexer 410 and clock divider 420. The clock element includes a clock source for processing the clock, clock control circuitry for outputting a functional clock control signal, and a test multiplexer (Test MUX). The test multiplexer, under the control of register 430 in functional mode, provides the functional clock control signal to the clock source, and in test mode, provides the test clock control signal to the clock source. The clock control circuitry of the clock element constitutes a low-speed domain 440, and the clock source of the clock element constitutes a high-speed domain 450.

[0099] Clock multiplexer 410 includes a clock multiplexing circuit 411 for processing clocks, a clock control circuit 412 controlled by register 430 in functional mode and outputting a functional clock control signal to multiplexing circuit 411, and a test multiplexer 413 that receives the functional clock control signal and a test clock control signal and selectively outputs them to multiplexing circuit 411. Clock divider 420 includes a clock divider circuit 421 for processing clocks, a clock control circuit 422 controlled by register 430 in functional mode and outputting a functional clock control signal to divider circuit 421, and a test multiplexer 423 that receives the functional clock control signal and a test clock control signal and selectively outputs them to divider circuit 421. Each clock element 410, 420 includes test multiplexers 413, 423 matched one-to-one with clock sources 411, 421.

[0100] Meanwhile, the clock management unit includes: a scan controller 460, which controls the reference clock supplied to the clock control circuits 412 and 422 constituting the low-speed domain 440 in test mode; and a test mode controller 470, which outputs test clock control signals to the test multiplexers 413 and 423 in test mode.

[0101] In functional mode, test multiplexers 413 and 423 transmit the functional clock control signals input from clock control circuits 412 and 422 to clock sources 411 and 421. When the on-chip system operates in test mode, each test multiplexer 413 and 423 transmits the test clock control signals input from test mode controller 470 to each clock source 411 and 421.

[0102] The test mode controller 470 may include: a test data register 471, which activates or deactivates test multiplexers 413 and 423 in test mode; and a test control test data register 472, which provides test clock control signals to the test multiplexers 413 and 423 activated in test mode. When test multiplexers 413 and 423 are deactivated in test mode, they operate in functional mode and transmit functional clock control signals input from clock control circuits 412 and 422 to clock sources 411 and 421. When the test mode is activated, they operate in test mode and transmit test clock control signals input from the test control test data register 472 of the test mode controller 470 to clock sources 411 and 421.

[0103] The test mode controller 470 can be a controller based on the built-in IEEE 1687 standard. The test mode controller 470 can configure the test mode test data register 471 and the test control test data register 472 via the Internal Joint Test Action Group (IJTAG) interface. The test mode test data register 471 and the test control test data register 472 can each be implemented as a flip-flop-based shift register structure.

[0104] The test mode test data register 471 can be composed of a flip-flop. The output data of the test mode test data register 471 is transmitted to the test multiplexers 413 and 423 so that the test multiplexers 413 and 423 can be activated / deactivated into test mode.

[0105] The test control test data register 472 can be composed of a trigger chain consisting of the number of bits of the test clock control signal provided to the clock sources 411 and 421. For example, when the multiplexing circuit 411 has two input clocks, it needs to output a 1-bit test clock control signal to the multiplexing circuit 411, and it needs to output a 4-bit test clock control signal according to the division ratio of the frequency divider circuit 421. In this case, the test control test data register 472 is composed of one flip-flop that needs to output the test clock control signal to the multiplexing circuit 411 and four flip-flops that need to output the test clock control signal to the frequency divider circuit 421, arranged in the form of a shift register chain.

[0106] The functional clocks and test clocks generated in the clock management unit can be passed to the IP block.

[0107] Figure 5 This is a structural diagram of the no-code clock management unit design system of the present invention. The no-code clock management unit design system of the present invention can be implemented through a computer system.

[0108] The no-code clock management unit design system of the present invention may include: a screen window processing unit 510, which detects user input and outputs the processing result of the user input to a display screen; a clock management unit processing unit 520, which generates at least one clock instance based on clock component information, generates a scan controller instance, sets the connection point between the clock instance and the scan controller instance, generates a test mode controller instance, and sets the connection point between the clock instance and the test mode controller instance to design the clock management unit; a data storage unit 530, which stores hardware code logic for generating hardware code based on clock component information, designed clock management unit information, and the designed clock management unit; and a hardware code processing unit 540, which uses the hardware code logic to generate hardware code corresponding to the designed clock management unit.

[0109] Figure 6 An example diagram illustrating the display screen of the clock management unit design system of the present invention in a code-free manner.

[0110] The display screen of the no-code clock management unit design system of the present invention may include: a command window 610 for inputting user commands; a clock component window 620 for displaying multiple clock component icons; a content window 630 for providing an environment for adding, deleting, and changing the list of clock management units under design, and displaying a list of clock instances constituting each clock management unit under design and functional information of each clock instance layer by layer; a design window 640 for displaying the clock diagram of the clock management unit under design, and providing an environment for adding, deleting, and changing the clock instances constituting the clock management unit under design; and a setting window 650 for providing a setting environment for the functions of the clock instances selected from the design window 640.

[0111] Command window 610 may include: a CHECK button, which receives a check instruction for errors in the clock diagram constituting the clock management unit under design and the setting values ​​of multiple clock instances of the clock management unit under design; an UNCHECK button, which receives an instruction to not activate the check results; a SAVE button, which receives an instruction to save the clock diagram displayed in design window 640; and a GENRTL button, which receives a hardware code generation instruction for the clock diagram displayed in design window 640.

[0112] The clock component window 620 can display multiple icons listing the clock components used in the design of the clock management unit. Clock components include a phase-locked loop controller component, a clock divider component, a clock multiplexer component, and a clock gating component. Each clock component internally includes a clock source block, a clock control circuit block, and a test multiplexer block. The clock source block is implemented using clock elements... Figure 4 The design block for the clock source operation, and the clock control circuit block are implemented using clock elements. Figure 4 The design block for the clock control circuit operation, and the test multiplexer block are implemented using clock elements. Figure 4 The design block for testing the operation of the multiplexer.

[0113] Content window 630 displays a list of clock management units under design, providing an environment for adding, deleting, and modifying clock management units. Furthermore, below each list of clock management units under design, a list of clock instances constituting the corresponding clock management unit can be displayed. Design window 640 displays the clock diagram of the clock management units under design, providing an environment for adding, deleting, and modifying the clock instances constituting the clock management units. When the user moves any clock component from clock component window 620 to design window 640 by dragging and dropping, a clock instance corresponding to the corresponding clock component can be generated in the corresponding clock management unit under design.

[0114] The settings window 650 provides an automatic clock gating (ACG) setting environment for the clock management unit under design, and provides a function setting environment for the clock instance selected from the design window 640.

[0115] Screen Window Processing Unit 510

[0116] The screen window processing unit 510 may include: a command window processing unit 511, which displays buttons for receiving user commands in the command window 610, detects input to each button in the command window 610, and executes the work corresponding to the input button; a content window processing unit 512, which displays a list of clock management units under design, a list of clock instances included in each clock management unit under design, and register information in the content window 630, and detects user input in the content window 630 and executes the work corresponding to the user input; a design window processing unit 513, which displays the clock diagram of the clock management unit under design selected by the user in the design window 640, detects user input in the design window 640, and executes the work corresponding to the user input; and a setting window processing unit 514, which displays the automatic clock gating setting information of the clock management unit under design selected by the user and the setting information of the clock instance selected by the user in the setting window 650, and detects user input in the setting window 650 and executes the work corresponding to the user input.

[0117] When the CHECK button is selected, the command window processing unit 511 checks for errors in the clock diagram of the clock management unit under design and the setting values ​​of each clock instance, and displays the erroneous parts. When the UNCHECK button is selected, the erroneous parts displayed in the clock diagram of the clock management unit under design are restored to their original state and redisplayed. When the SAVE button is selected, the work content of the clock management unit under design displayed in the design window 640 is stored in the data storage repository 530. When the GENRTL button is selected, hardware code is generated for the clock diagram of the clock management unit under design displayed in the design window 640.

[0118] The content window processing unit 512 provides an environment for adding, deleting, and modifying the list of clock management units under design and the list of clock instances contained in each clock management unit under design. The content window processing unit 512 can display the list of clock instances and the register information of each clock instance in a hierarchical manner below each clock management unit under design. Users can perform operations such as adding, deleting, and renaming clock management units under design in the content window 630, and add, delete, or modify the list of clock management units under design in the clock management unit repository 532 based on user input. When a user changes the name of a clock management unit under design, the content window processing unit 512 can not only change the name of that clock management unit, but also simultaneously change the names of its subordinate clock instances and registers.

[0119] The design window processing unit 513 displays the clock diagram of the clock management unit under design in the design window 640, providing an environment for adding, deleting, and changing clock instances that constitute the clock management unit under design. When the user adds any clock component from the clock component window 620 to the design window 640, the design window processing unit 513 detects it and performs the clock instance appending operation.

[0120] The setting window processing unit 514 displays the automatic clock gating (ACG) setting information of the clock management unit under design, and detects user input in the setting window 650 to perform work corresponding to the user input.

[0121] Data repository 530

[0122] The data repository 530 may include: a clock component repository 531, which stores clock component information; a content repository 532, which stores a list of clock instances and a list of registers corresponding to the clock instances of the clock management unit under design; a clock management unit repository 533, which stores functional information of individual clock instances included in the clock management unit under design, scan controller instance information and test mode controller instance information included in the clock management unit under design; and a hardware code logic repository 534, which stores hardware code logic that generates hardware code based on the designed clock management unit information.

[0123] Clock components stored in clock component repository 531 may include phase-locked loop controller components, clock divider components, clock multiplexer components, and clock gating components. Each clock component includes a clock source block, a clock control circuit block, and a test multiplexer block. When a clock instance corresponding to a clock component is generated, each clock instance includes a clock source block, a clock control circuit block, and a test multiplexer block. The clock instance is implemented in hardware code and serves as... Figure 4 The clock element operates, with the clock source block, clock control circuit block, and test multiplexer block implemented in hardware code and serving as... Figure 4 The clock source, clock control circuit, and test multiplexer are in operation.

[0124] Content repository 532 stores the automatic clock gating (ACG) setting information of the clock management unit under design, as well as the list of clock instances included in the clock management unit under design and the register list corresponding to the clock instances.

[0125] The clock management unit repository 533 stores clock instance information, scan controller instance information, connection point information between the clock control circuit block of the clock instance and the scan controller instance, test mode controller instance information, and connection point information between the test multiplexer block of the clock instance and the test mode controller instance for each clock instance included in the clock management unit under design.

[0126] The hardware code logic repository 534 stores the hardware code logic generated based on the designed clock management unit information, the automatic clock gating setting information of the clock management unit, clock instance information, and register information. When a clock instance is generated in the form of hardware code, it can be fabricated into a clock element. Thus, the clock control circuit block, clock source block, and test multiplexer block of each clock instance can be implemented as... Figure 4 The clock element includes a clock control circuit, a clock source, and a test multiplexer. Furthermore, the scan controller instance and the test mode controller instance are respectively controlled via... Figure 4The scan controller and test mode controller are implemented, the clock control circuit can be connected to the scan controller, and the test multiplexer is connected to the test mode controller.

[0127] Clock Management Unit Processing Section 520

[0128] The clock management unit processing section 520 includes: a clock instance generation section 521, which generates a new clock instance based on clock component information, including a clock source block, a clock control circuit block, and a test multiplexer block; a scan controller instance generation section 522, connected to the clock control circuit block, which generates a scan controller instance that controls the reference clock supplied to the clock control circuit block in test mode; and a test mode controller instance generation section 523, connected to the test multiplexer block, which generates a test mode controller instance that outputs a test clock control signal to the test multiplexer block in test mode. The scan controller instance and the test mode controller instance are implemented in hardware code and used as... Figure 4 The scan controller and test mode controller are working.

[0129] The clock instance generation unit 521 can be executed and generate a new clock instance when the user adds any clock component to the clock component window 620 in the design window 640. The name of the new clock instance may include the name of the clock management unit under design that has the new clock instance and the clock component type information of the new clock instance. The clock instance may internally include a clock source block, a clock control circuit block, and a test multiplexer block.

[0130] When generating a clock instance without user input, the scan controller instance generation unit 522 can automatically operate and generate a scan controller instance, and the connection point between the scan controller instance and the clock control circuit block can be set. The scan controller instance and the clock control circuit block can be transformed and implemented separately in hardware code form. Figure 4 The scanning controller 460 and clock control circuits 412 and 422.

[0131] When generating a clock instance without user input, the test mode controller instance generation unit 523 can automatically operate and generate a test mode controller instance. The test mode controller instance may include a test mode test data register block and a test control test data register block. The test mode test data register block determines whether to activate the test mode of the test multiplexer block, and the test control test data register block provides test clock control signals to the test multiplexer block. The test mode controller instance generation unit 523 can generate a test control test data register block consisting of a trigger chain comprising the number of bits of the test clock control signal controlling the target test multiplexer. The test mode test data register block and the test control test data register block are implemented in hardware code and used as... Figure 4 The test mode operates the test data register and the test control test data register.

[0132] Test mode controller instances can be controllers based on the built-in IEEE1687 standard. Test mode test data register blocks and test control test data register blocks can be designed to be set separately through the internal joint test action group interface.

[0133] Hardware Code Processing Unit 540

[0134] The hardware code processing unit 540 may include: a clock hardware code generation unit 541, which generates hardware code corresponding to the functional module of the clock element based on the designed clock instance information; a scan controller hardware code generation unit 542, which generates hardware code corresponding to the scan controller based on the scan controller instance information; and a test mode controller hardware code generation unit 543, which generates hardware code corresponding to the test mode controller based on the test mode controller instance information.

[0135] The hardware code processing unit 540 can be executed when the GENRTL button in the command window 610 is selected. The user can select the GENRTL button to execute it while the clock diagram of the clock management unit under design is displayed in the design window 640. Before running the GENRTL button, the check button can be executed to pre-verify whether there are any errors in the clock diagram.

[0136] Figure 7 This diagram illustrates the workflow of the no-code clock management unit design method of the present invention. The no-code clock management unit design method of the present invention can be executed by a computer system's processor.

[0137] The computer system includes: a clock component repository for storing clock component information, including clock source blocks, clock control circuit blocks, and test multiplexer blocks; and a hardware code logic repository for storing hardware code logic for transforming the designed clock management unit into hardware code.

[0138] The processor generates a new clock instance, including a clock source block, a clock control signal block, and a test multiplexer block, based on clock component information (step S710). The processor sets the connection point between the clock source block and the test multiplexer block, and sets the connection point between the test multiplexer block and the clock control signal block.

[0139] The processor generates a scan controller instance that controls the reference clock in test mode and sets the connection point between the scan controller instance and the clock control circuit block (step S720).

[0140] The processor generates a test mode controller instance for generating test clock control signals in test mode (step S730). The test mode controller instance includes a test mode test data register block and a test control test data register block. The test control test data register block may be composed of flip-flop blocks corresponding to the number of control bits in the clock source block.

[0141] The processor sets the test mode, test data register block, and test control. The connection point between the test data register block and the test multiplexer block is set (step S740).

[0142] The processor generates the hardware code for the designed clock management unit based on the clock instance, scan controller instance, test mode controller instance, their connection point settings, and hardware code logic (step S750).

[0143] Figure 8 An exemplary computing device 800 is shown for performing the methods and / or embodiments described above. According to one embodiment, the computing device 800 may be implemented using hardware and / or software for user interaction. Here, the computing device 800 may include, but is not limited to, a laptop, desktop, workstation, personal digital assistant, server, blade server, mainframe, etc. The components of the computing device 800 described above, their interconnections, and their functions are merely illustrative and should not be construed as limiting the embodiments of the invention described and / or claimed herein.

[0144] The computing device 800 includes a processor 810, a memory 820, a storage device 830, a communication device 840, a high-speed interface 850 connected to the memory 820 and a high-speed expansion port, and a low-speed interface 860 connected to a low-speed bus and the storage device. The structural elements 810, 820, 830, 840, 850, and 860 can be interconnected using various buses, and can be installed on the same mainboard or connected through other suitable methods. The processor 810 can perform basic arithmetic, logic, and input / output operations, thereby processing computer program instructions. For example, the processor 810 can process instructions stored in the memory 820, storage device 830, etc., and / or instructions running within the computing device 800, thereby displaying graphical information on an external input / output device 870, such as a display device, combined with the high-speed interface 850.

[0145] The communication device 840 can provide a structure or function that enables the input / output device 870 and the computing device 800 to communicate with each other via a network, and can also provide a structure or function that enables the input / output device 870 and / or the computing device 800 to communicate with other external devices. For example, requests or data generated by the processor of an external device according to arbitrary program code can be transmitted to the computing device 800 via the network under the control of the communication device 840. Conversely, control signals or instructions provided under the control of the processor 810 of the computing device 800 can be transmitted to other external devices via the communication device 840 and the network.

[0146] Figure 8 The diagram shows a computing device 800 including a processor 810, a memory 820, etc., but it is not limited to these. The computing device 800 can be implemented using multiple memories, multiple processors, and / or multiple buses, etc. Furthermore, Figure 8 The diagram shows the presence of a computing device 800, but is not limited to this; multiple computing devices can interact and perform the necessary work to execute the method.

[0147] The memory 820 can store information within the computing device 800. According to one embodiment, the memory 820 can be composed of volatile memory cells or multiple memory cells. Alternatively or additionally, the memory 820 can be composed of non-volatile memory cells or multiple memory cells. Furthermore, the memory 820 can be composed of other forms of computer-readable media such as a magnetic disk or optical disk. The memory 820 can also store an operating system and at least one program code and / or instructions.

[0148] Storage device 830 can be at least one high-capacity storage device for storing data for computing device 800. For example, storage device 830 can be a computer-readable medium including, or may include, semiconductor storage devices such as hard disks, magnetic discs, optical discs, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory devices, CD-ROMs, and DVD-ROMs. Furthermore, computer programs can be tangibly implemented on such computer-readable media.

[0149] The high-speed interface 850 and the low-speed interface 860 can be units for interacting with the input / output device 870. For example, the input device may include a camera, keyboard, microphone, mouse, etc., with an audio sensor and / or image sensor, and the output device may include a display, speaker, haptic feedback device, etc. In other examples, the high-speed interface 850 and the low-speed interface 860 can be units for interfacing with a device that integrates input and output structures or functions, such as a touchscreen.

[0150] According to one embodiment, high-speed interface 850 can manage bandwidth-intensive tasks on computing device 800, while low-speed interface 860 can manage less bandwidth-intensive tasks than high-speed interface 850; however, this functional allocation is merely illustrative. According to one embodiment, high-speed interface 850 can be integrated into memory 820, input / output device 870, and a high-speed expansion port capable of accommodating various expansion cards (not shown). Furthermore, low-speed interface 860 can be integrated into storage device 830 and low-speed expansion port. Additionally, low-speed expansion cards, which may include various communication ports (e.g., USB, Bluetooth, IoT, wireless IoT), can be integrated into at least one input / output device 870 such as a keyboard, pointing device, or scanner, or integrated into a network device such as a router or switch via a network adapter.

[0151] The computing device 800 can be implemented in various different forms. For example, the computing device 800 can be implemented as a standard server or as a group of multiple such standard servers. Additionally or alternatively, the computing device 800 can be implemented as part of a rack server system, or as a personal computer such as a laptop computer. In this case, the structural elements of the computing device 800 can be combined with other structural elements within any mobile device (not shown). Such a computing device 800 may include at least one other computing device, or communicate with at least one other computing device.

[0152] Figure 8 The input / output device 870 shown is not included in the computing device 800, but is not limited thereto, and can be configured as a single device with the computing device 800. Furthermore, Figure 8 The high-speed interface 850 and / or low-speed interface 860 are shown as separate elements of the processor 810, but are not limited thereto; the high-speed interface 850 and / or low-speed interface 860 may be included in the processor 810.

[0153] The methods and / or various embodiments described herein can be implemented using digital electronic circuits, computer hardware, firmware, software, and / or combinations thereof. Various embodiments of the invention can be executed using a data processing apparatus, such as at least one programmable processor and / or at least one computer device, or can be implemented using a computer-readable medium and / or a computer program stored on that medium. The computer program can be written in any form of programming language, including compiled or interpreted languages, and can be distributed in any form, such as as standalone programs, modules, subroutines, etc. The computer program can be distributed using a single computing device, multiple computing devices connected via the same network, and / or multiple computing devices distributed across multiple different network connections.

[0154] The methods and / or various embodiments described herein can operate based on input data or generate output data, thereby being executed by at least one processor configured to run at least one computer program for processing, storing, and / or managing arbitrary functions, etc. For example, the methods and / or various embodiments of the present invention can be executed by special-purpose logic circuits such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs), and the apparatus and / or system for executing the methods and / or embodiments of the present invention can be implemented as special-purpose logic circuits such as field-programmable gate arrays or application-specific integrated circuits.

[0155] At least one processor running a computer program may include at least one processor of a general-purpose or special-purpose micro processor and / or any type of digital computing device. The processor may receive instructions and / or data from read-only memory and random access memory, respectively, or may receive instructions and / or data from both read-only memory and random access memory. In this invention, the structural elements of the computing device for executing methods and / or embodiments may include at least one processor for executing instructions and at least one memory for storing instructions and / or data.

[0156] According to one embodiment, the computing device can send and receive data with at least one mass storage device for storing data. For example, the computing device can receive data from and transfer data to a magnetic disc or optical disc. Computer-readable media suitable for storing instructions and / or data related to computer programs may include, but are not limited to, non-volatile memory of any form having a semiconductor storage device such as an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory device. For example, computer-readable media may include magnetic discs such as internal hard disks or removable disks, photomagnetic discs, CD-ROMs, and DVD-ROMs.

[0157] To provide interaction with the user, a computing device may include, but is not limited to, display devices that provide or display information to the user (e.g., cathode ray tubes (CRTs), liquid crystal displays (LCDs), etc.) and pointing devices that allow the user to provide input and / or commands to the computing device (e.g., keyboards, mice, trackballs, etc.). That is, the computing device may also include any other type of device for providing interaction with the user. For example, to interact with the user, the computing device may provide sensory feedback of any form, including visual feedback, auditory feedback, and / or tactile feedback. In this regard, the user can provide input to the computing device through various gestures such as vision, voice, and movement.

[0158] In this invention, various embodiments can be implemented in a computer device including back-end structural elements (e.g., a data server), middleware structural elements (e.g., an application server), and / or front-end structural elements. In this case, the structural elements can be interconnected through any form or medium of digital data communication, such as a communication network. According to one embodiment, the communication network can consist of wired networks such as Ethernet, Power Line Communication, telephone line communication devices, and RS-serial communication; mobile communication networks; wireless local area networks (WLANs); Wi-Fi; Bluetooth; and wireless networks such as ZigBee, or combinations thereof. For example, the communication network may include local area networks (LANs), wide area networks (WANs), etc.

[0159] The computing device based on the exemplary embodiments described in this specification can be implemented using hardware and / or software that includes user equipment, user interface (UI) devices, user terminals, or client devices for interacting with a user. For example, the computing device may include portable computing devices such as laptop computers. Additionally or alternatively, the computing device may be a personal digital assistant (PDA), tablet computer, game console, wearable device, Internet of Things (IoT), virtual reality (VR), augmented reality (AR), etc., but is not limited thereto. The computing device may also include other types of devices for interacting with a user. Furthermore, the computing device may include portable communication devices (e.g., mobile phones, smartphones, wireless cellular phones, etc.) suitable for wireless communication via networks such as mobile communication networks. The computing device can communicate wirelessly with a network server using wireless communication technologies and protocols such as radio frequency (RF), microwave frequency (MWF), and / or infrared ray frequency (IRF).

[0160] In this invention, various embodiments, including specific structural and functional details, are illustrative examples. Therefore, the embodiments of this invention are not limited to the described content, but can be embodied in many different forms. Furthermore, the terminology used in this invention is used to describe some embodiments, not to limit the embodiments. For example, unless explicitly stated in the context, singular words include plural forms.

[0161] In this invention, unless otherwise defined, all terms used in this specification, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, the meanings of commonly used terms, such as those defined in dictionaries, are the same as their meanings within the same technical context.

[0162] In this specification, the invention has been described in connection with some embodiments. It is to be understood that those skilled in the art can make various modifications and alterations without departing from the scope of this invention. Furthermore, such modifications and alterations should fall within the scope of protection of the appended claims.

[0163] This study was supported by the Ministry of Small and Medium-sized Enterprises. This research was funded by the Korea Technology and Information Promotion Agency for SMEs (TIPA) through the Korea Technology and Information Promotion Agency for SMEs. (Project No.: 1425182152; Project No.: RS-2023-00302523; Research Project Title: Startup Growth Technology Development (R&D); Research Topic Title: Low-Code-Based Semiconductor Low-Power Solution; Implementing Agency: ITDA Semiconductor; Research Period: July 1, 2023 to June 30, 2026). The Government of the Republic of Korea does not own any intellectual property rights in any aspect of this invention concept.

Claims

1. A no-code clock management unit design system for designing a clock management unit in a no-code manner, comprising: a memory for storing at least one instruction; a clock component repository storing clock component information constituting a clock management unit; a hardware code logic repository storing hardware code logic for generating a designed clock management unit into hardware code; and at least one processor for executing the at least one instruction stored in the memory, wherein the at least one instruction comprises: an instruction for generating a clock instance comprising a clock source block, a clock control signal block, and a test multiplexer block based on the clock component information; an instruction for generating a test mode controller instance comprising a test mode test data register block corresponding to the test multiplexer block and a test control test data register block; an instruction for setting a connection point of the test multiplexer block and the test mode controller instance; and an instruction for generating hardware code based on the clock instance, the test mode controller instance, connection point information, and the hardware code logic. The at least one instruction comprises: an instruction for generating a scan controller instance corresponding to the clock control signal block; an instruction for setting a connection point of the clock control signal block and the scan controller instance; and an instruction for generating hardware code based on the scan controller instance and connection point information and the hardware code logic. The test mode controller instance is based on an IEEE 1687 standard implementation. 4.The no-code clock management unit design system of claim 1, wherein the test mode test data register block activates or deactivates a test mode, and the test control test data register block generates a test clock control signal in the test mode. The test control test data register block is constituted by a number of flip-flop blocks corresponding to a number of control bits of the clock source block. The test mode test data register block and the test control test data register block are respectively set through an internal Joint Test Action Group interface. The clock component is one of a phase-locked loop controller component, a clock divider component, a clock multiplexer component, and a clock gating component. 8.A no-code clock management unit design method executed by at least one processor in a computer system comprising a clock component repository storing clock component information constituting a clock management unit and a hardware code logic repository storing hardware code logic for generating a designed clock management unit into hardware code, the no-code clock management unit design method comprising: generating a clock instance comprising a clock source block, a clock control signal block, and a test multiplexer block based on the clock component information; generating a test mode controller instance comprising a test mode test data register block corresponding to the test multiplexer block and a test control test data register block; and generating hardware code based on the clock instance, the test mode controller instance, connection point information, and the hardware code logic. ​ ​ ​ 2. The no-code way clock management unit design system of claim 1, wherein, ​ ​ ​ ​ 3. The no-code way clock management unit design system of claim 1, wherein, ​ ​ ​ ​ 5. The no-code way clock management unit design system of claim 4, wherein, ​ 6. The no-code clock management unit design system of claim 1, wherein, ​ 7. The no-code way clock management unit design system of claim 1, wherein, ​ ​ ​ ​ setting connection points of the test multiplexer block and the test mode controller instance; and generating hardware code based on the clock instance, the test mode controller instance, connection point information and the hardware code logic.

9. The no-code approach to clock management unit design method of claim 8, wherein, Further comprising the following steps: generating a scan controller instance corresponding to the clock control signal block; setting connection points of the clock control signal block and the scan controller instance; and generating hardware code based on the scan controller instance and connection point information and the hardware code logic.

10. The no-code approach to clock management unit design method of claim 8, wherein, The test mode controller instance is based on the built-in IEEE1687 standard implementation.

11. The codeless clock management unit design method of claim 8, wherein the test mode test data register block activates or deactivates a test mode, the test control test data register block generates a test clock control signal in the test mode.

12. The no-code approach to clock management unit design method of claim 11, wherein, The test control test data register block is composed of a number of flip-flop blocks controlled by the clock source block.

13. The no-code approach to clock management unit design method of claim 8, wherein, The test mode test data register block and the test control test data register block are respectively set through an internal joint test action group interface.

14. The no-code approach to clock management unit design method of claim 8, wherein, The clock component is one of a phase-locked loop controller component, a clock divider component, a clock multiplexer component, and a clock gating component.

15. A computer program, characterized in that, A computer readable storage medium storing the method according to any one of claims 8 to 14 for execution in a computer.

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