A standard cell timing library simulation system, method and computer device

Abstract

The application provides a standard cell timing library simulation system, method and computer equipment, the system comprises: a parsing control module, used for executing a Tcl script to start a characterization process, and obtaining an extended command and a parameter in the Tcl script, and performing syntax analysis and basic database import on each command and parameter; a pre-simulation engine, used for initializing all cells to be characterized, so that each cell to be characterized becomes a characterizable state; a main simulation engine, used for calling a SPICE simulator, characterizing timing arcs of all initialized cells to be characterized, extracting model data of timing, power consumption and noise and storing the model data into a model database; and a modeling engine, used for reading the basic database and the model database and outputting an output file in a specific format. The scheme can realize efficient and automatic simulation and modeling of a standard cell timing library, and has good functional expandability and ease of use.

Description

Technical Field

[0001] This invention relates to the field of simulation system technology, and more particularly to a standard cell timing library simulation system, method, and computer equipment. Background Technology

[0002] In digital circuit back-end design, "standard cells" are the cornerstone of chip physical implementation. They are a set of pre-designed, verified "modular" circuit units with uniform height (multiple bit widths) and fixed pin positions.

[0003] Semi-custom design based on standard cells is an integrated circuit design method that can effectively shorten the design cycle. Its key feature is the pre-design of some basic cells and even modules with fairly complex functions (such as logic gates and flip-flops), establishing a standard cell library. During ASIC system design, these cell modules can be directly called and combined, thus achieving a good balance between performance and efficiency. A complete standard cell library typically includes the cell's schematic diagram, layout, timing library files (.lib), etc., where the timing library mainly describes the electrical characteristics of the cell, including lookup table models for timing, power consumption, and noise.

[0004] However, few mature commercial tools on the market can achieve fully automated library construction for various types of standard cells under different PVT conditions, and their support for timing, power consumption, and noise models is also incomplete. Most existing tools only cover point-level functions, lacking ease of use and functional extensibility. From the circuit netlist to the final generation of the .lib file, manual intervention is required to varying degrees, which increases time costs and the risk of errors, especially given the large number of libraries and cells. Therefore, there is an urgent need for a more automated method for constructing standard cell timing libraries that can adapt to diverse representation needs. Summary of the Invention

[0005] The purpose of this invention is to provide a standard cell timing library simulation system, method, and computer equipment that can achieve efficient and automated simulation and modeling of standard cell timing libraries, adapt to various characterization needs, construct complete timing, power consumption, and noise models, generate standard .lib timing library files, and has good functional scalability and ease of use.

[0006] The technical solution provided by this invention is as follows:

[0007] In a first aspect, this application provides a standard cell timing library simulation system, comprising:

[0008] The parsing control module is used to obtain the simulation input file input by the user, execute the Tcl script to start the characterization process, and obtain the extended commands and extended parameters in the Tcl script, and perform syntax parsing and basic database import for each of the extended commands and extended parameters.

[0009] The pre-simulation engine is used to initialize all the units to be represented, making each unit a representative state.

[0010] The main simulation engine is used to call the SPICE simulator to characterize the timing arcs of all units to be characterized after initialization, extract the model data of timing, power consumption, and noise, and store them in the model database.

[0011] The modeling engine is used to read the base database and the model database, generate timing, power consumption, and noise models, and output output files in a specific format.

[0012] In some implementations, the simulation input files include the device's SPICE model netlist file, cell subcircuit netlist file, and Tcl configuration file.

[0013] In some implementations, the parsing control module performs syntax parsing on each of the extended commands and the extended parameters to obtain the data structures of each of the extended commands and the extended parameters and stores them in the basic database. At the same time, it obtains the basic information of all units to be represented according to the extended commands and stores it in the basic database.

[0014] In some implementations, the pre-simulation engine includes:

[0015] The unit initialization module is used to initialize the basic information of each unit to be represented and to determine whether each unit to be represented is a combinational logic unit or a sequential logic unit.

[0016] The circuit topology identification module is used to perform topology analysis on the cell netlist corresponding to each cell to be represented, and extract the connection relationship and signal path between each channel connected block inside each cell to be represented.

[0017] The logic function identification module is used to call the SPICE simulator to perform unit simulation, extract the truth table of each unit to be represented, and the monotonicity between input and output pins; when the unit to be represented is a combinational logic unit, each output can be represented as a Boolean function of the input signal; when the unit to be represented is a sequential logic unit, it identifies the effective edge or effective level of the clock and represents the next state of the output as a Boolean function of the input and the current state.

[0018] The vector generation module initializes the timing arcs of all units to be represented based on the recognition results of the logic function recognition module and the circuit topology recognition module, as well as the extended commands.

[0019] The circuit segmentation module determines the circuit composition of the first and last level channel connected blocks based on the connection relationship between each channel connected block inside each unit to be characterized identified by the circuit topology recognition module.

[0020] In some implementations, the main simulation engine includes:

[0021] The pin state determination module is used to determine the state of each pin or node in each unit to be characterized.

[0022] The folder creation module is used to instantiate netlists and create a separate representation folder for each representation;

[0023] The representation netlist configuration module is used to configure the parameters of the representation netlist according to different representation types;

[0024] The simulation module is used to call the SPICE simulator to simulate the representation netlist;

[0025] The extraction module is used to extract the timing, power consumption, and noise model data of various types of units from the simulation results and store them in the model database.

[0026] In some implementations, the output file in the specific format includes standard .lib time series library files and datasheet files;

[0027] The modeling engine is also used to generate Tcl template files based on the extended commands and extended parameters in the basic database, for representing the repetitive configuration of the process.

[0028] Secondly, this application provides a standard cell timing library simulation method, including the following steps:

[0029] Obtain the simulation input file input by the user, which includes the device's SPICE model netlist file, cell subcircuit netlist file, and Tcl configuration file;

[0030] Execute the Tcl script to start the characterization process;

[0031] Obtain the extended commands and extended parameters in the Tcl script, and perform syntax parsing and basic database import for each extended command and extended parameter;

[0032] Initialize all units to be represented, making each unit a representative state.

[0033] The SPICE simulator is invoked to characterize the timing arcs of all units to be characterized after initialization, and the model data of timing, power consumption, and noise are extracted and stored in the model database.

[0034] Read the basic database and the model database, generate timing, power consumption, and noise models, and output a specific formatted output file.

[0035] In some implementations, the initialization of all units to be characterized, making each unit representative, specifically includes:

[0036] The basic information of each unit to be represented is initialized, and it is determined whether each unit to be represented is a combinational logic unit or a sequential logic unit.

[0037] A topology analysis is performed on the netlist of each cell to be characterized to extract the connection relationships and signal paths between each channel connected component within each cell to be characterized.

[0038] The SPICE simulator is called to perform cell simulation, extract the truth table of each cell to be represented and the monotonicity between the input and output pins; when the cell to be represented is a combinational logic cell, each output can be represented as a Boolean function of the input signal; when the cell to be represented is a sequential logic cell, the effective edge or effective level of the clock is identified, and the next state of the output is represented as a Boolean function of the input and the current state.

[0039] Based on the logical function identification results, topology identification results, and the extended commands of each unit to be represented, the timing arcs of all units to be represented are initialized.

[0040] Based on the connection relationship between the channel connected blocks within each unit to be characterized, the circuit composition of the first and last stage channel connected blocks is determined.

[0041] In some implementations, the step of calling the SPICE simulator to characterize the timing arcs of all initialized cells to be characterized, extracting the timing, power consumption, and noise model data, and storing them in the model database specifically includes:

[0042] Determine the state of each pin or node in each unit to be characterized;

[0043] Instantiate the netlist and create a separate representation folder for each representation;

[0044] Configure the parameters of the representation netlist according to different representation types;

[0045] The SPICE simulator is invoked to simulate the characterization netlist;

[0046] The timing, power consumption, and noise model data of each type of unit are extracted from the simulation results and stored in the model database.

[0047] Thirdly, this application provides a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the standard cell timing library simulation method described in the second aspect.

[0048] According to the standard cell timing library simulation system, method, and computer equipment provided by the present invention, only the device SPICE model file, cell subcircuit netlist file, and Tcl configuration file need to be provided by the user to complete the entire process, including cell analysis, logic topology identification, timing arc vector generation, simulation execution, modeling and library construction, and finally generate a standard .lib timing library file. At the same time, the user can also use a large number of Python-Tcl extension commands and parameters in the Tcl script to freely configure the representation process, adjust the algorithms, parameters, and function options of each step, etc., to adapt to various representation needs, and has good functional scalability and ease of use. Attached Figure Description

[0049] The preferred embodiments will now be described in a clear and easy-to-understand manner, with reference to the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages, and implementation methods of this solution.

[0050] Figure 1 This is a schematic diagram of the overall structure of one embodiment of the present invention;

[0051] Figure 2 This is a schematic diagram of the system characterization link according to an embodiment of the present invention;

[0052] Figure 3 This is a schematic diagram of the overall process of one embodiment of the present invention.

[0053] Numbering on the map:

[0054] 10-Analysis Control Module; 20-Pre-simulation Engine; 21-Unit Initialization Module; 22-Circuit Topology Recognition Module; 23-Logic Function Recognition Module; 24-Vector Generation Module; 25-Circuit Segmentation Module; 30-Main Simulation Engine; 31-Pin State Determination Module; 32-Folder Creation Module; 33-Characteristic Netlist Configuration Module; 34-Simulation Module; 35-Extraction Module; 40-Modeling Engine; 50-Basic Database; 60-Model Database. Detailed Implementation

[0055] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0056] To keep the drawings concise, only the parts relevant to the invention are shown schematically in each figure, and they do not represent the actual structure of the product. Furthermore, for ease of understanding, in some figures, only one of components with the same structure or function is shown schematically, or only one is labeled. In this document, "one" can mean not only "only one" but also "more than one".

[0057] In digital circuit back-end design, "standard cells" are the cornerstone of chip physical implementation. They are a set of pre-designed, verified, modular circuit units with uniform height (multiple bit widths are possible) and fixed pin positions. Semi-custom design based on standard cells is an integrated circuit design method that can effectively shorten the design cycle. Its characteristic is the pre-design of some basic units and even modules with fairly complex functions (such as logic gates and flip-flops), establishing a standard cell library. These unit modules can be directly called and combined during ASIC system design, thus achieving a good balance between performance and efficiency. For advanced process nodes, to meet design requirements including low power consumption, the number of libraries, as well as the types and quantities of cells, that wafer fabs need to provide under different PVT conditions are increasing significantly. Therefore, establishing a standard cell library for a specific process technology is a very time-consuming and labor-intensive task.

[0058] A complete standard cell library typically includes the cell's schematic, layout, and timing library files (.lib). The timing library primarily describes the cell's electrical characteristics, containing lookup table models for timing, power consumption, and noise. The model data comes from post-simulation verification of the cells. After extracting the cell's parasitic parameters, transistor-level simulations are performed under different boundary conditions (such as input signal slope and output load) to construct interpolation tables. These data-based lookup table models are subsequently used in the STA (Static Timing Analysis) of post-chip simulation.

[0059] Regarding the establishment of the aforementioned cell timing libraries, few mature commercial tools on the market can achieve fully automated library construction for various types of standard cells under different PVT conditions, and their support for timing, power consumption, and noise models is also incomplete. Most existing tools only cover point-level functions, lacking ease of use and functional extensibility. From the circuit netlist to the final generation of the .lib file, manual intervention is required to varying degrees, which increases time costs and the risk of errors, especially given the large number of libraries and cells. Therefore, while building a more user-friendly standard cell timing library simulation and modeling system that can adapt to diverse representation needs is technically more challenging, it is undoubtedly of significant importance to the industry's development.

[0060] This application utilizes Tcl scripts to extend commands and parameters, enabling flexible configuration of the characterization process. It also parses the options or values ​​of various extended commands and parameters, storing them in a basic database. This database can then be used to control subsequent characterization stages, with control methods and levels customizable as needed. Based on relevant commands, parameters, and pre-simulation results from the basic database, it can efficiently and accurately characterize all instantiated timing arcs. By reading all data from the basic and model databases and applying relevant extended commands, it can automatically generate timing, power consumption, and noise models for standard cells, outputting specific format files such as standard .lib timing library files and datasheet files, completing the entire simulation and model building process for the standard cell timing library. This solution not only improves the automation level of characterization and ensures the speed, completeness, and accuracy of library construction, but also achieves good user interactivity and subsequent functional expandability, facilitating application and maintenance. The following is a detailed description of this solution with reference to the accompanying drawings:

[0061] In one embodiment, refer to the appendix to the specification. Figure 1 and attached Figure 2 This application provides a standard cell timing library simulation system, including a parsing control module 10, a pre-simulation engine 20, a main simulation engine 30 and a modeling engine 40, and also includes a basic database 50 and a model database 60.

[0062] The parsing control module 10 is used to acquire the simulation input file input by the user, execute the Tcl script to start the characterization process, and sequentially call the pre-simulation engine 20, the main simulation engine 30, and the modeling engine 40 according to the extended commands to complete the extraction of unit features. The simulation input file includes the SPICE model netlist file of the device input by the user, the unit sub-circuit netlist file, and the Tcl configuration file.

[0063] The parsing control module 10 is also used to obtain extended commands and extended parameters in Tcl scripts, and to perform syntax parsing and basic database import for each extended command and extended parameter.

[0064] The pre-simulation engine 20 initializes all units to be characterized, making each unit representative. The main simulation engine 30 calls the SPICE simulator to characterize the timing arcs of all initialized units, extracting timing, power, and noise model data and storing them in the model database 60. The modeling engine 40 reads the basic database 50 and the model database 60, generates timing, power, and noise models, and outputs a specific formatted output file. Parallel processing can be used for different units and timing arcs to improve characterization efficiency.

[0065] This solution requires only the user to provide the device SPICE model file, cell subcircuit netlist file, and Tcl configuration file. It can complete the entire process, including cell analysis, logic topology identification, timing arc vector generation, simulation execution, modeling and library construction, ultimately generating a standard .lib timing library file. Furthermore, users can freely configure the characterization process within the Tcl script using numerous Python-Tcl extension commands and parameters, adjusting algorithms, parameters, and function options for each step. For example, they can define different table templates for timing, power consumption, and noise models, set temperature and voltage conditions, configure timing arcs, modify the output details of the timing library file, and even select different SPICE simulators. This allows the solution to adapt to various characterization needs, exhibiting excellent functional scalability and ease of use.

[0066] Users need to prepare three types of input files locally:

[0067] 1) The SPICE model netlist file (.sp) of the device needs to use the .model statement block to declare the MOSFET model used and complete the parameter extraction work in advance. Alternatively, the .LIB structure can be used to encapsulate the model parameters corresponding to different process corners.

[0068] 2) The sub-circuit netlist file (.sp) of the cell contains only the cell circuit topology declared by the .subckt statement block, including MOSFET model instances and extracted cell parasitic parameters.

[0069] 3) Tcl configuration file: Using the extended Tcl scripting language, users can easily configure the represented process, parameters, etc. in detail.

[0070] In one embodiment, based on the foregoing embodiment, the parsing control module 10 is used to perform syntax parsing on each extended command and extended parameter, obtain the data structure of each extended command and extended parameter and store it in the basic database 50, and at the same time obtain the basic information of all units to be represented according to the extended commands and store it in the basic database 50.

[0071] The parsing control module 10 can implement a large number of easy-to-use extended commands and parameters through the Python-Tcl interface. Extended commands generally adopt the syntax format of command [-option]|[-key value] [obj], that is, command can be followed by [-option] option parameters or [-key value] key-value pair parameters as needed, and the target object [obj] can also be added at the end; extended parameters are implemented using the dedicated command set_var [var_name][value], which has a high degree of customizability.

[0072] The parsing control module 10 parses the options or values ​​of various extended commands and parameters, storing them in the basic database 50. This database is used to control the characterization in subsequent stages, and the control method and level can be customized as needed. Using extended commands, basic information about all cells to be characterized can be obtained, such as the SPICE model of the specific process used and the cell sub-circuit connections (reading .sp files), temperature and voltage conditions, cell pin or node information (input, output, power supply, synchronous clock, asynchronous, internal nodes, etc.), power networks, and templates for various lookup models (cell delay, timing constraints, power consumption, ECSM voltage threshold, noise template), which are also stored in the basic database. Simultaneously, using extended commands, other module engines (pre-simulation engine, main simulation engine, modeling engine) can be called sequentially to complete the extraction of cell features.

[0073] In one embodiment, based on the foregoing embodiments, the pre-simulation engine 20 includes:

[0074] The unit initialization module 21 is used to initialize the basic information of each unit to be represented and to determine whether each unit to be represented is a combinational logic unit or a sequential logic unit.

[0075] The circuit topology identification module 22 is used to perform topology analysis on the cell netlist corresponding to each cell to be characterized, and extract the connection relationship and signal path between each channel connected block inside each cell to be characterized.

[0076] The logic function identification module 23 is used to call the SPICE simulator to perform unit simulation, extract the truth table of each unit to be represented and the monotonicity between the input and output pins; when the unit to be represented is a combinational logic unit, each output can be represented as a Boolean function of the input signal; when the unit to be represented is a sequential logic unit, it identifies the effective edge or effective level of the clock and represents the next state of the output as a Boolean function of the input and the current state.

[0077] The vector generation module 24 initializes the timing arcs of all units to be represented based on the recognition results of the logic function recognition module 23 and the circuit topology recognition module 22, as well as the extended commands.

[0078] The circuit segmentation module 25 determines the circuit composition of the first and last level channel connected blocks based on the connection relationship between each channel connected block inside each unit to be characterized identified by the circuit topology recognition module.

[0079] Specifically, before formal characterization begins, the pre-simulation engine 20 needs to perform a series of pre-operations on the elements to make them characterizable, including:

[0080] 1) Unit initialization: Instantiate each unit to be represented, initialize the basic information of each unit to be represented, and determine whether it is combinational logic or sequential logic, etc.

[0081] 2) Circuit topology identification: Perform topology analysis on the cell netlists stored in the basic database to extract the connection relationships and signal paths between the various channel connected blocks (CCBs) within the cell.

[0082] 3) Logic function identification: A series of simulation tasks are executed using the SPICE simulator to extract the truth table of the unit, the unateness (monotonicity) between input and output pins, etc., to determine the logic function. For combinational logic units, each output can be represented as a Boolean function of the input signal; for sequential logic units, the effective edge or effective level of the clock can be identified, and the next state of the output can be represented as a Boolean function of the input and the current state.

[0083] 4) Vector generation: Based on the results of logic and topology identification and extended commands, the timing arcs of all cells that need to be represented can be initialized, i.e., vector generation is performed. Supported representation types include delay timing arcs, power timing arcs, hidden timing arcs, constraint timing arcs, noise timing arcs, and static power vectors, etc.

[0084] 5) Circuit Segmentation: In CCSN noise simulation, it is usually only necessary to characterize the first and last two stages of CCB to save time. Therefore, circuit segmentation is required. The pre-simulation engine will determine the circuit composition after segmentation based on the aforementioned circuit topology analysis function. In addition, this module will properly handle the equivalent boundary conditions of the internal nodes exposed by the segmentation, such as calculating the equivalent load capacitance, thereby ensuring the electrical equivalence of the segmented circuit.

[0085] The analysis results of the pre-simulation engine 20 will also be stored in the basic database 50.

[0086] In one embodiment, based on the foregoing embodiments, the main simulation engine 30 includes:

[0087] Pin state determination module 31 is used to determine the state of each pin or node in each unit to be characterized;

[0088] The folder creation module 32 is used to instantiate netlists and create a separate representation folder for each representation.

[0089] The characterization netlist configuration module 33 is used to configure the parameters of the characterization netlist according to different characterization types;

[0090] Simulation module 34 is used to call the SPICE simulator to simulate the characterization netlist;

[0091] Extraction module 35 is used to extract the timing, power consumption, and noise model data of each type of unit from the simulation results and store them in the model database.

[0092] Specifically, the main simulation engine 30 can efficiently and accurately characterize all instantiated time-series arcs based on relevant commands, parameters, and pre-simulation results of units in the basic database 50. The characterization of each time-series arc involves the following steps:

[0093] 1) Determine the state of each pin of the unit, such as whether it is in a steady-state high level ('1'), a steady-state low level ('0'), connected to a rising signal source ('rise'), connected to a falling signal source ('fall'), or connected to a load capacitor ('output_c'), etc., so as to quickly build the external connections of the complete test circuit and the initial state declared by .nodeset or .ic.

[0094] 2) Instantiate the netlist and create a separate representation folder.

[0095] 3) Configure netlist details according to different representation types, including simulation settings (.option), process corner conditions (.param, .temp), parameterized signal source and load values ​​(.param), simulation statements (.dc, .ac, .tran), measurement statements (.meas), print statements (.print), and parameter scans for signal slope / load (.alter), etc. For the representation of a certain type of timing arc or model, the tool has default configuration methods to ensure the correctness and universality of the test netlist, but it also provides some extended commands or parameter interfaces, allowing users to modify details to meet broader needs, such as modifying simulation settings, selecting signal source waveforms (piecewise linear, linear and exponential splicing, custom, etc.), and modifying measurement voltage thresholds, etc.

[0096] 4) Use the SPICE simulator to simulate the netlist. The simulator to be used can be specified via specific commands in the Tcl file, facilitating comparison of the performance and accuracy of different simulators.

[0097] 5) Extract the original datasets for various lookup table models from the simulation result files, perform post-processing on the data if necessary, and store the results in the model database. Different simulators have different result file formats, but the result extraction module supports all of them.

[0098] Based on the above characterization process, this simulation tool can effectively extract various timing, power consumption, and noise models for different types of standard cells. The program characterizes delay timing arcs, power consumption timing arcs, hidden timing arcs, constraint timing arcs, and static power vectors by default. It extracts NLDM delay models and pin capacitance models from delay timing arcs, NLPM dynamic power consumption models from delay or power consumption timing arcs, NLDM pin capacitance models and NLPM dynamic power consumption models from hidden timing arcs, timing constraint models satisfied by timing cells from constraint timing arcs, and static power consumption models from static power vectors. Furthermore, users can further characterize CCS and ECSM delay and capacitance models, CCSP and ECSMP dynamic power consumption and parasitic models, as well as NLDM and CCSN noise models through extended commands. Since different timing arcs of different cells are independent in most cases, parallel processing techniques can be used to execute related characterization tasks, thereby improving the efficiency of library construction.

[0099] In one embodiment, based on the foregoing embodiments, the output file in a specific format includes a standard .lib timing library file and a datasheet file, both of which may optionally include specified timing, power consumption, and noise models. The modeling engine is also used to generate Tcl template files based on extended commands and parameters in the base database for characterizing repetitive configurations of the process.

[0100] In one embodiment, refer to the appendix to the specification. Figure 3 This application provides a standard cell timing library simulation method, including the following steps:

[0101] S100. Obtain the simulation input file input by the user. The simulation input file includes the device's SPICE model netlist file, the cell sub-circuit netlist file, and the Tcl configuration file.

[0102] S200, Execute the Tcl script to start the characterization process;

[0103] S300: Obtain extended commands and parameters from the Tcl script, and perform syntax parsing and basic database import for each extended command and parameter;

[0104] S400. Initialize all units to be characterized, so that each unit to be characterized becomes a characterizable state.

[0105] S500 calls the SPICE simulator to characterize the timing arcs of all units to be characterized after initialization, extracts the model data of timing, power consumption, and noise, and stores them in the model database.

[0106] S600 reads the basic database and model database, generates timing, power consumption, and noise models, and outputs output files in a specific format.

[0107] This solution requires only the user to provide the device SPICE model file, cell subcircuit netlist file, and Tcl configuration file to complete the entire process, including cell analysis, logic topology identification, timing arc vector generation, simulation execution, modeling and library construction, ultimately generating a standard .lib timing library file. Furthermore, users can freely configure the representation process in the Tcl script, adjusting the algorithms, parameters, and function options for each step, making this solution adaptable to various representation needs and possessing excellent functional scalability and ease of use.

[0108] In some implementations, all units to be characterized are initialized to make each unit in a characterizable state, specifically including:

[0109] S410. Initialize the basic information of each unit to be represented, and determine whether each unit to be represented is a combinational logic unit or a sequential logic unit.

[0110] S420. Perform topology analysis on the netlist of each cell to be characterized, and extract the connection relationship and signal path between each channel connected block inside each cell to be characterized.

[0111] S430. Perform logic function identification on each unit to be represented, that is, call the SPICE simulator to perform unit simulation, extract the truth table of each unit to be represented and the monotonicity between input and output pins; when the unit to be represented is a combinational logic unit, each output can be represented as a Boolean function of the input signal; when the unit to be represented is a sequential logic unit, identify the effective edge or effective level of the clock, and represent the next state of the output as a Boolean function of the input and the current state.

[0112] S440. Based on the logical function identification results, topology identification results, and extended commands of each unit to be represented, initialize the timing arc of all units to be represented.

[0113] S450. Based on the connection relationship between each channel connected block inside each unit to be characterized, determine the circuit composition of the first and last stage channel connected blocks.

[0114] In some implementations, the SPICE simulator is invoked to characterize the timing arcs of all initialized cells to be characterized, extracting the timing, power consumption, and noise model data and storing them in the model database. Specifically, this includes:

[0115] S510. Determine the state of each pin or node in each unit to be characterized.

[0116] S520, instantiate the netlist, and create a separate representation folder for each representation;

[0117] S530. Configure the parameters of the representation netlist according to different representation types;

[0118] S540. Call the SPICE simulator to simulate the characterization netlist;

[0119] S550 extracts the timing, power consumption, and noise model data of each type of unit from the simulation results and stores them in the model database.

[0120] In one embodiment, this application provides a computer device including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the standard cell timing library simulation method of the foregoing embodiments.

[0121] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A standard cell timing library simulation system, characterized by, The method comprises the following steps: The analysis control module is used for obtaining the simulation input file input by the user, executing the Tcl script to start the characterization process, and obtaining the extension command and the extension parameter in the Tcl script, and performing syntax analysis and basic database import on each of the extension command and the extension parameter; the simulation input file comprises a SPICE model netlist file of a device, a unit sub-circuit netlist file and a Tcl configuration file; The pre-simulation engine is used for initializing all units to be characterized, so that each unit to be characterized becomes a state that can be characterized; The main simulation engine is used for calling the SPICE simulator to characterize the timing arcs of all the initialized units to be characterized, and extracting the model data of timing, power consumption and noise and storing the model data into a model database; The modeling engine is used for reading the basic database and the model database, generating timing, power consumption and noise models, and outputting output files in a specific format; The pre-simulation engine comprises: The unit initialization module is used for initializing the basic information of each unit to be characterized, and judging whether each unit to be characterized is a combinational logic unit or a timing logic unit; The circuit topology identification module is used for performing topology structure analysis on the unit netlist corresponding to each unit to be characterized, and extracting the connection relationship between each channel connected block in each unit to be characterized and the signal path; The logic function identification module is used for calling the SPICE simulator to perform unit simulation, extracting the truth table of each unit to be characterized and the monotonicity between the input and output pins; when the unit to be characterized is a combinational logic unit, each output can be represented as a Boolean function of the input signal; when the unit to be characterized is a timing logic unit, the effective edge or effective level of the clock is identified, and the output next state is represented as a Boolean function of the input and present state; The vector generation module initializes the timing arcs of all units to be characterized based on the identification results of the logic function identification module and the circuit topology identification module and the extension command; The circuit segmentation module determines the circuit composition of the first and last channel connected blocks based on the connection relationship between each channel connected block in each unit to be characterized identified by the circuit topology identification module.

2. The standard cell timing library simulation system of claim 1, wherein, The analysis control module performs syntax analysis on each of the extension command and the extension parameter, obtains the data structure of each of the extension command and the extension parameter and stores the data structure into the basic database, and obtains the basic information of all units to be characterized according to the extension command and stores the basic information into the basic database.

3. The standard cell timing library simulation system of claim 1, wherein, The main simulation engine comprises: The pin state determination module is used for determining the state of each pin or node in each unit to be characterized; The folder creation module is used for instantiating the netlist and creating an independent characterization folder for each characterization; The characterization netlist configuration module is used for performing parameter configuration of the characterization netlist according to different characterization types; The simulation module is used for calling the SPICE simulator to simulate the characterization netlist; The extraction module is used for extracting the model data of timing, power consumption and noise of each type of unit from the simulation result and storing the model data into the model database.

4. The standard cell timing library simulation system of claim 1, wherein, The output file in the specific format includes a standard.lib timing library file and a Datasheet data table file. The modeling engine is further configured to generate a Tcl template file according to the extension commands and the extension parameters in the basic database, so as to characterize the repetitive configuration of the flow.

5. A standard cell timing library simulation method, characterized by, The method comprises the steps of: obtaining a simulation input file input by a user, the simulation input file comprising a SPICE model netlist file of a device, a unit sub-circuit netlist file and a Tcl configuration file; executing a Tcl script to start a characterization flow; obtaining extension commands and extension parameters in the Tcl script, and performing syntax analysis and basic database import on each of the extension commands and the extension parameters; initializing all units to be characterized, so that each unit to be characterized is in a state of being characterizable; calling a SPICE simulator to characterize timing arcs of all the initialized units to be characterized, and extracting model data of timing, power consumption and noise and storing the model data into a model database; reading the basic database and the model database, generating timing, power consumption and noise models, and outputting output files in a specific format; the step of initializing all units to be characterized, so that each unit to be characterized is in a state of being characterizable, specifically comprises: initializing basic information of each unit to be characterized, and judging whether each unit to be characterized is a combinational logic unit or a timing logic unit; performing topological structure analysis on a unit netlist corresponding to each unit to be characterized, and extracting a connection relationship between each channel communication block in each unit to be characterized and a signal path; calling a SPICE simulator to perform unit simulation, and extracting a truth table of each unit to be characterized and monotonicity between input and output pins; when the unit to be characterized is a combinational logic unit, each output can be represented as a Boolean function of an input signal; when the unit to be characterized is a timing logic unit, an effective edge or an effective level of a clock is identified, and a next state of the output is represented as a Boolean function of an input and a present state; initializing timing arcs of all units to be characterized based on a logical function identification result, a topological identification result of each unit to be characterized and the extension commands; determining circuit compositions of first and last channel communication blocks based on the connection relationship between each channel communication block in each unit to be characterized.

6. The standard cell timing library simulation method of claim 5, wherein, the step of calling a SPICE simulator to characterize timing arcs of all the initialized units to be characterized, and extracting model data of timing, power consumption and noise and storing the model data into a model database, specifically comprises: determining states of each pin or node in each unit to be characterized; instantiating a netlist to create an independent characterization folder for each characterization; performing parameter configuration of a characterization netlist according to different characterization types; calling a SPICE simulator to simulate the characterization netlist; extracting model data of timing, power consumption and noise of each type of unit from a simulation result and storing the model data into a model database.

7. A computer device comprising a memory, a processor, and a computer program stored on the memory, wherein the computer program comprises instructions that, when executed by the processor, cause the processor to perform the method of any one of claims 1-6. The processor executes the computer program to implement the steps of the standard unit timing library simulation method according to any one of claims 5-6.

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