A method for simulating MOSFET devices, a computer device, and a storage medium.

Abstract

This invention provides a method, computer device, and storage medium for calculating a MOSFET device simulation model, including: transferring values ​​of internal parameter variables of the simulation model based on external input parameters; performing variable anomaly checks during scaling, updating the equivalent oxide layer thickness of the electrical gate first, and then calculating the edge field capacitance; performing range checks on the scaled internal parameter variables and performing anomaly checks on correlated variables; introducing a volume bias coefficient with a non-uniform depletion width effect to calculate the model internal parameter variables that are within the range, obtaining the current, charge, conductance, and capacitance of each node; filling in the elements of the model matrix based on the model calculation results, and introducing multiplication parameters to multiply the current, charge, and FN noise respectively. This scheme can further improve the correctness and accuracy of the MOSFET device model, and thus better ensure the reliability of the simulation results when simulating the entire circuit.

Description

Technical Field

[0001] This invention relates to the field of EDA simulation technology, and more particularly to a method for calculating a MOSFET device simulation model, a computer device, and a storage medium. Background Technology

[0002] The first MOSFET model adopted as a standard by the industry was BSIM3v3 (the third iteration of the third-generation MOSFET simulation model developed by the University of California, Berkeley). Since then, it has been widely used by most semiconductor and IC design companies worldwide for device modeling and CMOS IC design. As device feature sizes continue to shrink and physical effects are added / corrected, the most widely recognized and applied MOSFET model as an extension of the BSIM3v3 model is now BSIM4 (the fourth-generation MOSFET simulation model developed by the University of California, Berkeley). It models the physical effects of MOSFETs in the sub-100nm process. Due to its physical basis, accuracy, scalability, reliability, and predictability, BSIM4 has been used in advanced technology nodes such as 0.13μm, 90nm, 65nm, 45 / 40nm, 23 / 28nm, and 22 / 20nm.

[0003] However, with the increasing application scenarios of MOSFET devices, there are some issues in the existing MOSFET models that need to be corrected. These issues will affect the accuracy of the models and, consequently, the reliability of the simulation results of the entire circuit. Summary of the Invention

[0004] The purpose of this invention is to provide a MOSFET device simulation model calculation method, computer equipment, and storage medium, which can further improve the correctness and accuracy of the MOSFET device model, and thus better ensure the reliability of the simulation results when simulating the entire circuit.

[0005] The technical solution provided by this invention is as follows:

[0006] Firstly, this application provides a method for calculating a simulation model of a MOSFET device, including:

[0007] The simulation model internal parameter variables are transferred according to the external input parameters. The external input parameters include model parameters, instance parameters, gate-induced drain current clamping parameters, and noise clamping parameters.

[0008] The model's internal parameter variables are scaled according to temperature or geometry, and anomaly checks are performed on the model's internal parameter variables and intermediate calculation variables during scaling. The equivalent oxide thickness of the electrical gate is updated first during scaling, and then the edge field capacitance is calculated based on the updated equivalent oxide thickness value of the electrical gate.

[0009] The range of the internal parameter variables of the scaled model is checked, and anomaly checks of the associated variables are performed during the range check.

[0010] A volume bias coefficient with a non-uniform depletion width effect is introduced to perform model calculations on the internal parameter variables of the model that are not out of range, to obtain the current I, charge Q, conductance G and capacitance C of each node, and to correct the variables that cause the terminal current to be non-zero when all terminal voltages are zero during model calculation.

[0011] Based on the model calculation results, the elements of the I, G, Q, and C model matrices are filled in and the matrices are solved. Multiplication parameters are introduced to multiply the current I, charge Q, and FN noise respectively.

[0012] In some implementations, anomaly checks are performed on the model's internal parameter variables and intermediate calculation variables during scaling, specifically including:

[0013] When scaling the internal parameter variables of the model, the surface potential phi is checked, and the program is stopped and an error is reported when the surface potential is negative.

[0014] When scaling the internal parameter variables of the model, the intermediate variable phieot for calculating the effective gate-source voltage is checked. If the intermediate variable is negative, the program will stop running and report an error.

[0015] In some implementations, anomaly checks of the associated variables are performed during the range check, including:

[0016] The temperature parameter tempeot is checked when the equivalent silica thickness is measured. If the temperature parameter is less than 0 K, the program will stop running and report an error.

[0017] In some implementations, the transfer of values ​​for the internal parameter variables of the simulation model based on external input parameters includes:

[0018] Obtain the external input parameters, and when the external input parameters are set in the netlist, pass their values ​​to the model's internal parameter variables;

[0019] If the external input parameters are not set in the netlist, then the model's internal parameters are assigned default values;

[0020] The model's internal parameters also include internal parameters corresponding to the gate-induced drain current clamping parameters and noise clamping parameters.

[0021] In some implementations, during the scaling process, the equivalent oxide thickness of the electrical gate is updated first, and then the edge field capacitance is calculated based on the updated equivalent oxide thickness value of the electrical gate. Specifically, this includes:

[0022] Determine whether to select a new material model, wherein the new material model is a non-silicon dioxide gate insulating layer, a non-polysilicon gate, and a non-silicon channel model;

[0023] If the new material model is selected, the gate oxide thickness and dielectric constant under the new material model are calculated, and the equivalent oxide thickness of the electrical gate is updated based on the calculation results.

[0024] If it is determined that a non-new material model is selected, the gate oxide thickness and dielectric constant under the non-new material model are calculated, and the equivalent oxide thickness of the electrical gate is updated based on the calculation results.

[0025] The edge field capacitance is calculated based on the updated equivalent oxide thickness of the electrical gate.

[0026] In some implementations, the correction during model calculation for variables that cause non-zero terminal currents when all terminal voltages are zero includes:

[0027] Replace the effective voltage used to calculate the gate-channel tunneling current Igc and the gate-substrate tunneling current Igb with the actual voltage.

[0028] In some implementations, the step of performing model calculations based on the model's internal parameter variables that are not out of range includes:

[0029] The DC quantity is calculated based on the volume bias coefficient keta of the volume charge effect and its dependent parameters. The dependent parameters of the volume bias coefficient keta of the volume charge effect include the length dependent term lketa, the width dependent term wketa, and the length-width product dependent term pketa.

[0030] A volume bias coefficient ketac for the non-uniform depletion width effect is introduced. The volume CV is calculated based on the volume bias coefficient ketac for the non-uniform depletion width effect and its dependent parameters. The dependent parameters of the volume bias coefficient ketac for the non-uniform depletion width effect include the parameter length dependency lketac, the parameter width dependency wketac, and the parameter length-width product dependency pketac. The default values ​​of the volume bias coefficient ketac for the non-uniform depletion width effect and its dependent parameters are consistent with the default values ​​of the volume bias coefficient keta for the volume charge effect and its dependent parameters.

[0031] In some implementations, the introduction of multiplication parameters multiplies the current I, charge Q, and FN noise, respectively, including:

[0032] The parameters MULT_I, MULT_Q, and MULT_FN are introduced to multiply the current, charge, and FN noise, respectively. The MULT_I and MULT_Q parameters are applied to the element filling of the model I, G, Q, and C matrices, and the MULT_FN parameter is used to multiply the FN noise.

[0033] In a second aspect, this application provides a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the MOSFET device simulation model calculation method described in the first aspect.

[0034] Thirdly, this application provides a computer storage medium storing a computer program or instructions thereon, wherein when the computer program or instructions are executed by a processor, the steps of the MOSFET device simulation model calculation method described in the first aspect are implemented.

[0035] The MOSFET device simulation model calculation method, computer equipment, and storage medium provided by this invention can further improve the correctness and accuracy of the MOSFET device model, thereby better ensuring the reliability of the simulation results when simulating the entire circuit. Attached Figure Description

[0036] The preferred embodiments will now be described in a clear and easy-to-understand manner, with reference to the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages, and implementation methods of this solution.

[0037] Figure 1 This is a schematic diagram of the overall process of one embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram of the internal calculation execution flow of a MOSFET device model according to an embodiment of the present invention;

[0039] Figure 3 This is a schematic diagram of the edge field capacitance calculation process for MOSFET device models in the prior art;

[0040] Figure 4 This is a schematic diagram of the edge field capacitance calculation process for a MOSFET device model according to an embodiment of the present invention;

[0041] Figure 5 This is a schematic diagram of the calculation process of the gate-channel tunneling current Igc of a MOSFET device model according to an embodiment of the present invention;

[0042] Figure 6 This is a schematic diagram of the calculation process of the gate-substrate tunneling current Igb of a MOSFET device model according to an embodiment of the present invention;

[0043] Figure 7 This is a schematic diagram illustrating the calculation process of inter-terminal capacitance and channel current in a MOSFET device model in the prior art.

[0044] Figure 8 This is a schematic diagram illustrating the calculation process of inter-terminal capacitance and channel current of a MOSFET device model according to an embodiment of the present invention. Detailed Implementation

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0046] To keep the drawings concise, only the parts relevant to the invention are shown schematically in each figure, and they do not represent the actual structure of the product. Furthermore, for ease of understanding, in some figures, only one of components with the same structure or function is shown schematically, or only one is labeled. In this document, "one" can mean not only "only one" but also "more than one".

[0047] The emergence and development of integrated circuits (ICs) and computer science and technology have complemented each other. As IC integration density and feature size decrease, IC complexity and circuit scale increase dramatically, making computer-aided design (CAD) indispensable. Now, a single chip typically constitutes a system, leading to the evolution of design systems from the relatively traditional CAD to the more advanced Electronic Design Automation (EDA). Today, EDA is hailed as the "mother of chips," forming the foundation of the entire electronics industry. Its crucial role in integrated circuit design is undeniable: it can significantly shorten product development cycles, reduce costs, and improve product reliability and testability. The most important metric for evaluating EDA products is the accuracy and reliability of the results. As one of the three major components of EDA (IO, engine, and device model), the device model has a significant impact on simulation accuracy.

[0048] The first MOSFET model adopted as a standard by the industry was BSIM3v3 (the third iteration of the third-generation MOSFET simulation model developed by the University of California, Berkeley). Since then, it has been widely used by most semiconductor and IC design companies worldwide for device modeling and CMOS IC design. It incorporates many important physical effects, such as channel length modulation (CLM), drain-induced barrier reduction (DIBL), channel charge distribution, parasitic resistance and capacitance, polysilicon gate depletion, non-equilibrium carrier transport, subthreshold current, and temperature effects. It can also handle different structures and processes, such as channel geometry, gate oxide thickness, doping concentration, and LDD structures.

[0049] As device feature sizes shrink and physical effects are added / corrected, the most widely accepted and applied MOSFET model, as an extension of the BSIM3v3 model, is BSIM4 (the fourth-generation MOSFET simulation model developed by the University of California, Berkeley). It models the physical effects of MOSFETs in the sub-100nm process. Due to its physical basis and its accurate, scalable, reliable and predictable characteristics, BSIM4 has been used in advanced technology nodes of 0.13μm, 90nm, 65nm, 45 / 40nm, 23 / 28nm and 22 / 20nm. Compared to BSIM3v3, BSIM4 mainly adds and improves the following features: an accurate model for intrinsic resistance, an adjustable substrate resistance network, a channel thermal noise model and a sensed gate noise partitioning model, a non-quasi-static effect model, a direct tunneling effect model, a geometry-dependent parasitic parameter model, an improved model for steep-slope reverse-doped profiles, a better model for the threshold voltage and volume charge effect of pocket-injected devices, an asymmetric and bias-dependent source / drain resistance, selectable electrical / physical oxide thickness or equivalent oxide thickness as input, a quantum mechanical charge layer thickness model that considers both current-voltage (IV) and capacitance-voltage (CV) characteristics, a more accurate mobility model, and consideration of the work function difference between the source / drain and the gate. The model includes: gate-induced source / drain (GIDL / GISL) current model, unified flicker noise model considering volume charge effect, source / drain asymmetric diode IV and CV characteristics, junction diode breakdown with or without current limitation, gate dielectric constant as a model parameter, scalable stress effect model, unified current saturation model including velocity saturation, velocity overshoot and source velocity limitation, new temperature model format, improved material models for non-SiO2 gate insulators, non-polysilicon gates and non-silicon channels, new threshold voltage definition introduced into the CV model, model for predicting mobility behavior in high-k / metal gate structures, width-dependent trap-assisted tunneling model, coherence coefficient of coherent noise, new thermal noise model, and improved DIBL / ROUT model.

[0050] Although BSIM4 is one of the most widely accepted models, it still has some issues that need to be addressed. These include the tendency to use incorrect parameter values ​​in temperature effect calculations, errors or omissions in range checks and calculation order for some variables, missing parameter values, missing multiplication parameters for independent control of current / charge / FN noise, non-zero terminal current when all voltages are zero, and negative capacitance under high supply voltage, high reverse bias, and negative Keta conditions. These issues affect model accuracy and, consequently, the reliability of the simulation results for the entire circuit. This solution addresses these issues by making corresponding corrections to the MOSFET model to improve model accuracy and, consequently, the reliability of the simulation results for the entire circuit. The following is a detailed description of this solution with reference to the accompanying figures:

[0051] In one embodiment, refer to the appendix to the specification. Figure 1 This application provides a method for calculating a simulation model of a MOSFET device, including:

[0052] S100. Transfer the values ​​of the internal parameter variables of the simulation model according to the external input parameters. The external input parameters include model parameters and instance parameters. The model parameters include gate-induced drain current clamping parameters and noise clamping parameters.

[0053] This improved model maintains the same internal calculation and execution flow as the original MOSFET model, such as... Figure 2 As shown, the solution first obtains external input parameters, which are netlists containing the external connections of each node in the circuit and the initial voltage values. The netlists also include model parameters (such as model version, new material model selector MTRLMOD, flat band voltage VFB, and other basic model information, process information, etc.) and instance parameters (such as channel length L, channel width W, number of fingers nf, and other device geometry information). The external input parameters are parsed and passed in by the system I / O part.

[0054] When transferring values ​​to internal parameter variables of the simulation model based on external input parameters, the specific steps include:

[0055] Obtain external input parameters and pass their values ​​to the model's internal parameter variables if the external input parameters are set in the netlist; assign default values ​​to the model's internal parameters if the external input parameters are not set in the netlist. The default values ​​are specified by the model publisher and detailed information can be obtained from the publisher's model manual.

[0056] Furthermore, for the parameters GIDLCLAMP (gate-induced drain current clamping parameter) and IDovVDSC (noise clamping parameter), if values ​​are not passed, the model will use their default values ​​(-1e-5 and 1e-9 respectively), which are hard-coded into the code, losing their adjustability. Therefore, the improvement in this application is that the values ​​of the gate-induced drain current clamping parameter and the noise clamping parameter are passed from external input parameters to internal parameter variables. During value passing, when the parameter values ​​of these two parameters are defined in the external netlist, their values ​​can be passed into the model code. Their adjustable values ​​make the model more flexible and conform to the operating logic of the parameters themselves.

[0057] S200: Scale the model's internal parameter variables according to temperature or geometry, and perform anomaly checks on the model's internal parameter variables and intermediate calculation variables during scaling. Also, update the equivalent oxide layer thickness of the electrical gate before scaling, and then calculate the edge field capacitance based on the updated equivalent oxide layer thickness value of the electrical gate.

[0058] In one specific implementation, this application performs anomaly checks on internal model parameters and intermediate computation variables during scaling, specifically including:

[0059] When scaling the internal parameter variables of the model, the surface potential phi is checked, and the program stops running and reports an error when the surface potential is negative.

[0060] When scaling the internal parameter variables of the model, the intermediate variable phieot for calculating the effective gate-source voltage is checked. If the intermediate variable is negative, the program will stop running and report an error.

[0061] Specifically, this solution adds checks to the variables phi and phieot before they are involved in calculations to prevent unreasonable values ​​or errors caused by negative numbers in square root operations. For example, the calculation of phi corresponds to the scaling of temperature / geometry parameters, and its formula is:

[0062] ,

[0063] Here, phi represents the surface potential; Vtm0 is... Where kB and q represent the Boltzmann constant and the charge of an electron, respectively; Tnom represents the nominal temperature (in Kelvin); ndep represents the doping concentration at the edge of the depletion region of the zero-body bias; phin represents the non-uniform vertical doping effect on the surface potential; and ni is the intrinsic carrier concentration in the channel region.

[0064] In the next step, the square root of phi will be used for subsequent calculations (such as the threshold voltage Vth):

[0065] .

[0066] If the value of phi is not checked between the two equations, it may result in taking the square root of a negative value, thus returning the incorrect result NaN (Not a Number). Therefore, when scaling the internal parameter variables of the model, it is necessary to check the surface potential phi, and stop the program and report an error if the surface potential is negative.

[0067] In addition, when the existing MOSFET model executes the calculation process, the variable phieot (an intermediate variable used to calculate the effective gate-source voltage) also lacks a check before entering the square root operation. Therefore, when scaling the internal parameter variables of the model, the intermediate variable phieot for calculating the effective gate-source voltage is checked first. If the intermediate variable is negative, the program will stop running and report an error. This will not be elaborated here.

[0068] After the parameter values ​​are set, the temperature / geometric scaling step begins. This part calculates parameters based on temperature (e.g., the parameter value extracted from the nominal temperature TNOM, considering the change of this parameter from the nominal temperature to the actual operating temperature T) and geometric dimensions such as channel length and width. For example, a calculation formula based on temperature is:

[0069] ,

[0070] Where: Vfb(T) is the flat band voltage at the actual operating temperature T, Vfb(TNOM) is the flat band voltage extracted at the nominal temperature TNOM, and KT1 is the temperature coefficient of the threshold voltage.

[0071] When scaling the internal parameters of the model, this application moves the position of the CF calculation module to use the updated TOXE value. Specifically, during scaling, the equivalent oxide thickness of the electrical gate is updated first, and then the edge field capacitance is calculated based on the updated equivalent oxide thickness value of the electrical gate. This includes:

[0072] Determine whether to use the new material model. The new material model is a non-silicon dioxide gate insulating layer, a non-polysilicon gate, and a non-silicon channel model.

[0073] If the new material model is selected, the gate oxide thickness and dielectric constant under the new material model are calculated, and the equivalent oxide thickness of the electrical gate is updated based on the calculation results.

[0074] If it is determined that a non-new material model is selected, the gate oxide thickness and dielectric constant under the non-new material model are calculated, and the equivalent oxide thickness of the electrical gate is updated based on the calculation results.

[0075] The edge field capacitance is calculated based on the updated equivalent oxide thickness of the electrical gate.

[0076] Reference manual attached Figure 3 and attached Figure 4 , Figure 3 This is a schematic diagram of the edge field capacitance calculation process for MOSFET device models in the prior art. Figure 4 This is a schematic diagram of the edge field capacitance calculation process for a MOSFET device model according to an embodiment of the present invention. Comparing the original calculation logic with the improved model: the logic of selecting whether to execute code block 1 (calculation of gate oxide thickness and dielectric constant under the non-new material model) or code block 2 (calculation of gate oxide thickness and dielectric constant under the new material model) based on mtrlMod (new material model selector, which is selected by the user to choose whether to use the new material process: mtrlMod=1 means new material model, i.e., non-silicon dioxide gate insulating layer, non-polysilicon gate and non-silicon channel; while the default mtrlMod=0 means no new material process, i.e., silicon dioxide gate insulating layer, polysilicon gate and silicon channel) remains unchanged; however, in the original logic, the calculation of CF (edge ​​field capacitance) is under the condition branch of mtrlMod=0, after the execution of code block 1, and the TOXE (electric gate equivalent oxide thickness) update operation is performed only after the CF calculation; and under the condition branch of mtrlMod≠0, the TOXE update is performed after the execution of code block 2, without the calculation of CF. Based on this, the modified process in this application separates the calculation of CF from the judgment of mtrlMod and changes its position to after the TOXE update entered by code blocks 1 and 2, ensuring that the updated TOXE value is used in the calculation of CF regardless of whether mtrlMod is 0.

[0077] S300. Perform range checks on the internal parameter variables of the scaled model, and perform anomaly checks on associated variables during the range check.

[0078] After scaling the internal parameters of the model by temperature / geometric scaling, the processed parameters are then checked for range. This checks whether the parameters exceed their specified upper and lower limits. For example, for the range check of the polysilicon gate doping concentration NGATE, it will be checked whether it is within the range of (0, 1e25). If it is below or above this range, the program will directly report an error and indicate that the value is unreasonable.

[0079] When performing range checks on the internal parameter variables of the scaled model, this application also performs anomaly checks on associated variables. Specifically, it checks the temperature parameter tempeot when the equivalent silica thickness is measured, and stops the program and reports an error when the temperature parameter is less than 0 K.

[0080] The parameter `tempeot` represents the temperature at which the EOT (Equivalent Silica Thickness) is measured, and its unit is Kelvin (K). 0 K is the theoretical lowest temperature, corresponding to the state where particle thermal motion ceases (which is practically unattainable). Therefore, it is essential to check whether the parameter `tempeot` is greater than 0 in the parameter checking section to avoid abnormal calculation results caused by unreasonable parameter values. Therefore, this scheme checks the temperature parameter `tempeot` at the time of EOT measurement when performing range checks on the internal parameter variables of the scaled model. If the temperature parameter is less than 0 K, the program stops running and reports an error.

[0081] S400 introduces a volume bias coefficient with a non-uniform depletion width effect to perform model calculations on the internal parameter variables of the model that are not out of range, obtains the current I, charge Q, conductance G and capacitance C of each node, and corrects the variables that cause the terminal current to be non-zero when all terminal voltages are zero during model calculation.

[0082] Specifically, in the model formula calculation section, the parameter values ​​calculated and checked in the previous steps are substituted into the model formula for calculation. The formula covers multiple parts such as temperature, pressure, threshold voltage, channel charge and subthreshold swing, gate direct tunneling current, drain current, body current, capacitance model, new material model, high-speed / RF model, etc. Finally, the current I and charge Q values ​​of each node and their derivatives with respect to the voltage of each node, namely conductance G and capacitance C, are calculated.

[0083] In one specific implementation, model calculation based on internal model parameter variables that are within the specified range also includes:

[0084] The DC quantity is calculated based on the volume bias coefficient keta of the volume charge effect and its dependent parameters. The dependent parameters of the volume bias coefficient keta of the volume charge effect include the length dependent term lketa, the width dependent term wketa, and the length-width product dependent term pketa.

[0085] The volume bias coefficient ketac of the non-uniform depletion width effect is introduced. The CV is calculated based on the volume bias coefficient ketac of the non-uniform depletion width effect and its dependent parameters. The dependent parameters of the volume bias coefficient ketac of the non-uniform depletion width effect include the parameter length dependency lketac, the parameter width dependency wketac, and the parameter length-width product dependency pketac.

[0086] The default values ​​of the bulk bias coefficient ketac and its dependent parameters for the non-uniform depletion width effect are consistent with the default values ​​of the bulk bias coefficient keta and its dependent parameters for the bulk charge effect.

[0087] For details, please refer to the attached instruction manual. Figure 7 and attached Figure 8 , Figure 7 This is a schematic diagram illustrating the calculation process of inter-terminal capacitance and channel current in a MOSFET device model in the prior art. Figure 8 This is a schematic diagram illustrating the calculation process of inter-terminal capacitance and channel current of a MOSFET device model according to an embodiment of the present invention.

[0088] For cases with high Vdd, high reverse bias, and negative capacitance due to a negative parameter keta (volume bias coefficient of the volume charge effect), new model parameters are introduced: the volume bias coefficient ketac of the non-uniform depletion width effect in dynamic calculations and its geometric dependencies (length dependency lketac, width dependency wketac, and length-width product dependency pketac) to decouple the dc(iv) / cv behavior. In the original logic, the parameters keta, lketa, wketa, and pketac are used to calculate the binning value of keta to include its geometric dependencies, according to the following formula:

[0089] ,

[0090] Leff and Weff represent the effective channel length and width, respectively. Keta is then used to calculate quantities modeled for the volume charge effect, namely the volume charge effect coefficient Abulk and the common intermediate variable Abulk0 for the volume charge effect coefficient AbulkCV used in the capacitance-voltage model. Abulk is used to calculate DC quantities, such as channel current-related quantities like Vdsat (saturation voltage), Vasat (Erley voltage when drain-source voltage Vds = Vdsat), and VADIBL (DIBL, the Erley voltage caused by drain-induced barrier reduction). AbulkCV is used to calculate CV quantities, such as inter-terminal capacitance. This process demonstrates that Keta, acting simultaneously on both DC and CV, lacks the flexibility to independently control both, potentially leading to the aforementioned abnormal negative capacitance.

[0091] In the improved model, the parameters ketac, lketac, wketac, and pketac are introduced. Similarly, ketac includes the binning value of the geometric dependency, which is calculated as follows:

[0092] ,

[0093] Unlike the original model, in the new logic, `ketac` is used to calculate the new intermediate variable `Abulk0_Q` for the capacitor-voltage model of `AbulkCV`, and then `AbulkCV` is used to calculate the CV value; the calculation process for the DC value retains the original logic and is calculated using the original parameter `keta`. Figure 4As shown in the flowchart of the improved model on the right, the calculations of IV and CV are now decoupled and can be controlled by their respective independent parameters. Furthermore, to ensure compatibility with the original model, the default values ​​of the new parameters are consistent with those of the original parameters: the calculation formulas for Abulk0_Q and Abulk0 are identical, only the variable used is changed (ketac replaces keta). Therefore, when ketac = keta, the final CV result of the improved model is consistent with the original model. Independently controlling the ketac value, for example, assigning a non-negative value to ketac when keta is negative, can prevent negative capacitance values ​​from occurring under high Vdd and high reverse bias conditions.

[0094] Considering the common issue in model calculations where all terminal voltages are zero but the terminal current is non-zero, this application corrects the variables that cause this problem during model calculations. Specifically, this includes:

[0095] Replace the effective voltage used to calculate the gate-channel tunneling current Igc and the gate-substrate tunneling current Igb with the actual voltage.

[0096] Reference manual attached Figure 5 and attached Figure 6 This application improves the calculation of the gate-channel tunneling current Igc and the gate-substrate tunneling current Igb. For each, there are separate model selectors igcMod and igbMod. Each current is enabled only when its selector value is greater than 0; otherwise, the current is disabled. For the calculation of Igc, the intermediate variable T2 is first calculated under the condition that igcMod is greater than 0. The improvement in this step is that the effective voltage Vgs_eff used to calculate T2 is replaced with Vgs (gate-source voltage), that is, the effective voltage is replaced with the actual voltage. Similarly, for the calculation of Igb, under the condition that its selector value is greater than 0, the calculation of the intermediate quantity T2, which is used by both components Igbacc and Igbinv, is improved. The original effective voltages Vgs_eff and Vbseff are also replaced with the actual voltages Vgs and Vbs (substrate-source voltage). In the calculation formulas for T2 and Igc, Igbacc, and Igbinv for their respective parts, since the terms other than Vgs and Vbs are consecutive multiplication terms without additional addition or subtraction terms, when the actual voltage Vgs = 0, Igc = 0 is guaranteed; and when the actual voltages Vgs = 0 and Vbs = 0, Igbacc = 0 and Igbinv = 0 are guaranteed, thus Igb = 0. For example, the calculation formula for Igbacc is as follows:

[0097] ,

[0098] The consecutive multiplication terms T11, T2, and T6 are intermediate quantities in the calculation of Igbacc; and T2 is calculated as follows:

[0099] ,

[0100] Where Vaux is an intermediate quantity for calculating T2; from the above two equations, it is obvious that when the voltage Vgs=0 and Vbs=0, T2=0, therefore Igbacc=0.

[0101] S500: Based on the model calculation results, fill in the element values ​​of the I, G, Q, and C model matrices and solve the matrices, and introduce multiplication parameters to multiply the current I, charge Q, and FN noise respectively.

[0102] The values ​​calculated in the previous step will be filled into the elements corresponding to each node in the I, G, Q, C matrices (to be passed to the engine to build the large matrix of the entire circuit, and to solve the matrix).

[0103] Multiplication parameters are introduced to multiply the current I, charge Q, and FN noise respectively. Specifically, the parameters MULT_I, MULT_Q, and MULT_FN are introduced to multiply the current, charge, and FN noise respectively. The MULT_I and MULT_Q parameters are applied to the element filling values ​​of the model I, G, Q, and C matrices, and the MULT_FN parameter is used to multiply the FN noise.

[0104] Specifically, this application introduces instance parameters MULT_I, MULT_Q, and MULT_FN to multiply current, charge, and FN noise, respectively. MULT_I and MULT_Q are applied to the element filling parts of the model I,G,Q,C matrices: the former multiplies the contribution of each current and conductance, and the latter multiplies the contribution of each charge and capacitance. MULT_FN only multiplies FN noise caused by material defects, etc., and does not affect other types of noise, such as thermal noise generated by the thermal motion of charge carriers in the resistor, and shot noise caused by current fluctuations due to the random motion of discrete charges (such as electrons).

[0105] In addition, for all the above modifications, this application may also introduce a new model parameter betaflag to allow users to choose to enable the modified model (when betaflag>0) or to keep the original model (betaflag≤0), providing users with sufficient flexibility and personalized choices.

[0106] In one embodiment, based on the foregoing embodiments, this application provides a computer device including a memory, a processor, and a computer program stored in the memory. The processor executes the computer program to implement the steps of the MOSFET device simulation model calculation method of the foregoing embodiments.

[0107] In one embodiment, based on the foregoing embodiments, this application provides a computer storage medium storing a computer program or instructions, wherein the computer program or instructions, when executed by a processor, implement the steps of the MOSFET device simulation model calculation method of the foregoing embodiments.

[0108] The MOSFET device simulation model calculation method of this application can be implemented using computer-executable program code. Therefore, these code snippets can be stored in a storage device for execution by a computing device, or they can be fabricated as individual integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this invention is not limited to any particular hardware and software combination.

[0109] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for calculating a simulation model of a MOSFET device, characterized in that, include: The simulation model internal parameter variables are transferred according to external input parameters. The external input parameters include model parameters and instance parameters. The model parameters include gate-induced drain current clamping parameters and noise clamping parameters. The model's internal parameter variables are scaled according to temperature or geometry, and anomaly checks are performed on the model's internal parameter variables and intermediate calculation variables during scaling. The equivalent oxide thickness of the electrical gate is updated first during scaling, and then the edge field capacitance is calculated based on the updated equivalent oxide thickness value of the electrical gate. The range of the internal parameter variables of the scaled model is checked, and anomaly checks of the associated variables are performed during the range check. A volume bias coefficient with a non-uniform depletion width effect is introduced to perform model calculations on the internal parameter variables of the model that are not out of range, to obtain the current I, charge Q, conductance G and capacitance C of each node, and to correct the variables that cause the terminal current to be non-zero when all terminal voltages are zero during model calculation. Based on the model calculation results, the elements of the I, G, Q, and C model matrices are filled in and the matrices are solved. Multiplication parameters are introduced to multiply the current I, charge Q, and FN noise respectively.

2. The MOSFET device simulation model calculation method according to claim 1, characterized in that, During scaling, anomaly checks are performed on the model's internal parameter variables and intermediate calculation variables, including: When scaling the internal parameter variables of the model, the surface potential phi is checked, and the program is stopped and an error is reported when the surface potential is negative. When scaling the internal parameter variables of the model, the intermediate variable phieot for calculating the effective gate-source voltage is checked. If the intermediate variable is negative, the program will stop running and report an error.

3. The MOSFET device simulation model calculation method according to claim 1, characterized in that, Anomaly checks for associated variables are performed during the range check, including: The temperature parameter tempeot is checked when the equivalent silica thickness is measured. If the temperature parameter is less than 0 K, the program will stop running and report an error.

4. The MOSFET device simulation model calculation method according to claim 1, characterized in that, The transfer of values ​​for the internal parameter variables of the simulation model based on external input parameters includes: Obtain the external input parameters, and when the external input parameters are set in the netlist, pass their values ​​to the model's internal parameter variables; If the external input parameters are not set in the netlist, then the model's internal parameters are assigned default values; The model's internal parameters also include internal parameters corresponding to the gate-induced drain current clamping parameters and noise clamping parameters.

5. The MOSFET device simulation model calculation method according to claim 1, characterized in that, During the scaling process, the equivalent oxide layer thickness of the electrical gate is updated first, and then the edge field capacitance is calculated based on the updated equivalent oxide layer thickness value. Specifically, this includes: Determine whether to select a new material model, wherein the new material model is a non-silicon dioxide gate insulating layer, a non-polysilicon gate, and a non-silicon channel model; If the new material model is selected, the gate oxide thickness and dielectric constant under the new material model are calculated, and the equivalent oxide thickness of the electrical gate is updated based on the calculation results. If it is determined that a non-new material model is selected, the gate oxide thickness and dielectric constant under the non-new material model are calculated, and the equivalent oxide thickness of the electrical gate is updated based on the calculation results. The edge field capacitance is calculated based on the updated electrical gate equivalent oxide thickness value.

6. The MOSFET device simulation model calculation method according to claim 1, characterized in that, The corrections made during model calculations for variables that cause non-zero terminal currents when all terminal voltages are zero include: Replace the effective voltage used to calculate the gate-channel tunneling current Igc and the gate-substrate tunneling current Igb with the actual voltage.

7. The MOSFET device simulation model calculation method according to claim 1, characterized in that, Model calculations are performed based on the model's internal parameter variables that are not outside their range, including: The DC quantity is calculated based on the volume bias coefficient keta of the volume charge effect and its dependent parameters. The dependent parameters of the volume bias coefficient keta of the volume charge effect include the length dependent term lketa, the width dependent term wketa, and the length-width product dependent term pketa. A volume bias coefficient ketac for the non-uniform depletion width effect is introduced. The volume bias coefficient ketac for the non-uniform depletion width effect and its dependent parameters are used to calculate the CV. The dependent parameters of the volume bias coefficient ketac for the non-uniform depletion width effect include the parameter length dependency lketac, the parameter width dependency wketac, and the parameter length-width product dependency pketac. The default values ​​of the volume bias coefficient ketac and its dependent parameters for the non-uniform depletion width effect are consistent with the default values ​​of the volume bias coefficient keta and its dependent parameters for the volume charge effect.

8. The MOSFET device simulation model calculation method according to claim 7, characterized in that, The introduced multiplication parameters multiply the current I, charge Q, and FN noise respectively, including: The parameters MULT_I, MULT_Q, and MULT_FN are introduced to multiply the current, charge, and FN noise, respectively. The MULT_I and MULT_Q parameters are applied to the element filling of the model I, G, Q, and C matrices, and the MULT_FN parameter is used to multiply the FN noise.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the MOSFET device simulation model calculation method according to any one of claims 1-8.

10. A computer storage medium having a computer program or instructions stored thereon, characterized in that, When the computer program or instructions are executed by the processor, they implement the steps of the MOSFET device simulation model calculation method according to any one of claims 1-8.

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