CMOS-Nscan circuit with enhanced stability and driving force

Abstract

The invention relates to the technical field of circuit design, and provides a CMOS-Nscan circuit with enhanced stability and driving force, which comprises a plurality of interlaced cascaded driving units, the driving unit comprises a cascade driving module, a low-level maintaining output module, a high-level pulse output module, a high-level pulse output control module and an eleventh transistor; the low-level IGZO output and the high-level PMOS-LTPS output are adopted, the low-level IGZO output capacity is high, the PMOS-LTPS high-level output capacity is high, and therefore the circuit driving force is higher, and the maintaining state is more stable.

Description

Technical Field

[0001] This invention relates to the field of circuit design technology, and in particular to a CMOS-Nscan circuit with enhanced stability and driving force. Background Technology

[0002] like Figure 2 The IGZO-GOA driving circuit shown has the following problems: 1) The IGZO mobility is low and the driving capability is weak; 2) During reliability testing, the drift of IGZO characteristics causes a decrease in output capability, resulting in unstable output. Summary of the Invention

[0003] In order to overcome the shortcomings of the prior art, the purpose of this invention is to provide a CMOS-Nscan circuit with enhanced stability and driving force, so as to solve the problems of poor driving capability and unstable output of traditional circuits.

[0004] To achieve the above objectives, the present invention provides the following solution: A CMOS-Nscan circuit with enhanced stability and driving force includes: a plurality of interlaced cascaded driving units; each driving unit includes: a cascaded driving module, a low-level sustain output module, a high-level pulse output module, a high-level pulse output control module, and an eleventh transistor; the cascaded driving module includes: a first transistor, a second transistor, a third transistor, a first fourth transistor, a second fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor; the low-level sustain output module includes: a thirteenth transistor; the high-level pulse output module includes: a twelfth transistor and a third capacitor; the high-level pulse output control module includes: a ninth transistor and a tenth transistor; The first fourth transistor and the second fourth transistor are connected in series; the gates of the first fourth transistor and the second fourth transistor are connected; the second fourth transistor is connected to the gate of the second transistor, the first transistor, and the sixth transistor; the sixth transistor is connected to the gate of the eighth transistor and the second capacitor; the fifth transistor is connected to the gate of the third transistor, the gate of the seventh transistor, the second transistor, and the first capacitor; the first capacitor is connected to the gate and source of the seventh transistor; the first transistor and the third transistor are connected; the second capacitor is connected to the gate and source of the eighth transistor. The gates of the seventh, eighth, and ninth transistors and the gate of the thirteenth transistor are connected to each other; the ninth transistor is connected to the tenth and eleventh transistors respectively; the eleventh transistor is connected to the gate of the twelfth transistor; the third capacitor is connected to the gate and drain of the twelfth transistor respectively; the twelfth transistor and the thirteenth transistor are connected; the connection line of the seventh and eighth transistors in the odd-numbered rows of the driving units is connected to the first fourth transistor in the next-level driving unit in the odd-numbered rows; the connection line of the seventh and eighth transistors in the even-numbered rows of the driving units is connected to the first fourth transistor in the next-level driving unit in the even-numbered rows. The first fourth transistor in the driving unit is connected; in the odd-numbered rows of the driving unit, the third and tenth transistors are respectively connected to the external VGH terminal, the gates of the sixth, ninth, and eleventh transistors are respectively connected to the external VGL terminal, the thirteenth transistor is connected to the external VGL1 terminal, the second transistor, the gates of the first fourth transistor, the second fourth transistor, and the tenth transistor are respectively connected to the external CK1 terminal, the gate of the first transistor and the eighth transistor are respectively connected to the external XCK1 terminal, and the twelfth transistor is connected to the external CKA terminal; in the even-numbered rows of the driving unit... The third and tenth transistors are respectively connected to the VGH terminal; the gates of the sixth, ninth, and eleventh transistors are respectively connected to the VGL terminal; the thirteenth transistor is connected to the external VGL2 terminal; the gates of the second, first, and second fourth transistors, and the tenth transistor are respectively connected to the external CK2 terminal; the gate of the first transistor and the eighth transistor are respectively connected to the external XCK2 terminal; and the twelfth transistor is connected to the external CKB terminal. The connection line between the twelfth and thirteenth transistors is connected to the switching transistor of the pixel driving circuit of the external display area. The cascaded drive module is used to shift the input low-level pulse signal; the low-level sustain output module is used to provide a low-level output signal during the sustain phase; the high-level pulse output module is used to provide a high-level pulse signal during the high-level pulse output phase; and the high-level pulse output control module is used to control the switching between the sustain phase and the high-level pulse output phase.

[0005] The present invention discloses the following technical effects: This invention provides a CMOS-Nscan circuit with enhanced stability and driving force, which solves the problems of poor driving capability and unstable output of traditional circuits, and improves the driving force and stable state maintenance capability of the circuit. Attached Figure Description

[0006] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0007] Figure 1 A CMOS-Nscan circuit diagram for enhancing stability and driving force provided in embodiments of the present invention; Figure 2 This is a conventional all-IGZO-GOA driving circuit diagram provided in an embodiment of the present invention; Figure 3 The GOA circuit diagram and corresponding timing diagram provided for embodiments of the present invention; Figure 4 Circuit diagrams of odd-numbered and even-numbered circuit units provided for embodiments of the present invention; Figure 5 This is a schematic diagram of the cascaded relationship of the driving GOA circuit provided in an embodiment of the present invention; Figure 6 The operating timing sequence corresponding to the cascading of upper and lower stages of the circuit provided in the embodiments of the present invention.

[0008] Explanation of reference numerals in the attached figures: T1 - First transistor, T2 - Second transistor, T3 - Third transistor, T4 - Fourth transistor, T5 - Fifth transistor, T6 - Sixth transistor, T7 - ​​Seventh transistor, T8 - Eighth transistor, T9 - Ninth transistor, T10 - Tenth transistor, T11 - Eleventh transistor, T12 - Twelfth transistor, T13 - Thirteenth transistor, C1 - First capacitor, C2 - Second capacitor, C3 - Third capacitor. Detailed Implementation

[0009] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0010] The purpose of this invention is to provide a CMOS-Nscan circuit with enhanced stability and driving force, solving the problems of poor driving capability and unstable output of traditional circuits.

[0011] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0012] Figure 1 The CMOS-Nscan circuit diagram provided for the embodiments of the present invention, which enhances stability and driving force, is as follows: Figure 1 As shown, this invention provides a CMOS-Nscan circuit with enhanced stability and driving force, comprising: a plurality of interlaced cascaded driving units; each driving unit includes: a cascaded driving module, a low-level sustain output module, a high-level pulse output module, a high-level pulse output control module, and an eleventh transistor T11; the cascaded driving module includes: a first transistor T1, a second transistor T2, a third transistor T3, a first fourth transistor T4_1, a second fourth transistor T4_2, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first capacitor C1, and a second capacitor C2; the low-level sustain output module includes: a thirteenth transistor T13; the high-level pulse output module includes: a twelfth transistor T12 and a third capacitor C3; the high-level pulse output control module includes: a ninth transistor T9 and a tenth transistor T10; The first fourth transistor T4_1 and the second fourth transistor T4_2 are connected in series; the gates of the first fourth transistor T4_1 and the second fourth transistor T4_2 are connected; the second fourth transistor T4_2 is connected to the gate of the second transistor T2, the first transistor T1, and the sixth transistor T6; the sixth transistor T6 is connected to the gate of the eighth transistor T8 and the second capacitor C2; the fifth transistor T5 is connected to the gate of the third transistor T3, the gate of the seventh transistor T7, the second transistor T2, and the first capacitor C1. The first capacitor C1 is connected to the gate and source of the seventh transistor T7; the first transistor T1 and the third transistor T3 are connected; the second capacitor C2 is connected to the gate and source of the eighth transistor T8; the gates of the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the thirteenth transistor T13 are connected to each other; the ninth transistor T9 is connected to the tenth transistor T10 and the eleventh transistor T11; the eleventh transistor T11 is connected to the gate of the twelfth transistor T12; the third capacitor C3 is connected to the gate of the twelfth transistor T12. The gate and drain of transistor T12 are connected; the twelfth transistor T12 and the thirteenth transistor T13 are connected; the connection lines of the twelfth transistor T12 and the thirteenth transistor T13 in the driving units of the odd-numbered rows are connected to the first fourth transistor T4_1 in the next-level driving unit of the odd-numbered rows; the connection lines of the twelfth transistor T12 and the thirteenth transistor T13 in the driving units of the even-numbered rows are connected to the first fourth transistor T4_1 in the next-level driving unit of the even-numbered rows; the third transistor T3 and the tenth transistor T10 in the driving units of the odd-numbered rows... The gates of the sixth transistor T6, the ninth transistor T9, and the eleventh transistor T11 are respectively connected to the external VGH terminal. The gates of the thirteenth transistor T13 are connected to the external VGL terminal. The gates of the second transistor T2, the first fourth transistor T4_1, the second fourth transistor T4_2, and the tenth transistor T10 are respectively connected to the external CK1 terminal. The gates of the first transistor T1 and the eighth transistor T8 are respectively connected to the external XCK1 terminal. The twelfth transistor T12 is connected to the external CKA terminal.In the even-numbered rows of the driving unit, the third transistor T3 and the tenth transistor T10 are respectively connected to the VGH terminal; the gates of the sixth transistor T6, the ninth transistor T9, and the eleventh transistor T11 are respectively connected to the VGL terminal; the thirteenth transistor T13 is connected to the external VGL2 terminal; the gates of the second transistor T2, the first fourth transistor T4_1, the second fourth transistor T4_2, and the tenth transistor T10 are respectively connected to the external CK2 terminal; the gate of the first transistor T1 and the eighth transistor T8 are respectively connected to the external XCK2 terminal; and the twelfth transistor T12 is connected to the external CKB terminal. The connection line between the twelfth transistor T12 and the thirteenth transistor T13 is connected to the switching transistor of the pixel driving circuit of the external display area. The cascaded drive module is used to shift the input low-level pulse signal; the low-level sustain output module is used to provide a low-level output signal during the sustain phase; the high-level pulse output module is used to provide a high-level pulse signal during the high-level pulse output phase; and the high-level pulse output control module is used to control the switching between the sustain phase and the high-level pulse output phase.

[0013] Specifically, the main structural functions, connections, and functions of the circuit are as follows: 1) Cascaded drive module: This module shifts the input STV low-level pulse signal and outputs a Next signal, which is a low-level pulse signal shifted backward relative to STV. The Next signal is connected to the high-level pulse output control module and the low-level sustain output module, and is also connected to the next cascaded module. 2) Low-level sustain output module: The VGL1 is controlled by the thirteenth transistor T13 to write the OUT signal, providing a low-level output signal for the OUT signal sustaining phase; 3) High-level pulse output module: The CKA signal provides an effective high-level pulse signal for the OUT signal output through the twelfth transistor T12. The third capacitor C3 acts as a boost capacitor in the output stage to pull N5 low, ensuring that the falling edge of the CKA signal is output to OUT without loss, ensuring the integrity of the high-level pulse, and is connected to the pulse output control module through N5. 4) High-level pulse output control module: During the high-level pulse output phase, a low-level signal provided by VGL1 is provided to N5 to control the normal output of the high-level pulse. During the low-level maintenance phase, VGH is provided to N2 so that the twelfth transistor T12 is in the off state during the maintenance output phase and cannot output a high-level pulse, thus ensuring the stability of the signal during the maintenance phase.

[0014] Furthermore, the circuit design and driving method are as follows. (Reference) Figure 3The circuit's workflow is as follows: S1: IN signal is written, CK1 is turned on, N4 is written to low level, N2 is written to low level, at this time both the seventh transistor T7 and the eighth transistor T8 are turned on, the Next signal is high level, the thirteenth transistor T13 is turned on, and OUT outputs low level. S2: CK1 moves from VGL to VGH. At this time, node N2 writes to VGH, the seventh transistor T7 is turned off, the eighth transistor T8 is turned on, XCK1 is still at a high level, the Next signal is at a high level, the thirteenth transistor T13 is turned on, and OUT outputs a low level. S3: XCK1 moves from VGH to VGL. At this time, Next outputs a low level, the thirteenth transistor T13 is turned off, the ninth transistor T9 is turned on, CK1 is turned off, VGL is written to node N5, and since CKA is low at this time, OUT maintains a low output level. S4: At this time, CKA changes from VGL to VGH, and OUT outputs VGH; S5: At this time, CKA changes from VGH to VGL, and OUT outputs VGL. When OUT outputs low, the third capacitor C3 further pulls N5 low to ensure that VGL is fully output to OUT. S6: XCK1 changes from VGL to VGH, the Next signal is VGH, at this time the thirteenth transistor T13 is turned on, and OUT outputs a stable low level; S7: At this time, CK1 is turned on again, VGH is written to N5 to turn off the twelfth transistor T12, and the thirteenth transistor T13 is turned on to stably output a low level to OUT; The VGL1 voltage is set to VGL1>VGL to ensure that the Next signal VGL1 can turn off the thirteenth transistor T13, thereby improving output stability.

[0015] Specifically, the transmission method and timing are as follows: Figure 4 , Figure 5 and Figure 6 As shown: interlaced cascading is used, that is, odd-numbered rows are connected and cascaded together, and even-numbered rows are connected and cascaded together.

[0016] The beneficial effects of this invention are as follows: This invention employs a low-level IGZO output and a high-level PMOS-LTPS output. The low-level IGZO has a stronger output capability, while the high-level PMOS-LTPS has a stronger output capability, thus resulting in a stronger circuit driving force and a more stable state.

[0017] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0018] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A CMOS-N scan circuit with stability and drive strength enhancement, characterized by, The application relates to a driving unit for cascaded driving of a display panel. The driving unit comprises a cascade driving module, a low-level maintaining output module, a high-level pulse output module, a high-level pulse output control module and an eleventh transistor; the cascade driving module comprises a first transistor, a second transistor, a third transistor, a first fourth transistor, a second fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor and a second capacitor; the low-level maintaining output module comprises a thirteenth transistor; the high-level pulse output module comprises a twelfth transistor and a third capacitor; and the high-level pulse output control module comprises a ninth transistor and a tenth transistor. ​ The first fourth transistor and the second fourth transistor are connected in series; the gates of the first fourth transistor and the second fourth transistor are connected; the second fourth transistor is connected with the gate of the second transistor, the first transistor, and the sixth transistor respectively; the sixth transistor is connected with the gate of the eighth transistor and the second capacitor respectively; the fifth transistor is connected with the gate of the third transistor, the gate of the seventh transistor, the second transistor, and the first capacitor respectively; the first capacitor is connected with the gate and the source of the seventh transistor respectively; the first transistor and the third transistor are connected; the second capacitor is connected with the gate and the source of the eighth transistor respectively; the gates of the seventh transistor, the eighth transistor, the ninth transistor, and the gate of the thirteenth transistor are connected with each other; the ninth transistor is connected with the tenth transistor and the eleventh transistor respectively; the eleventh transistor is connected with the gate of the twelfth transistor; the third capacitor is connected with the gate and the drain of the twelfth transistor respectively; the twelfth transistor and the thirteenth transistor are connected; the connection lines of the seventh transistor and the eighth transistor in the driving unit of the odd-numbered row are connected with the first fourth transistor in the next-level driving unit in the odd-numbered row; the connection lines of the seventh transistor and the eighth transistor in the driving unit of the even-numbered row are connected with the first fourth transistor in the next-level driving unit in the even-numbered row; the third transistor and the tenth transistor in the driving unit of the odd-numbered row are connected with the VGH terminal outside respectively, the gate of the sixth transistor, the ninth transistor, and the gate of the eleventh transistor are connected with the VGL terminal outside respectively, the thirteenth transistor is connected with the VGL1 terminal outside, the second transistor, the gate of the first fourth transistor, the gate of the second fourth transistor, and the gate of the tenth transistor are connected with the CK1 terminal outside respectively, the gate of the first transistor and the eighth transistor are connected with the XCK1 terminal outside respectively, and the twelfth transistor is connected with the CKA terminal outside; the third transistor and the tenth transistor in the driving unit of the even-numbered row are connected with the VGH terminal respectively, the gate of the sixth transistor, the ninth transistor, and the gate of the eleventh transistor are connected with the VGL terminal respectively, the thirteenth transistor is connected with the VGL2 terminal outside, the second transistor, the gate of the first fourth transistor, the gate of the second fourth transistor, and the gate of the tenth transistor are connected with the CK2 terminal outside respectively, the gate of the first transistor and the eighth transistor are connected with the XCK2 terminal outside respectively, and the twelfth transistor is connected with the CKB terminal outside; the connection lines of the twelfth transistor and the thirteenth transistor are connected with the switch tube of the pixel driving circuit of the display area outside; The cascade drive module is used for shifting the input low level pulse signal; the low level maintaining output module is used for providing a low level output signal in a maintaining stage; the high level pulse output module is used for providing a high level pulse signal in a high level pulse output stage; and the high level pulse output control module is used for controlling the switching of the maintaining stage and the high level pulse output stage.

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