Bus holding circuit and bus holder

Abstract

The embodiment of the invention provides a bus holding circuit and a bus holder. The bus holding circuit comprises a bus holding module, a configuration module and an anti-backflow module, the bus holding module comprises a pull-up unit and a pull-down unit, the anti-backflow module comprises an input unit and an output unit, the configuration module is used for responding to the voltage of the input end of the bus holding circuit and controlling the pull-up unit or the pull-down unit to be conducted, and the bus holding module is used for locking the voltage state of the input end of the bus holding circuit; the first end of the input unit is connected with the input end of the bus holding circuit, the control end of the input unit is connected with the control end of the output unit, and the output unit is used for mirroring the current of the input unit when the voltage of the input end of the bus holding circuit is greater than a first voltage or the first voltage is powered down. According to the scheme, the applicability of the bus holding circuit to different processes can be expanded.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a bus hold circuit and a bus hold device. Background Technology

[0002] Currently, bus hold circuits are widely used in various integrated circuits to provide a stable bus voltage input for functional circuit sections.

[0003] Existing bus hold circuits typically include an inverter, a high-side switch, and a low-side switch. By inverting the input voltage through the inverter, the on / off states of the high-side and low-side switches are controlled, thus achieving voltage level control. To prevent reverse current flow when the input voltage exceeds the chip's power supply voltage, a diode can be added to the high-side branch to maintain unidirectional current flow. However, the introduction of the diode reduces the holding voltage level and necessitates limiting the shoot-through current of the inverter, significantly restricting the applicability of the bus hold circuit. Summary of the Invention

[0004] This invention provides a bus holding circuit and a bus holder to improve the applicability of the bus holding circuit while achieving backflow prevention.

[0005] According to one aspect of the present invention, a bus holding circuit is provided, comprising: a bus holding module, a configuration module, and an anti-backflow module;

[0006] The bus holding module includes a pull-up unit and a pull-down unit, and the anti-backflow module includes an input unit and an output unit. The first terminal of the pull-up unit is connected to a first voltage, the second terminal of the pull-up unit is connected to the first terminal of the output unit, the second terminal of the output unit is connected to the first terminal of the pull-down unit at a first node, the first node is connected to the input terminal of the bus holding circuit, the second terminal of the pull-down unit is connected to a second voltage, the first terminal of the configuration module is connected to the control terminal of the pull-up unit, and the second terminal of the configuration module is connected to the control terminal of the pull-down unit. The configuration module is used to control the pull-up unit or the pull-down unit to conduct in response to the voltage at the input terminal of the bus holding circuit, and the bus holding module is used to lock the voltage state at the input terminal of the bus holding circuit.

[0007] The first end of the input unit is connected to the input end of the bus hold circuit, the control end of the input unit is connected to the control end of the output unit, and the output unit is used to mirror the current of the input unit when the voltage at the input end of the bus hold circuit is greater than the first voltage, or when the first voltage is de-energized.

[0008] Wherein, the first voltage is greater than the second voltage.

[0009] Optionally, the input unit includes a first transistor and a current source, and the output unit includes a second transistor;

[0010] The first terminal of the first transistor is connected to the input terminal of the bus holding circuit, the second terminal of the first transistor is connected to the first terminal of the current source, the second terminal of the current source is grounded, the gate of the first transistor is connected to the second terminal of the first transistor, the gate of the second transistor is connected to the gate of the first transistor, the first terminal of the second transistor is connected to the second terminal of the pull-up unit, and the second terminal of the second transistor is connected to the first node.

[0011] Optionally, the channel width-to-length ratio of the first transistor is the same as that of the second transistor.

[0012] Optionally, the current source includes a third transistor and a first resistor, wherein the first terminal of the third transistor is connected to the second terminal of the first transistor, the second terminal of the third transistor is connected to the first terminal of the first resistor, the second terminal of the first resistor is grounded, and the gate of the third transistor is connected to the second terminal of the first resistor;

[0013] The third transistor is an intrinsic device with a negative threshold voltage.

[0014] Optionally, the anti-backflow module further includes a voltage selection unit, a first terminal of which is connected to the input terminal of the bus holding circuit, a second terminal of which is connected to the first voltage, and a third terminal of which is connected to the body terminal of the first transistor and the body terminal of the second transistor. The voltage selection unit is used to output the maximum of the first voltage and the voltage at the input terminal of the bus holding circuit.

[0015] Both the first transistor and the second transistor are P-type transistors.

[0016] Optionally, the voltage selection unit includes a fourth transistor and a fifth transistor. The gate of the fourth transistor is connected to the first voltage. The first terminal of the fourth transistor is connected to the input terminal of the bus hold circuit. The second terminal of the fourth transistor is connected to the second terminal of the fifth transistor and serves as the third terminal of the voltage selection unit. The gate of the fifth transistor is connected to the input terminal of the bus hold circuit. The first terminal of the fifth transistor is connected to the first voltage.

[0017] Optionally, the configuration module further includes a third terminal, which is connected to a trigger signal and is used to disable or enable the holding function of the bus holding module according to the trigger signal.

[0018] Optionally, the configuration module includes an OR gate, an AND gate, and a first inverter. The first input of the OR gate is connected to the trigger signal, the second input of the OR gate is connected to the inverse signal of the voltage at the input of the bus holding circuit, and the output of the OR gate is connected to the control terminal of the pull-up unit.

[0019] The first input terminal of the AND gate is connected to the output terminal of the first inverter, the input terminal of the first inverter is connected to the trigger signal, and the second input terminal of the AND gate is connected to the second input terminal of the OR gate.

[0020] Optionally, the pull-up unit includes a sixth transistor and a second resistor, and the pull-down unit includes a seventh transistor and a third resistor;

[0021] The first terminal of the sixth transistor is connected to the first terminal of the second resistor, the second terminal of the second resistor is connected to the first voltage, the second terminal of the sixth transistor is connected to the first terminal of the output unit, the first terminal of the seventh transistor is connected to the second terminal of the output unit, the second terminal of the seventh transistor is connected to the first terminal of the third resistor, the second terminal of the third resistor is connected to the second voltage, the gate of the sixth transistor is connected to the first terminal of the configuration module, and the gate of the seventh transistor is connected to the second terminal of the configuration module; wherein, the channel type of the sixth transistor and the channel type of the seventh transistor are opposite.

[0022] The bus hold module further includes a second inverter, the input of which is connected to the first node, and the output of which is connected to the fourth terminal of the configuration module. The configuration module is used to control the pull-up unit or the pull-down unit to be turned on according to the inverse signal of the voltage at the input terminal of the bus hold circuit connected to its fourth terminal.

[0023] According to another aspect of the present invention, a bus hold is provided, including the bus hold circuit provided in any embodiment of the present invention.

[0024] The technical solution provided in this invention configures the bus hold module via a configuration module, enabling the bus hold module to remove the floating input terminal of the bus hold circuit from the high-impedance indeterminate state, thus providing a stable voltage state for the bus. Furthermore, when the voltage at the input terminal IN of the bus hold circuit is higher than a first voltage, or when the first voltage drops, the current of the input unit is mirrored by the output unit to prevent backflow into the power supply terminal from the input terminal of the bus hold circuit. However, unlike solutions provided in related technologies, this does not introduce a forward voltage drop, thereby reducing the performance requirements of the circuit and broadening the applicability of the bus hold circuit to different processes.

[0025] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A schematic diagram of a bus holding circuit provided for related technologies;

[0028] Figure 2 This is a schematic diagram of a bus holding circuit provided in an embodiment of the present invention;

[0029] Figure 3 A schematic diagram of another bus hold circuit provided in an embodiment of the present invention;

[0030] Figure 4 This is a schematic diagram of the structure of a current source provided in an embodiment of the present invention;

[0031] Figure 5 A schematic diagram of another bus hold circuit provided in an embodiment of the present invention;

[0032] Figure 6 A schematic diagram of another bus hold circuit provided in an embodiment of the present invention;

[0033] Figure 7 A schematic diagram of another bus hold circuit provided in an embodiment of the present invention;

[0034] Figure 8 This is a schematic diagram of another bus hold circuit provided in an embodiment of the present invention. Detailed Implementation

[0035] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0036] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0037] Figure 1 A schematic diagram of a bus hold circuit is provided for related technologies, for reference. Figure 1 In related technologies, when the signal at the input terminal IN of the bus hold circuit is low, transistor MN1 in inverter INV1 is off and transistor MP1 is on, causing transistor MNH1 in inverter INV2 to turn on and transistor MPH1 to turn off, thereby locking the signal at the input terminal IN to a low level. When the signal at the input terminal IN of the bus hold circuit is high, transistor MP1 is off and transistor MN1 is on, causing transistor MPH1 to turn on and transistor MNH1 to turn off, thereby locking the signal at the input terminal IN to a high level.

[0038] Diode D1 is used to prevent reverse current flow. When the power supply fails or the signal level at input terminal IN is higher than the power supply voltage, diode D1 can block the reverse current flowing from input terminal IN to the power supply port. Resistors RP and RN are used to adjust the bus holding current capability.

[0039] When the signal at the input terminal IN of the bus holding circuit is at a high level, transistor MPH1 is turned on and transistor MNH1 is turned off. Due to the forward voltage drop VD1 of diode D1, the input terminal IN can only maintain a maximum voltage level of VDD-VD1, where VDD is the power supply voltage. If VD1 is higher than the threshold voltage of transistor MP1, both transistors MP1 and MN1 in inverter INV1 will turn on, causing inverter INV1 to shoot through, which increases power consumption due to the introduced shooting current. To prevent inverter INV1 from shooting through, the forward voltage drop VD1 of diode D1 must be less than the threshold voltage of transistor MP1, which obviously limits the applicability of this circuit to different manufacturing processes.

[0040] To address the aforementioned problems, embodiments of the present invention provide a novel bus hold circuit. Figure 2This is a schematic diagram of a bus hold circuit provided in an embodiment of the present invention, with reference to... Figure 2 The bus holding circuit provided in this embodiment includes a bus holding module 10, a configuration module 20, and an anti-backflow module 30. The bus holding module 10 includes a pull-up unit 101 and a pull-down unit 102. The anti-backflow module 30 includes an input unit 301 and an output unit 302. The first terminal of the pull-up unit 101 is connected to a first voltage V1, and the second terminal of the pull-up unit 101 is connected to the first terminal of the output unit 302. The second terminal of the output unit 302 and the first terminal of the pull-down unit 102 are connected to a first node N1. The first node N1 is connected to the input terminal IN of the bus holding circuit. The second terminal of the pull-down unit 102 is connected to a second voltage V2. The first terminal of the configuration module 20 is connected to the input terminal IN of the bus holding circuit. The control terminal of the pull-up unit 101 is connected, and the second terminal of the configuration module 20 is connected to the control terminal of the pull-down unit 102. The configuration module 20 is used to control the pull-up unit 101 or the pull-down unit 102 to be turned on in response to the voltage of the input terminal IN of the bus holding circuit. The bus holding module 10 is used to lock the voltage state of the input terminal IN of the bus holding circuit. The first terminal of the input unit 301 is connected to the input terminal IN of the bus holding circuit, and the control terminal of the input unit 301 is connected to the control terminal of the output unit 302. The output unit 302 is used to mirror the current of the input unit 301 when the voltage of the input terminal IN of the bus holding circuit is greater than the first voltage V1, or when the first voltage V1 is de-energized.

[0041] Wherein, the first voltage V1 is greater than the second voltage V2. For example, the first voltage V1 is the power supply voltage (high level), and the second voltage V2 is the ground voltage (low level). The bus holding module 10 can, when the input terminal IN of the bus holding circuit is in a high-impedance state (i.e., the bus is in a high-impedance state), pull up the level of the input terminal IN of the bus holding circuit to the level when that port was last driven as an output port, through the pull-up unit 101 or pull-down unit 102. In other words, when the bus is released and enters a high-impedance state, the bus holding module 10 can maintain the bus at the level state when it was last driven, preventing the bus from becoming floating when not driven by any device, thereby avoiding level instability or interference.

[0042] For example, when the input terminal IN of the bus holding circuit is in a high-level state for the last time it is driven, the configuration module 20 responds to the high level of the input terminal IN by turning on the pull-up unit 101 and turning off the pull-down unit 102, locking the voltage of the first node N1 to the first voltage V1, that is, locking the input terminal IN of the bus holding circuit to a high-level state. When the input terminal IN of the bus holding circuit is in a low-level state for the last time it is driven, the configuration module 20 responds to the low level of the input terminal IN by turning on the pull-down unit 102 and turning off the pull-up unit 101, locking the voltage of the first node N1 to the second voltage V2, that is, locking the input terminal IN of the bus holding circuit to a low-level state.

[0043] When the voltage at the input terminal IN of the bus holding circuit is higher than the first voltage V1, or when the first voltage V1 is de-energized, the input unit 301 and the output unit 302 form a current mirror. The output unit 302 mirrors the current in the input unit 301, and the current flowing through the output unit 302 is controlled by the input unit 301.

[0044] Specifically, for reverse current to occur, the reverse current flowing from the input terminal IN of the bus holding circuit into the power supply terminal (the power supply terminal is used to output the first voltage V1) needs to be greater than the current that the output unit 302 can provide. However, the characteristic of the current mirror is that the current of the output unit 302 is determined by the current of the input unit 301 and remains constant. Therefore, when the reverse current is less than the current of the output unit 302, the output unit 302 can handle the reverse current through constant current, preventing the reverse current from flowing further into the power supply terminal. When the reverse current is greater than the current of the output unit 302, since the current of the output unit 302 is locked to the current of the input unit 301 (mirror current), the excess reverse current will cause the voltage difference across the output unit 302 to change, causing the output unit 302 to enter the off state, thereby blocking the reverse current from flowing into the power supply terminal.

[0045] The technical solution provided in this embodiment of the invention configures the bus holding module 10 through the configuration module 20, enabling the bus holding module 10 to remove the floating input terminal IN of the bus holding circuit from the high-impedance indeterminate state, thus providing a stable voltage state for the bus. Furthermore, when the voltage at the input terminal IN of the bus holding circuit is higher than the first voltage V1, or when the first voltage V1 is de-energized, the current of the input unit 301 is mirrored through the output unit 302, preventing backflow of the input terminal IN of the bus holding circuit into the power supply. However, unlike solutions provided in related technologies, this does not introduce a conduction voltage drop, thereby reducing the performance requirements of the circuit and broadening the applicability of the bus holding circuit to different processes.

[0046] Figure 3 This is a schematic diagram of another bus hold circuit provided in an embodiment of the present invention, with reference to... Figure 3 Based on the above embodiments, optionally, the input unit 301 includes a first transistor M1 and a current source IL, and the output unit 302 includes a second transistor M2. The first terminal of the first transistor M1 is connected to the input terminal IN of the bus holding circuit, the second terminal of the first transistor M1 is connected to the first terminal of the current source IL, the second terminal of the current source IL is grounded, the gate of the first transistor M1 is connected to the second terminal of the first transistor M1, the gate of the second transistor M2 is connected to the gate of the first transistor M1, the first terminal of the second transistor M2 is connected to the second terminal of the pull-up unit 101, and the second terminal of the second transistor M2 is connected to the first node N1.

[0047] The second transistor M2 has the same channel width-to-length ratio as the first transistor M1, so that the current of the second transistor M2 is limited to the current of the current source IL, thereby preventing backflow.

[0048] In this embodiment, in order to reduce the leakage current at the input terminal IN of the bus holding circuit, the current of the current source IL can be set to the submicroamp level. Figure 4 This is a schematic diagram of a current source provided in an embodiment of the present invention, combined with... Figure 3 and Figure 4 The current source IL includes a third transistor M3 and a first resistor R1. The first terminal of the third transistor M3 is connected to the second terminal of the first transistor M1. The second terminal of the third transistor M3 is connected to the first terminal of the first resistor R1. The second terminal of the first resistor R1 is grounded. The gate of the third transistor M3 is connected to the second terminal of the first resistor R1.

[0049] In this design, the third transistor M3 is an intrinsic device with a negative threshold voltage to reduce the current value, thereby reducing the mirror current. For example, the third transistor M3 can be a metal-oxide-semiconductor field-effect transistor. In this case, the current of the current source IL can be characterized as VTH / r1, where VTH is the threshold voltage of the third transistor M2, and r1 is the resistance value of the first resistor R1.

[0050] In this embodiment, since the current source IL can provide a stable and predictable reference current, the current mirror formed by the first transistor M1 and the second transistor M2 can more accurately replicate the current, avoiding additional leakage current due to current mirror mismatch. Furthermore, since the reference current provided by the current source IL is very small (e.g., less than 1 microamp), the second transistor M2 can mirror this reference current 1:1. Therefore, regardless of how much higher the voltage at the input terminal IN of the bus holding circuit is than the first voltage V1, the leakage current between the input terminal IN of the bus holding circuit and the power supply terminal can be limited to the level of this reference current. This significantly reduces leakage current while preventing reverse current flow, effectively blocking reverse current flow.

[0051] Figure 5 This is a schematic diagram of another bus hold circuit provided in an embodiment of the present invention, with reference to... Figure 5 Based on the above embodiments, optionally, the anti-backflow module 30 further includes a voltage selection unit 303. The first end of the voltage selection unit 303 is connected to the input terminal IN of the bus holding circuit, the second end of the voltage selection unit 303 is connected to the first voltage V1, and the third end of the voltage selection unit 303 is connected to the body terminal of the first transistor M1 and the body terminal of the second transistor M2. The voltage selection unit 303 is used to output the larger of the first voltage V1 and the voltage of the input terminal IN of the bus holding circuit.

[0052] In this configuration, both the first transistor M1 and the second transistor M2 are P-type transistors. The voltage selection unit 303 transmits the maximum of the first voltage V1 and the voltage at the input terminal IN of the bus hold circuit to the body terminals of the first transistor M1 and the second transistor M2. This ensures that the parasitic body diodes of the first transistor M1 and the second transistor M2 do not conduct forward, eliminating the leakage path from the input terminal IN of the bus hold circuit through the parasitic body diode of the second transistor M2 to the power supply terminal. This reduces the leakage path for reverse current and further prevents current reverse flow. Here, the body terminal of the transistor refers to the N-well Bulk terminal of the transistor.

[0053] Optionally, continue to refer to Figure 5 The voltage selection unit 303 includes a fourth transistor M4 and a fifth transistor M5. The gate of the fourth transistor M4 is connected to a first voltage V1. The first terminal of the fourth transistor M4 is connected to the input terminal IN of the bus holding circuit. The second terminal of the fourth transistor M4 is connected to the second terminal of the fifth transistor M5 and serves as the third terminal of the voltage selection unit 303. The gate of the fifth transistor M5 is connected to the input terminal IN of the bus holding circuit. The first terminal of the fifth transistor M5 is connected to the first voltage V1.

[0054] Specifically, both the fourth transistor M4 and the fifth transistor M5 are P-type transistors. When the voltage at the input terminal IN of the bus hold circuit is greater than the first voltage V1, the fourth transistor M4 is turned on and the fifth transistor M5 is turned off. The voltage at the input terminal IN of the bus hold circuit is transmitted to the body terminals of the first transistor M1 and the second transistor M2 via the fourth transistor M4. When the voltage at the input terminal IN of the bus hold circuit is less than the first voltage V1, the fourth transistor M4 is turned off and the fifth transistor M5 is turned on. The first voltage V1 is transmitted to the body terminals of the first transistor M1 and the second transistor M2 via the fifth transistor M5. This voltage selection unit 303 has a simple structure. Regardless of whether the voltage at the input terminal IN of the bus hold circuit is large or the first voltage V1 is large, it can ensure that the parasitic body diodes of the first transistor M1 and the second transistor M2 are in the off state, further blocking the reverse current.

[0055] Figure 6 This is a schematic diagram of another bus hold circuit provided in an embodiment of the present invention, with reference to... Figure 6 Optionally, based on the above embodiments, the configuration module 20 further includes a third terminal, which is connected to a trigger signal VP. This third terminal is used to disable or enable the holding function of the bus holding module 10 according to the trigger signal VP. In other words, regardless of whether the voltage at the input terminal IN of the bus holding circuit is high or low, the configuration module 20 can respond to the trigger signal VP to disable or enable the holding function of the bus holding module 10.

[0056] The enabling of the holding function of the bus holding module 10 means that the trigger signal VP no longer forcibly controls the output of the first and second terminals of the configuration module 20. The signals output by the first and second terminals of the configuration module 20 are determined by the voltage of the input terminal IN of the bus holding circuit, and thus determine the enabling state of the pull-up unit 101 and the pull-down unit 102.

[0057] The holding function of the shielded bus holding module 10 refers to the fact that the trigger signal VP forcibly controls the outputs of the first and second terminals of the configuration module 20. Under the control of the trigger signal VP, the signals output by the first and second terminals of the configuration module 20 keep the pull-up unit 101 and the pull-down unit 102 in a constantly off state. At this time, regardless of whether the driving capability of the preceding device corresponding to the input terminal IN of the bus holding circuit is strong or weak, the input terminal IN of the bus holding circuit can be easily switched from one locked state to another locked state.

[0058] Optionally, the bus hold circuit can be packaged in the chip, and the third terminal of the configuration module 20 can be brought out to the outside of the chip pins, facilitating flexible configuration of the input terminal IN of the bus hold circuit to enable or disable the bus hold function. Alternatively, during the chip packaging stage, the third terminal can be shorted to the port of the first voltage V1 (high-level port) or the port of the second voltage V1 (low-level port) by wire bonding, thereby forming a product with the bus hold function enabled and a product with the bus hold function disabled, respectively.

[0059] Figure 7 This is a schematic diagram of another bus hold circuit provided in an embodiment of the present invention, with reference to... Figure 7Based on the above embodiments, optionally, the pull-up unit 101 includes a sixth transistor M6 and a second resistor R2, and the pull-down unit 102 includes a seventh transistor M7 and a third resistor R3. The first terminal of the sixth transistor M6 is connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is connected to a first voltage V1. The second terminal of the sixth transistor M6 is connected to the first terminal of the output unit 302, the first terminal of the seventh transistor M7 is connected to the second terminal of the output unit 302, the second terminal of the seventh transistor M7 is connected to the first terminal of the third resistor R3, and the second terminal of the third resistor R3 is connected to a second voltage V2. The gate of the sixth transistor M6 is connected to the first terminal of the configuration module 20, and the gate of the seventh transistor M7 is connected to the second terminal of the configuration module 20.

[0060] In this configuration, the sixth transistor M6 and the seventh transistor M7 have opposite channel types; for example, the sixth transistor M6 is a P-type transistor and the seventh transistor M7 is an N-type transistor, so that the configuration module 20 can control the sixth transistor M6 and the seventh transistor M7 respectively. Here, the sixth transistor M6 and the seventh transistor M7 are turned on in a time-sharing manner.

[0061] Optionally, the bus hold module 10 further includes a second inverter IV2. The input of the second inverter IV2 is connected to the first node N1, and the output of the second inverter IV2 is connected to the fourth terminal of the configuration module 20. The configuration module 20 is used to control the pull-up unit 101 or the pull-down unit 102 to be turned on according to the inverse signal of the voltage of the input terminal IN of the bus hold circuit connected to its fourth terminal. For example, after the configuration module 20 enables the hold function of the bus hold module 10, if the voltage of the input terminal IN of the bus hold circuit is high and lower than the first voltage V1, the configuration module 20 responds to the low level output of the second inverter IV2 and turns on the sixth transistor M6. At this time, since the voltage of the input terminal IN of the bus hold circuit is lower than the first voltage V1, and the gates of the first transistor M1 and the second transistor M2 are at the same potential, the second transistor M2 will necessarily be turned on, thereby keeping the voltage of the input terminal IN of the bus hold circuit at a high level, and the voltage of the input terminal IN of the bus hold circuit close to the first voltage V1, effectively preventing the bus hold module 10 from forming a punch-through current. If the voltage at the input terminal IN of the bus hold circuit is low, the configuration module 20 responds to the high level output of the second inverter IV2 by turning on the seventh transistor M7, thereby keeping the voltage at the input terminal IN of the bus hold circuit low.

[0062] Configuration module 20 responds to the signal output by the second inverter IV2 to control the sixth transistor M6 or the seventh transistor M7 to turn on.

[0063] Optionally, the second inverter IV2 can be a Schmitt trigger inverter. Utilizing the hysteresis characteristic of the Schmitt trigger inverter, the noise immunity of the input IN of the bus hold circuit can be improved. The second resistor R2 and the third resistor R3 are used to adjust the latch-up capability of the input IN of the bus hold circuit, so that the sixth transistor M6 can pull the input IN of the bus hold circuit high, or the seventh transistor M6 can pull the input IN of the bus hold circuit low.

[0064] Figure 8 This is a schematic diagram of another bus hold circuit provided in an embodiment of the present invention, with reference to... Figure 8 Based on the above embodiments, optionally, the configuration module 20 includes an OR gate, an AND gate, and a first inverter IV1. The first input terminal of the OR gate is connected to a trigger signal VP, and the second input terminal of the OR gate is connected to the inverse signal of the voltage of the input terminal IN of the bus holding circuit (i.e., connected to the output terminal of the second inverter IV2). The output terminal of the OR gate is connected to the control terminal of the pull-up unit 101. The first input terminal of the AND gate is connected to the output terminal of the first inverter IV1, the input terminal of the first inverter IV1 is connected to the trigger signal VP, and the second input terminal of the AND gate is connected to the second input terminal of the OR gate.

[0065] Specifically, when the trigger signal VP is high, regardless of whether the voltage at the input terminal IN of the bus hold circuit is low or high, the OR gate always outputs a high level and the AND gate always outputs a low level. Therefore, the sixth transistor M6 and the seventh transistor M7 are always turned off, thus disabling the hold function of the input terminal IN of the bus hold circuit.

[0066] When the trigger signal VP is low, the hold function of the input terminal IN of the bus hold circuit is enabled. If the voltage at the input terminal IN of the bus hold circuit is high and lower than the first voltage V1, then the OR gate outputs a low level, the AND gate outputs a low level, the sixth transistor M6 is turned on, and the seventh transistor M7 is turned off. Since the voltage at the input terminal IN of the bus hold circuit is lower than the first voltage V1, and the gates of the first transistor M1 and the second transistor M2 are at the same potential, the second transistor M2 will necessarily be turned on, thereby keeping the voltage at the input terminal IN of the bus hold circuit at a high level. Furthermore, the voltage at the input terminal IN of the bus hold circuit is close to the first voltage V1, effectively preventing the bus hold module 10 from generating a punch-through current. If the voltage at the input terminal IN of the bus hold circuit is low, then the OR gate outputs a high level, the AND gate outputs a high level, the sixth transistor M6 is turned off, and the seventh transistor M7 is turned on, thereby keeping the voltage at the input terminal IN of the bus hold circuit at a low level.

[0067] The present invention provides a bus hold circuit that can help the floating input terminal IN get out of the high-impedance indeterminate state, and the anti-backflow module 30 can block the backflow current flowing from the input terminal IN to the power supply terminal, but will not introduce a conduction voltage drop like the diode in the related technology. At the same time, the bus hold function can be enabled or disabled by the configuration module 20, thereby extending the applicability of the bus hold circuit.

[0068] Optionally, the present invention also provides a bus holder, which includes the bus holding circuit provided in any embodiment of the present invention. Therefore, the bus holder also has the beneficial effects described in the above embodiments.

[0069] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0070] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A bus hold circuit, characterized by, The application relates to a bus holding module, a configuration module and an anti-backflow module. The bus holding module comprises a pull-up unit and a pull-down unit, the anti-backflow module comprises an input unit and an output unit, the first end of the pull-up unit is connected to a first voltage, the second end of the pull-up unit is connected to the first end of the output unit, the second end of the output unit is connected to the first end of the pull-down unit at a first node, the first node is connected to the input end of the bus holding circuit, the second end of the pull-down unit is connected to a second voltage, the first end of the configuration module is connected to the control end of the pull-up unit, the second end of the configuration module is connected to the control end of the pull-down unit, the configuration module is used for controlling the pull-up unit or the pull-down unit to be turned on in response to the voltage of the input end of the bus holding circuit, and the bus holding module is used for locking the voltage state of the input end of the bus holding circuit. The first end of the input unit is connected to the input end of the bus holding circuit, the control end of the input unit is connected to the control end of the output unit, and the output unit is used for mirroring the current of the input unit when the voltage of the input end of the bus holding circuit is greater than the first voltage or the first voltage is powered off. The first voltage is greater than the second voltage. The input unit comprises a first transistor and a current source, and the output unit comprises a second transistor.

2. The bus-keeping circuit according to claim 1, characterized in that The first pole of the first transistor is connected to the input end of the bus holding circuit, the second pole of the first transistor is connected to the first end of the current source, the second end of the current source is grounded, the gate of the first transistor is connected to the second pole of the first transistor, the gate of the second transistor is connected to the gate of the first transistor, the first pole of the second transistor is connected to the second end of the pull-up unit, and the second pole of the second transistor is connected to the first node. The channel width-length ratio of the first transistor is the same as the channel width-length ratio of the second transistor.

3. The bus-keeping circuit according to claim 2, characterized in that The current source comprises a third transistor and a first resistor, the first pole of the third transistor is connected to the second pole of the first transistor, the second pole of the third transistor is connected to the first end of the first resistor, the second end of the first resistor is grounded, and the gate of the third transistor is connected to the second end of the first resistor.

4. The bus-keeping circuit of claim 2, wherein, The third transistor is an intrinsic device with a negative threshold voltage. The anti-backflow module further comprises a voltage selection unit, the first end of the voltage selection unit is connected to the input end of the bus holding circuit, the second end of the voltage selection unit is connected to the first voltage, the third end of the voltage selection unit is connected to the bulk terminal of the first transistor and the bulk terminal of the second transistor, and the voltage selection unit is used for outputting the maximum of the first voltage and the voltage of the input end of the bus holding circuit.

5. The bus-keeper circuit of claim 2, wherein, The first transistor and the second transistor are both P-type transistors. ​ 6. The bus-keeping circuit of claim 5, wherein, The voltage selection unit comprises a fourth transistor and a fifth transistor, a gate of the fourth transistor is connected to the first voltage, a first pole of the fourth transistor is connected to an input end of the bus holding circuit, a second pole of the fourth transistor is connected to a second pole of the fifth transistor and serves as a third end of the voltage selection unit, a gate of the fifth transistor is connected to the input end of the bus holding circuit, and a first pole of the fifth transistor is connected to the first voltage.

7. The bus-keeper circuit of claim 1, wherein, The configuration module further comprises a third end, and the third end of the configuration module is connected to a trigger signal, so as to shield or open the holding function of the bus holding module according to the trigger signal.

8. The bus-keeping circuit of claim 7, wherein, The configuration module comprises an OR gate, an AND gate and a first inverter, a first input end of the OR gate is connected to the trigger signal, a second input end of the OR gate is connected to an inverse signal of the voltage of the input end of the bus holding circuit, and an output end of the OR gate is connected to a control end of the pull-up unit. A first input end of the AND gate is connected to an output end of the first inverter, an input end of the first inverter is connected to the trigger signal, and a second input end of the AND gate is connected to the second input end of the OR gate.

9. The bus-keeper circuit of claim 1, wherein, The pull-up unit comprises a sixth transistor and a second resistor, and the pull-down unit comprises a seventh transistor and a third resistor. A first pole of the sixth transistor is connected to a first end of the second resistor, a second end of the second resistor is connected to the first voltage, a second pole of the sixth transistor is connected to a first end of the output unit, a first pole of the seventh transistor is connected to a second end of the output unit, a second pole of the seventh transistor is connected to a first end of the third resistor, a second end of the third resistor is connected to the second voltage, a gate of the sixth transistor is connected to the first end of the configuration module, and a gate of the seventh transistor is connected to the second end of the configuration module; wherein the channel type of the sixth transistor is opposite to the channel type of the seventh transistor. The bus holding module further comprises a second inverter, an input end of the second inverter is connected to the first node, and an output end of the second inverter is connected to a fourth end of the configuration module, so as to control the pull-up unit or the pull-down unit to be turned on according to the inverse signal of the voltage of the input end of the bus holding circuit connected to the fourth end of the configuration module.

10. A bus holder, characterized by The bus holding circuit comprises the bus holding circuit according to any one of claims 1-9.

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