A frequency control method and system for a digitally controlled oscillator

Abstract

This invention provides a frequency control method and system for a digitally controlled oscillator, relating to the technical field of frequency control for digitally controlled oscillators. The method includes obtaining the current gate length value of the digitally controlled oscillator, performing gate counting on the output clock of the oscillator based on the current gate length value to obtain an in-gate counting sequence, calculating a noise estimate based on the in-gate counting sequence, determining a target gate length value based on the noise estimate, determining an instantaneous frequency ratio based on the target gate length value, calculating a smoothing factor based on the noise estimate and the target gate length value, smoothing the instantaneous frequency ratio based on the smoothing factor to obtain a smoothed frequency ratio, determining a target frequency tuning word based on the smoothed frequency ratio, and adjusting the output frequency of the digitally controlled oscillator based on the target frequency tuning word. This method improves the dynamic performance, steady-state accuracy, and environmental adaptability of the digitally controlled oscillator's frequency control.

Description

Technical Field

[0001] This invention relates to the technical field of frequency control of digitally controlled oscillators, and in particular to a frequency control method and system for digitally controlled oscillators. Background Technology

[0002] As the core frequency source in modern communication, radar, and test and measurement equipment, the stability and accuracy of the output frequency of a digitally controlled oscillator directly determine the performance of the entire system. Especially in applications such as broadcasting and software-defined radio, digitally controlled oscillators are required to have extremely low phase noise and frequency jitter during steady-state operation to meet strict spectrum mask specifications. They are also required to have fast frequency switching and locking capabilities during dynamic processes such as channel switching and mode reconstruction to improve system throughput and response efficiency.

[0003] In digital logic platforms such as FPGAs, a typical method for closed-loop control of the frequency of a digitally controlled oscillator (DCO) is to employ a gate-based counting technique. The basic principle of this method is as follows: a gate signal is generated within a highly stable reference clock domain; the clock cycles of the DCO are counted during the effective period of this gate signal; and the DCO frequency is estimated by processing the count value. This results in the generation of a frequency tuning word for feedback correction of the DCO, forming a closed-loop control system.

[0004] However, existing solutions typically employ a fixed gating period combined with a fixed-parameter filtering algorithm. This fixed-parameter design paradigm has the following drawbacks: First, while a long fixed gate period can effectively smooth noise and achieve lower steady-state jitter, it leads to slow system response and excessively long convergence time to the new frequency point during frequency switching or system startup due to the need to accumulate a large amount of counting data. Second, while a short fixed gate period can quickly output measurement values ​​and has a fast response speed, the variance of individual measurement values ​​is large, resulting in significant noise and large steady-state frequency output jitter. Furthermore, fixed-parameter filters cannot adapt to environmental changes and are prone to significant transient spectral interference during large frequency step updates. Summary of the Invention

[0005] In view of the above-mentioned shortcomings in the existing technology, the purpose of this invention is to provide a frequency control method for a digitally controlled oscillator, which has the characteristics of improving the dynamic performance, steady-state accuracy and environmental adaptability of the frequency control of the digitally controlled oscillator.

[0006] The above-mentioned objective of this invention is achieved through the following technical solution:

[0007] A frequency control method for a digitally controlled oscillator, comprising:

[0008] Obtain the current gate duration value of the digitally controlled oscillator, and perform gated counting on the output clock of the digitally controlled oscillator based on the current gate duration value to obtain the gate counting sequence;

[0009] The noise estimate is calculated based on the gate counting sequence.

[0010] Based on the noise estimate, the target gate length value is determined;

[0011] Based on the target gate length value, determine the instantaneous frequency ratio;

[0012] The smoothing factor is calculated based on the noise estimate and the target gate length value;

[0013] The instantaneous frequency ratio is smoothed based on the smoothing factor to obtain a smoothed frequency ratio.

[0014] The target frequency tuning word is determined based on the smooth frequency ratio, and the output frequency of the digitally controlled oscillator is adjusted based on the target frequency tuning word.

[0015] By adopting the above technical solution, the noise estimate of the gate counting sequence can be calculated in real time, and the target gate length and the smoothing factor of the exponentially weighted smoothing can be dynamically adjusted accordingly. This effectively solves the technical problem that long gates have small steady-state jitter but slow response, while short gates have fast response but large noise under fixed gate periods. This not only enables rapid convergence during frequency switching and startup, and maintains low noise during steady-state operation, but also ensures smooth frequency switching without jumps through smoothing processing, thereby improving dynamic response speed, steady-state accuracy and overall reliability.

[0016] Preferably, the step of calculating the noise estimate based on the gate counting sequence includes:

[0017] From the counting sequence within the gate, a subsequence of a preset length is extracted in chronological order to construct a calculation window;

[0018] Calculate the statistical dispersion of all count values ​​within the calculation window to obtain the initial statistic.

[0019] The initial statistics are normalized and scaled to obtain the noise estimate.

[0020] By adopting the above technical solution, a sliding calculation window is constructed and the statistical dispersion of the count values ​​within the window is calculated. This effectively captures and quantifies the short-term fluctuation characteristics of the gated count sequence in the time domain, thereby achieving accurate and real-time estimation of measurement noise. Furthermore, by normalizing and scaling the initial statistics, the influence of the absolute value of the gate length on the noise assessment results is eliminated, making the final noise estimate an accurate and standardized evaluation index.

[0021] Preferably, determining the target gate length value based on the noise estimate includes:

[0022] The noise estimate is compared with a preset upper threshold and a preset lower threshold, respectively.

[0023] If the noise estimate is greater than the preset upper limit threshold, then the current gate length value is increased to obtain an adjustment value;

[0024] If the noise estimate is less than the preset lower threshold, then the current gate length value is reduced to obtain the adjustment value;

[0025] If the noise estimate is between the preset upper threshold and the preset lower threshold, then the current gate length value is used as the adjustment value;

[0026] Based on the adjusted values, the target gate duration value is determined.

[0027] By adopting the above technical solution, the gate length can be automatically adjusted according to the real-time noise level: when the noise is high, the gate length is automatically extended to improve measurement accuracy, and when the noise is low, the gate length is automatically shortened to speed up the response. This dual-threshold control strategy avoids frequent jitter of the gate length near the threshold and ensures that its dynamic performance can be automatically optimized under different noise environments, thereby achieving an adaptive balance between suppressing measurement noise and improving response speed.

[0028] Preferably, determining the target threshold length value based on the adjusted value includes:

[0029] The adjusted value is compared with the preset minimum threshold value and the preset maximum threshold value, respectively.

[0030] If the adjustment value is greater than the preset maximum threshold value, then the preset maximum threshold value is used as the target threshold length value.

[0031] If the adjustment value is less than the preset minimum threshold value, then the preset minimum threshold value is used as the target threshold length value;

[0032] If the adjusted value is between the preset minimum threshold value and the preset maximum threshold value, then the adjusted value is used as the target threshold length value.

[0033] By adopting the above technical solution, the adjusted gate duration value is limited to a preset minimum and maximum value, ensuring that the gate duration length is always within the effective working range. This not only prevents the measurement noise from increasing sharply due to an excessively short gate duration, but also avoids the system response lag caused by an excessively long gate duration. Thus, while ensuring the flexibility of adaptive adjustment, it also provides a fundamental guarantee for the accuracy and real-time performance of frequency control.

[0034] Preferably, determining the instantaneous frequency ratio corresponding to the current gating count based on the target gate duration value includes:

[0035] The target gate length value is used to perform gate counting to obtain the actual count value of the current gate period;

[0036] The instantaneous frequency ratio is obtained based on the ratio of the actual count value to the target gate length value.

[0037] By adopting the above technical solution, the target gate length value determined adaptively is used for actual counting, and the instantaneous frequency ratio is obtained by calculating the ratio of the count value to the gate length. This realizes the direct frequency measurement principle based on gated counting, effectively eliminates the problem of inconsistent measurement benchmarks caused by gate changes, ensures the accuracy and comparability of the instantaneous frequency ratio, and thus guarantees the measurement accuracy and stability of frequency control.

[0038] Preferably, the step of smoothing the instantaneous frequency ratio based on the smoothing factor to obtain a smoothed frequency ratio includes:

[0039] Obtain the historical smoothed frequency ratio;

[0040] Based on the smoothing factor, the historical smoothing frequency ratio, and the instantaneous frequency ratio, the smoothing frequency ratio is calculated using exponential weighted smoothing.

[0041] By adopting the above technical solution, the ratio of the current instantaneous frequency measured is exponentially weighted and fused with the historical smoothed value. This not only effectively utilizes the stability of historical data but also takes into account the real-time nature of the current measurement. It can effectively suppress the fluctuation of the measured value caused by short-term noise while maintaining the ability to track the real changes in frequency. Thus, the stability and accuracy of frequency control are improved while ensuring dynamic response performance.

[0042] Preferably, determining the target frequency tuning word based on the smooth frequency ratio includes:

[0043] The initial frequency tuning word is determined based on the preset output frequency value, the smoothed frequency ratio, and the bit width of the frequency tuning word register of the digitally controlled oscillator.

[0044] The initial frequency tuning word is rounded down to obtain the target frequency tuning word.

[0045] By adopting the above technical solution, the initial frequency tuning word is accurately calculated by comprehensively considering the preset output frequency value, smooth frequency ratio, and register bit width. After rounding, the final target frequency tuning word is obtained, ensuring the precise matching between the frequency control instruction and the hardware characteristics of the digitally controlled oscillator.

[0046] The second objective of this invention is to provide a frequency control system for a digitally controlled oscillator, which features improved dynamic performance, steady-state accuracy, and environmental adaptability of the digitally controlled oscillator's frequency control.

[0047] The second objective of this invention is achieved through the following technical solution:

[0048] A frequency control system for a digitally controlled oscillator, comprising:

[0049] The gated counting module is used to obtain the current gate length value of the digitally controlled oscillator and perform gated counting on the output clock of the digitally controlled oscillator based on the current gate length value to obtain the gate counting sequence;

[0050] The noise estimation module is used to calculate the noise estimate based on the gate counting sequence;

[0051] A gate duration adaptive module is used to determine the target gate duration value based on the noise estimate;

[0052] The frequency ratio calculation module is used to determine the instantaneous frequency ratio based on the target gate length value;

[0053] A smoothing factor calculation module is used to calculate a smoothing factor based on the noise estimate and the target threshold length value;

[0054] A smoothing module is used to smooth the instantaneous frequency ratio based on the smoothing factor to obtain a smoothed frequency ratio.

[0055] The frequency tuning word adjustment module is used to determine the target frequency tuning word based on the smoothed frequency ratio, and to adjust the output frequency of the digitally controlled oscillator based on the target frequency tuning word.

[0056] By adopting the above technical solution, a closed-loop control system integrating noise perception, parameter adaptation, and smooth control was constructed. The system uses a gate counting module to convert the time-domain instability of the DCO output frequency into an in-gate counting sequence. The noise estimation module calculates the noise estimate in real time to accurately assess the signal-to-noise ratio of the measurement environment. The gate duration adaptation module dynamically adjusts the target gate duration length according to the noise estimate, effectively solving the technical problems of slow response but low steady-state jitter for long gates and high noise for short gates under fixed gate duration. The smoothing factor calculation module maps the noise estimate and the target gate duration length together into a smoothing factor. The smoothing processing module performs exponential weighted smoothing on the instantaneous frequency ratio accordingly, forming a dual adaptive mechanism. The frequency tuning word adjustment module determines the target frequency tuning word based on the smoothed frequency ratio. While ensuring frequency control accuracy, the system achieves rapid convergence during frequency switching and low noise performance during steady-state operation, thereby improving the dynamic response speed, steady-state accuracy, and overall reliability of the system.

[0057] The third objective of this invention is to provide an electronic device that improves the dynamic performance, steady-state accuracy, and environmental adaptability of digitally controlled oscillators in frequency control.

[0058] The above-mentioned objective three of this invention is achieved through the following technical solution:

[0059] An electronic device includes a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and execute the frequency control method of any of the above-described digitally controlled oscillators.

[0060] The fourth objective of this invention is to provide a computer storage medium capable of storing corresponding programs, which facilitates the improvement of the dynamic performance, steady-state accuracy, and environmental adaptability of digitally controlled oscillators in frequency control.

[0061] The fourth objective of this invention is achieved through the following technical solution:

[0062] A computer-readable storage medium storing a computer program that can be loaded by a processor and executed as a frequency control method for any of the aforementioned digitally controlled oscillators.

[0063] In summary, the present invention has at least one of the following beneficial technical effects:

[0064] 1. This invention effectively solves the contradiction between response speed and steady-state noise when the gate period is fixed by dynamically adjusting the gate period length and smoothing factor by estimating the noise level of the gate counting sequence in real time. It achieves fast convergence of frequency switching and steady-state low-noise operation, and effectively improves the dynamic response speed, steady-state accuracy and overall reliability of digitally controlled oscillators.

[0065] 2. This invention limits the gate duration value to a preset minimum and maximum value, effectively preventing noise increase caused by excessively short gate duration and response hysteresis caused by excessively long gate duration. While ensuring the flexibility of adaptive adjustment, it provides a fundamental guarantee for the accuracy and real-time performance of frequency control. Attached Figure Description

[0066] Figure 1 This is a flowchart illustrating the steps of a frequency control method for a digitally controlled oscillator provided in Embodiment 1 of the present invention.

[0067] Figure 2 This is a structural block diagram of a frequency control system for a digitally controlled oscillator provided in Embodiment 2 of the present invention. Detailed Implementation

[0068] This invention provides a frequency control method and system for a digitally controlled oscillator, addressing the technical problem in existing technologies where intelligent adjustment based on actual conditions is impossible, leading to the inability to simultaneously achieve the conflicting performance indicators of "fast dynamic response" and "high steady-state accuracy." It effectively improves the dynamic performance, steady-state accuracy, and environmental adaptability of the digitally controlled oscillator's frequency control.

[0069] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0070] It should be noted that the terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this disclosure.

[0071] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article, unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0072] Example 1:

[0073] Please see Figure 1 The present invention provides a frequency control method for a digitally controlled oscillator, comprising:

[0074] Step 101: Obtain the current gate duration value of the digitally controlled oscillator, and perform gated counting on the output clock of the digitally controlled oscillator based on the current gate duration value to obtain the gate counting sequence.

[0075] A digitally controlled oscillator (DCO) is an oscillator whose output frequency is directly controlled by a digital frequency tuning word. Its output frequency is determined by the input frequency tuning word, and it is the core device for realizing digital-to-frequency conversion.

[0076] The current gate length value refers to the length of the time window used for the current frequency measurement. This value is measured in the number of cycles of the system reference clock and determines the duration reference of a single frequency measurement.

[0077] The output clock refers to the high-frequency clock signal generated by a digitally controlled oscillator, and is the target of frequency measurement.

[0078] The gate counting sequence refers to a series of count values ​​obtained by counting the output clock within a continuous time gate period, which is used to reflect the fluctuation of the output frequency over time.

[0079] Understandably, after the system starts or completes the previous frequency control cycle, it first retrieves the current gate duration value N from the configurable gate duration parameter register. It is worth mentioning that the system's initial gate duration value is a preset minimum gate duration value. In the formula, Here, m is the minimum gate duration value, and m is the adjustment gate duration value. The range of m is limited to... Between, for example =[20,26], corresponding to the threshold length value Then in The change between [variable values]. Set the initial threshold to [value]. This ensures that effective frequency measurements can be performed immediately upon system startup, frequency switching, or relocking, thereby achieving rapid convergence.

[0080] Subsequently, a synchronization gating signal generated by digital logic enables counting of the high-frequency clock signal output by the digitally controlled oscillator (DCO) within a time window lasting N reference clock cycles. The gating counting operation is completed under the control of cross-clock domain synchronization logic to ensure reliable synchronization between the high-frequency counting signal and the reference clock domain. When the gating signal is valid, the counter increments on the rising edge of the DCO output clock. When the gating signal ends, the counter value is latched into the data register, forming the in-gate count value for the current gate period. Simultaneously, the counter automatically resets to prepare for the next measurement, and the sequence of count values ​​obtained from multiple consecutive threshold measurements is calculated. This constitutes the gate counting sequence.

[0081] It is understandable that, within a given k-th gate period, The count value is calculated as follows:

[0082] In the formula, This represents the actual count value of the DCO output clock during the k-th gate period. Let k be the length value of the kth gate period. The output clock frequency of the DCO. This is the system's reference clock frequency.

[0083] It should be noted that, It is a highly stable preset constant provided by an external clock chip (such as AD9517). This value is an optimal value determined based on comprehensive factors such as DCO performance, experimental manual, system frequency requirements and resolution. At the same time, the clock chip usually contains a phase-locked loop, and its lock detection signal is used to indicate whether the output clock is in a stable and locked state.

[0084] In this embodiment of the invention, if it is the first execution, gating count is performed based on the initial gate duration length. If the previous frequency control cycle has been completed, the current gate duration length value is obtained from the gate duration parameter register to perform gating count and obtain the gate count sequence.

[0085] Step 102: Calculate the noise estimate based on the gate counting sequence.

[0086] Noise estimator is a statistical indicator used to quantify the short-term fluctuation characteristics of in-gate counting sequences, reflecting the signal-to-noise ratio level under the current measurement environment.

[0087] Preferably, step 102 may include the following sub-steps:

[0088] S11. Extract a subsequence of a preset length from the counting sequence inside the gate in chronological order to construct a calculation window.

[0089] A subsequence is a subset of count values ​​extracted sequentially from a complete gate counting sequence. It contains local features of the original sequence within a specific time period and is used to focus on and analyze recent frequency measurement fluctuations.

[0090] A computation window is a logical structure or storage area used for temporary storage and manipulation of subsequences. The preset length defines the number of samples used for each noise statistical calculation. The window is usually updated in a sliding manner, following the first-in-first-out principle to ensure that the calculation is always based on the latest continuous measurement data, thereby enabling dynamic real-time tracking of the system noise state.

[0091] Preferably, the preset length L is a positive integer, used to achieve a balance between sensitive capture of short-term noise changes and computational overhead. The specific preset length L can be 4, 8 or 16, etc. The length value can be set according to time requirements and is not limited here.

[0092] It is understandable that in obtaining the gate counting sequence... Then, following the first-in, first-out principle, maintain a sliding window of length L. Whenever a new doorway count value is obtained... When the time comes, the value is moved into the window, while the oldest count value in the window is moved out, thus forming a continuously updated current calculation window. .

[0093] In this embodiment of the invention, a first-in-first-out queue of length L is constructed as a calculation window. Whenever a new gate count value is generated, it is moved into the queue, while the oldest count value in the queue is removed. This dynamically forms a subsequence in the gate count sequence, arranged in chronological order and composed of the most recent count values, which can reflect the instantaneous changes in the system frequency stability in real time and accurately.

[0094] S12. Calculate the statistical dispersion of all count values ​​within the calculation window to obtain the initial statistic.

[0095] The count value refers to the integer result obtained by counting the output clock of a digitally controlled oscillator within a single gated time window; it is the raw data for frequency measurement.

[0096] Statistical dispersion refers to a statistical indicator used to quantify the degree of numerical difference or fluctuation within a dataset, reflecting the stability and consistency of the measured values.

[0097] The initial statistic refers to the original calculation result of the statistical dispersion of all count values ​​within the calculation window.

[0098] It is worth mentioning that statistical dispersion calculation can be implemented using one or more of the following algorithms:

[0099] 1. Variance: The variance of the counts within the window is calculated using the sliding window method or recursive method. This algorithm is extremely sensitive to random fluctuations in the data and can effectively quantify the overall jitter level of the measurement sequence.

[0100] 2. Range: Calculates the difference between the maximum and minimum count values ​​within the window. This algorithm is simple to calculate and responds quickly to outliers or sudden changes, making it suitable for rapid detection of sudden noise.

[0101] 3. Allan-like index: By calculating the mean square error between two adjacent calculation windows as a statistic, this algorithm is more sensitive to short-time random walks and frequency drift, and is suitable for analyzing specific types of noise components in the system.

[0102] It should be noted that the above algorithms can be flexibly selected or combined according to different requirements for noise type sensitivity, computational complexity, and real-time performance in actual application scenarios. This is achieved by quantifying the fluctuation of the count values ​​within the window into specific initial statistics.

[0103] Preferably, in this embodiment, a recursive method is used to calculate the variance of the count values ​​within the window. Specifically, while updating the sliding window, the cumulative sum S and the cumulative squared sum Q of the count values ​​within the window are maintained recursively. Whenever a new count value enters the window and an old value is removed, the window is updated as follows:

[0104]

[0105] Then, the variance of the current window is calculated using the following formula:

[0106] It is worth mentioning that this recursive calculation method avoids retracing all L data in the window each time, reducing the computational complexity from O(L) to O(1), reducing the consumption of logic resources and improving real-time processing efficiency, and is especially suitable for pipelined, low-latency implementation scenarios in FPGA.

[0107] In this embodiment of the invention, a suitable algorithm is selected to calculate all count values ​​within the calculation window to obtain the initial statistics.

[0108] S13. Normalize and scale the initial statistics to obtain the noise estimate.

[0109] Normalization refers to converting an initial statistic into a dimensionless, standardized value to eliminate the influence of differences in measurement conditions such as gate duration, thereby ensuring comparability under different conditions.

[0110] Scaling refers to the linear transformation of initial statistics based on the system's preset scaling coefficients.

[0111] Noise estimate refers to the final standardized index used to characterize the current noise level after normalization and scaling.

[0112] It should be noted that the processing in this embodiment is performed in two steps sequentially:

[0113] Step 1: Normalization: Divide the initial statistic by its corresponding current threshold length value. For example, when the initial statistic is variance When calculating the normalized value When the initial statistic is the range When calculating the normalized value The normalization process eliminates the dominant influence of gate length on the absolute value of the statistic, making the noise levels calculated under different gate periods comparable.

[0114] The second step is to normalize the statistics. Multiply by a preset scaling factor That is, the final noise estimate is obtained. , where the coefficient The coefficient can be determined based on the system design objectives (such as Hz-level jitter tolerance) and the inherent jitter spectrum of the DCO. This coefficient is set according to the actual situation and is used to map the normalized dimensionless statistics to a numerical range that has physical meaning and is easy to compare thresholds.

[0115] Preferred coefficient The method for determining this can be achieved by measuring the variance of the gate count sequence of the DCO in a static state, setting a target noise estimate range, and then back-calculating the coefficients.

[0116] In this embodiment of the invention, the initial statistics are first normalized and then scaled in series, and the resulting noise estimate can effectively overcome the problem of inconsistency in the benchmark caused by changes in the gate period.

[0117] Step 103: Determine the target gate length value based on the noise estimate.

[0118] The target gate length value refers to the optimal gate length determined for the next frequency measurement cycle after adaptive adjustment based on the current noise estimation results. It is used to achieve a dynamic balance between response speed and measurement accuracy.

[0119] Preferably, step 103 may include the following sub-steps:

[0120] S21. Compare the noise estimate with the preset upper threshold and the preset lower threshold respectively.

[0121] The preset upper limit threshold refers to the noise threshold value that triggers the gate extension operation. When the noise estimate exceeds this threshold, it indicates that the current measurement noise is too large and the accuracy needs to be improved by extending the gate period.

[0122] The preset lower threshold refers to the noise threshold value that triggers the gate shortening operation. When the noise estimate is lower than this threshold, it indicates that the current measurement environment is good, and the system response speed can be improved by shortening the gate.

[0123] In this embodiment of the invention, a preset upper limit threshold is used. Set to 150, preset lower threshold. The value is set to 50, and the specific comparison logic is as follows:

[0124] When noise estimate When the noise level is ≥ the preset upper limit threshold, it indicates that the noise level is too high; when When the value is ≤ the preset lower threshold, it indicates a low noise level; when When the noise level is between the preset lower threshold and the preset upper threshold, it indicates that the current noise level is moderate.

[0125] It should be noted that this set of thresholds can be calibrated at the factory or slowly and adaptively fine-tuned during operation, based on the phase noise characteristics of the DCO and the specific requirements of the system for output frequency jitter.

[0126] In this embodiment of the invention, the noise estimate is compared with a preset upper threshold and a preset lower threshold.

[0127] S22. If the noise estimate is greater than the preset upper limit threshold, increase the current gate length value to obtain the adjustment value.

[0128] In this embodiment of the invention, when the comparison result is determined... At this time, the gate duration adaptive module performs a gate duration extension operation, specifically, it increases the exponent m of the current control gate duration by 1, that is... Thus, the adjusted exponent value is obtained. Since the gate duration length N and m satisfy The mapping relationship allows the gate duration value to be approximately doubled, effectively suppressing noise and improving steady-state measurement accuracy by increasing the measurement time window.

[0129] S23. If the noise estimate is less than the preset lower threshold, reduce the current gate length value to obtain the adjusted value.

[0130] In this embodiment of the invention, when the comparison result is determined... At this time, the gate duration adaptive module performs a gate duration extension operation. Specifically, it reduces the exponent m of the current gate duration control by 1. In this way, the gate duration value can be approximately halved, which shortens the system response time and speeds up the tracking of frequency changes while ensuring that the measurement accuracy still meets the requirements.

[0131] S24. If the noise estimate is between the preset upper threshold and the preset lower threshold, then the current gate length value is used as the adjustment value.

[0132] In this embodiment of the invention, when the comparison result is determined... When this occurs, it indicates that the current noise level is within the acceptable equilibrium range of the system. The existing gate period strategy is maintained, and the gate period exponent m is not adjusted. This approach avoids frequent gate switching caused by noise fluctuations within a small range, thus enhancing the stability and robustness of the control system.

[0133] S25. Based on the adjusted values, determine the target gate duration value.

[0134] The target gate length value refers to the final gate length value after threshold comparison and amplitude limiting, which is used for the next frequency measurement and control cycle.

[0135] Preferably, S25 may include the following sub-steps:

[0136] S1. Compare the adjusted value with the preset minimum threshold value and the preset maximum threshold value respectively.

[0137] The preset minimum threshold value refers to the lower limit of the threshold length value allowed by the system, and its corresponding threshold index is: This is used to ensure that a single frequency measurement has a basic time reference.

[0138] The preset maximum threshold value is the upper limit of the threshold length that the system allows to set, and its corresponding threshold index is... This is used to limit the unlimited growth of the gate duration, avoiding system response delays or resource waste caused by an excessively long gate duration.

[0139] It is worth mentioning that the initial gate duration value used when the system starts in step 101 is the same preset parameter as the minimum gate duration value allowed during the gate duration adaptive adjustment process here. This configuration ensures that the system's gate regulation behavior is logically consistent and self-consistent throughout its entire lifecycle, from startup to stable operation: it starts at the fastest speed... When in working condition, the operating speed is at the minimum limit. With the upper limit of accuracy Optimal adaptive adjustment is performed between them.

[0140] In this embodiment of the invention, the preset minimum threshold value and the preset maximum threshold value together define the effective range of the adaptive threshold adjustment. , ],in and Based on the system's comprehensive requirements for frequency jitter and response speed, the typical value range is [20, 26]. The establishment of this range takes into account the balance between steady-state low noise and dynamic response, and provides a clear and reliable adjustment boundary.

[0141] S2. If the adjusted value is greater than the preset maximum threshold value, then the preset maximum threshold value will be used as the target threshold length value.

[0142] In an embodiment of the present invention, when If the suggested gate period is too long, and to prevent the gate period from growing indefinitely and causing system lag, an upper limit operation is performed, reducing the target gate period index. Forced to be set as ,Right now The corresponding target threshold length value Determined as This is used to ensure that the system maintains the necessary response performance even when the noise is extremely low.

[0143] S3. If the adjusted value is less than the preset minimum threshold value, then the preset minimum threshold value will be used as the target threshold length value.

[0144] In an embodiment of the present invention, when If the suggested threshold period is too short, to prevent a sharp increase in measurement noise due to an excessively short threshold period, a lower limit limiting operation is performed to adjust the target threshold period index. Forced to be set as ,Right now The corresponding target threshold length value Determined as This value serves as the mandatory initial gate period when the system starts up, switches frequencies, or relocks the PLL, in order to achieve fast convergence.

[0145] S4. If the adjusted value is between the preset minimum threshold value and the preset maximum threshold value, then the adjusted value will be used as the target threshold length value.

[0146] In an embodiment of the present invention, when When this occurs, it indicates that the adjustment value is within the effective design range, and it can be directly adopted. The corresponding target threshold length value Determined as This ensures that the gate duration can be freely optimized within the preset boundaries based on the real-time noise estimation results, ultimately achieving gate duration adaptive closed-loop control.

[0147] Step 104: Determine the instantaneous frequency ratio based on the target gate length value.

[0148] The instantaneous frequency ratio refers to the raw frequency ratio obtained from the current gate period measurement without smoothing, reflecting the instantaneous proportional relationship between the DCO output frequency and the reference clock frequency in the latest measurement period.

[0149] Preferably, step 104 may include the following sub-steps:

[0150] S31. Use the target gate period length value to perform gate counting and obtain the actual count value of the current gate period.

[0151] S32. Based on the ratio of the actual count value to the target gate length value, the instantaneous frequency ratio is obtained.

[0152] The actual count value refers to the value using the target threshold length. The final integer result obtained by gating and counting the output clock of the digitally controlled oscillator within the defined time window.

[0153] It should be noted that after receiving the target threshold length value determined and written to the register in step 103, a complete gating counting operation is immediately initiated. This operation is the same as the process in step 101, generating a threshold value that matches the current target threshold. Corresponding actual count value and based on The ratio is calculated in a manner that yields the instantaneous frequency ratio. .

[0154] In this embodiment of the invention, the adaptively determined optimal gate length is combined with the corresponding actual measurement value and transformed into a key variable that can be directly used for subsequent smoothing processing to characterize the instantaneous frequency state.

[0155] Step 105: Calculate the smoothing factor based on the noise estimate and the target gate length value.

[0156] The smoothing factor refers to the dynamic weighting coefficient used in the exponentially weighted smoothing algorithm. It determines the system's confidence weight for the ratio of the instantaneous frequency of a new measurement to the ratio of the historical smoothed frequency, and is a key adjustment parameter for achieving dynamic response of frequency control and balance of steady-state noise.

[0157] It is understandable that the noise estimate in step 102... And the target gate duration value in step 103 According to the functional relationship The smoothing factor for the current period is calculated, and this functional relationship is constructed to simultaneously with... and Negative correlation can be implemented using a piecewise linear function or a lookup table, ensuring that the output value is constrained within a preset range, which can be (0, 0.5).

[0158] It should be noted that this functional relationship is constructed to be simultaneously with... and Negative correlation refers to the period when the gate is closed. Increase, or noise estimate When it increases, the calculated smoothing factor It should become smaller, or conversely, when or When it shrinks, It gets bigger.

[0159] It is worth mentioning that the piecewise linear function implementation is as follows:

[0160] Input variables and The range of values ​​is divided into several small intervals, such as the noise estimate. Divide the data into several intervals, such as [0,50), [50,100), [100,150], [150,...). Within each interval, use a linear formula... To calculate the output.

[0161] It should be noted that the coefficients A (slope) and B (intercept) of the piecewise linear function are pre-calibrated according to the system's requirements for dynamic response speed and steady-state accuracy. Specifically, by simulating and testing the dynamic performance of the DCO under different noise scenarios, a set of coefficients is selected to ensure that the smoothing factor remains at a high level in the low noise range to guarantee fast tracking, and that the smoothing factor rapidly decreases to a preset lower limit as the noise increases in the high noise range to strongly suppress jitter. These coefficients can be loaded during system initialization or slowly adjusted through an online self-learning mechanism.

[0162] For example, suppose that when the noise estimate Reaching its preset lower threshold (50) Smoothing factor Take the maximum value To ensure the system operates in noise At its maximum, it can effectively suppress jitter, and a preset upper limit threshold is set when the noise estimate reaches its maximum value. When (150), the smoothing factor reaches its minimum value. Substituting the boundary conditions into the linear formula yields a system of equations, which, when solved, gives A = -0.004 and B = 0.7. Therefore, within the transition region [50, 150), the linear formula is specifically as follows: .

[0163] The implementation method using the table lookup method is as follows:

[0164] First, in the system design phase, for all possible... (For example, m ranges from 20 to 26, a total of 7 types) and (For example, combinations from 0 to 255, resulting in 256 possible combinations after quantization), based on the desired functional relationship. Pre-calculate the corresponding Values, and then these Values ​​are stored in a lookup table in address order. This table can be a two-dimensional array, with addresses determined by... and The system is composed of multiple parts, and finally, during system runtime, the current... and As a union address, directly retrieve the corresponding address from the lookup table. value.

[0165] In this embodiment of the invention, the noise level is evaluated in real time. Compared with the current threshold used by the system Common mapping to smoothing factor It achieves adaptive adjustment of smoothing intensity: when the noise is large or the gate period is long, the smoothing factor is automatically reduced to enhance the filtering effect and suppress fluctuations; when the noise is small and the gate period is short, the smoothing factor is increased, thereby improving the system's response speed to frequency changes and ensuring automatic optimization of the frequency control loop between dynamic performance and steady-state accuracy.

[0166] Step 106: Smooth the instantaneous frequency ratio based on the smoothing factor to obtain the smoothed frequency ratio.

[0167] The smoothed frequency ratio refers to the frequency ratio estimate after processing by the exponential weighted smoothing algorithm. It is used to suppress noise and jitter in instantaneous measurements and reflects the smooth and stable proportional relationship between the DCO output frequency and the reference clock frequency. It is the direct input for generating the frequency tuning word.

[0168] Preferably, step 106 may include the following sub-steps:

[0169] S41. Obtain the historical smoothing frequency ratio.

[0170] S42. Based on the smoothing factor, historical smoothed frequency ratio, and instantaneous frequency ratio, the smoothed frequency ratio is calculated using exponential weighted smoothing.

[0171] The historical smoothed frequency ratio refers to the smoothed frequency ratio output calculated and stored in this step of the previous control cycle, which serves as the historical benchmark for the smoothing calculation of the current cycle.

[0172] It should be noted that if there is no previous control cycle, the historical smoothed frequency ratio will be initialized to a preset initial value. This preset initial value can be initialized directly using the first instantaneous frequency ratio, or based on the theoretical ratio of the nominal frequency of the DCO to the reference clock frequency, or it can be set to a fixed safety default value.

[0173] Exponentially weighted smoothing is a filtering algorithm that uses exponentially decreasing weights to weight and fuse current measurements with historical estimates.

[0174] It is worth mentioning that the historical smoothed frequency ratio stored in the previous cycle is retrieved from the register. and receive the instantaneous frequency ratio from step 104. (Right now (and the smoothing factor in step 105) .

[0175] Then according to the formula The calculation is performed to obtain the smooth frequency ratio of the current cycle.

[0176] It should be noted that, It will be updated in the register as the historical smoothed frequency ratio for the next cycle.

[0177] In this embodiment of the invention, through the above-described exponentially weighted smoothing calculation, the system reduces the noisy instantaneous measurement value. Compared with stable historical estimates Perform dynamic weighted fusion, when the smoothing factor When the value is small, the algorithm relies more on historical values, resulting in smooth output and strong noise suppression. When the value is large, the algorithm tracks the instantaneous value more closely, and the response speed is fast, ensuring that the final smooth frequency ratio has both low noise and good tracking ability, providing a high-precision and stable feedback for frequency control.

[0178] Step 107: Determine the target frequency tuning word based on the smooth frequency ratio, and adjust the output frequency of the digitally controlled oscillator based on the target frequency tuning word.

[0179] The target frequency tuning word refers to the integer value that is finally calculated and will be loaded into the DCO register. It is a direct digital instruction that controls the output frequency of the DCO.

[0180] Output frequency refers to the actual clock frequency generated by the digitally controlled oscillator under the control of the target frequency tuning word.

[0181] Preferably, determining the target frequency tuning word based on the smooth frequency ratio may include the following sub-steps:

[0182] S51. Determine the initial frequency tuning word based on the preset output frequency value, smooth frequency ratio, and the bit width of the frequency tuning word register of the digitally controlled oscillator.

[0183] S52. Perform a rounding operation on the initial frequency tuning word to obtain the target frequency tuning word.

[0184] The preset output frequency value refers to the target frequency that the system requires the DCO to output. This value can be determined according to the specific application scenario. For example, in a broadcast transmitter, this value is the channel carrier frequency that needs to be transmitted. In a communication system, this value is the specified frequency that the local oscillator needs to generate. No specific limitation is made here.

[0185] The frequency tuning word register bit width refers to the data bit width supported by the DCO frequency tuning word register, which determines the value range of FTW. This value depends on the model and configuration of the selected DCO chip, and is not specifically limited here.

[0186] The initial frequency tuning word refers to the original frequency tuning word value calculated according to the frequency control formula, without rounding.

[0187] It is worth mentioning that the preset output frequency value, the frequency tuning word register bit width, and the initial frequency tuning word together constitute the system-level boundary conditions for frequency tuning word calculation. These conditions originate from the hardware design and application requirements outside the system and are loaded into the FPGA logic during system initialization.

[0188] It should be noted that the method for calculating the initial frequency tuning word is as follows:

[0189] In the formula, For the preset output frequency value, To smooth the frequency ratio, For the frequency tuning word register bit width, This is the system's reference clock frequency.

[0190] Furthermore, the method for calculating the target frequency tuning word is as follows:

[0191] In the formula, The target frequency tuning word.

[0192] It should be noted that before adjusting the output frequency of the digitally controlled oscillator based on the target frequency tuning word, the step of loading the target frequency tuning word into the digitally controlled oscillator may also be included:

[0193] Specifically, the target frequency tuning word is subject to step limits and loading interval control. That is, before loading (i.e., rewriting), the target frequency tuning word is calculated. And the previously loaded value The difference, the absolute value of which is greater than the preset step limit. (Its equivalent output frequency variation is usually set to ≤1Hz), then for Cut to ensure Meanwhile, it is also controlled by a minimum load interval timer to avoid excessively frequent updates. Through the dual mechanism of step limiting and minimum interval, frequency hopping of the output frequency is effectively avoided and the stable operation of the DCO is ensured.

[0194] Furthermore, the specific trimming operation for step-limiting the target frequency tuning word is as follows:

[0195] Calculate the current target frequency tuning word Difference from the previously loaded value ,like Then output directly. As the final load value, if Then output As the final load value, if Then output As the final load value.

[0196] For example, suppose the previously loaded value was newly calculated =100, 1) Newly calculated =100, the difference between the two =10, judge If the positive limit is exceeded, then after clipping, the output will be 100 + 5 = 105; 2) If the newly calculated... =92, the difference between the two is -8, determine... If the negative limit is exceeded, then the output after clipping is 100-5=95; if the newly calculated... =97, the difference between the two is 3, determine... Within the allowed range, output directly. =97.

[0197] It should be noted that the load operation follows standard bus protocols such as AXI4-Stream, specifically:

[0198] After the TVALID signal becomes valid, the system waits for the DCO interface to return the TREADY signal. Loading to the DCO only occurs within the same clock cycle when both TVALID and TREADY are valid, and a phase reset signal is issued simultaneously within this critical clock cycle. This synchronization mechanism ensures the synchronous update of the I (in-phase) and Q (quadrature) branches, enabling synchronous updates based on a new phase reference and fundamentally preventing phase jumps caused by asynchronous loading.

[0199] Furthermore, during the loading process, abnormal situations will be monitored and handled in real time. Specifically:

[0200] 1. DCO Output Monitoring: If the actual count value obtained from the gated counter is... If the output is significantly lower than the theoretical expected value, it indicates that the DCO output may be intermittent or stopped. In this case, all FTW update and load operations should be frozen immediately, and an alarm flag should be triggered to prevent the system from continuing to run in an invalid state.

[0201] 2. Reference clock monitoring: If the clock chip's lock detection signal LD=0 is detected, it indicates that the reference clock is out of lock or unstable. Loading operation is immediately prohibited, and the entire system is controlled to switch to the lock-up observation state. In this state, the system pauses the adaptive control loop until LD=1 is detected again and remains stable for a period of time before exiting the state and resuming normal operation. This is to ensure that the frequency reference of the entire system is reliable and stable.

[0202] In this embodiment of the invention, the smoothed frequency ratio Precise mapping to DCO-recognizable integer control words establishes a direct bridge from frequency measurement to frequency control, ensuring that the DCO output frequency accurately tracks the preset output frequency value. Finally, the output frequency is written to the DCO register through the loading interface, thus completing the closed-loop control of the output frequency.

[0203] Example 2:

[0204] Please see Figure 2 The present invention provides a frequency control system for a digitally controlled oscillator, comprising:

[0205] The gate counting module 101 is used to obtain the current gate length value of the digitally controlled oscillator and perform gate counting on the output clock of the digitally controlled oscillator based on the current gate length value to obtain the gate counting sequence.

[0206] The noise estimation module 102 is used to calculate the noise estimate based on the gate counting sequence.

[0207] The gate duration adaptive module 103 is used to determine the target gate duration value based on the noise estimate.

[0208] The frequency ratio calculation module 104 is used to determine the instantaneous frequency ratio based on the target gate length value.

[0209] The smoothing factor calculation module 105 is used to calculate the smoothing factor based on the noise estimate and the target gate length value.

[0210] The smoothing module 106 is used to smooth the instantaneous frequency ratio based on the smoothing factor to obtain the smoothed frequency ratio.

[0211] The frequency tuning word adjustment module 107 is used to determine the target frequency tuning word based on the smooth frequency ratio, and adjust the output frequency of the digitally controlled oscillator based on the target frequency tuning word.

[0212] Preferably, the frequency tuning word adjustment module 107 may include the following sub-modules:

[0213] The loading control submodule is used to implement step limits on the target frequency tuning word, ensuring that the difference between two adjacent loading values ​​does not exceed the preset step limit, while controlling the minimum loading time interval to avoid updates being too frequent.

[0214] The monitoring module is used to monitor the critical status of the system in real time and trigger protection mechanisms when an anomaly is detected.

[0215] Preferably, the monitoring module may include the following sub-modules:

[0216] The output monitoring submodule is used to monitor the output status of the digitally controlled oscillator: when the actual count value obtained by the gating counter is zero or continuously much lower than the theoretical expected value, it is determined to be an output abnormality, triggering an alarm and freezing the frequency tuning word update.

[0217] The clock monitoring submodule is used to monitor the reference clock status: when the lock detection signal of the external clock chip is invalid, it is determined that the reference clock is lost, the control system switches to the relock observation state, and the adaptive control loop is paused.

[0218] Since the above is a system corresponding to a frequency control method for a digitally controlled oscillator, its implementation principle is the same as that of a frequency control method for a digitally controlled oscillator, and will not be repeated here.

[0219] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the system and modules described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0220] The following is an application example of adaptive frequency control in a software-defined radio transmitter provided in this embodiment:

[0221] A software-defined radio transmitter based on an FPGA uses a digitally controlled oscillator as its core frequency source. Its output frequency is controlled by a 32-bit frequency tuning word, maintaining a stable 100MHz. The current gate length N is of medium length (e.g., m=23). (Reference clock cycles), with a smoothing factor of a moderate value (e.g., 0.1), the system receives a task to quickly switch from the current transmission frequency of 100MHz to 102MHz and maintain extremely high frequency stability at the new frequency point.

[0222] The gate counting module immediately counts the DCO's output clock using the current gate duration, obtaining a series of in-gate count values ​​as an in-gate count sequence. Then, the noise estimation module calculates the statistical variance from the latest count sequence (e.g., truncating the last 8 values), normalizes and scales it to obtain the current noise estimate. Since the frequency has just started switching, the DCO output is not yet stable, and the count value fluctuates greatly. Assuming the calculated noise estimate is 180, the gate duration adaptive module compares the noise estimate with preset upper and lower thresholds, determining that the current noise is too high. The module decides to increase the gate duration to improve measurement accuracy, increasing the gate duration exponent m by 1. Next, the frequency ratio calculation module performs a gate count using the new, longer target gate duration value, obtaining the actual count value and calculating the instantaneous frequency ratio. The smoothing factor calculation module... Simultaneously, a smoothing factor is calculated based on a large noise estimate and the target gate length. The smoothing module performs exponential weighted smoothing on the instantaneous frequency ratio and the historical smoothed frequency ratio based on the smoothing factor to obtain a new smoothed frequency ratio. The frequency tuning word adjustment module calculates the target frequency tuning word based on the target frequency of 102MHz and the new smoothed frequency ratio. Through the loading control submodule, the difference between the target frequency tuning word and the loaded frequency tuning word is calculated to be within the maximum step range. The contents of the gate counting module to the frequency tuning word adjustment module are repeated. As the frequency tends to stabilize, the noise estimate gradually decreases. When the noise estimate is below 50, the system automatically shortens the gate and increases the smoothing factor to accelerate convergence. Finally, the system achieves stable locking when both the gate and the smoothing factor reach moderate values, and the output frequency is accurately maintained at 102MHz.

[0223] Example 3:

[0224] An electronic device according to an embodiment of the present invention includes: a memory and a processor, wherein the memory stores a computer program; when the computer program is executed by the processor, the processor performs a frequency control method for a digitally controlled oscillator as described in any of the above embodiments.

[0225] The memory can be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. The memory has storage space for program code used to perform any of the method steps described above. For example, the storage space for program code may include individual program codes for implementing the various steps in the methods described above. This program code can be read from or written to one or more computer program products. These computer program products include program code carriers such as hard disks, compact discs (CDs), memory cards, or floppy disks. The program code may be compressed, for example, in a suitable form. When run by a computing processing device, this code causes the computing processing device to perform the various steps in the methods described above.

[0226] Example 4:

[0227] This invention provides a computer-readable storage medium storing a computer program thereon, which, when executed, implements the frequency control method of the digitally controlled oscillator of any of the above embodiments.

[0228] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0229] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0230] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0231] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0232] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0233] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A frequency control method for a digitally controlled oscillator, characterized in that, include: Obtain the current gate duration value of the digitally controlled oscillator, and perform gated counting on the output clock of the digitally controlled oscillator based on the current gate duration value to obtain the gate counting sequence; The noise estimate is calculated based on the gate counting sequence. Based on the noise estimate, the target gate length value is determined; Based on the target gate length value, determine the instantaneous frequency ratio; The smoothing factor is calculated based on the noise estimate and the target gate length value; The instantaneous frequency ratio is smoothed based on the smoothing factor to obtain a smoothed frequency ratio. The target frequency tuning word is determined based on the smooth frequency ratio, and the output frequency of the digitally controlled oscillator is adjusted based on the target frequency tuning word. Determining the target gate length value based on the noise estimate includes: The noise estimate is compared with a preset upper threshold and a preset lower threshold, respectively. If the noise estimate is greater than the preset upper limit threshold, then the current gate length value is increased to obtain an adjustment value; If the noise estimate is less than the preset lower threshold, then the current gate length value is reduced to obtain the adjustment value; If the noise estimate is between the preset upper threshold and the preset lower threshold, then the current gate length value is used as the adjustment value; Based on the adjusted values, the target threshold length value is determined; The calculation of the smoothing factor based on the noise estimate and the target gate length value includes: Substituting the noise estimate and the target gate length value into the functional relationship ,in, The noise estimate is... The target gate duration is... The smoothing factor is mentioned above.

2. The frequency control method for a digitally controlled oscillator according to claim 1, characterized in that, The step of calculating the noise estimate based on the in-gate counting sequence includes: From the counting sequence within the gate, a subsequence of a preset length is extracted in chronological order to construct a calculation window; Calculate the statistical dispersion of all count values ​​within the calculation window to obtain the initial statistic. The initial statistics are normalized and scaled to obtain the noise estimate.

3. The frequency control method for a digitally controlled oscillator according to claim 1, characterized in that, Determining the target threshold length value based on the adjusted value includes: The adjusted value is compared with the preset minimum threshold value and the preset maximum threshold value, respectively. If the adjustment value is greater than the preset maximum threshold value, then the preset maximum threshold value is used as the target threshold length value. If the adjustment value is less than the preset minimum threshold value, then the preset minimum threshold value is used as the target threshold length value; If the adjusted value is between the preset minimum threshold value and the preset maximum threshold value, then the adjusted value is used as the target threshold length value.

4. The frequency control method for a digitally controlled oscillator according to claim 1, characterized in that, The step of determining the instantaneous frequency ratio corresponding to the current gating count based on the target gate duration value includes: The target gate length value is used to perform gate counting to obtain the actual count value of the current gate period; The instantaneous frequency ratio is obtained based on the ratio of the actual count value to the target gate length value.

5. The frequency control method for a digitally controlled oscillator according to claim 1, characterized in that, The smoothing process based on the smoothing factor to obtain the smoothed frequency ratio includes: Obtain the historical smoothed frequency ratio; Based on the smoothing factor, the historical smoothing frequency ratio, and the instantaneous frequency ratio, the smoothing frequency ratio is calculated using exponential weighted smoothing.

6. The frequency control method for a digitally controlled oscillator according to claim 1, characterized in that, Determining the target frequency tuning word based on the smoothed frequency ratio includes: The initial frequency tuning word is determined based on the preset output frequency value, the smoothed frequency ratio, and the bit width of the frequency tuning word register of the digitally controlled oscillator. The initial frequency tuning word is rounded down to obtain the target frequency tuning word.

7. A frequency control system for a digitally controlled oscillator, characterized in that, The system for implementing the frequency control method of the digitally controlled oscillator as described in claim 1 includes: The gated counting module is used to obtain the current gate length value of the digitally controlled oscillator and perform gated counting on the output clock of the digitally controlled oscillator based on the current gate length value to obtain the gate counting sequence; The noise estimation module is used to calculate the noise estimate based on the gate counting sequence; A gate duration adaptive module is used to determine the target gate duration value based on the noise estimate; The frequency ratio calculation module is used to determine the instantaneous frequency ratio based on the target gate length value; A smoothing factor calculation module is used to calculate a smoothing factor based on the noise estimate and the target threshold length value; A smoothing module is used to smooth the instantaneous frequency ratio based on the smoothing factor to obtain a smoothed frequency ratio. The frequency tuning word adjustment module is used to determine the target frequency tuning word based on the smoothed frequency ratio, and to adjust the output frequency of the digitally controlled oscillator based on the target frequency tuning word.

8. An electronic device, characterized in that, It includes a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executed as described in any one of claims 1 to 6 for frequency control of a digitally controlled oscillator.

9. A computer-readable storage medium, characterized in that, The computer program stores a frequency control method for a digitally controlled oscillator as described in any one of claims 1 to 6 that can be loaded by a processor.

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