Capacitor Structure and Formation Method

Abstract

This invention provides a capacitor structure and a method for forming the same. The method includes: forming a bottom dielectric layer; forming a bottom metal electrode plate within the bottom dielectric layer; forming a dielectric stack on the bottom metal electrode plate; forming a top dielectric layer on the dielectric stack; and forming a top metal electrode plate within the top dielectric layer. The top metal electrode plate has a narrow portion and a wide portion, forming a stepped structure that is wider at the top and narrower at the bottom. The ratio of the width of the narrow portion to the width of the wide portion of the top metal electrode plate is selected from (0.85, 1), and the ratio of the thickness of the narrow portion to the thickness of the wide portion of the top metal electrode plate is greater than or equal to 1.5. Using this method, the performance of the capacitor structure can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a capacitor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing processes, the withstand voltage performance of high-voltage isolation capacitors is often limited by the dielectric insulation strength and the electric field concentration at the electrode edges. Traditional designs, to mitigate the risk of breakdown, typically increase the capacitor area to reduce the average electric field. However, this directly leads to a decrease in chip area utilization, making it difficult to meet the high-density integration requirements of modern integrated circuits.

[0003] In the field of digital isolators, the capacitor structure is a parallel-plate capacitor with silicon dioxide filling between parallel metal plates. Capacitive coupling schemes have become an ideal choice for high-voltage applications such as industrial and automotive electronics due to their small size, low power consumption, and high transmission rate. However, the problem of electric field concentration at the edges of the plates severely limits the voltage withstand capability of the capacitor.

[0004] Therefore, how to provide technical solutions to suppress edge electric fields and improve the performance of capacitor structures has become an urgent technical problem to be solved. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a capacitor structure and a method for forming the same, which can improve the quality of the capacitor structure.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a capacitor structure, comprising: forming a bottom dielectric layer; forming a bottom metal electrode plate within the bottom dielectric layer; forming a dielectric stack on the bottom metal electrode plate; forming a top dielectric layer on the dielectric stack; and forming a top metal electrode plate within the top dielectric layer, wherein the top metal electrode plate has a narrow portion and a wide portion, forming a stepped structure that is wider at the top and narrower at the bottom; wherein the ratio of the width of the narrow portion of the top metal electrode plate to the width of the wide portion of the top metal electrode plate is selected from (0.85, 1), and the ratio of the thickness of the narrow portion of the top metal electrode plate to the thickness of the wide portion of the top metal electrode plate is greater than or equal to 1.5.

[0007] Optionally, the step of forming the top metal electrode includes: forming a top dielectric stack on the dielectric stack, the top dielectric stack comprising a first top dielectric layer and a second top dielectric layer from bottom to top; etching the top dielectric stack to obtain a first top electrode trench and a second top electrode trench, the bottom of the first top electrode trench exposing the dielectric stack, the width of the first top electrode trench being smaller than the width of the second top electrode trench; filling the first top electrode trench and the second top electrode trench using a double damask process, and using a planarization process to obtain the top metal electrode; wherein, when the potential of the top metal electrode is higher than the potential of the bottom metal electrode, the dielectric constant of the first top dielectric layer is smaller than the dielectric constant of the second top dielectric layer.

[0008] Optionally, the step of filling the first top plate groove and the second top plate groove further includes: forming a barrier layer that covers the bottom and sidewalls of the first top plate groove and the bottom and sidewalls of the second top plate groove.

[0009] Optionally, the bottom dielectric layer is a stacked structure of a first bottom dielectric layer and a second bottom dielectric layer from bottom to top, and the bottom metal electrode has a narrow portion and a wide portion, forming a stepped structure that is narrower at the top and wider at the bottom; the step of forming the bottom metal electrode includes: forming the first bottom dielectric layer; etching the first bottom dielectric layer to obtain a first bottom electrode trench; filling the first bottom electrode trench using a damascus process and using a planarization process to obtain the wide portion of the bottom metal electrode; forming the second bottom dielectric layer on the first bottom dielectric layer; etching the second bottom dielectric layer to obtain a second bottom electrode trench, the width of the second bottom electrode trench being smaller than the width of the first bottom electrode trench; filling the second bottom electrode trench using a damascus process and using a planarization process to obtain the narrow portion of the bottom metal electrode; wherein, when the potential of the top metal electrode is higher than the potential of the bottom metal electrode, the dielectric constant of the first bottom dielectric layer is smaller than the dielectric constant of the second bottom dielectric layer.

[0010] Optionally, the first top dielectric layer is silicon oxide; the second top dielectric layer is silicon nitride; the first bottom dielectric layer is silicon oxide; and the second bottom dielectric layer is silicon nitride.

[0011] Optionally, the dielectric stack is an alternating stack of multiple silicon oxide layers and multiple silicon nitride layers; the step of forming the dielectric stack includes: forming a first silicon oxide layer, the first silicon oxide layer covering the bottom metal electrode; forming a first silicon nitride layer on the first silicon oxide layer; forming a second silicon oxide layer on the first silicon nitride layer; forming a second silicon nitride layer on the second silicon oxide layer; wherein the dielectric stack includes at least: a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer and a second silicon nitride layer, and the thickness of the silicon oxide layer is greater than the thickness of the silicon nitride layer.

[0012] This invention also provides a capacitor structure, comprising: a bottom dielectric layer; a bottom metal electrode plate located within the bottom dielectric layer; a dielectric stack covering the bottom metal electrode plate; a top dielectric layer located on the dielectric stack; and a top metal electrode plate having a narrow portion and a wide portion, forming a stepped structure that is wider at the top and narrower at the bottom, located within the top dielectric layer; wherein the ratio of the width of the narrow portion of the top metal electrode plate to the width of the wide portion of the top metal electrode plate is selected from (0.85, 1), and the ratio of the thickness of the narrow portion of the top metal electrode plate to the thickness of the wide portion of the top metal electrode plate is greater than or equal to 1.5.

[0013] Optionally, one or more of the following conditions must be met: the cross-sectional shape of the wide portion of the top metal electrode plate is a rounded rectangle; the cross-sectional shape of the narrow portion of the top metal electrode plate is a rounded rectangle; the vertical cross-sectional shape of the wide portion of the top metal electrode plate is a trapezoid or a rectangle; the vertical cross-sectional shape of the narrow portion of the top metal electrode plate is a trapezoid, an arc, or a rectangle; the vertical cross-sectional shape of the wide portion of the bottom metal electrode plate is a trapezoid or a rectangle; and the vertical cross-sectional shape of the narrow portion of the bottom metal electrode plate is a trapezoid, an arc, or a rectangle.

[0014] Optionally, the top dielectric layer and the top metal electrode plate include: a first top dielectric layer; a narrow portion of the top metal electrode plate located within the first top dielectric layer; a second top dielectric layer; and a wide portion of the bottom metal electrode plate located within the second top dielectric layer.

[0015] Optionally, the bottom dielectric layer and the bottom metal electrode plate include: a first bottom dielectric layer; a wide portion of the bottom metal electrode plate located within the first bottom dielectric layer; a second bottom dielectric layer; and a narrow portion of the bottom metal electrode plate located within the second bottom dielectric layer; wherein, when the potential of the top metal electrode plate is higher than the potential of the bottom metal electrode plate, the dielectric constant of the first bottom dielectric layer is less than the dielectric constant of the second bottom dielectric layer.

[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0017] The capacitor structure and its formation method provided in this invention include: forming a top metal plate and a bottom metal plate corresponding to each other in the capacitor structure, wherein the top metal plate has a narrow portion and a wide portion, forming a stepped structure that is wider at the top and narrower at the bottom; wherein the ratio of the width of the narrow portion to the width of the wide portion of the top metal plate is selected from (0.85, 1), and the ratio of the thickness of the narrow portion to the thickness of the wide portion of the top metal plate is greater than or equal to 1.5. This method disperses the electric field at the edge of the top metal plate by designing the top metal plate as a stepped form with a specific size ratio, thereby effectively suppressing the edge electric field and improving the capacitor performance. Furthermore, by controlling the width ratio of the narrow portion to the wide portion of the top metal plate between 0.85 and 1, a gradually transitioning integrated field plate structure is formed, redistributing the electric field peak originally concentrated at the edge of the plate into a more gradual gradient field, thereby significantly reducing the local electric field intensity. Furthermore, the thickness of the narrow section is at least 1.5 times that of the wide section, providing robust mechanical support for the wide section and further dispersing the electric field at the edge of the top metal plate through the thicker narrow section, thus optimizing the continuity of the electric field line distribution. 0.85 × 1.5 = 1.275, 1 × 1 = 1, therefore the cross-sectional area ratio of the narrow section to the wide section should be greater than 1.275. The larger cross-sectional area of ​​the narrow section allows it to better disperse the edge electric field of the wide section. This collaborative design optimizes the distribution of electric field lines without significantly increasing the chip area, significantly improving the capacitor's breakdown voltage and long-term reliability, and helping to resolve the contradiction between field strength concentration and integration density in high-voltage applications. Therefore, the capacitor structure and its formation method can improve the performance of the capacitor structure. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the invention in this specification, the drawings used in the description of the embodiments of the invention or the prior art in this specification will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating a method for forming a capacitor structure according to an embodiment of the present invention;

[0020] Figures 2 to 6 This is a schematic diagram of some steps in a capacitor structure formation method according to an embodiment of the present invention;

[0021] Figure 7 This is a top view of the top metal plate of a capacitor structure in an embodiment of the present invention;

[0022] Figure 8This is a cross-sectional schematic diagram of the top metal plate of a capacitor structure in an embodiment of the present invention;

[0023] Figures 9 to 11 This is a cross-sectional schematic diagram of the top metal plate of three other capacitor structures in the embodiments of the present invention.

[0024] Figure 12 Cross-sectional view of the electric field distribution at the edge structure of a traditional parallel electrode and a stepped plate;

[0025] Figure 13 The electric field distribution characteristics of traditional parallel plate structures and stepped plate structures with different dielectric layer thicknesses are shown.

[0026] Explanation of reference numerals in the attached figures:

[0027] Substrate 200, first bottom dielectric layer 201, first bottom electrode trench 201a, second bottom dielectric layer 202, first top dielectric layer 203, second top dielectric layer 204;

[0028] Bottom metal electrode 210, wide portion 210a of bottom metal electrode, narrow portion 210b of bottom metal electrode, dielectric stack 220, first silicon oxide layer 221, first silicon nitride layer 222, second silicon oxide layer 223, second silicon nitride layer 224, top metal electrode 230, narrow portion 230a of top metal electrode, wide portion 230b of top metal electrode, width W1 of the wide portion of top metal electrode, width W2 of the narrow portion of top metal electrode, thickness T1 of the wide portion of top metal electrode, thickness T2 of the narrow portion of top metal electrode. Detailed Implementation

[0029] The technical solutions of the present invention will be described in detail below with reference to specific embodiments and accompanying drawings. The embodiments described herein are specific implementations of the present invention, used to illustrate the concept of the present invention. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. These descriptions are illustrative and exemplary, and should not be construed as limiting the implementation of the present invention or the scope of protection of the present invention. In addition to the embodiments described herein, those skilled in the art can also adopt other obvious technical solutions based on the content disclosed in the claims and specification of this application. These technical solutions include those that make any obvious substitutions and modifications to the embodiments described herein.

[0030] It should be noted that the accompanying drawings in this embodiment are schematic diagrams used to illustrate the concept of the invention and to schematically show the shape and interrelationship of the various parts. It should be understood that, in order to clearly show the structure of the various components of the invention, the drawings are not drawn to the same scale, and the same reference numerals are used to indicate the same parts in the drawings.

[0031] In semiconductor manufacturing processes, the withstand voltage performance of high-voltage isolation capacitors is often limited by the dielectric insulation strength and the electric field concentration at the electrode edges. Traditional designs, to mitigate the risk of breakdown, typically increase the capacitor area to reduce the average electric field. However, this directly leads to a decrease in chip area utilization, making it difficult to meet the high-density integration requirements of modern integrated circuits.

[0032] In the field of digital isolators, the capacitor structure is a parallel-plate capacitor with silicon dioxide filling between parallel metal plates. Capacitive coupling schemes have become an ideal choice for high-voltage applications such as industrial and automotive electronics due to their small size, low power consumption, and high transmission rate. However, the problem of electric field concentration at the edges of the plates severely limits the voltage withstand capability of the capacitor.

[0033] Therefore, how to provide technical solutions to suppress edge electric fields and improve the performance of capacitor structures has become an urgent technical problem to be solved.

[0034] To address the aforementioned technical problems, the capacitor structure and its formation method provided in this invention include: forming a top-layer metal plate and a bottom-layer metal plate corresponding to each other in the capacitor structure, wherein the top-layer metal plate has a narrow portion and a wide portion, forming a stepped structure that is wider at the top and narrower at the bottom; wherein the ratio of the width of the narrow portion to the width of the wide portion of the top-layer metal plate is selected from (0.85, 1), and the ratio of the thickness of the narrow portion to the thickness of the wide portion of the top-layer metal plate is greater than or equal to 1.5. This method disperses the electric field at the edge of the top-layer metal plate by designing it as a stepped form with a specific size ratio, thereby effectively suppressing the edge electric field and improving capacitor performance. Furthermore, by controlling the width ratio of the narrow portion to the wide portion of the top-layer metal plate between 0.85 and 1, a gradually transitioning integrated field plate structure is formed, redistributing the electric field peak originally concentrated at the edge of the plate into a more gradual gradient field, thereby significantly reducing the local electric field intensity. Furthermore, the thickness of the narrow section is at least 1.5 times that of the wide section, providing robust mechanical support for the wide section and further dispersing the electric field at the edge of the top metal plate through the thicker narrow section, thus optimizing the continuity of the electric field line distribution. This collaborative design optimizes the electric field line distribution without significantly increasing the chip area, significantly improving the capacitor's breakdown voltage and long-term reliability, and helping to resolve the contradiction between field strength concentration and integration density in high-voltage applications. Therefore, the capacitor structure and its formation method can improve the performance of the capacitor structure.

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] See Figure 1 , Figure 1This is a schematic flowchart of a method for forming a capacitor structure according to an embodiment of the present invention. The method can be performed by executing the following steps S101 to S105.

[0037] In step S101, a bottom dielectric layer is formed.

[0038] In step S102, a bottom metal electrode is formed within the bottom dielectric layer.

[0039] In step S103, a dielectric stack is formed on the bottom metal electrode plate.

[0040] In step S104, a top dielectric layer is formed on the dielectric stack.

[0041] In step S105, a top metal electrode plate is formed within the top dielectric layer. The top metal electrode plate has a narrow portion and a wide portion, forming a stepped structure that is wider at the top and narrower at the bottom.

[0042] The following combination Figures 2 to 8 The above methods will be explained.

[0043] refer to Figures 2 to 6 , Figures 2 to 6 This is a schematic diagram of some steps in a capacitor structure formation method according to an embodiment of the present invention.

[0044] See Figure 2 , Figure 2 This is a schematic cross-sectional view of a semiconductor structure.

[0045] Substrate 200 is provided.

[0046] The substrate 200 is used to provide a process platform for the formation of the capacitor structure.

[0047] The substrate may include, from bottom to top, a semiconductor substrate, an isolation layer, transistor gate and source / drain electrodes, an interlayer dielectric layer, and a metal interconnect layer. The metal interconnect layer includes contact pads for electrical connection to the lower electrode of the capacitor. The substrate surface has a planarized surface formed by chemical mechanical polishing (CMP) to ensure uniformity of the capacitor layers.

[0048] In this embodiment, the substrate 200 may contain a semiconductor device structure whose previous processes have been completed, providing an integrated technical platform for capacitor fabrication. The substrate 200 includes planarized interlayer dielectric layers, metal interconnects, and silicon-based transistors, forming a surface with specific topological morphology and electrical properties, providing a reliable mechanical support substrate for the deposition of each layer of the capacitor structure.

[0049] In some embodiments, the substrate 200 achieves electrical connection between the lower electrode and the underlying circuit through a preset contact via, thereby ensuring the compatibility of the capacitor with existing semiconductor processes and the stability of the final device performance.

[0050] The method includes: forming an underlying dielectric layer.

[0051] The underlying dielectric layer has a stacked structure.

[0052] The underlying dielectric layer includes: a first underlying dielectric layer 201 and a second underlying dielectric layer 202 (see...). Figure 4 ).

[0053] The first bottom dielectric layer 201 is located on the substrate 200.

[0054] The second bottom dielectric layer 202 covers the first bottom dielectric layer 201.

[0055] The bottom dielectric layer is a stacked structure of a first bottom dielectric layer 201 and a second bottom dielectric layer 202 from bottom to top (see [link]). Figure 4 ).

[0056] The first bottom dielectric layer 201 is made of a low-k dielectric constant material.

[0057] The dielectric constant of the first bottom dielectric layer 201 material is taken from 2.5 to 4.5.

[0058] The material of the first bottom dielectric layer 201 can be silicon oxide, carbon-doped oxide, or porous organosilicon.

[0059] Specifically, carbon-doped silicon oxide has a dielectric constant that can be tuned from 2.7 to 3.5, and the carbon doping concentration can be controlled by the precursor gas flow rate ratio; fluorine-doped silicon glass has a dielectric constant of approximately 3.5 to 3.8 and possesses excellent interstitial filling capabilities; porous organosilicon has a dielectric constant as low as 2.5 and forms a nanoporous structure through a template agent; polyimide has a dielectric constant of approximately 3.2 to 3.5 and is suitable for flexible electronic integration scenarios. If the simplicity, maturity, and absolute reliability of the process are prioritized, and the performance improvement requirements are not extremely stringent, then using silicon oxide is a completely reasonable and recommended choice. If the ultimate performance breakthrough is pursued, and the highest theoretical withstand voltage value is desired, then materials with lower dielectric constants, such as carbon-doped oxides, should be given priority. In this embodiment, the first bottom dielectric layer 201 is made of silicon oxide.

[0060] When the first bottom dielectric layer 201 is silicon dioxide, it can be formed using PECVD or thermal oxidation. In this embodiment, the first bottom dielectric layer 201 is formed using plasma-enhanced chemical vapor deposition. For example, silane and nitrous oxide are introduced into a reaction chamber as reaction gases, and a silicon dioxide thin film is deposited on the substrate as the first bottom dielectric layer 201.

[0061] In some embodiments, a carbon-doped silicon oxide thin film with a dielectric constant of about 3.0 can be deposited by adjusting the flow rate ratio of the reactant gas (e.g., introducing methane gas).

[0062] Rapid thermal annealing can be performed on deposited films to improve their film density, reduce internal stress, and enhance insulation performance.

[0063] When the first bottom dielectric layer is a carbon-doped oxide, PECVD is used and a carbon-containing precursor (such as CH4) is introduced.

[0064] When the first bottom dielectric layer is polyimide, it is formed by spin coating.

[0065] It should be specifically noted that the aforementioned method for forming the first bottom dielectric layer 201 by chemical vapor deposition is merely an exemplary embodiment, and the scope of protection of this invention is not limited to this specific process. Those skilled in the art should understand that any process capable of forming a dielectric layer with the required dielectric constant and insulating properties on a substrate is applicable to this invention. This includes, but is not limited to: physical vapor deposition (such as reactive sputtering), solution-based processes (such as spin-coating glass technology), sol-gel methods, atomic layer deposition, thermal oxidation, and combinations of any two or more of the above methods. In specific implementations, the most suitable film formation method can be flexibly selected based on the characteristics of the dielectric layer material, thickness requirements, and compatibility with preceding and following processes. These obvious process substitutions or combinations should all be considered to fall within the scope of protection of this invention.

[0066] The first bottom dielectric layer 201 has a first bottom electrode groove 201a.

[0067] Specifically, a first bottom dielectric layer 201 is formed, which covers the substrate 200. The first bottom dielectric layer 201 is etched to obtain a first bottom electrode trench 201a. The bottom of the first bottom electrode trench 201a exposes the substrate 200.

[0068] The first bottom electrode groove 201a provides process space for the formation of the width portion 210a of the subsequent bottom metal electrode.

[0069] The method for etching the first bottom electrode groove 201a is as follows:

[0070] A photoresist layer is uniformly spin-coated onto the first bottom dielectric layer 201 to form a photoresist layer.

[0071] The photoresist layer is patterned by selectively exposing the photoresist using a pre-prepared photomask with the first bottom electrode groove 201a pattern defined on it, and then dissolving the exposed (or unexposed, depending on the type of photoresist) areas with a developer, thereby precisely forming a window on the photoresist layer corresponding to the target pattern of the first bottom electrode groove 201a.

[0072] The first bottom dielectric layer 201 is etched. Specifically, the remaining photoresist layer is used as a mask, and a dry etching process, such as reactive ion etching, is used to selectively remove the bottom dielectric layer material exposed under the window until it stops at a preset depth, thereby forming the first bottom electrode trench 201a with the required size and sidewall morphology. This etching process needs to have good anisotropy to ensure the verticality of the trench wall.

[0073] Photoresist removal and cleaning: Specifically, the residual photoresist is thoroughly removed using ashing or wet photoresist removal processes, and the wafer is rigorously cleaned to remove all process residues and obtain a clean electrode trench structure, preparing it for subsequent metal filling steps.

[0074] It should be specifically noted that the aforementioned patterning process based on photolithography and reactive ion etching is only an exemplary embodiment for forming the first bottom electrode trench 201a, but the scope of protection of this invention is not limited thereto. Those skilled in the art will understand that any process capable of selectively removing the underlying dielectric layer material to form a predetermined pattern is applicable to this invention. This includes, but is not limited to: wet etching, ion beam etching, laser ablation, or any combination of the above methods. The specific process selection can be adapted according to the characteristics of the dielectric layer material, the required aspect ratio of the trench, and the sidewall morphology, etc., and these obvious changes or substitutions should be considered to fall within the scope of protection of this invention.

[0075] See also Figure 3 and Figure 4 A bottom metal electrode plate 210 is formed within the bottom dielectric layer.

[0076] The bottom metal electrode 210 has a narrow portion and a wide portion, forming a stepped structure that is narrower at the top and wider at the bottom; the steps for forming the bottom metal electrode 210 include:

[0077] The first bottom electrode groove 201a is filled using the damascus process, and the width portion 210a of the bottom metal electrode is obtained by using a planarization process.

[0078] Specifically, the first bottom electrode plate groove 201a is metallized and filled using a damascus process. First, a barrier layer / adhesion layer and a seed layer are sequentially formed on the inner wall of the first bottom electrode plate groove 201a. Then, the main conductive metal is filled into the groove and covered on the surface of the surrounding dielectric layer through an electrochemical electroplating process. Finally, excess metal on the surface is removed through a chemical mechanical polishing process, so that the surface of the filled metal and the surface of the surrounding bottom dielectric layer are globally planarized, thereby forming the wide portion 210a of the bottom metal electrode plate.

[0079] It should be noted that the filling process can also be replaced by alternatives such as inlay process, selective deposition, physical vapor deposition or metal reflow, and the planarization process can also be replaced by etch-back or laser planarization methods. These process variants can all achieve the purpose of metal filling in the tank and surface planarization.

[0080] In some embodiments, the bottom metal electrode 210 may include only the wide portion 210a of the bottom metal electrode.

[0081] See Figure 4 This forms the second bottom dielectric layer 202 and the narrow portion 210b of the bottom metal electrode plate.

[0082] The formation steps are as follows:

[0083] The second bottom dielectric layer 202 is formed on the first bottom dielectric layer 201.

[0084] Specifically, the second bottom dielectric layer 202 formed covers the first bottom dielectric layer 201 and the wide portion 210a of the bottom metal electrode plate.

[0085] The second bottom dielectric layer 202 is made of a high-k dielectric constant material.

[0086] The dielectric constant of the second bottom dielectric layer 202 material can be taken from 6.5 to 10.5.

[0087] The material of the second bottom dielectric layer 202 can be silicon nitride, silicon oxynitride, aluminum nitride, or hafnium oxide.

[0088] Specifically, silicon nitride, formed by plasma-enhanced chemical vapor deposition, has a dielectric constant of approximately 7.0 to 7.5. Silicon oxynitride has a dielectric constant of 4.5 to 6.5, and stress and k-value are synergistically optimized by adjusting the oxygen-nitrogen ratio; aluminum nitride has a dielectric constant of approximately 8.5-9.0 and also possesses high thermal conductivity; hafnium oxide has a dielectric constant of approximately 20-25 and is suitable for ultra-high voltage applications. In this embodiment, the second bottom dielectric layer 202 is made of silicon nitride.

[0089] The second bottom dielectric layer 202 is formed by plasma-enhanced chemical vapor deposition, specifically including: introducing silane and ammonia into a reaction chamber in a nitrogen-containing reaction atmosphere, and depositing a silicon nitride dielectric layer on the surface of the first bottom dielectric layer 201 and the wide portion 210a of the bottom metal electrode. The deposition temperature is controlled between 250°C and 400°C, the radio frequency power density is 0.1-1.0 W / cm², and the reaction pressure is maintained between 100 and 1000 Pa. The stress within the dielectric layer is controlled by adjusting the flow rate ratio of silane to ammonia.

[0090] It should be noted that the dielectric layer can also be formed by low-pressure chemical vapor deposition, atomic layer deposition or pulsed laser deposition, and the dielectric material can be replaced with silicon oxynitride, aluminum nitride or hafnium oxide high-k dielectric. These equivalent substitutions of processes and materials are all within the protection scope of this invention.

[0091] The method further includes etching the second bottom dielectric layer 202 to obtain a second bottom electrode groove.

[0092] Those skilled in the art should understand that the formation of the second bottom electrode trench can be achieved by referring to the etching process of the first bottom electrode trench 201a in the foregoing embodiments of this specification, specifically including standard semiconductor patterning steps such as photoresist spin coating, mask alignment, exposure and development, and anisotropic dry etching. Given that this process flow is highly consistent with the foregoing embodiments in terms of process principle, equipment configuration, and parameter selection, to maintain the brevity of the specification, the detailed process descriptions already provided will not be repeated here. Any adjustment of process parameters based on the foregoing etching process principle and without substantially deviating from the core inventiveness of this invention should be considered to fall within the protection scope of this invention.

[0093] It should be noted that the width of the second bottom electrode groove is smaller than the width of the first bottom electrode groove 201a, which is used to form the narrow portion 210b of the bottom metal electrode plate later.

[0094] The second bottom electrode groove is filled using the damascus process, and a planarization process is used to obtain the narrow portion 210b of the bottom metal electrode.

[0095] Specifically, the second bottom electrode plate groove is metallized and filled using a damascus process. First, a barrier layer / adhesion layer and a seed layer are sequentially formed on the inner wall of the second bottom electrode plate groove. Then, the main conductive metal is filled into the groove and covered on the surface of the surrounding dielectric layer by an electrochemical electroplating process. Finally, excess metal on the surface is removed by a chemical mechanical polishing process, so that the surface of the filled metal and the surface of the surrounding bottom dielectric layer are globally planarized, thereby forming the narrow portion 210b of the bottom metal electrode plate.

[0096] At the bottom of the second bottom electrode plate groove, the barrier layer / adhesive layer on the top surface of the wide portion 210a of the bottom metal electrode plate needs to be removed to maintain electrical contact between the wide portion 210a and the narrow portion 210b of the bottom metal electrode plate. Thus, the bottom metal electrode plate 210 is obtained.

[0097] It should be noted that the filling process can also be replaced by alternatives such as inlay process, selective deposition, physical vapor deposition or metal reflow, and the planarization process can also be replaced by etch-back or laser planarization methods. These process variants can all achieve the purpose of metal filling in the tank and surface planarization.

[0098] In this embodiment, before forming the barrier layer, the surface of the substrate 200 is first cleaned by Ar ion sputtering, that is, the bottom and sidewalls of the metal electrode groove are cleaned.

[0099] The barrier layer / adhesive layer is made of one or more of the following materials: titanium, tantalum, cobalt, ruthenium, molybdenum, titanium nitride, and tantalum nitride. The barrier layer prevents metal from diffusing from the metal electrode to the substrate 200 or the surrounding dielectric layer, thereby improving the thermal stability and long-term operational reliability of the device in the substrate 200. The barrier layer / adhesive layer also enhances the bonding force between the bottom metal electrode 210 and the substrate 200, preventing delamination and peeling of the bottom metal electrode 210 and ensuring the mechanical integrity of the multilayer structure.

[0100] The material of the bottom metal electrode plate 210 is selected from one or more of the following combinations: copper, aluminum, tungsten, ruthenium, and copper-aluminum alloy.

[0101] In some embodiments, the wide portion 210a and the narrow portion 210b of the bottom metal electrode plate 210 may be made of the same material or different materials.

[0102] See Figure 5 A dielectric stack 220 is formed on the bottom metal electrode 210.

[0103] The dielectric stack 220 is a stack of multiple dielectric layers.

[0104] This multilayer structure, by arranging dielectric materials with different coefficients of thermal expansion, allows the dielectric layers with varying coefficients to compensate for each other, significantly reducing the risk of dielectric layer cracking due to thermal stress and enhancing structural integrity. Furthermore, by optimizing the thickness ratio and stacking order of each dielectric layer, it is possible to maintain high capacitance density while synergistically optimizing multiple parameters such as quality factor, voltage linearity, and temperature stability, overcoming the inherent performance and reliability bottlenecks of traditional single-dielectric capacitors. It should be noted that this multilayer architecture also provides flexibility for customized designs. Capacitance can be controlled by adjusting the number of dielectric layers, and the interlayer interface characteristics can be adjusted or functional dielectric layers can be introduced to meet the extreme requirements of specific application scenarios for high-frequency response, radiation resistance, or long-term reliability.

[0105] In this embodiment, the dielectric stack 220 is an alternating stack of multiple silicon oxide layers and multiple silicon nitride layers, and the thickness of the silicon oxide layer is greater than the thickness of the silicon nitride layer.

[0106] Specifically, the dielectric stack 220 achieves a balance between electric field modulation and structural integrity through complementary material properties and a synergistic design of thickness ratios. This structure fully utilizes the superior intrinsic insulation strength of silicon oxide (breakdown field strength ≥ 10 MV / cm) as the primary insulation barrier. The thicker silicon oxide layer bears the majority of the voltage drop in the operating voltage, ensuring basic withstand voltage capability. Silicon nitride, with its higher dielectric constant, introduces necessary capacitance density compensation in the stack, avoiding a significant decrease in capacitance due to over-reliance on low-k silicon oxide. More importantly, the polarization effect at the heterogeneous interface effectively reshapes the electric field distribution. The silicon nitride layer, acting as an electric field modulator, smooths out potential field strength jumps caused by abrupt changes in dielectric constant, while the thicker silicon oxide layer ensures that peak field strengths are sufficiently diluted. In terms of mechanical reliability, this thickness design cleverly balances the difference in thermal expansion coefficients between the two materials, effectively absorbing and dispersing interfacial shear stress generated during thermal cycling, significantly suppressing the risk of dielectric layer cracking or delamination. This "thick silicon oxide-thin silicon nitride" periodic structure, compared to a single dielectric or equal-thickness stack, helps to improve breakdown voltage and reduce leakage current while maintaining the same capacitance density. It should be noted that this architecture is perfectly compatible with standard CMOS processes, and high-precision stacking can be achieved through plasma-enhanced chemical vapor deposition, providing an optimized path that combines performance and process feasibility for developing high-voltage, high-reliability on-chip capacitors.

[0107] The step of forming the dielectric stack 220 includes:

[0108] A first silicon oxide layer 221 is formed, which covers the bottom metal electrode 210.

[0109] A first silicon nitride layer 222 is formed on the first silicon oxide layer 221;

[0110] A second silicon oxide layer 223 is formed on the first silicon nitride layer 222;

[0111] A second silicon nitride layer 224 is formed on the second silicon oxide layer 223.

[0112] In this embodiment, a plasma-enhanced chemical vapor deposition (PECVD) process is employed. First, a mixture of silane and nitrous oxide is introduced to form the first layer of silicon oxide. Then, the reactant gas is switched to a mixture of silane and ammonia, and silicon nitride is deposited at the same temperature. Alternating stacking is achieved by periodically switching the reactant gas type and deposition time. The density and internal stress of each dielectric layer can be precisely controlled by adjusting the radio frequency power (100-500W) and the reaction pressure (50-500Pa). It should be noted that this stacking process can also be implemented using low-pressure chemical vapor deposition, atomic layer deposition, or pulsed laser deposition methods, and equivalent changes to the thickness configuration of each dielectric layer, the number of cycles, and the interface treatment process (such as nitrogen plasma surface treatment) are all within the scope of protection of this invention.

[0113] It should be noted that the dielectric stack 220 includes at least a first silicon oxide layer 221, a first silicon nitride layer 222, a second silicon oxide layer 223, and a second silicon nitride layer 224 stacked sequentially. The thickness of each silicon oxide layer is greater than the thickness of the adjacent silicon nitride layer. This specific thickness configuration achieves an optimal balance between electric field optimization and capacitance density by balancing the ratio of high breakdown field strength material to high dielectric constant material. It should be understood that the above four-layer structure is only a minimal embodiment illustrating the core concept of this invention. In practical applications, the dielectric stack 220 can be expanded to include more dielectric layer pairs, such as a third silicon oxide layer, a third silicon nitride layer, a fourth silicon oxide layer, and a fourth silicon nitride layer. Increasing the number of stacking cycles can further improve the breakdown voltage and reliability. Any equivalent changes based on the core design principle of "silicon oxide layer thickness greater than silicon nitride layer thickness," achieved by increasing or decreasing the number of stacked layers or adjusting the thickness parameters of a single layer to optimize dielectric performance, fall within the scope of protection of this invention.

[0114] See Figure 6 A top dielectric layer is formed on the dielectric stack 220, and a top metal electrode 230 is formed within the top dielectric layer.

[0115] The step of forming the top metal electrode 230 includes:

[0116] A top dielectric layer is formed on the dielectric layer, and the top dielectric layer comprises a first top dielectric layer 203 and a second top dielectric layer 204 from bottom to top.

[0117] The top dielectric stack is etched to obtain a first top electrode plate trench and a second top electrode plate trench. The bottom of the first top electrode plate trench exposes the dielectric stack 220. The width of the first top electrode plate trench is smaller than the width of the second top electrode plate trench.

[0118] The first and second top-layer electrode slots are filled using a double damask process, and a planarization process is used to obtain the top-layer metal electrode 230.

[0119] The top dielectric layer has a stacked structure, i.e., a top dielectric stack.

[0120] The top layer dielectric stack includes: a first top layer dielectric layer 203 and a second top layer dielectric layer 204.

[0121] The first top dielectric layer 203 is located on the dielectric stack 220.

[0122] The second top dielectric layer 204 covers the first top dielectric layer 203.

[0123] The top layer is a stacked structure of a first top layer 203 and a second top layer 204 from bottom to top.

[0124] The first top dielectric layer 203 is made of a low-k dielectric constant material.

[0125] The dielectric constant of the first top dielectric layer 203 material is taken from 2.5 to 4.5.

[0126] The material of the first top dielectric layer 203 can be silicon oxide, carbon-doped oxide, or porous organosilicon.

[0127] Specifically, carbon-doped silicon oxide has a dielectric constant that can be tuned from 2.7 to 3.5, and the carbon doping concentration can be controlled by the precursor gas flow rate ratio; fluorine-doped silicon glass has a dielectric constant of approximately 3.5 to 3.8 and possesses excellent interstitial filling capabilities; porous organosilicon has a dielectric constant as low as 2.5 and forms a nanoporous structure through a template agent; polyimide has a dielectric constant of approximately 3.2 to 3.5 and is suitable for flexible electronic integration scenarios. If the simplicity, maturity, and absolute reliability of the process are prioritized, and the performance improvement requirements are not extremely stringent, then using silicon oxide is a completely reasonable and recommended choice. If the ultimate performance breakthrough is pursued, and the highest theoretical withstand voltage value is desired, then materials with lower dielectric constants, such as carbon-doped oxides, should be given priority. In this embodiment, the first top dielectric layer 203 is made of silicon oxide.

[0128] It should be noted that those skilled in the art should understand that the formation of the first top dielectric layer 203 can be achieved by referring to the process method for the first bottom dielectric layer 201 described in the foregoing embodiments of this specification. Specifically, the first top dielectric layer 203 can be formed using the same deposition process (such as plasma-enhanced chemical vapor deposition), the same range of process parameters (including temperature, pressure, power, and reactive gas flow rate), and the same material system (such as silicon dioxide or carbon-doped oxides) as the process for forming the first bottom dielectric layer 201. Given that this process flow is highly consistent and repeatable with the process for forming the first bottom dielectric layer 201 in terms of technical principles, equipment configuration, and material selection, the detailed process descriptions will not be repeated here to maintain the brevity of the specification. Any adaptive adjustments to process parameters based on the foregoing process principles and adapted to the characteristics of the top layer structure (such as coverage optimization for structures with different aspect ratios) should be considered to fall within the protection scope of this invention.

[0129] A second top-layer dielectric layer 204 is formed on the first top-layer dielectric layer 203, and the formed second top-layer dielectric layer 204 covers the first top-layer dielectric layer 203.

[0130] The second top dielectric layer 204 is made of a high-k dielectric constant material.

[0131] The dielectric constant of the second top dielectric layer 204 material can be taken from 6.5 to 10.5.

[0132] The material of the second top dielectric layer 204 can be silicon nitride, silicon oxynitride, aluminum nitride, or hafnium oxide.

[0133] Specifically, silicon nitride, formed by plasma-enhanced chemical vapor deposition, has a dielectric constant of approximately 7.0 to 7.5. Silicon oxynitride has a dielectric constant of 4.5 to 6.5, and stress and k-value are synergistically optimized by adjusting the oxygen-nitrogen ratio; aluminum nitride has a dielectric constant of approximately 8.5-9.0 and also possesses high thermal conductivity; hafnium oxide has a dielectric constant of approximately 20-25 and is suitable for ultra-high voltage applications. In this embodiment, the second top dielectric layer 204 is made of silicon nitride.

[0134] The second top dielectric layer 204 is formed by plasma-enhanced chemical vapor deposition, specifically including: introducing silane and ammonia into a reaction chamber in a nitrogen-containing reaction atmosphere, and depositing a silicon nitride dielectric layer on the surface of the first top dielectric layer 203. The deposition temperature is controlled between 250°C and 400°C, the radio frequency power density is 0.1-1.0 W / cm², and the reaction pressure is maintained between 100 and 1000 Pa. The stress within the dielectric layer is controlled by adjusting the flow rate ratio of silane to ammonia.

[0135] It should be noted that the second top dielectric layer 204 can also be formed by low-pressure chemical vapor deposition, atomic layer deposition or pulsed laser deposition, and the dielectric material can be replaced with silicon oxynitride, aluminum nitride or hafnium oxide high-k dielectric. These equivalent substitutions of processes and materials are all within the protection scope of this invention.

[0136] The top dielectric layer is etched to obtain a first top electrode plate groove and a second top electrode plate groove. Specifically, the bottom of the first top electrode plate groove exposes the dielectric layer 220, and the sidewall of the first top electrode plate groove is the sidewall of the first top dielectric layer 203. That is, the first top electrode plate groove is obtained by etching the first top dielectric layer 203.

[0137] In the step of forming the first top electrode trench, the silicon nitride layer on top of the dielectric stack 220 can be used as an etching barrier layer.

[0138] Those skilled in the art should understand that the formation of the first top-layer electrode trench and the second top-layer electrode trench can be achieved by referring to the etching process of the first bottom-layer electrode trench 201a in the foregoing embodiments of this specification, specifically including standard semiconductor patterning steps such as photoresist spin coating, mask alignment, exposure and development, and anisotropic dry etching. Given that this process flow is highly consistent with the foregoing embodiments in terms of process principle, equipment configuration, and parameter selection, to maintain the brevity of the specification, the detailed process descriptions already provided will not be repeated here. Any adjustment of process parameters based on the foregoing etching process principle and not substantially deviating from the core inventiveness of this invention should be considered to fall within the protection scope of this invention.

[0139] In this embodiment, the width of the first top plate groove is smaller than the width of the second top plate groove.

[0140] The first and second top-layer electrode slots provide process space for the subsequent formation of the top-layer metal electrode 230.

[0141] The first and second top-layer electrode slots are filled using a double damask process, followed by planarization to obtain the top-layer metal electrode plate. Specifically, a barrier layer is formed on the surface of the dielectric layer with a stepped electrode slot structure in the first and second top-layer electrode slots. A tantalum nitride (or titanium nitride) barrier layer and a copper seed layer are sequentially formed by physical vapor deposition. Subsequently, an electrochemical electroplating process is used to fill the first (narrow) and second top-layer electrode slots with copper metal. Finally, global planarization is performed using a chemical mechanical polishing process to sequentially remove excess copper, the barrier layer, and the seed layer until the surface of the second top-layer dielectric layer 204 is exposed, forming a top-layer metal electrode plate 230 flush with the top surface of the second top-layer dielectric layer 204. This electrode plate naturally forms a stepped morphology that is narrower at the bottom and wider at the top through the double damask process, with the narrow part fitting the first top-layer electrode slot and the wide part fitting the second top-layer electrode slot.

[0142] It should be noted that the process can also use cobalt, ruthenium or tungsten as the main filler metal, and the planarization process can be replaced by a hybrid process combining back etching and chemical mechanical polishing.

[0143] In some embodiments, the first top plate groove and the second top plate groove are filled by two electroplating processes respectively. By adjusting the current density (1-5A / dm²) and additive concentration of the two electroplating processes, the filling consistency of the narrow groove and the wide groove can be precisely controlled to avoid the generation of gaps and voids.

[0144] It should be noted that the formation steps of the top metal electrode 230 can also refer to the formation method of the bottom metal electrode 210 described above, to form the narrow portion 230a and the wide portion 230b of the top metal electrode 230 respectively. Those skilled in the art should understand that the top metal electrode 230 can be formed using the same process principle as the bottom metal electrode 210, constructing its narrow portion 230a and wide portion 230b respectively. Specifically, referring to the formation method of the wide portion 210a of the bottom metal electrode 230, the narrow portion 230a of the top metal electrode 230a is formed on the dielectric stack 220 through a first round of damascus sizing and chemical mechanical polishing; subsequently, referring to the formation method of the narrow portion of the bottom metal electrode 230, the wide portion 230b of the top metal electrode 230b is constructed on the narrow portion 230a through a second round of damascus sizing and chemical mechanical polishing. It should be noted that although the process principle is the same, due to the step height difference in the top layer structure, the process parameters of chemical mechanical polishing can be adaptively adjusted during implementation, including adjusting the polishing pressure and optimizing the polishing liquid composition. These parameter optimizations based on the same process principle and made to adapt to the structural characteristics should all be considered to fall within the protection scope of this invention.

[0145] In this embodiment, before forming the barrier layer, the surface of the substrate 200 is first cleaned by Ar ion sputtering, that is, the bottom and sidewalls of the metal electrode groove are cleaned.

[0146] A barrier layer is formed, covering the bottom and sidewalls of the first top-layer electrode slot and the bottom and sidewalls of the second top-layer electrode slot. The material of the barrier layer / adhesive layer is selected from one or more of the following: titanium, tantalum, cobalt, ruthenium, molybdenum, titanium nitride, and tantalum nitride. The barrier layer is used to prevent metal in the metal electrode from diffusing into the dielectric stack 220 or the top dielectric stack, thereby improving the thermal stability and long-term operational reliability of the capacitor. The barrier layer / adhesive layer can enhance the bonding force between the top metal electrode 230 and the surrounding dielectric layer, preventing the top metal electrode 230 from delaminating and peeling off, and ensuring the mechanical integrity of the multilayer structure.

[0147] The material of the top metal electrode plate 230 is selected from one or more of the following combinations: copper, aluminum, and copper-aluminum alloy.

[0148] The top metal plate 230 has a narrow portion 230a and a wide portion 230b, forming a stepped structure that is wider at the top and narrower at the bottom.

[0149] See also Figure 6 , Figure 7 and Figure 8 , Figure 7 This is a top view of the top metal plate of a capacitor structure according to an embodiment of the present invention. The view direction is opposite to the Z direction. As shown in the figure, the narrow portion 230a and the wide portion 230b of the top metal plate 230 have a concentric rounded rectangle structure in this view.

[0150] The ratio of the width W2 of the narrow portion 230a of the top metal electrode plate 230 to the width W1 of the wide portion 230b of the top metal electrode plate is selected from (0.85, 1). The ratio of the thickness T2 of the narrow portion of the top metal electrode plate to the thickness T1 of the wide portion of the top metal electrode plate is greater than or equal to 1.5. 0.85 × 1.5 = 1.275, 1 × 1 = 1. Therefore, the ratio of the cross-sectional area of ​​the narrow portion to the wide portion should be greater than 1.275, and the cross-sectional area of ​​the narrow portion is larger, so that the narrow portion can better disperse the edge electric field of the wide portion.

[0151] The narrow portion 230a and the wide portion 230b of the top metal electrode plate 230 adopt a concentric rounded rectangular structure, which is an improvement on the traditional right-angle structure based on the basic principle of electric field distribution. The core advantage of this design is that by eliminating all sharp corners, the radius of curvature of the conductor surface is maximized, thereby significantly reducing the electric field concentration coefficient at the electrode edge according to Maxwell's electromagnetic field theory. The rounded corner structure makes the electric field lines continuously and smoothly distributed in the corner region, avoiding the electric field singularity and local field strength multiplication effect that a right-angle structure will inevitably produce at the corner. The rounded corner edges of the concentrically arranged narrow portion 230a and wide portion 230b form a continuously gradually changing equipotential surface, constructing a uniformly transitioning potential distribution in three-dimensional space, so that the highest electric field region originally concentrated at the corner is dispersed to the entire rounded arc surface. This geometric optimization, in conjunction with the aforementioned stepped field plate structure, not only solves the edge electric field problem in the straight-edge region, but also completely eliminates the weakest breakdown point in traditional designs—the right-angle corner. This improves the overall breakdown voltage of the structure under the same dielectric thickness, significantly enhances the voltage cycle life and high-temperature stability of the device, and improves the performance of the capacitor structure described in this invention under high voltage.

[0152] In this embodiment, when the potential of the top metal plate 230 is higher than that of the bottom metal plate 210, the dielectric constant of the first top dielectric layer 230a is less than that of the second top dielectric layer 230b, and the dielectric constant of the first bottom dielectric layer 210a is less than that of the second bottom dielectric layer 210b. The capacitor structure, through precise coupling of the spatial gradient of the dielectric constant and the electrode shape, successfully reduces the peak value of the edge electric field significantly, thus alleviating the problem of electric field concentration at edge corners. This directly translates to a significant increase in breakdown voltage, a reduction in leakage current by an order of magnitude, and improved device reliability, while maintaining high integration, which helps to resolve the inherent contradiction between high voltage and miniaturization.

[0153] The first top dielectric layer 230a, the second top dielectric layer 230b, the first bottom dielectric layer 210a, and the second bottom dielectric layer 210b, through the precise matching of their spatial gradient distribution of dielectric constant with the corresponding electrode structure, collaboratively construct a multidimensional electric field control system.

[0154] Specifically, electric field lines tend to pass through media with higher dielectric constants because high dielectric constant materials are more easily polarized and can accommodate more electric displacement vectors. When the top metal plate 230 is at a high potential, its field plate function is to "pull" the electric field lines downwards. The second top dielectric layer 230b uses a high-k dielectric, which is equivalent to establishing an efficient "pull channel" for the top metal plate 230. The electric field lines will preferentially choose this low-resistance path, achieving active dissipation of the edge electric field. The first bottom dielectric layer 210a serves as the main voltage drop bearing layer, utilizing its low dielectric constant to ensure a reasonable distribution of electric field intensity across the wide portion 210a of the bottom metal plate. The second bottom dielectric layer 210b serves as the edge electric field absorption layer, leveraging its high dielectric constant to localize the electric field concentration effect at the edge of the narrow portion 210b of the bottom metal plate. The first top dielectric layer 230a, together with the former, forms a low dielectric constant core region, jointly bearing the operating voltage. The second top dielectric layer 230b serves as the field plate efficiency enhancement layer, maximizing the electric field guidance effect across the wide portion of the top plate through its high dielectric constant. The four dielectric layers, through alternating changes in dielectric constant, reconstruct the electric field from "edge concentration" to "bulk uniformity," ultimately achieving the invention's objective of increasing breakdown voltage and enhancing reliability.

[0155] To address the aforementioned technical problems, this application also provides a capacitor structure.

[0156] The capacitor structure provided in this embodiment of the invention includes: a bottom dielectric layer; a bottom metal electrode plate located within the bottom dielectric layer; a dielectric stack covering the bottom metal electrode plate; a top dielectric layer located on the dielectric stack; and a top metal electrode plate having a narrow portion and a wide portion, forming a stepped structure that is wider at the top and narrower at the bottom, located within the top dielectric layer. The ratio of the width of the narrow portion to the width of the wide portion of the top metal electrode plate is selected from (0.85, 1), and the ratio of the thickness of the narrow portion to the thickness of the wide portion of the top metal electrode plate is greater than or equal to 1.5. This structure, by designing the top metal electrode plate as a stepped form with a specific size ratio, disperses the electric field at the edge of the top metal electrode plate, thereby effectively suppressing the edge electric field and improving capacitor performance. Furthermore, by controlling the width ratio of the narrow to wide portion of the top metal electrode plate between 0.85 and 1, a gradually transitioning integrated field plate structure is formed. This redistributes the electric field peaks originally concentrated at the electrode edge into a smoother gradient field, significantly reducing the local electric field intensity. In addition, the thickness of the narrow portion is at least 1.5 times the thickness of the wide portion, providing robust mechanical support for the wide portion and further dispersing the electric field at the edge of the top metal electrode plate through the thicker narrow portion, thus optimizing the continuity of the electric field line distribution. This collaborative design optimizes the electric field line distribution without significantly increasing the chip area, significantly improving the capacitor's breakdown voltage and long-term reliability, and helping to resolve the contradiction between field intensity concentration and integration density in high-voltage applications. Therefore, the capacitor structure and its formation method can improve the performance of the capacitor structure.

[0157] See Figure 6 , Figure 6 This is a cross-sectional schematic diagram of a capacitor structure in an embodiment of the present invention.

[0158] The capacitor structure includes: substrate 200.

[0159] The substrate 200 is used to provide a process platform for the formation of the capacitor structure.

[0160] The substrate may include, from bottom to top, a semiconductor substrate, an isolation layer, transistor gate and source / drain electrodes, an interlayer dielectric layer, and a metal interconnect layer. The metal interconnect layer includes contact pads for electrical connection to the lower electrode of the capacitor. The substrate surface has a planarized surface formed by chemical mechanical polishing (CMP) to ensure uniformity of the capacitor layers.

[0161] In this embodiment, the substrate 200 may contain a semiconductor device structure whose previous processes have been completed, providing an integrated technical platform for capacitor fabrication. The substrate 200 includes planarized interlayer dielectric layers, metal interconnects, and silicon-based transistors, forming a surface with specific topological morphology and electrical properties, providing a reliable mechanical support substrate for the deposition of each layer of the capacitor structure.

[0162] In some embodiments, the substrate 200 achieves electrical connection between the lower electrode and the underlying circuit through a preset contact via, thereby ensuring the compatibility of the capacitor with existing semiconductor processes and the stability of the final device performance.

[0163] The capacitor structure includes: a bottom dielectric layer.

[0164] The underlying dielectric layer has a stacked structure.

[0165] The underlying dielectric layer includes: a first underlying dielectric layer 201 and a second underlying dielectric layer 202.

[0166] The first bottom dielectric layer 201 is located on the substrate 200.

[0167] The second bottom dielectric layer 202 covers the first bottom dielectric layer 201.

[0168] The bottom dielectric layer is a stacked structure of a first bottom dielectric layer 201 and a second bottom dielectric layer 202 from bottom to top.

[0169] The first bottom dielectric layer 201 is made of a low-k dielectric constant material.

[0170] The dielectric constant of the first bottom dielectric layer 201 material is taken from 2.5 to 4.5.

[0171] The material of the first bottom dielectric layer 201 can be silicon oxide, carbon-doped oxide, or porous organosilicon.

[0172] The bottom metal plate 210 is located on the substrate 200 and within the bottom dielectric layer.

[0173] The bottom metal plate 210 has a narrow portion 210b and a wide portion 210a, forming a stepped structure that is narrower at the top and wider at the bottom.

[0174] The second bottom dielectric layer 202 covers the first bottom dielectric layer 201 and part of the width portion 210a of the bottom metal electrode plate.

[0175] The second bottom dielectric layer 202 is made of a high-k dielectric constant material.

[0176] The dielectric constant of the second bottom dielectric layer 202 material can be taken from 6.5 to 10.5.

[0177] The material of the second bottom dielectric layer 202 can be silicon nitride, silicon oxynitride, aluminum nitride, or hafnium oxide.

[0178] In this embodiment, the material of the second bottom dielectric layer 202 is silicon nitride.

[0179] The wide portion 210a of the bottom metal electrode plate is located within the first bottom dielectric layer; the narrow portion 210b of the bottom metal electrode plate is located within the second bottom dielectric layer.

[0180] In some embodiments, the bottom metal electrode 210 may include only the wide portion 210a of the bottom metal electrode.

[0181] The capacitor structure includes: a dielectric stack 220.

[0182] The dielectric stack 220 covers the bottom metal electrode 210.

[0183] The dielectric stack 220 is a stack of multiple dielectric layers.

[0184] This multilayer structure, by arranging dielectric materials with different coefficients of thermal expansion, allows the dielectric layers with varying coefficients to compensate for each other, significantly reducing the risk of dielectric layer cracking due to thermal stress and enhancing structural integrity. Furthermore, by optimizing the thickness ratio and stacking order of each dielectric layer, it is possible to maintain high capacitance density while synergistically optimizing multiple parameters such as quality factor, voltage linearity, and temperature stability, overcoming the inherent performance and reliability bottlenecks of traditional single-dielectric capacitors. It should be noted that this multilayer architecture also provides flexibility for customized designs. Capacitance can be controlled by adjusting the number of dielectric layers, and the interlayer interface characteristics can be adjusted or functional dielectric layers can be introduced to meet the extreme requirements of specific application scenarios for high-frequency response, radiation resistance, or long-term reliability.

[0185] In this embodiment, the dielectric stack 220 is an alternating stack of multiple silicon oxide layers and multiple silicon nitride layers, and the thickness of the silicon oxide layer is greater than the thickness of the silicon nitride layer.

[0186] The dielectric stack 220 includes at least a first silicon oxide layer 221, a first silicon nitride layer 222, a second silicon oxide layer 223, and a second silicon nitride layer 224, which are stacked sequentially. The thickness of each silicon oxide layer is greater than the thickness of the adjacent silicon nitride layer. This specific thickness configuration achieves an optimal balance between electric field optimization and capacitance density by balancing the ratio of high breakdown field strength material to high dielectric constant material. It should be understood that the above four-layer structure is only a minimum embodiment illustrating the core concept of the present invention. In practical applications, the dielectric stack 220 can be expanded to include more dielectric layer pairs, such as a third silicon oxide layer, a third silicon nitride layer, a fourth silicon oxide layer, and a fourth silicon nitride layer. Increasing the number of stacking cycles can further improve the breakdown voltage and reliability. Any equivalent changes based on the core design principle of "silicon oxide layer thickness greater than silicon nitride layer," achieved by increasing or decreasing the number of stacked layers or adjusting the thickness parameters of individual layers to optimize dielectric performance, fall within the scope of protection of this invention.

[0187] The top dielectric layer is located on the dielectric stack 220.

[0188] The top dielectric layer has a stacked structure, i.e., a top dielectric stack.

[0189] The top layer dielectric stack includes: a first top layer dielectric layer 203 and a second top layer dielectric layer 204.

[0190] The first top dielectric layer 203 is located on the dielectric stack 220.

[0191] The second top dielectric layer 204 covers the first top dielectric layer 203.

[0192] The top layer is a stacked structure of a first top layer 203 and a second top layer 204 from bottom to top.

[0193] The first top dielectric layer 203 is made of a low-k dielectric constant material.

[0194] The dielectric constant of the first top dielectric layer 203 material is taken from 2.5 to 4.5.

[0195] The material of the first top dielectric layer 203 can be silicon oxide, carbon-doped oxide, or porous organosilicon.

[0196] The second top dielectric layer 204 is made of a high-k dielectric constant material.

[0197] The dielectric constant of the second top dielectric layer 204 material can be taken from 6.5 to 10.5.

[0198] The material of the second top dielectric layer 204 can be silicon nitride, silicon oxynitride, aluminum nitride, or hafnium oxide.

[0199] The top metal electrode 230 has a narrow portion 230a and a wide portion 230b, forming a stepped structure that is wider at the top and narrower at the bottom, and is located within the top dielectric layer.

[0200] The narrow portion 230a of the top metal electrode is located within the first top dielectric layer 203; the wide portion 230b of the bottom metal electrode is located within the second top dielectric layer 204.

[0201] The material of the top metal electrode 230 is selected from one or more of the following: copper, aluminum, and copper-aluminum alloy. In this embodiment, the material of the top metal electrode 230 is copper.

[0202] In some embodiments, the sidewall of the top metal electrode width 230b is an outwardly convex curved surface, and the convex direction of the convex curved surface is away from the top metal electrode width 230b.

[0203] In some embodiments, the sidewall of the bottom metal electrode width 210a is an outwardly convex curved surface, and the convex direction of the convex curved surface is away from the bottom metal electrode width 210a.

[0204] See also Figures 6 to 11 ,in, Figures 9 to 11 These are different embodiments of the top metal electrode plate.

[0205] It should be noted that, Figure 7 The fact that the narrow portion 230a and the wide portion 230b of the top metal electrode plate 230 are distinguished by different colors does not mean that the narrow portion 230a and the wide portion 230b of the top metal electrode plate 230 are made of different materials.

[0206] Figure 8 In the diagram, the dotted line indicated by the arrow represents the rounded corners at the contact points between the narrow portion 230a and the wide portion 230b of the top metal electrode plate 230, thereby reducing the possibility of electric field concentration. This design is not limited to this embodiment and can be used in combination in other embodiments.

[0207] The ratio of the width W2 of the narrow portion of the top metal electrode to the width W1 of the wide portion of the top metal electrode is selected from (0.85, 1), and the ratio of the thickness T2 of the narrow portion of the top metal electrode to the thickness T1 of the wide portion of the top metal electrode is greater than or equal to 1.5. It should be noted that if the thickness T2 of the narrow portion of the top metal electrode is too small, it will not be able to disperse the electric field at the electrode edge, or its effect will be insignificant. Conversely, the thickness T2 of the narrow portion of the top metal electrode cannot be too large; if it is greater than 5 times, a new electric field concentration will form at the electrode edge corner of the narrow portion 230a of the top metal electrode. The width W2 of the narrow portion of the top metal electrode cannot be less than 0.85 of the width W1 of the wide portion of the top metal electrode. If the width W2 of the narrow portion of the top metal electrode is too small, it will not be able to disperse the electric field at the electrode edge, or its effect will be insignificant. Therefore, 0.85 × 1.5 = 1.275, 1 × 1 = 1. Thus, the ratio of the cross-sectional area of ​​the narrow portion 230a to the wide portion 230b should be greater than 1.275. The narrow portion has a larger cross-sectional area, which allows it to better disperse the edge electric field of the wide portion.

[0208] See also Figure 8 and Figure 12 , Figure 13 , Figure 12 Cross-sectional view of the electric field distribution at the edge structure of a traditional parallel electrode and a stepped plate; Figure 13 The electric field distribution characteristics of traditional parallel plate structures and stepped plate structures with different dielectric layer thicknesses under an applied voltage of 1000V are shown.

[0209] See Figure 12 Taking a dielectric stack 220 with a thickness of 5 μm as an example, the capacitive isolation performance of a traditional parallel electrode structure and a stepped electrode structure under a 1000V applied voltage is compared and analyzed. The results show that there are significant differences in the electric field distribution characteristics of the two electrode structures. The stepped structure introduces some electric field lines into the narrow portion 230a of the top metal electrode plate, and this portion of the electric field eventually flows into the middle of the bottom metal electrode plate 210 and away from the edge. As a result, the electric field uniformity of the stepped electrode structure is superior to that of the traditional parallel electrode structure. Under normal operating conditions, a more uniform electric field distribution can effectively alleviate electrode edge aging, reduce the risk of failure, and improve device reliability.

[0210] See Figure 13The electric field distribution characteristics of traditional parallel electrode structures and stepped electrode structures under a 1000V applied voltage were compared and analyzed. Taking the thicknesses of the dielectric stack 220 as 5μm, 6μm, and 7μm as examples, the maximum electric field strength of the traditional structure decreases with increasing thickness: 5.71MV / cm for 5μm, 5MV / cm for 6μm, and 4.33MV / cm for 7μm. Notably, the maximum electric field strength of the 5μm stepped structure is only 4.37MV / cm, showing a significant advantage over the traditional structure. This result indicates that by optimizing the electrode geometry, the thickness of the dielectric stack 220 can be reduced by approximately 30% (from 7μm to 5μm) while maintaining the same withstand voltage level, thereby effectively improving the device's integration density and performance.

[0211] Specifically, by ensuring a smooth transition between the wide portion 230b and the narrow portion 230a of the top metal plate, sharp edges are avoided, thereby reducing the electric field peak and achieving a fundamental improvement in the corner electric field.

[0212] In this embodiment, the ratio of the width W2 of the narrow portion of the top metal electrode to the width W1 of the wide portion of the top metal electrode is 0.9. This structure helps the narrow portion 230a of the top metal electrode to disperse the edge electric field of the wide portion 230b of the top metal electrode. It can reduce the electric field peak generated at the corners of traditional right-angle structures.

[0213] Meanwhile, the vertical configuration with T2 / T1≥1.5 provides enhanced structural stiffness to the narrow section, ensuring that the wide section of the field plate maintains its predetermined geometry in the corner region, preventing new electric field concentration points from arising due to collapse of the field plate edges caused by process stress or thermal deformation. This combination of horizontal quasi-continuity and vertical high stiffness is beneficial for reducing the equipotential line distribution density at the corners, transforming the electric field lines from a traditional radial clustered distribution to a uniformly divergent pattern along the rounded corner tangential direction, which is conducive to improving the breakdown voltage threshold.

[0214] See also Figures 7 to 11 The narrow portion 230a and the wide portion 230b of the top metal electrode 230 adopt a concentric rounded rectangle structure, which is an improvement on the traditional right-angle structure based on the basic principle of electric field distribution. The core advantage of this design is that by eliminating sharp corners, the radius of curvature of the conductor surface is maximized, thereby significantly reducing the electric field concentration coefficient at the electrode edge according to Maxwell's electromagnetic field theory.

[0215] The cross-sectional shape of the wide portion 230b of the top metal electrode plate is a rounded rectangle.

[0216] The cross-sectional shape of the narrow portion 230a of the top metal electrode plate is a rounded rectangle.

[0217] The vertical cross-section of the wide portion 230b of the top metal electrode plate is trapezoidal or rectangular.

[0218] The shape of the vertical cross section of the narrow portion 230a of the top metal electrode plate is trapezoidal, arc-shaped, or rectangular.

[0219] The vertical cross-section of the wide portion 210a of the bottom metal electrode plate is trapezoidal or rectangular.

[0220] The vertical cross-section of the narrow portion 210b of the bottom metal electrode plate is trapezoidal, arc-shaped, or rectangular.

[0221] The core advantage of this design lies in maximizing the radius of curvature of the conductor surface by eliminating all sharp corners, thereby significantly reducing the electric field concentration coefficient at the electrode edges based on Maxwell's electromagnetic field theory. The rounded corner structure ensures a continuous and smooth distribution of electric field lines in the corner region, avoiding the electric field singularities and local field strength multiplication effects that are inevitable at corners in right-angle structures.

[0222] When the potential of the top metal plate 230 is higher than that of the bottom metal plate 210, the dielectric constant of the first bottom dielectric layer 201 is less than that of the second bottom dielectric layer 202, and the dielectric constant of the first top dielectric layer 203 is less than that of the second top dielectric layer 204. This capacitor structure, through precise coupling of the spatial gradient of the dielectric constant and the electrode shape, successfully reduces the peak value of the edge electric field significantly, thus alleviating the problem of electric field concentration at edge corners. This directly translates to a significant increase in breakdown voltage, a reduction in leakage current by orders of magnitude, and improved device reliability, while maintaining high integration, which helps resolve the inherent contradiction between high voltage and miniaturization. Therefore, this capacitor structure can improve the performance of capacitor structures.

[0223] This invention also provides a semiconductor device comprising the capacitor structure described in any of the preceding embodiments.

[0224] The semiconductor devices include logic chips and memory chips.

[0225] It should be understood that in the embodiments of this application, the logic chip can be a central processing unit (CPU), which can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc.

[0226] It should also be understood that the memory chip in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be ROM, Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), or flash memory. The volatile memory can be Random Access Memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate Synchronous DRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

[0227] This invention also provides an electronic device, including any of the semiconductor devices described above.

[0228] The semiconductor device can be built into or externally connected to the electronic device, which includes, but is not limited to, mobile phones, computers, tablets, servers, cloud platforms, etc.

[0229] It is understood that the above description of capacitor structure and formation method, semiconductor device, and electronic device has multiple embodiments. The optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed in this invention.

[0230] It should be understood that "multiple" in the embodiments of this application refers to two or more.

[0231] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0232] It should be noted that the sequence number of each step in this embodiment does not represent a limitation on the execution order of each step.

[0233] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a capacitor structure, comprising: The method comprises the following steps: forming a bottom dielectric layer; forming a bottom metal electrode plate in the bottom dielectric layer; forming a dielectric stack on the bottom metal electrode plate; forming a top dielectric layer on the dielectric stack; forming a top metal electrode plate in the top dielectric layer, the top metal electrode plate having a narrow part and a wide part, and having a stepped structure of wide top and narrow bottom; wherein the ratio of the width of the narrow part of the top metal electrode plate to the width of the wide part of the top metal electrode plate is selected from (0.85, 1), and the ratio of the thickness of the narrow part of the top metal electrode plate to the thickness of the wide part of the top metal electrode plate is greater than or equal to 1.5; the step of forming the top metal electrode plate comprises: forming a top dielectric stack on the dielectric stack, the top dielectric stack comprising a first top dielectric layer and a second top dielectric layer from bottom to top; etching the top dielectric stack to obtain a first top electrode plate slot and a second top electrode plate slot, the bottom of the first top electrode plate slot exposing the dielectric stack, and the width of the first top electrode plate slot being smaller than the width of the second top electrode plate slot; filling the first top electrode plate slot and the second top electrode plate slot by using a double damascene process, and obtaining the top metal electrode plate by using a planarization process; wherein in the case that the potential of the top metal electrode plate is higher than the potential of the bottom metal electrode plate, the dielectric constant of the first top dielectric layer is smaller than the dielectric constant of the second top dielectric layer.

2. The method of claim 1, wherein, The step of filling the first top electrode plate slot and the second top electrode plate slot further comprises: forming a barrier layer covering the bottom and sidewall of the first top electrode plate slot and the bottom and sidewall of the second top electrode plate slot.

3. The method of claim 1, wherein, The bottom dielectric layer is a stacked structure of a first bottom dielectric layer and a second bottom dielectric layer from bottom to top, and the bottom metal electrode plate has a narrow part and a wide part, and has a stepped structure of narrow top and wide bottom; the step of forming the bottom metal electrode plate comprises: forming the first bottom dielectric layer; etching the first bottom dielectric layer to obtain a first bottom electrode plate slot; filling the first bottom electrode plate slot by using a damascene process, and obtaining the wide part of the bottom metal electrode plate by using a planarization process; forming the second bottom dielectric layer on the first bottom dielectric layer; etching the second bottom dielectric layer to obtain a second bottom electrode plate slot, the width of the second bottom electrode plate slot being smaller than the width of the first bottom electrode plate slot; filling the second bottom electrode plate slot by using a damascene process, and obtaining the narrow part of the bottom metal electrode plate by using a planarization process; wherein in the case that the potential of the top metal electrode plate is higher than the potential of the bottom metal electrode plate, the dielectric constant of the first bottom dielectric layer is smaller than the dielectric constant of the second bottom dielectric layer.

4. The method of claim 3, wherein, The first top dielectric layer is silicon oxide; The second top dielectric layer is silicon nitride; The first bottom dielectric layer is silicon oxide; The second bottom dielectric layer is silicon nitride.

5. The method of claim 1, wherein, The dielectric stack is an alternating stack of a plurality of silicon oxide layers and a plurality of silicon nitride layers; the step of forming the dielectric stack comprises: forming a first silicon oxide layer, the first silicon oxide layer covering the bottom metal electrode plate; forming a first silicon nitride layer on the first silicon oxide layer; forming a second silicon oxide layer on the first silicon nitride layer; forming a second silicon nitride layer on the second silicon oxide layer; The medium stack comprises at least a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer and a second silicon nitride layer, and the thickness of the silicon oxide layer is greater than the thickness of the silicon nitride layer.

6. A capacitor structure, characterized by comprise: a bottom medium layer; a bottom metal electrode plate in the bottom medium layer; a medium stack covering the bottom metal electrode plate; a top medium layer on the medium stack; a top metal electrode plate with a narrow part and a wide part in a stepped structure of wide top and narrow bottom in the top medium layer; The ratio of the width of the narrow part of the top metal electrode plate to the width of the wide part of the top metal electrode plate is selected from (0.85, 1), and the ratio of the thickness of the narrow part of the top metal electrode plate to the thickness of the wide part of the top metal electrode plate is greater than or equal to 1.

5. The top metal electrode plate comprises: a top medium layer on the medium stack, the top medium layer comprising a first top medium layer and a second top medium layer from bottom to top; a first top electrode plate slot and a second top electrode plate slot are obtained by etching the top medium layer, the bottom of the first top electrode plate slot exposes the medium stack, the width of the first top electrode plate slot is less than the width of the second top electrode plate slot, and the top metal electrode plate is obtained by filling the first top electrode plate slot and the second top electrode plate slot by double damascene process and by planarization process; In the case that the potential of the top metal electrode plate is higher than that of the bottom metal electrode plate, the dielectric constant of the first top medium layer is less than that of the second top medium layer.

7. The capacitance structure of claim 6, wherein, One or more of the following are met: The cross section of the wide part of the top metal electrode plate is a rounded rectangle; The cross section of the narrow part of the top metal electrode plate is a rounded rectangle; The vertical section of the wide part of the top metal electrode plate is a trapezoidal or rectangular shape; The vertical section of the narrow part of the top metal electrode plate is a trapezoidal, arcuate or rectangular shape; The vertical section of the wide part of the bottom metal electrode plate is a trapezoidal or rectangular shape; The vertical section of the narrow part of the bottom metal electrode plate is a trapezoidal, arcuate or rectangular shape.

8. The capacitance structure of claim 6, wherein, The top medium layer and the top metal electrode plate comprise: a first top medium layer; a narrow part of the top metal electrode plate in the first top medium layer; a second top medium layer; a wide part of the top metal electrode plate in the second top medium layer.

9. The capacitance structure of claim 6, wherein, The bottom medium layer and the bottom metal electrode plate comprise: a first bottom medium layer; a wide part of the bottom metal electrode plate in the first bottom medium layer; a second bottom medium layer; a narrow part of the bottom metal electrode plate in the second bottom medium layer; In the case that the potential of the top metal electrode plate is higher than that of the bottom metal electrode plate, the dielectric constant of the first bottom medium layer is less than that of the second bottom medium layer.

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