Semiconductor device

Abstract

A semiconductor device may include: a first substrate; a first active pattern on the first substrate and extending in a first direction; a first gate electrode on the first active pattern and extending in a second direction different from the first direction; a gate cap pattern on the first gate electrode; a gate contact extending into the gate cap pattern and electrically connected to the first gate electrode; a bonding layer on the gate cap pattern; a second substrate on the bonding layer; a second active pattern on the second substrate and extending in the first direction, where the second active pattern includes a lower pattern and a sheet pattern on the lower pattern; a second gate electrode on the second active pattern and extending in a second direction; and a connection via on the gate contact and electrically connected to each of the gate contact and the second gate electrode, where the connection via extends into the second substrate.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Semiconductor devices are core components used to control or amplify electrical signals in electronic devices, and various types of semiconductor devices can be manufactured. For example, memory devices are primarily used for storing and retrieving data, while non-memory devices can be used to control or amplify electrical signals. Semiconductor devices are core components of electronic devices and play an important role in various fields, including computers, communication equipment, and consumer electronics.

[0003] With industrial development, the demands on the performance and functionality of electronic devices are constantly increasing. Therefore, high-performance characteristics of semiconductor devices are a fundamental requirement, and the integration density of semiconductor devices is increasing to meet these requirements. Various methods are being investigated for forming semiconductor devices with excellent performance and improved integration density. Summary of the Invention

[0004] To address one or more problems (e.g., the problems mentioned above and / or other problems not explicitly described herein), this disclosure provides a semiconductor device with improved electrical characteristics and reliability.

[0005] According to some embodiments of this disclosure, the integration density of a semiconductor device can be improved by forming a gate contact and a connection via between the first gate electrode and the second gate electrode.

[0006] According to some embodiments of this disclosure, the reliability of a semiconductor device can be improved by forming a connection via on the lower surface of the second gate electrode.

[0007] According to some embodiments of this disclosure, a semiconductor device includes: a first substrate; a first active pattern on the first substrate and extending in a first direction; a first gate electrode on the first active pattern and extending in a second direction different from the first direction; a gate cap pattern on the first gate electrode; a gate contact extending into the gate cap pattern and electrically connected to the first gate electrode; a bonding layer on the gate cap pattern; a second substrate on the bonding layer; a second active pattern on the second substrate and extending in the first direction, wherein the second active pattern includes a lower pattern and a sheet pattern on the lower pattern; a second gate electrode on the second active pattern and extending in the second direction; and a connection via on the gate contact and electrically connected to each of the gate contact and the second gate electrode, wherein the connection via extends into the second substrate.

[0008] According to some embodiments of this disclosure, a semiconductor device includes: a first substrate; a first active pattern on the first substrate and extending in a first direction; a first gate electrode on the first active pattern and extending in a second direction different from the first direction; a first gate isolation structure on a sidewall of the first gate electrode and extending in the first direction; a gate contact on the first gate electrode; a second substrate on the gate contact; a second active pattern on the second substrate and extending in the first direction, wherein the second active pattern includes a lower pattern and a patch pattern on the lower pattern; a second gate electrode on the second active pattern and extending in the second direction; a connection via on the gate contact and electrically connected to each of the gate contact and the second gate electrode; and a second gate isolation structure on a sidewall of the second gate electrode and extending in the first direction, wherein the connection via is spaced apart from the lower pattern in the second direction.

[0009] According to some embodiments of this disclosure, a semiconductor device includes: a first substrate; a first active pattern on the first substrate and extending in a first direction, wherein the first active pattern includes a first lower pattern and a first sheet pattern on the first lower pattern; a first gate electrode on the first active pattern and extending in a second direction different from the first direction; a gate cap pattern on the first gate electrode; a first gate isolation structure extending into the gate cap pattern and the first gate electrode and extending in the first direction; an interlayer insulating film, a contact etch stop film, and a bonding layer on the gate cap pattern; and a gate contact on the first gate electrode and extending into the first direction. The second active pattern is located in the gate cover pattern and interlayer insulating film; a second substrate is located on the bonding layer; a second active pattern is located on the second substrate and extends in a first direction, wherein the second active pattern includes a second lower pattern and a second sheet pattern on the second lower pattern; a second gate electrode is located on the second active pattern and extends in a second direction; a connection via is located on the gate contact and electrically connected to each of the gate contact and the second gate electrode; and a second gate isolation structure is located on the sidewall of the second gate electrode and extends in the first direction, wherein the connection via extends into the second substrate and is spaced apart from the second lower pattern in the second direction. Attached Figure Description

[0010] The above and other embodiments and features of this disclosure will become clearer by referring to the accompanying drawings and describing in detail the exemplary embodiments of this disclosure.

[0011] Figure 1 These are example plan views provided to explain semiconductor devices according to some embodiments.

[0012] Figure 2 It is along Figure 1 The sectional view taken by line AA.

[0013] Figure 3 It is along Figure 1 The sectional view taken by line BB.

[0014] Figure 4 It is provided to explain Figure 3 A magnified view of region Q1.

[0015] Figure 5 These are diagrams provided to explain semiconductor devices according to some embodiments.

[0016] Figure 6 These are diagrams provided to explain semiconductor devices according to some embodiments.

[0017] Figure 7 These are diagrams provided to explain semiconductor devices according to some embodiments.

[0018] Figures 8 to 10 These are diagrams provided to explain semiconductor devices according to some embodiments.

[0019] Figures 11 to 28 This is a diagram illustrating an intermediate stage of a method for manufacturing a semiconductor device according to some embodiments. Detailed Implementation

[0020] In the following, a semiconductor device and a method for manufacturing a semiconductor device according to some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Here, sequential terms (such as first, second, etc.) are used to distinguish elements having the same / similar functions, and the ordinal numbers may be interchanged according to the order in which the terms are mentioned. For the sake of clarity, parts irrelevant to the description will be omitted, and the same elements or equivalents will be referred to by the same reference numerals throughout the specification. Furthermore, since the dimensions and thicknesses of the constituent components shown in the drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the dimensions and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are shown excessively for better understanding and ease of description.

[0021] It will be understood that when an element (such as a layer, film, region, or substrate) is referred to as being “on” another element, the element may be directly on the other element, or an intervening element may be present. Conversely, when an element is referred to as being “directly on” another element, no intervening element is present. Additionally, for ease of description, spatial relative terms (such as “below,” “under,” “lower,” “above,” “upper,” etc.) may be used herein to describe the relationship of one element or feature shown in the figures to another element or feature. It will be understood that, in addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as being “below” or “under” another element or feature would be oriented “above” another element or feature. Thus, the term “below” can cover both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0022] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. It will also be understood that when the term “comprising” and its variations are used herein, they specify the presence of the stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. The term “and / or” includes any and all combinations of one or more of the associated listed items. The term “connection” may be used herein to refer to a physical connection and / or an electrical connection, and may refer to a direct or indirect physical connection and / or electrical connection.

[0023] Figure 1 These are example plan views provided to explain semiconductor devices according to some embodiments. Figure 2 It is along Figure 1 The sectional view taken by line AA. Figure 3 It is along Figure 1 A sectional view taken from the BB line. Figure 4 It is provided to explain Figure 3 An enlarged view of region Q1. For reference, the structure other than the first substrate 100, the first active pattern AP1, the first gate electrode 120, the first gate isolation structure 140, the gate contact 170, and the connection via 180 is shown in... Figure 1 The middle part is omitted.

[0024] Reference Figures 1 to 4According to some embodiments, a semiconductor device may include a first substrate 100, a second substrate 200, a first active pattern AP1, a second active pattern AP2, a first gate electrode 120, a second gate electrode 220, a first gate isolation structure 140, a second gate isolation structure 240, a first gate cover pattern 165, a second gate cover pattern 265, a gate contact 170, a connection via 180, a bonding layer 196, etc.

[0025] The semiconductor device according to some embodiments may include a metal-oxide-semiconductor field-effect transistor (MOSFET), and more specifically, may include a gate-all-around (GAA) transistor and a three-dimensional multi-stacked semiconductor device known as a multi-bridge channel FET (MBCFET).

[0026] The first substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, the first substrate 100 may include, but is not limited to, silicon-germanium (SiGe), silicon-germanium-on-insulator (SGOI), indium antimony, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimony.

[0027] A first active pattern AP1 may be disposed on a first substrate 100. The first active pattern AP1 may extend in a first direction D1. The first active pattern AP1 may be disposed spaced apart from an adjacent first active pattern AP1 in a second direction D2. In this case, the first direction D1 is a direction that intersects with the second direction D2. Each of the first direction D1 and the second direction D2 may be a direction parallel to the upper surface 100_US of the first substrate 100.

[0028] The first active pattern AP1 can be a multi-channel active pattern. The first active pattern AP1 may include a first lower pattern BP1 and multiple first sheet patterns NS1.

[0029] A first lower pattern BP1 may protrude from a first substrate 100. The first lower pattern BP1 may extend in a first direction D1. The first lower pattern BP1 may be spaced apart from an adjacent first lower pattern BP1 in a second direction D2. The first lower pattern BP1 and the adjacent first lower pattern BP1 may be isolated by a first device isolation trench ST1. The first device isolation trench ST1 may be defined by an upper surface 100_US of the first substrate 100 and a side surface of the first lower pattern BP1.

[0030] Multiple first patterns NS1 may be disposed on a first lower pattern BP1. The multiple first patterns NS1 may be spaced apart from the first lower pattern BP1 in a third direction D3. Each of the first patterns NS1 may be spaced apart from each other in the third direction D3. The third direction D3 may be a direction intersecting each of the first direction D1 and the second direction D2. The third direction D3 may be a direction perpendicular to the upper surface 100_US of the first substrate 100. The third direction D3 may be the thickness direction of the first substrate 100. The first patterns NS1 may have a nanosheet shape (e.g., a pattern extending in the first direction D1 and surrounded by the first gate electrode 120 in the plane of the second direction D2 and the third direction D3). Although three first patterns NS1 are shown, the embodiment is not limited thereto.

[0031] The first lower pattern BP1 can be formed by etching a portion of the first substrate 100. However, embodiments are not limited thereto. For example, the first lower pattern BP1 may include an epitaxial layer grown from the first substrate 100. The first lower pattern BP1 may include an elemental semiconductor material (such as silicon (Si) or germanium (Ge)). Furthermore, the first lower pattern BP1 may include a compound semiconductor. For example, the first lower pattern BP1 may include a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0032] For example, a group IV-IV compound semiconductor can be a binary or ternary compound comprising at least two or more of carbon (C), silicon (Si), germanium (Ge) and / or tin (Sn).

[0033] For example, a III-V compound semiconductor can be a binary, ternary, or quaternary compound formed by combining at least one of aluminum (Al) or gallium (Ga) and / or indium (In) as a group III element with one of phosphorus (P), arsenic (As), and / or antimony (Sb) as a group V element.

[0034] The first pattern NS1 may include one of the following: elemental semiconductor materials (such as silicon (Si), silicon germanium (SiGe)), group IV-IV compound semiconductors, and / or group III-V compound semiconductors. The first pattern NS1 may include the same material as the first lower pattern BP1, or it may include a different material from the first lower pattern BP1.

[0035] The first lower pattern BP1 and the plurality of first sheet patterns NS1 may comprise silicon (Si). In other embodiments, the first lower pattern BP1 and the plurality of first sheet patterns NS1 may comprise silicon germanium (SiGe).

[0036] A first field insulating film 105 may be disposed on a first substrate 100. The first field insulating film 105 may fill at least a portion of a first device isolation trench ST1. The first field insulating film 105 may be disposed between adjacent first lower patterns BP1. The first field insulating film 105 may extend in a first direction D1. The first field insulating film 105 may be formed on the upper surface 100_US of the first substrate 100. The first field insulating film 105 may cover, overlap with, or be disposed on the side surface of the first lower pattern BP1. For example, the first field insulating film 105 may cover, overlap with, or be disposed on the side surface of the first lower pattern BP1, but may not be disposed on the upper surface of the first lower pattern BP1.

[0037] For example, the first field insulating film 105 may comprise oxides, nitrides, oxynitrides, or combinations thereof. Although the first field insulating film 105 is shown as a single film, this is for ease of description only, and the embodiments are not limited thereto. For example, the first field insulating film 105 may be formed from multiple films.

[0038] The first source / drain pattern 150 can be disposed on the first active pattern AP1. The first source / drain pattern 150 can be disposed on the first lower pattern BP1. The first source / drain pattern 150 can be connected to the first pattern NS1. A portion of the side surface of the first source / drain pattern 150 can contact the first pattern NS1. Another portion of the side surface of the first source / drain pattern 150 can contact the first gate insulating film 130. The first source / drain pattern 150 can connect the first patterns NS1 that are spaced apart from each other in the first direction D1. The first source / drain pattern 150 can be disposed between the first patterns NS1 that are spaced apart from each other in the first direction D1.

[0039] The first source / drain pattern 150 may be disposed at least on one side of the first gate electrode 120. The first source / drain pattern 150 may be disposed between the first gate electrodes 120 that are adjacent to each other in the first direction D1. Unlike what is shown, the first source / drain pattern 150 may be disposed on one side of the first gate electrode 120 and may not be disposed on the other side of the first gate electrode 120.

[0040] The first source / drain pattern 150 can be an epitaxial pattern formed by a selective epitaxial growth process using a first active pattern AP1 as a seed. The first source / drain pattern 150 can be used as the source / drain of a transistor in which the first pattern NS1 is used as the channel region.

[0041] The first source / drain pattern 150 may include a semiconductor material. For example, the first source / drain pattern 150 may include an elemental semiconductor material (such as silicon (Si) or germanium (Ge)). Furthermore, for example, the first source / drain pattern 150 may include a binary or ternary compound comprising at least two or more of carbon (C), silicon (Si), germanium (Ge), and / or tin (Sn), or a compound doped with a group IV element. For example, the first source / drain pattern 150 may include silicon (Si), silicon-germanium (SiGe), germanium (Ge), silicon carbide (SiC), etc., but is not limited thereto.

[0042] The first source / drain pattern 150 may include impurities doped into the semiconductor material. The doped impurities may include at least one of boron (B), phosphorus (P), carbon (C), arsenic (As), antimony (Sb), bismuth (Bi), and / or oxygen (O), but the embodiments are not limited thereto.

[0043] Although the first source / drain pattern 150 is shown as a single film, this is for ease of description only, and the embodiments are not limited thereto. The first source / drain pattern 150 may comprise multiple films comprising different materials. In other embodiments, the first source / drain pattern 150 may comprise multiple layers comprising the same material, and may comprise multiple layers comprising constituent materials with different concentrations.

[0044] Although not shown, the semiconductor device according to some embodiments may also include a lower source / drain contact. The lower source / drain contact may be disposed on the first source / drain pattern 150. The lower source / drain contact may penetrate or extend into the first interlayer insulating film 160 and the first etch stop film 155, and be connected to the first source / drain pattern 150. In other embodiments, the lower source / drain contact may penetrate or extend into the first substrate 100, and be electrically connected to the first source / drain pattern 150.

[0045] A first gate electrode 120 may extend on a first substrate 100 in a second direction D2. The first gate electrode 120 may intersect a first active pattern AP1. The first gate electrode 120 may be disposed on a first lower pattern BP1. The first gate electrode 120 may be spaced apart from adjacent first gate electrodes in the first direction D1. The first gate electrode 120 may surround a plurality of first sheet patterns NS1. The first gate electrode 120 may surround four surfaces of the first sheet pattern NS1. For example, the first gate electrode 120 may surround the upper surface, lower surface, and two side surfaces of the first sheet pattern NS1. The upper and lower surfaces of the first sheet pattern NS1 may refer to the surfaces intersecting a third direction D3, and the two side surfaces of the first sheet pattern NS1 may refer to the surfaces intersecting the second direction D2.

[0046] The first gate electrode 120 may include a first upper gate electrode 120_U and a first lower gate electrode 120_B. The first lower gate electrode 120_B may be disposed between adjacent first patterns NS1 on the third direction D3. The first lower gate electrode 120_B may be disposed between multiple first patterns NS1, and may be disposed between the first lower pattern BP1 and the lowermost first pattern NS1 among the multiple first patterns NS1. The first upper gate electrode 120_U may be disposed on the uppermost first pattern NS1 among the multiple first patterns NS1.

[0047] In some embodiments, the first active pattern AP1 may include a plurality of first patterns NS1, and the first gate electrode 120 may include a plurality of first lower gate electrodes 120_B. In this case, the number of first lower gate electrodes 120_B may be proportional to the number of first patterns NS1 included in the first active pattern AP1. The number of first lower gate electrodes 120_B may be the same as the number of first patterns NS1. For example, as Figure 2 As shown, the number of first lower gate electrodes 120_B can be the same as the number of first pattern NS1, which can be three. However, the embodiments are not limited to this.

[0048] The first gate electrode 120 may include at least one of the following: metal, metal alloy, conductive metal nitride, metal silicide, doped semiconductor material, conductive metal oxide, and / or conductive metal oxide nitride. For example, the first gate electrode 120 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), aluminum titanium nitride (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), and tungsten (W). The materials may include, but are not limited to, at least one of the following: aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (NiPt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and / or combinations thereof. Conductive metal oxides and conductive metal nitrides may include, but are not limited to, the oxides of the materials mentioned above.

[0049] The first gate isolation structure 140 can penetrate or extend into the first gate cover pattern 165 and the first gate electrode 120. The first gate isolation structure 140 can extend in a first direction D1 and a third direction D3. The first gate electrode 120 can be isolated in a second direction D2 by the first gate isolation structure 140. The lower part of the first gate isolation structure 140 can penetrate or extend into the upper surface of the first field insulating film 105. The lower surface of the first gate isolation structure 140 can be disposed in the first field insulating film 105. The lower surface of the first gate isolation structure 140 can contact the first field insulating film 105.

[0050] In some embodiments, the first gate isolation structure 140 may have a tapered shape. That is, the width of the first gate isolation structure 140 in the second direction D2 may decrease toward the first substrate 100. However, the embodiments are not limited to the above. For example, unlike what is shown, the width of the first gate isolation structure 140 may be constant.

[0051] The first gate insulating film 130 may be disposed between the first gate electrode 120 and a plurality of first patterns NS1, between the first gate electrode 120 and a first lower pattern BP1, and between the first gate electrode 120 and a first source / drain pattern 150. Specifically, the first gate insulating film 130 may be disposed between the first upper gate electrode 120_U and the uppermost first pattern NS1 among the plurality of first patterns NS1. The first gate insulating film 130 may be disposed between the first lower gate electrode 120_B and the first pattern NS1. The first gate insulating film 130 may surround the first pattern NS1. The first gate insulating film 130 may extend along the upper and lower surfaces of the first pattern NS1 in a first direction D1.

[0052] In some embodiments, the first gate insulating film 130 may include multiple films. For example, the first gate insulating film 130 may include a first interface insulating film and a first high-k insulating film. For example, the first interface insulating film may include silicon oxide. The first high-k insulating film may include a high-k material having a dielectric constant greater than that of the first interface insulating film. For example, the first high-k insulating film may include at least one of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate.

[0053] The first gate spacer 145 may be disposed on the side surface of the first upper gate electrode 120_U and the side surface of the first gate cover pattern 165. For example, the first gate spacer 145 may extend along the side surface of the first upper gate electrode 120_U and the side surface of the first gate cover pattern 165. The first gate spacer 145 may not be located between the first lower pattern BP1 and the first sheet pattern NS1. The first gate spacer 145 may not be located between the first sheet patterns NS1 that are adjacent to each other on the third direction D3.

[0054] For example, the first gate spacer 145 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and / or combinations thereof. Although the first gate spacer 145 is shown as a single film, this is only for ease of description, and the embodiments are not limited thereto.

[0055] A first gate cap pattern 165 may be disposed on the first upper gate electrode 120_U. The first gate cap pattern 165 may cover the upper surface of the first upper gate electrode 120_U, overlap with the upper surface of the first upper gate electrode 120_U, or be disposed on the upper surface of the first upper gate electrode 120_U. The first gate cap pattern 165 may be overlapped with the first upper gate electrode 120_U on a third direction D3 or on the first upper gate electrode 120_U. The first gate cap pattern 165 may be disposed between the first gate spacers 145. The side surface of the first gate cap pattern 165 may contact the first gate spacers 145. The upper surface of the first gate cap pattern 165 may be disposed on the same plane as the upper surface of the first interlayer insulating film 160. However, the embodiments are not limited thereto.

[0056] Although a first gate cap pattern 165 is shown disposed between the first gate spacers 145, the embodiment is not limited thereto. For example, the side surface of the first gate cap pattern 165 may contact the first etch stop film 155. In this case, the first gate cap pattern 165 may be disposed on the upper surface of the first upper gate electrode 120_U and the upper surface of the first gate spacer 145.

[0057] For example, the first gate cover pattern 165 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and / or combinations thereof. The first gate cover pattern 165 may include a material having etch selectivity relative to the first interlayer insulating film 160.

[0058] The first etch stop film 155 may extend along the contour of the side surface of the first gate spacer 145 and the upper surface of the first source / drain pattern 150. Although not shown, the first etch stop film 155 may be disposed on the upper surface of the first field insulating film 105.

[0059] The first etch stop film 155 may include a material that has etch selectivity relative to the first interlayer insulating film 160. For example, the first etch stop film 155 may include at least one of silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and / or combinations thereof.

[0060] The first interlayer insulating film 160 may be disposed on the first etch stop film 155. The first interlayer insulating film 160 may be disposed on the first source / drain pattern 150. The first interlayer insulating film 160 may be disposed on one side of the first upper gate electrode 120_U. The first interlayer insulating film 160 may be disposed between the first upper gate electrodes 120_U.

[0061] For example, the first interlayer insulating film 160 may include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and / or a low-k material. For example, the low-k material may include, but is not limited to, tetraethyl orthosilicate (FTEOS), silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilane borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), tonil silazane (TOSZ), fluorosilicate glass (FSG), polyimide nanofoam (such as polypropylene oxide), carbon-doped silicon oxide (CDO), organosilicon glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica degel, mesoporous silica, and / or combinations thereof.

[0062] A second interlayer insulating film 192 may be disposed on the first gate cap pattern 165. The second interlayer insulating film 192 may extend along the upper surface of the first gate cap pattern 165. The second interlayer insulating film 192 may include an insulating material. The description of the material of the second interlayer insulating film 192 may be the same as the description of the material of the first interlayer insulating film 160. For example, the second interlayer insulating film 192 may include silicon oxide (SiO).

[0063] A gate contact 170 may be disposed on the first gate electrode 120. The gate contact 170 may penetrate or extend into the second interlayer insulating film 192 and the first gate cap pattern 165, and is disposed on the upper surface of the first gate electrode 120. The gate contact 170 may be connected to the first gate electrode 120. In some embodiments, the upper surface of the gate contact 170 may be disposed on the same plane as the upper surface of the second interlayer insulating film 192.

[0064] The gate contact 170 may be configured to be spaced apart from the first active pattern AP1 in the second direction D2. In other words, the gate contact 170 may not overlap with the first active pattern AP1 in the third direction D3. However, the embodiments are not limited to the above. For example, a portion of the gate contact 170 may overlap with at least a portion of the first active pattern AP1 in the third direction D3.

[0065] In some embodiments, a gate contact 170 may be disposed on a first gate isolation structure 140. The gate contact 170 may be stacked on a third direction D3 with the first gate isolation structure 140. The gate contact 170 may contact the first gate isolation structure 140. A portion of the first gate isolation structure 140 may be recessed to correspond to the shape of the gate contact 170.

[0066] The gate contact 170 may include a conductive material. The gate contact 170 may include at least one of ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten (W), tungsten nitride (WN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), two-dimensional materials (2D materials), aluminum (Al), copper (Cu), silver (Ag), gold (Au), manganese (Mn), and / or molybdenum (Mo).

[0067] The second etch stop film 194 may be disposed on the second interlayer insulating film 192. The bonding layer 196 may be disposed on the second etch stop film 194. That is, the second interlayer insulating film 192, the second etch stop film 194 and the bonding layer 196 may be sequentially stacked on the first gate cover pattern 165.

[0068] The description of the material of the second etch stop film 194 may be the same as the description of the material of the first etch stop film 155. For example, the bonding layer 196 may include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and / or combinations thereof.

[0069] The second substrate 200 may be disposed on the bonding layer 196. The second substrate 200 may be bulk silicon or SOI. Alternatively, the second substrate 200 may include, but is not limited to, silicon germanium (SiGe), SGOI, indium antimony, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0070] The second active pattern AP2 can be disposed on the second substrate 200. The second active pattern AP2 can extend in the first direction D1. The second active pattern AP2 can be disposed on the first active pattern AP1. The second active pattern AP2 can be superimposed on the first active pattern AP1 in the third direction D3.

[0071] The first active pattern AP1 may be a region in which a PMOS is formed, and the second active pattern AP2 may be a region in which an NMOS is formed. In other embodiments, the first active pattern AP1 may be a region in which an NMOS is formed, and the second active pattern AP2 may be a region in which a PMOS is formed.

[0072] The second active pattern AP2 can be a multi-channel active pattern. The second active pattern AP2 may include a second lower pattern BP2 and multiple second sheet patterns NS2.

[0073] The second lower pattern BP2 may protrude from the second substrate 200. The second lower pattern BP2 may extend in the first direction D1. The second lower pattern BP2 may be configured to be spaced apart from an adjacent second lower pattern BP2 in the second direction D2. The second lower pattern BP2 and the adjacent second lower pattern BP2 may be isolated by a second device isolation trench ST2. The second device isolation trench ST2 may be defined by the upper surface 200_US of the second substrate 200 and the side surface BP2_SS of the second lower pattern BP2.

[0074] Multiple second sheet patterns NS2 may be disposed on the second lower pattern BP2. The multiple second sheet patterns NS2 may be spaced apart from the second lower pattern BP2 in the third direction D3. The second sheet patterns NS2 may be spaced apart from each other in the third direction D3. The second sheet patterns NS2 may have a nanosheet shape. Although three second sheet patterns NS2 are shown, the embodiment is not limited thereto.

[0075] The description of the material of the second lower pattern BP2 and the second piece pattern NS2 can be the same as the description of the material of each of the first lower pattern BP1 and the first piece pattern NS1.

[0076] A second field insulating film (or "device isolation film") 205 may be disposed on the second substrate 200. The second field insulating film 205 may fill at least a portion of the second device isolation trench ST2. The second field insulating film 205 may be disposed between adjacent second lower patterns BP2. The second field insulating film 205 may extend in a first direction D1. The second field insulating film 205 may be formed on the upper surface 200_US of the second substrate 200. The second field insulating film 205 may cover or be disposed on the side surface of the second lower pattern BP2. For example, the second field insulating film 205 may cover or be disposed on the side surface of the second lower pattern BP2, but may not be disposed on the upper surface of the second lower pattern BP2.

[0077] The second gate electrode 220 may extend on the second substrate 200 in the second direction D2. The second gate electrode 220 may intersect with the second active pattern AP2. The second gate electrode 220 may be disposed on the second lower pattern BP2. The second gate electrode 220 may be spaced apart from adjacent second gate electrodes in the first direction D1. The second gate electrode 220 may surround a plurality of second patterns NS2. The second gate electrode 220 may extend around or around the four surfaces of the second pattern NS2. For example, the second gate electrode 220 may extend around the upper surface, lower surface, and two side surfaces of the second pattern NS2, or around the upper surface, lower surface, and two side surfaces of the second pattern NS2. The upper and lower surfaces of the second pattern NS2 may refer to the surfaces intersecting with the third direction D3, and the two side surfaces of the second pattern NS2 may refer to the surfaces intersecting with the second direction D2.

[0078] The second gate electrode 220 may include a second upper gate electrode 220_U and a second lower gate electrode 220_B. The second lower gate electrode 220_B may be disposed between adjacent second patterns NS2 on the third direction D3. The second lower gate electrode 220_B may be disposed between multiple second patterns NS2, and may be disposed between the second lower pattern BP2 and the lowermost second pattern NS2 among the multiple second patterns NS2. The second upper gate electrode 220_U may be disposed on the uppermost second pattern NS2 among the multiple second patterns NS2.

[0079] In some embodiments, the second active pattern AP2 may include a plurality of second patterns NS2, and the second gate electrode 220 may include a plurality of second lower gate electrodes 220_B. In this case, the number of second lower gate electrodes 220_B may be proportional to the number of second patterns NS2 included in the second active pattern AP2. The number of second lower gate electrodes 220_B may be the same as the number of second patterns NS2. For example, as Figure 2As shown, the number of second lower gate electrodes 220_B is three, the same as the number of second pattern NS2. However, the embodiments are not limited to this.

[0080] The second gate electrode 220 may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and / or a conductive metal oxynitride. The description of the material of the second gate electrode 220 may be the same as the description of the material of the first gate electrode 120.

[0081] Although each of the first gate electrode 120 and the second gate electrode 220 is shown as a single film, the embodiments are not limited thereto. For example, each of the first gate electrode 120 and the second gate electrode 220 may include a work function control film (or work function regulating film) for adjusting the work function (or "work function") and a filling conductive film for filling the space formed by the work function control film. The work function regulating film may include at least one of, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), titanium aluminum carbide (TiAlC), and / or combinations thereof. The filling conductive film may include, for example, tungsten (W) or aluminum (Al).

[0082] In some embodiments, the work function adjustment film of the first gate electrode 120 and the work function adjustment film of the second gate electrode 220 may comprise different materials. The work function adjustment film of the first gate electrode 120 may comprise a P-type work function adjustment film, and the work function adjustment film of the second gate electrode 220 may comprise an N-type work function adjustment film. In other embodiments, the work function adjustment film of the first gate electrode 120 may comprise an N-type work function adjustment film, and the work function adjustment film of the second gate electrode 220 may comprise a P-type work function adjustment film.

[0083] The second gate isolation structure 240 can penetrate the second gate cap pattern 265 and the second gate electrode 220. The second gate isolation structure 240 can extend in the first direction D1 and the third direction D3. The second gate electrode 220 can be isolated in the second direction D2 by the second gate isolation structure 240. The lower part of the second gate isolation structure 240 can penetrate the upper surface of the second field insulating film 205 or extend into the upper surface of the second field insulating film 205. The lower surface of the second gate isolation structure 240 can be disposed in the second field insulating film 205. The lower surface of the second gate isolation structure 240 can contact the second field insulating film 205. In some embodiments, the distance H1 from the upper surface 200_US of the second substrate 200 to the lower surface of the second gate isolation structure 240 can be less than the distance H2 from the upper surface 200_US of the second substrate 200 to the upper surface of the connecting via 180.

[0084] In some embodiments, the second gate isolation structure 240 may have a tapered shape. That is, the width of the second gate isolation structure 240 in the second direction D2 may decrease toward the second substrate 200. However, the embodiments are not limited to the above. For example, unlike what is shown, the width of the second gate isolation structure 240 may be constant.

[0085] The second gate insulating film 230 may be disposed between the second gate electrode 220 and a plurality of second patterns NS2, between the second gate electrode 220 and the second lower pattern BP2, and between the second gate electrode 220 and the second source / drain pattern 250. Specifically, the second gate insulating film 230 may be disposed between the second upper gate electrode 220_U and the uppermost second pattern NS2 among the plurality of second patterns NS2. The second gate insulating film 230 may be disposed between the second lower gate electrode 220_B and the second pattern NS2. The second gate insulating film 230 may surround or extend around the second pattern NS2. The second gate insulating film 230 may extend along the upper and lower surfaces of the second pattern NS2 in a first direction D1.

[0086] In some embodiments, the second gate insulating film 230 may include multiple films. For example, the second gate insulating film 230 may include a second interface insulating film and a second high-k insulating film. The description of the materials of the second interface insulating film and the second high-k insulating film may be the same as the description of the materials of each of the first interface insulating film and the first high-k insulating film.

[0087] A via 180 may be disposed on the gate contact 170. The via 180 may penetrate or extend into the second field insulating film 205, the second substrate 200, the bonding layer 196, and the second etch stop film 194. The via 180 may be connected to each of the gate contact 170 and the second gate electrode 220. For example, one end of the via 180 may contact the upper surface of the gate contact 170, and the other end of the via 180 may contact the lower surface of the second gate electrode 220.

[0088] A portion of the connecting via 180 may be disposed within the second field insulating film 205. The second field insulating film 205 may extend around or around a portion of the connecting via 180. The connecting via 180 may be spaced apart from the second lower pattern BP2 in the second direction D2. The second field insulating film 205 may be disposed between the connecting via 180 and the second lower pattern BP2. The connecting via 180 may be spaced apart from the second sheet pattern NS2 in the second direction D2. In other words, the connecting via 180 may not overlap with the second sheet pattern NS2 in the third direction D3.

[0089] The second gate insulating film 230 may extend around or around the side surface of the connection via 180. The second gate insulating film 230 may extend along the side surface of the connection via 180 and may contact the second etch stop film 194 and the gate contact 170. From a cross-sectional perspective, the second gate insulating film 230 (e.g., a portion of the second gate insulating film 230) may be disposed on both side surfaces of the connection via 180.

[0090] In some embodiments, a second gate isolation structure 240 may be disposed on a connection via 180. The connection via 180 may be stacked on the second gate isolation structure 240 in a third direction D3. The connection via 180 may contact the second gate isolation structure 240. A portion of the connection via 180 may be recessed to correspond to the shape of the second gate isolation structure 240.

[0091] The connection via 180 may include a conductive material. The connection via 180 may include a material different from that of the second gate electrode 220. The connection via 180 may include at least one of the following: molybdenum (Mo), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), two-dimensional materials (2D materials), aluminum (Al), copper (Cu), silver (Ag), gold (Au), and / or manganese (Mn).

[0092] Separate wiring may be required to electrically connect the first gate electrode 120 and the second gate electrode 220. For example, wiring structures connecting to the lower portion of the first gate electrode 120 and wiring structures connecting to the upper portion of the second gate electrode 220 may be required. In some embodiments, the semiconductor device may electrically connect the first gate electrode 120 and the second gate electrode 220 to a gate contact 170 disposed on the upper surface of the first gate electrode 120 and a connection via 180 disposed on the lower surface of the second gate electrode 220. Therefore, the integration density of the semiconductor device can be improved.

[0093] The second gate cover pattern 265 may be disposed on the second upper gate electrode 220_U. The second gate cover pattern 265 may cover the upper surface of the second upper gate electrode 220_U, overlap with the upper surface of the second upper gate electrode 220_U, or be disposed on the upper surface of the second upper gate electrode 220_U. The second gate cover pattern 265 may be overlapped with the second upper gate electrode 220_U on a third direction D3. The second gate cover pattern 265 may be disposed between the second gate spacers 245. The side surface of the second gate cover pattern 265 may contact the second gate spacers 245. The upper surface of the second gate cover pattern 265 may be disposed on the same plane as the upper surface of the third interlayer insulating film 260. However, the embodiments are not limited thereto.

[0094] Although a second gate cap pattern 265 is shown disposed between the second gate spacers 245, the embodiment is not limited thereto. For example, the side surface of the second gate cap pattern 265 may contact the third etch stop film 255. In this case, the second gate cap pattern 265 may be disposed on the upper surface of the second upper gate electrode 220_U and the upper surface of the second gate spacer 245.

[0095] The second gate spacer 245 may be disposed on the side surface of the second upper gate electrode 220_U and the side surface of the second gate cover pattern 265. For example, the second gate spacer 245 may extend along the side surface of the second upper gate electrode 220_U and the side surface of the second gate cover pattern 265. The second gate spacer 245 may not be located between the second lower pattern BP2 and the second sheet pattern NS2. The second gate spacer 245 may not be located between the second sheet patterns NS2 that are adjacent to each other on the third direction D3.

[0096] The description of the materials of the second gate cover pattern 265 and the second gate spacer 245 may be the same as the description of the materials of each of the first gate cover pattern 165 and the first gate spacer 145.

[0097] The second source / drain pattern 250 can be disposed on the second active pattern AP2. The second source / drain pattern 250 can be disposed on the second lower pattern BP2. The second source / drain pattern 250 can be connected to the second pattern NS2. A portion of the side surface of the second source / drain pattern 250 can contact the second pattern NS2. Another portion of the side surface of the second source / drain pattern 250 can contact the second gate insulating film 230. The second source / drain pattern 250 can connect to the second patterns NS2 spaced apart in the first direction D1. The second source / drain pattern 250 can be disposed between the second patterns NS2 spaced apart in the first direction D1.

[0098] The second source / drain pattern 250 may be disposed at least on one side of the second gate electrode 220. The second source / drain pattern 250 may be disposed between adjacent second gate electrodes 220 in the first direction D1. Unlike the illustration, the second source / drain pattern 250 may be disposed on one side of the second gate electrode 220 and may not be disposed on the other side of the second gate electrode 220.

[0099] The second source / drain pattern 250 can be an epitaxial pattern formed by a selective epitaxial growth process using a second active pattern AP2 as a seed. The second source / drain pattern 250 can be used as the source / drain of a transistor in which the second pattern NS2 is used as the channel region.

[0100] The second source / drain pattern 250 may include a semiconductor material. The description of the material of the second source / drain pattern 250 may be the same as the description of the material of the first source / drain pattern 150. In embodiments, the first source / drain pattern 150 and the second source / drain pattern 250 may include different conductivity types.

[0101] Although the second source / drain pattern 250 is shown as a single film, this is for ease of description only, and the embodiments are not limited thereto. The second source / drain pattern 250 may comprise multiple films comprising different materials. In other embodiments, the second source / drain pattern 250 may comprise multiple layers comprising the same material, and may comprise multiple layers comprising constituent materials with different concentrations.

[0102] Although not shown, the semiconductor device according to some embodiments may also include upper source / drain contacts. The upper source / drain contacts may be disposed on the second source / drain pattern 250. The upper source / drain contacts may penetrate or extend into the third interlayer insulating film 260 and the third etch stop film 255 and be connected to the second source / drain pattern 250.

[0103] The third etch stop film 255 may extend along the contour of the side surface of the second gate spacer 245 and the upper surface of the second source / drain pattern 250. Although not shown, the third etch stop film 255 may be disposed on the upper surface of the second field insulating film 205.

[0104] The third interlayer insulating film 260 may be disposed on the third etch stop film 255. The third interlayer insulating film 260 may be disposed on the second source / drain pattern 250. The third interlayer insulating film 260 may be disposed on one side of the second upper gate electrode 220_U. The third interlayer insulating film 260 may be disposed between the second upper gate electrodes 220_U.

[0105] The third etch stop film 255 may include a material that has etch selectivity relative to the third interlayer insulating film 260. The description of the material of the third etch stop film 255 may be the same as the description of the material of the first etch stop film 155. The description of the material of the third interlayer insulating film 260 may be the same as the description of the material of the first interlayer insulating film 160.

[0106] Figure 5 These are diagrams provided to explain semiconductor devices according to some embodiments. For ease of description, the main description will be related to... Figures 1 to 4 The constructions described in the text are different from the constructions described in the text.

[0107] Reference Figure 5 In a semiconductor device according to some embodiments, the connection via 180 may include the same material as the second gate electrode 220. The boundary surface between the connection via 180 and the second gate electrode 220 may not be distinguished.

[0108] In some embodiments, the connection via 180 and the second gate electrode 220 can be formed simultaneously. In other words, the connection via 180 and the second gate electrode 220 can be formed using the same process.

[0109] Figure 6 These are diagrams provided to explain semiconductor devices according to some embodiments. For ease of description, the main description will be related to... Figures 1 to 4 The constructions described in the text are different.

[0110] Reference Figure 6 In a semiconductor device according to some embodiments, the gate contact 170 and the connection via 180 may include multiple layers.

[0111] The gate contact 170 may include a first barrier film 172 and a first filler film 174. The first barrier film 172 may be disposed along the gate contact trench 170_T. The first barrier film 172 may contact each of the second interlayer insulating film 192, the first gate cap pattern 165, the first gate electrode 120, and the first gate isolation structure 140. The first filler film 174 may be disposed on the first barrier film 172. The first filler film 174 may fill the gate contact trench 170_T.

[0112] The connection via 180 may include a second barrier film 182 and a second filler film 184. The second barrier film 182 may be disposed along the connection via trench 180_T. The second barrier film 182 may be disposed along a second gate insulating film 230 disposed on the connection via trench 180_T. The second filler film 184 may be disposed on the second barrier film 182. The second filler film 184 may fill the connection via trench 180_T.

[0113] In some embodiments, the second barrier film 182 may be disposed between the second filling film 184 and the first filling film 174. A portion of the second barrier film 182 may contact the first filling film 174. However, the embodiments are not limited to the above. For example, the second barrier film 182 may not be disposed between the second filling film 184 and the first filling film 174, and the second filling film 184 may contact the first filling film 174.

[0114] Each of the first barrier film 172 and the second barrier film 182 may include at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and / or 2D materials. Each of the first filler film 174 and the second filler film 184 may include at least one of, for example, aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), and / or molybdenum (Mo).

[0115] Figure 7 These are diagrams provided to explain semiconductor devices according to some embodiments. For ease of description, the main description will be related to... Figures 1 to 4 The constructions described in the text are different.

[0116] Reference Figure 7 In a semiconductor device according to some embodiments, a first gate isolation structure 140 may be disposed on a first field insulating film 105.

[0117] The first gate isolation structure 140 may penetrate the first gate cover pattern 165, the first gate electrode 120, and the first gate insulating film 130, or extend into the first gate cover pattern 165, the first gate electrode 120, and the first gate insulating film 130. The lower surface of the first gate isolation structure 140 may be disposed on the upper surface of the first field insulating film 105. According to some embodiments, the first gate isolation structure 140 may not penetrate the first field insulating film 105, or may not extend into the first field insulating film 105.

[0118] The second gate isolation structure 240 may penetrate the second gate cover pattern 265, the second gate electrode 220, and the second gate insulating film 230, or extend into the second gate cover pattern 265, the second gate electrode 220, and the second gate insulating film 230. The lower surface of the second gate isolation structure 240 may be disposed on the upper surface of the second field insulating film 205. The second gate isolation structure 240 may not penetrate the second field insulating film 205, or may not extend into the second field insulating film 205. The lower surface of the second gate isolation structure 240 may contact the connection via 180.

[0119] Figures 8 to 10 These are diagrams provided to explain semiconductor devices according to some embodiments. For reference, Figure 8 These are plan views provided to explain semiconductor devices according to some embodiments. Figure 9 It is along Figure 8 The sectional view taken by line AA. Figure 10 It is along Figure 8 A sectional view taken along the BB line. For ease of description, the main description will be... Figures 1 to 4 The constructions described in the text are different.

[0120] A first active pattern AP1 may be disposed on a first substrate 100. A second active pattern AP2 may be disposed on a second substrate 200. The first active pattern AP1 may be a region in which a PMOS is formed, and the second active pattern AP2 may be a region in which an NMOS is formed.

[0121] The first source / drain pattern 150 may be disposed in the source / drain recess 150_R. The first source / drain pattern 150 may include a first semiconductor layer 152 and a second semiconductor layer 154.

[0122] A first semiconductor layer 152 may extend along the side and bottom surfaces of the source / drain recess 150_R. The first semiconductor layer 152 may contact the first lower pattern BP1, the first gate insulating film 130, the first gate spacer 145, and the first sheet pattern NS1. A second semiconductor layer 154 may be disposed on the first semiconductor layer 152. The second semiconductor layer 154 may fill the source / drain recess 150_R.

[0123] Each of the first semiconductor layer 152 and the second semiconductor layer 154 may include silicon-germanium. The germanium fraction of the first semiconductor layer 152 may differ from the germanium fraction of the second semiconductor layer 154. For example, the germanium fraction of the first semiconductor layer 152 may be less than the germanium fraction of the second semiconductor layer 154.

[0124] In some embodiments, each of the first semiconductor layer 152 and the second semiconductor layer 154 may further include a doped P-type impurity. For example, the P-type impurity may be boron (B), but is not limited thereto.

[0125] The inner gate spacer 242 may be disposed between the second lower gate electrode 220_B and the second source / drain pattern 250. The second source / drain pattern 250 and the second gate insulating film 230 may be disposed on two side surfaces of the inner gate spacer 242. The second gate electrode 220 may be spaced apart from the second source / drain pattern 250 by the inner gate spacer 242.

[0126] For example, the inner gate spacer 242 may include at least one of silicon oxide (SiO), silicon oxynitride (SiON), silicon boron nitride (SiBN), silicon carbonitride (SiOCN), and / or silicon nitride (SiN).

[0127] Although the inner gate spacer 242 is shown disposed between the second source / drain pattern 250 and the second gate electrode 220, the embodiment is not limited thereto. For example, the inner gate spacer may be disposed between the first source / drain pattern 150 and the first gate electrode 120.

[0128] A gate contact 170 may be disposed on the first gate electrode 120. The gate contact 170 may be connected to the first gate electrode 120. The gate contact 170 may be configured to be spaced apart from the first gate isolation structure 140 in the second direction D2. In other words, the gate contact 170 may not overlap with the first gate isolation structure 140 in the third direction D3.

[0129] A connection via 180 may be disposed between the gate contact 170 and the second gate electrode 220. The connection via 180 may be configured to be spaced apart from the second gate isolation structure 240 in the second direction D2. In other words, the connection via 180 may not overlap with the second gate isolation structure 240 in the third direction D3.

[0130] Figures 11 to 28 This is a diagram illustrating an intermediate stage of a method for manufacturing a semiconductor device according to some embodiments. Figure 11 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments. Figure 12 , Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 and Figure 27 It is along Figure 11 The sectional view taken by line AA. Figure 13 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 and Figure 28 It is along Figure 11 A sectional view taken from line BB. Furthermore, for Figures 11 to 28 The description of the construction and the Figures 1 to 10 The above description of the construction is repeated and can be omitted.

[0131] Reference Figures 11 to 13 A method for manufacturing a semiconductor device according to some embodiments may include forming a first active pattern AP1, a first gate electrode 120, a first gate insulating film 130, a first source / drain pattern 150, a first etch stop film 155, a first interlayer insulating film 160, and a first gate cap pattern 165 on a first substrate 100.

[0132] A first gate isolation structure 140 may be formed that penetrates or extends into the first gate cover pattern 165 and the first gate electrode 120. The first gate isolation structure 140 may extend in a first direction D1 and a third direction D3. The first gate electrodes 120 disposed on both sides of the first gate isolation structure 140 may be insulated from each other.

[0133] Reference Figure 14 A gate contact 170 can be formed on the first gate electrode 120.

[0134] Specifically, a second interlayer insulating film 192 may be formed on the first gate cap pattern 165 and the first gate isolation structure 140. A gate contact trench 170_T may be formed by etching the second interlayer insulating film 192 and the first gate cap pattern 165. The gate contact trench 170_T may expose a portion of the upper surface of the first gate electrode 120.

[0135] In some embodiments, the gate contact trench 170_T may be stacked on the third-direction D3 with the first gate isolation structure 140. The gate contact trench 170_T may expose a portion of the first gate isolation structure 140.

[0136] The gate contact 170 can be formed by partially or completely filling the gate contact trench 170_T with a conductive material.

[0137] Reference Figure 15 and Figure 16 A second etch stop film 194 and a bonding layer 196 can be formed on the second interlayer insulating film 192.

[0138] A second etch stop film 194 may be formed on the second interlayer insulating film 192 and the gate contact 170. A bonding layer 196 may be formed on the second etch stop film 194. That is, the second etch stop film 194 and the bonding layer 196 may be sequentially stacked on the second interlayer insulating film 192.

[0139] Reference Figure 17 and Figure 18 A second substrate 200, a second lower pattern BP2, and a stacked structure S_ST can be formed on the bonding layer 196.

[0140] In some embodiments, a second substrate 200, a second underpattern BP2, and a stacked structure S_ST can be formed and disposed on a separate wafer. For example, the stacked structure S_ST, the second underpattern BP2, and the second substrate 200 can be formed on a carrier wafer. The carrier wafer is movable such that the second substrate 200 can be disposed on the bonding layer 196, and the second substrate 200 and the bonding layer 196 can be combined. However, the embodiments are not limited to the above. For example, the second substrate 200, the second underpattern BP1, and the stacked structure S_ST can be sequentially stacked on the bonding layer 196.

[0141] A portion of the stacked structure S_ST can be etched to form a second device isolation trench ST2. A second field insulating film 205 can be formed on the second device isolation trench ST2.

[0142] Reference Figure 19 and Figure 20 A connecting via trench 180_T can be formed on the second field insulating film 205, and a protective insulating film 212 can be formed on the stacked structure S_ST, the second field insulating film 205, and the connecting via trench 180_T.

[0143] Specifically, a portion of the second field insulating film 205 may be removed to form a connection via trench 180_T. The connection via trench 180_T may penetrate the second field insulating film 205, the second substrate 200, and the bonding layer 196, or extend into the second field insulating film 205, the second substrate 200, and the bonding layer 196. The connection via trench 180_T may expose a portion of the upper surface of the second etch stop film 194. The connection via trench 180_T may be stacked with the gate contact 170 on the third direction D3.

[0144] A protective insulating film 212 may be formed on the stacked structure S_ST, the second field insulating film 205, and the connecting via trench 180_T. The protective insulating film 212 may cover the upper surface of the stacked structure S_ST or be superimposed on the upper surface of the stacked structure S_ST. The protective insulating film 212 may cover the side and bottom surfaces of the connecting via trench 180_T or be superimposed on the side and bottom surfaces of the connecting via trench 180_T.

[0145] Reference Figure 21 and Figure 22 A gate sacrifice pattern 220_SC and a hard mask pattern 220_HM can be formed on the protective insulating film 212.

[0146] Specifically, polysilicon can be formed on the stacked structure S_ST. Furthermore, using a hard mask pattern 220_HM as a mask, the polysilicon can be patterned to form a gate sacrifice pattern 220_SC. The hard mask pattern 220_HM on the gate sacrifice pattern 220_SC may not be removed. The gate sacrifice pattern 220_SC may extend in the second direction D2. The gate sacrifice pattern 220_SC may intersect with the stacked structure S_ST. The gate sacrifice pattern 220_SC may cover a portion of the protective insulating film 212 or be stacked with a portion of the protective insulating film 212.

[0147] Reference Figures 23 to 24 A second source / drain pattern 250, a third etch stop film 255, and a third interlayer insulating film 260 can be formed on the second substrate 200.

[0148] Specifically, the stacked structure S_ST can be patterned using a hard mask pattern 220_HM as an etch mask. A portion of the protective insulating film 212 and a portion of the stacked structure S_ST can be removed to form an upper source / drain recess, and a second source / drain pattern 250 can be formed on the upper source / drain recess. A third etch stop film 255 and a third interlayer insulating film 260 can be formed on the second source / drain pattern 250.

[0149] The remaining portion of the protective insulating film 212 and the hard mask pattern 220_HM can be removed to expose the gate sacrificial pattern 220_SC. The gate sacrificial pattern 220_SC and the sacrificial semiconductor layer SCL can be removed to form the gate electrode trench 220_T. Additionally, the sacrificial semiconductor layer SCL can be removed to form the second active pattern AP2.

[0150] Reference Figure 25 and Figure 26 A second gate insulating film 230 may be formed inside the gate electrode trench 220_T and on the second pattern NS2, the second gate spacer 245 and the connecting via trench 180_T.

[0151] Specifically, a second gate insulating film 230 can be formed along the sidewalls and bottom surface of the connection via trench 180_T. For example, the second gate insulating film 230 can be formed using an atomic layer deposition (ALD) process. The second gate insulating film 230 disposed on the bottom surface of the connection via trench 180_T can be removed by an etching process. A portion of the second gate insulating film 230 and the second etch stop film 194 can be removed to increase the depth of the connection via trench 180_T. As a result, the connection via trench 180_T exposes the upper surface of the gate contact 170.

[0152] Reference Figure 27 and Figure 28 It can form a connection via 180, a second gate electrode 220, and a second gate cover pattern 265.

[0153] Specifically, a connection via 180 may be formed to connect to the gate contact 170. A second gate electrode 220 may be formed on the connection via 180. The connection via 180 can electrically connect the second gate electrode 220 and the gate contact 170. The second gate electrode 220 may extend around or around the second pattern NS2. A second gate cap pattern 265 may be formed on the second gate electrode 220.

[0154] In the process of forming a wiring structure for electrically connecting the first gate electrode 120 and the second gate electrode 220, the electrical characteristics of the semiconductor device may be degraded. For example, in the process of forming a through-hole that penetrates the second gate electrode 220 or extends into the second gate electrode 220 and connects to the first gate electrode 120, the second active pattern AP2 may be damaged and the electrical characteristics of the semiconductor device may be degraded.

[0155] According to some embodiments, the semiconductor device includes a connection via 180 formed on a gate contact 170 and a second gate electrode 220 formed on the connection via 180. The second active pattern AP2 is not damaged during the process of forming the connection via 180, thus improving the electrical characteristics and reliability of the semiconductor device.

[0156] Reference Figure 3 It can further form a second gate isolation structure 240 that penetrates the second gate electrode 220 or extends into the second gate electrode 220.

[0157] Although specific embodiments of this disclosure have been described with reference to the accompanying drawings, it will be understood by those skilled in the art to which this disclosure pertains that this disclosure may be implemented in other specific forms without altering its technical concept or features. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive.

Claims

1. A semiconductor device comprising: a first substrate; a first active pattern on the first substrate and extending in a first direction; a first gate electrode on the first active pattern and extending in a second direction different from the first direction; a gate cap pattern on the first gate electrode; a gate contact extending into the gate cap pattern and electrically connected to the first gate electrode; a bonding layer on the gate cap pattern; a second substrate on the bonding layer; a second active pattern on the second substrate and extending in the first direction, wherein the second active pattern includes a lower pattern and a sheet pattern on the lower pattern; a second gate electrode on the second active pattern and extending in the second direction; and a connection via on the gate contact and electrically connected to each of the gate contact and the second gate electrode, wherein the connection via extends into the second substrate.

2. The semiconductor device according to claim 1, wherein The connection via is spaced apart from the lower pattern in the second direction.

3. The semiconductor device according to claim 1, wherein The connection via is not superposed on the sheet pattern in a third direction perpendicular to an upper surface of the second substrate.

4. The semiconductor device according to claim 1, further comprising: an interlayer insulating film between the bonding layer and the gate cap pattern, wherein the gate contact extends into the interlayer insulating film.

5. The semiconductor device according to claim 4, further comprising: an etching stop film between the interlayer insulating film and the bonding layer, wherein the connection via extends into the etching stop film.

6. The semiconductor device according to claim 1, further comprising: a device isolation trench defined by the upper surface of the second substrate and a side surface of the lower pattern, wherein a portion of the connection via is in the device isolation trench.

7. The semiconductor device according to claim 6, further comprising: a device isolation film on the device isolation trench, wherein the device isolation film surrounds the portion of the connection via.

8. The semiconductor device according to claim 1, further comprising: a gate insulating film between the second active pattern and the second gate electrode, wherein a portion of the gate insulating film is on a side surface of the connection via.

9. The semiconductor device according to claim 1, wherein The second gate electrode and the connection via include the same material.

10. The semiconductor device according to claim 1, wherein The gate contact includes a barrier layer and a fill layer on the barrier layer.

11. The semiconductor device according to claim 1, further comprising: a first gate isolation structure on a side wall of the first gate electrode and extending in the first direction, wherein a portion of the gate contact is in contact with the first gate isolation structure.

12. The semiconductor device according to claim 1, wherein The first gate electrode and the second gate electrode include different materials.

13. A semiconductor device comprising: a first substrate; a first active pattern on the first substrate and extending in a first direction; a first gate electrode on the first active pattern and extending in a second direction different from the first direction; a first gate isolation structure on a side wall of the first gate electrode and extending in the first direction; a gate contact on the first gate electrode; a second substrate on the gate contact; a second active pattern on the second substrate and extending in the first direction, wherein the second active pattern includes a lower pattern and a sheet pattern on the lower pattern; a second gate electrode on the second active pattern and extending in the second direction; and a connection via on the gate contact and electrically connected to each of the gate contact and the second gate electrode; and a second gate isolation structure on a sidewall of the second gate electrode and extending in the first direction, wherein the connection via is spaced apart from the lower pattern in the second direction.

14. The semiconductor device according to claim 13, wherein A distance from the upper surface of the second base to a lower surface of the second gate isolation structure is less than a distance from the upper surface of the second base to an upper surface of the connection via.

15. The semiconductor device according to claim 13, wherein A portion of the gate contact is superposed with the first gate isolation structure in a third direction, and wherein the third direction is perpendicular to the upper surface of the second base.

16. The semiconductor device of claim 13, further comprising: a gate insulating film between the second active pattern and the second gate electrode, wherein a portion of the gate insulating film is on a side surface of the connection via.

17. The semiconductor device according to claim 13, wherein the gate contact is spaced apart from the first gate isolation structure in the second direction, and wherein the connection via is spaced apart from the second gate isolation structure in the second direction.

18. The semiconductor device of claim 13, further comprising: a first source / drain pattern on at least one side of the first gate electrode; and a second source / drain pattern on at least one side of the second gate electrode, wherein the first source / drain pattern and the second source / drain pattern comprise different conductive types.

19. The semiconductor device of claim 18, further comprising: an inner gate spacer between the second source / drain pattern and the second gate electrode.

20. A semiconductor device, comprising: a first base; a first active pattern on the first base and extending in a first direction, wherein the first active pattern comprises a first lower pattern and a first sheet pattern on the first lower pattern; a first gate electrode on the first active pattern and extending in a second direction different from the first direction; a gate cap pattern on the first gate electrode; a first gate isolation structure extending into the gate cap pattern and the first gate electrode and extending in the first direction; an interlayer insulating film, a contact etching stop film, and a bonding layer on the gate cap pattern; a gate contact on the first gate electrode and extending into the gate cap pattern and the interlayer insulating film; a second base on the bonding layer; a second active pattern on the second base and extending in the first direction, wherein the second active pattern comprises a second lower pattern and a second sheet pattern on the second lower pattern; a second gate electrode on the second active pattern and extending in the second direction; a connection via on the gate contact and electrically connected to each of the gate contact and the second gate electrode; and a second gate isolation structure on a sidewall of the second gate electrode and extending in the first direction, wherein the connection via extends into the second base and the connection via is spaced apart from the second lower pattern in the second direction. ​

Images