Multipath input voltage adjustable constant current topology circuit with power-on sequence

Abstract

The invention discloses a multi-path input voltage adjustable constant-current topology circuit with a power-on sequence. The multi-path input voltage adjustable constant-current topology circuit comprises a multi-path input voltage topology circuit and an adjustable constant-current topology circuit, the multi-path input voltage topology circuit comprises a first input voltage topology circuit to an Mth input voltage topology circuit; the input end of the Kth input voltage topology circuit is connected with the Kth power supply end and the (K-1) th power supply end, and the output end of the Kth input voltage topology circuit is the input end of the adjustable constant-current topology circuit and is used for supplying power to the adjustable constant-current topology circuit; the output end of the adjustable constant current topology circuit is connected with a load and is used for providing a constant current source for the load; when power is supplied to the first input voltage topological circuit to the Mth input voltage topological circuit at the same time, if the first input voltage topological circuit is selected to supply power to the constant current regulating topological circuit, the multiple input voltage topological circuits except the first input voltage topological circuit in the multiple input voltage topological circuits are all in an open-circuit state. The power-on sequence is clear, and the power-on loss can be reduced.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of circuits, in particular to a multi-input voltage adjustable constant current topology circuit with power-on sequence. BACKGROUND

[0002] The prior art adopts a multi-selection chip to realize multi-input, and the multi-selection is limited. If the required multi-input is greater than the selectable channel of the single chip, another chip needs to be purchased to build a circuit. Most of the selected channels work normally, but the unselected channels are in the power-on state for a long time, which causes power-on loss and increases the risk of the circuit. SUMMARY

[0003] In view of this, the application provides a multi-input voltage adjustable constant current topology circuit with power-on sequence.

[0004] The application discloses a multi-input voltage adjustable constant current topology circuit with power-on sequence, which comprises a multi-input voltage topology circuit and an adjustable constant current topology circuit. The multi-input voltage topology circuit comprises a first input voltage topology circuit to an Mth input voltage topology circuit. The input end of the Kth input voltage topology circuit is connected with the Kth power supply end and the K-1th power supply end, and the output end is the input end of the adjustable constant current topology circuit, which is used for supplying power to the adjustable constant current topology circuit. The output end of the adjustable constant current topology circuit is connected with a load, which is used for providing a constant current source for the load. The value range of K is 1 to M. K is a positive integer greater than 1. When the first input voltage topology circuit to the Mth input voltage topology circuit are simultaneously powered, if the first input voltage topology circuit is selected to supply power to the adjustable constant current topology circuit, then a plurality of input voltage topology circuits in the multi-input voltage topology circuit, except the first input voltage topology circuit, are in an open circuit state.

[0005] Further, the first input voltage topology circuit comprises a first resistor, a second resistor, a first light-emitting diode, a first NMOS tube, a fifth voltage stabilizing diode, a sixth voltage stabilizing diode and a third PMOS tube. One end of the first resistor, one end of the second resistor, the cathode of the fifth voltage stabilizing diode, the cathode of the sixth voltage stabilizing diode and the source of the third PMOS tube are connected with the first power supply end. The other end of the first resistor is connected with the gate of the first NMOS tube through the first light-emitting diode. The other end of the second resistor and the anode of the fifth voltage stabilizing diode are grounded through the drain and source of the first NMOS tube in sequence. The anode of the sixth voltage stabilizing diode is grounded through the drain and source of the sixth PMOS tube in the second input voltage topology circuit and the drain and source of the second NMOS tube in sequence.

[0006] Further, the second input voltage topology circuit comprises a third resistor, a second light emitting diode, a second NMOS tube, a fourth resistor, a fifth PMOS tube, a sixth PMOS tube, an eleventh resistor, a relay, a fourth light emitting diode and a first capacitor; In the second input voltage topology circuit, one end of the third resistor, one end of the fourth resistor and the source of the fifth PMOS tube are connected with the second power supply end; the other end of the third resistor is connected with the first wiring end of the relay through the second light emitting diode; the other end of the fourth resistor is grounded through the drain and the source of the second NMOS tube; the gate of the fifth PMOS tube is connected with the other end of the fourth resistor through the drain and the source of the sixth PMOS tube; the gate of the second NMOS tube is connected with the second wiring end of the relay; the anode of the fourth light emitting diode is connected with the first power supply end, and the cathode is connected with the first terminal of the coil of the relay; one end of the first capacitor is connected with the first power supply end, and the other end is connected with the second terminal of the coil of the relay; the second terminal of the coil of the relay is grounded.

[0007] Further, the circuit structures and working principles of the second input voltage topology circuit to the Mth input voltage topology circuit are the same; the output end of the second input voltage topology circuit is the drain of the fifth PMOS tube and the drain of the sixth PMOS tube; the drain of the fifth PMOS tube is connected with the source of the third PMOS tube, and the drain of the sixth PMOS tube is connected with the gate of the third PMOS tube; the connection relationship between the output ends of the third input voltage topology circuit to the Mth input voltage topology circuit and the third PMOS tube is the same as that between the output end of the second input voltage topology circuit and the third PMOS tube.

[0008] Further, when the first input voltage topology circuit to the Mth input voltage topology circuit are powered at the same time, the first input voltage topology circuit works normally; the relay in the second input voltage topology circuit is powered on, and a pulling force is generated on the first wiring end and the second wiring end thereof, so that the first wiring end and the second wiring end are disconnected, resulting in that the second power supply end cannot supply power to the gate of the second NMOS tube, and then the fifth PMOS tube and the sixth PMOS tube are in an open circuit state, i.e. cannot provide a gate voltage for the third PMOS tube and cannot supply power to the input end of the adjustable constant current topology circuit.

[0009] Further, the fifth voltage stabilizing diode and the sixth voltage stabilizing diode are connected in parallel between the first power supply end and the ground end, so as to protect the voltage drop difference between the gate and the source of the third PMOS tube from exceeding the specified maximum withstand voltage.

[0010] Further, the adjustable constant current topology circuit comprises a fifth resistor, a third light emitting diode, a second capacitor, a third capacitor, a sixth resistor, a fourth voltage stabilizing diode, a potentiometer, an operational amplifier, a fourth NMOS tube and an eighth resistor. The fifth resistor and the third LED are connected in series between the output terminal and the ground terminal of the multi-input voltage topology circuit; the second capacitor and the third capacitor are connected in parallel between the output terminal and the ground terminal of the multi-input voltage topology circuit; the sixth resistor and the fourth Zener diode are connected in series between the output terminal and the ground terminal of the multi-input voltage topology circuit; the potentiometer is connected in parallel with the fourth Zener diode; the non-inverting input terminal of the operational amplifier is connected to the sliding terminal of the potentiometer, the inverting input terminal is grounded through the eighth resistor, the output terminal is connected to the gate of the fourth NMOS transistor, and the power supply terminal is connected to the zeroth power supply terminal; the drain of the fourth NMOS transistor and the output terminal of the multi-input voltage topology circuit are connected across the load to provide a constant current to the load; the source of the fourth NMOS transistor is grounded through the eighth resistor.

[0011] Furthermore, the zeroth power supply terminal is connected to the output terminal of the multi-input voltage topology circuit, or the output terminal of the multi-input voltage topology circuit is connected to the zeroth power supply terminal after voltage division.

[0012] Furthermore, the third LED indicates whether the circuit containing the fifth resistor is energized; If the adjustable constant current topology circuit is working normally, the third LED will be constantly lit; if the third LED is not lit, check if the third PMOS transistor is working normally. If the third PMOS transistor is normal, then check whether the components connected to the third PMOS transistor are faulty.

[0013] Furthermore, when the value of the eighth resistor is fixed, an adjustable constant current can be achieved by adjusting the resistance of the potentiometer.

[0014] Due to the adoption of the above technical solution, this application has the following advantages: 1. Multiple input voltages with a clearly defined power-on sequence; 2. Apart from the selected path working normally, the other paths are powered on but consume no additional energy; 3. It features constant current output and adjustable constant current value; 4. LEDs can be used to visually locate malfunctioning links, shortening the troubleshooting cycle; 5. This application mainly consists of MOSFETs, capacitors, resistors, diodes, and operational amplifiers, and can be gradually miniaturized and integrated. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0016] Figure 1 This is a schematic diagram of a multi-channel input voltage adjustable constant current topology circuit with power-on sequence according to an embodiment of this application; Figure 2 This is a schematic diagram of a multi-input voltage topology circuit according to an embodiment of this application; Figure 3 A schematic diagram of the equivalent circuit topology of the multi-input voltage topology circuit when VCC1 and VCC2 are powered simultaneously in an embodiment of this application. Figure 4 This is a schematic diagram of the adjustable constant current topology circuit according to an embodiment of this application; Figure 5 This is a schematic diagram of a 3-channel adjustable constant current topology circuit with power-on sequence according to an embodiment of this application. Detailed Implementation

[0017] The present application will be further described in conjunction with the accompanying drawings and embodiments. The described embodiments are only some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of the present application.

[0018] See Figure 1 This application provides an embodiment of a multi-input voltage adjustable constant current topology circuit with a power-on sequence, which includes a multi-input voltage topology circuit and an adjustable constant current topology circuit; the multi-input voltage topology circuit includes a first input voltage topology circuit to an Mth input voltage topology circuit; the input terminal of the Kth input voltage topology circuit is connected to the Kth power supply terminal and the (K-1)th power supply terminal, and the output terminal is the input terminal of the adjustable constant current topology circuit, used to power the adjustable constant current topology circuit; the output terminal of the adjustable constant current topology circuit is connected to the load RL, used to provide a constant current source for the load RL; the value range of K is 1 to M; K is a positive integer greater than 1; when the first input voltage topology circuit to the Mth input voltage topology circuit are powered simultaneously, if the first input voltage topology circuit is selected to power the adjustable constant current topology circuit, then the several input voltage topologies circuits other than the first input voltage topology circuit in the multi-input voltage topology circuit are all in an open circuit state.

[0019] Optionally, the first input voltage topology circuit includes a first resistor R1, a second resistor R2, a first light-emitting diode D1, a first NMOS transistor Q1, a fifth Zener diode D5, a sixth Zener diode D6, and a third PMOS transistor Q3; One end of the first resistor R1, one end of the second resistor R2, the cathode of the fifth Zener diode D5, the cathode of the sixth Zener diode D6, and the source of the third PMOS transistor Q3 are all connected to the first power supply terminal VCC1; the other end of the first resistor R1 is connected to the gate of the first NMOS transistor Q1 through the first light-emitting diode D1; the other end of the second resistor R2 and the anode of the fifth Zener diode D5 are grounded sequentially through the drain and source of the first NMOS transistor Q1; the anode of the sixth Zener diode D6 is grounded sequentially through the drain and source of the sixth PMOS transistor Q6 in the second input voltage topology circuit, and the drain and source of the second NMOS transistor Q2.

[0020] Optionally, the second input voltage topology circuit includes a third resistor R3, a second light-emitting diode D2, a second NMOS transistor Q2, a fourth resistor R4, a fifth PMOS transistor Q5, a sixth PMOS transistor Q6, an eleventh resistor R11, a relay J1, a fourth light-emitting diode D4, and a first capacitor C1. In the second input voltage topology circuit, one end of the third resistor R3, one end of the fourth resistor R4, and the source of the fifth PMOS transistor Q5 are all connected to the second power supply terminal VCC2; the other end of the third resistor R3 is connected to the first terminal of the relay J1 through the second light-emitting diode D2; the other end of the fourth resistor R4 is grounded through the drain and source of the second NMOS transistor Q2; the gate of the fifth PMOS transistor Q5 and the drain and source of the sixth PMOS transistor Q6 are connected to the other end of the fourth resistor R4; the gate of the second NMOS transistor Q2 is connected to the second terminal of the relay J1; the anode of the fourth light-emitting diode D4 is connected to the first power supply terminal VCC1, and the cathode is connected to the first terminal of the coil of the relay J1; one end of the first capacitor C1 is connected to the first power supply terminal VCC1, and the other end is connected to the second terminal of the coil of the relay J1; the second terminal of the coil of the relay J1 is grounded.

[0021] Optionally, the circuit structure and operating principle of the second input voltage topology circuit to the Mth input voltage topology circuit are the same; the output terminal of the second input voltage topology circuit is the drain of the fifth PMOS transistor Q5 and the drain of the sixth PMOS transistor Q6; the drain of the fifth PMOS transistor Q5 is connected to the source of the third PMOS transistor Q3, and the drain of the sixth PMOS transistor Q6 is connected to the gate of the third PMOS transistor Q3; the connection relationship between the output terminal of the third input voltage topology circuit to the Mth input voltage topology circuit and the third PMOS transistor Q3 is the same as the connection relationship between the output terminal of the second input voltage topology circuit and the third PMOS transistor Q3.

[0022] Optionally, when the first input voltage topology circuit to the Mth input voltage topology circuit are powered simultaneously, the first input voltage topology circuit operates normally; the relay J1 in the second input voltage topology circuit is energized, which pulls on its first and second terminals, causing the first and second terminals to disconnect, resulting in the second power supply terminal VCC2 being unable to supply power to the gate of the second NMOS transistor Q2. Consequently, the fifth PMOS transistor Q5 and the sixth PMOS transistor Q6 are in an open circuit state, that is, they cannot provide gate voltage to the third PMOS transistor Q3, and cannot supply power to the input terminal of the adjustable constant current topology circuit.

[0023] Optionally, the fifth Zener diode D5 and the sixth Zener diode D6 are connected in parallel to the first power supply terminal VCC1 and the ground terminal to protect the voltage drop difference between the gate and source of the third PMOS transistor Q3 from exceeding the specified maximum withstand voltage.

[0024] Optionally, the adjustable constant current topology circuit includes a fifth resistor R5, a third light-emitting diode D3, a second capacitor C2, a third capacitor C3, a sixth resistor R6, a fourth Zener diode D04, a potentiometer R7, an operational amplifier U1, a fourth NMOS transistor Q4, and an eighth resistor R8. The fifth resistor R5 and the third LED D3 are connected in series between the output terminal VDD1 of the multi-input voltage topology and the ground terminal; the second capacitor C2 and the third capacitor C3 are connected in parallel between the output terminal VDD1 of the multi-input voltage topology and the ground terminal; the sixth resistor R6 and the fourth Zener diode D04 are connected in series between the output terminal VDD1 of the multi-input voltage topology and the ground terminal; the potentiometer R7 is connected in parallel with the fourth Zener diode D04; the non-inverting input terminal of the operational amplifier U1 is connected to the sliding terminal of the potentiometer R7, the inverting input terminal is grounded through the eighth resistor R8, the output terminal is connected to the gate of the fourth NMOS transistor Q4, and the power supply terminal is connected to the zero-supply terminal VDD2; the drain of the fourth NMOS transistor Q4 and the output terminal VDD1 of the multi-input voltage topology are connected across the load RL to provide a constant current to the load RL; the source of the fourth NMOS transistor Q4 is grounded through the eighth resistor R8.

[0025] Optionally, the zero power supply terminal VDD2 is connected to the output terminal VDD1 of the multi-input voltage topology circuit, or the output terminal VDD1 of the multi-input voltage topology circuit is connected to the zero power supply terminal VDD2 after voltage division; for example, VDD1 is grounded through the ninth and tenth resistors connected in series, and the common terminal of the ninth and tenth resistors is connected to the zero power supply terminal VDD2.

[0026] Optionally, the third light-emitting diode D3 indicates whether the circuit containing the fifth resistor R5 is energized; If the adjustable constant current topology circuit is working normally, the third LED D3 will be constantly lit; if the third LED D3 is not lit, check if the third PMOS transistor Q3 is working normally. If the third PMOS transistor Q3 is normal, then check whether the components connected to the third PMOS transistor Q3 are faulty.

[0027] Optionally, when the value of the eighth resistor R8 is fixed, an adjustable constant current can be output by adjusting the resistance value of potentiometer R7.

[0028] In the above embodiments, when VCC1 and VCC2 are connected individually, the entire circuit can operate normally. In the first circuit topology (input voltage topology), if VCC1 and VCC2 are powered simultaneously, only VCC1 is effective for the entire circuit. At this time, VCC2 cannot turn on the electronic switch and cannot power the second circuit topology. Immediately after disconnecting VCC1, VCC2 takes over and starts working, powering the second circuit topology. The second circuit topology (adjustable constant current topology) is powered by VDD1 and VDD2. VDD2 is the power supply terminal for the operational amplifier. Depending on the required input range, the power supply may be directly provided by VDD1 or divided from VDD1 to provide power to VDD2.

[0029] The first part is the circuit topology, such as Figure 2 As shown. VCC1 supplies power to the gate of the first NMOS transistor Q1 through the first resistor R1 and the first LED D1, and simultaneously supplies power to the drain of the first NMOS transistor Q1 through the second resistor R2. Q1 operates normally, outputting C. VCC2 supplies power to the gate of the second NMOS transistor Q2 through the third resistor R3, the second LED D2, and the switch terminal of relay J1 (open when energized, closed when not energized), and simultaneously supplies power to the drain of Q2 through the fourth resistor R4. Q2 operates normally, outputting D. VCC1 and VCC2 converge at point F, simultaneously supplying power to the source of the third PMOS transistor Q3. The output C of Q1 and the output D of Q2 simultaneously supply power to the gate of Q3. The fifth Zener diode D5 and the sixth Zener diode D6 are connected in parallel between the output C and the convergence point F and between the output D and the convergence point F, respectively, to protect the source-gate voltage drop of Q3 from exceeding the maximum withstand voltage specified in the PMOS transistor datasheet.

[0030] The third PMOS transistor, Q3, is an electronic switch. When VCC1 is the only power supply, both the source and gate of Q3 are energized, creating a voltage drop difference. This turns on the channel of Q3, meaning VCC1 conducts from the source (S) to the drain (D) of Q3, outputting VDD1 to power the second part of the circuit topology. When VCC2 is powered alone, Q5 and Q6 conduct, and both the source and gate of Q3 are energized, creating a voltage drop difference. This turns on the channel of Q3, meaning VCC2 conducts from the source (S) to the drain (D) of Q3, outputting VDD1 to power the second part of the circuit topology. When VCC1 and VCC2 are powered simultaneously, VCC1 powers the flux terminals (the first and second terminals of the coil) of relay J1, causing a pulling force between the flux terminals and the terminals, forcing the terminals to disconnect. This prevents VCC2 from powering the gate of Q2, resulting in Q2 being open-circuited and having no output. Q5 and Q6 also have no gate voltage, making them open-circuited. Therefore, VCC2 cannot output E through Q5, nor can it output D through Q6 via resistor R4, causing the VCC2 link to disconnect from Q3. Figure 3 As shown. Therefore, the power-on sequence when VCC1 and VCC2 are powered simultaneously is achieved. Observe. Figure 2 The first part of the circuit topology states that when VCC1 and VCC2 are working simultaneously, the VCC2 link has no connection to the first part of the circuit topology, making VCC2 an open circuit and effectively reducing circuit losses.

[0031] The first LED D1 and the second LED D2 indicate the power-on path, and the fourth LED D4 indicates that the relay J1 is working.

[0032] The circuit topology for the second part is as follows: Figure 4 As shown, VDD1 is functionally divided into three links: the first link supplies power to the third LED D3 via the fifth resistor R5; the second link, via the sixth resistor R6, the parallel circuit of the fourth Zener diode D04 and potentiometer R7, provides a positive input signal to the operational amplifier U1; the third link, via the load RL (between... Figure 4 The area between points A and B is the drain power supply for the fourth NMOS transistor Q4. The eighth resistor R8 is the negative feedback resistor for operational amplifier U1. VDD2 can be obtained by voltage division of VDD1, depending on whether the value of VDD1 exceeds the maximum power supply range of the operational amplifier. If VDD1 is small, there is no need for voltage division, and VDD1 can be used directly.

[0033] Adjustable constant current topology bypass analysis: LED D3 indicates that VDD1 is powered on. In this second part of the adjustable constant current topology, regardless of which input voltage channel is selected in the first part, D3 will always be lit during normal operation. If D3 is not lit, check whether the electronic switch Q3 is working properly, and then troubleshoot step by step to clarify the fault location. C2 and C3 generally refer to high frequency and low frequency filter capacitors, and can be a set of capacitors. For example, C2 can be multiple 220uF capacitors, and C3 can be multiple 1000pF capacitors.

[0034] Adjustable constant current topology adjustment principle analysis: The sixth resistor R6, potentiometer R7, and fourth Zener diode D04 combine to form the positive input voltage U+ of the operational amplifier. This voltage and the value of the eighth resistor R8 determine the magnitude of the constant current output. When R8 is fixed, moving potentiometer R7 achieves adjustable constant current output.

[0035] Analysis of the constant current principle of adjustable constant current topology: The positive and negative inputs of operational amplifier U1 are virtually shorted, i.e. Figure 4 In the equation, U+ = U-, the voltage at point H is U-, and for resistor R8, point G is connected to the ground of the first part, so the current I flowing through R8 is as shown in equation 3-1.

[0036] (3-1) When operational amplifier U1 is working normally, the output UO supplies power to the gate of Q4, and VDD1 supplies power to the drain of Q4, so Q4 is turned on. Figure 4 The medium current passes through points A and B, then through the channel of Q4 from the drain (D) to the source (S), and then through points H and G, forming a series circuit. The current I is provided by equation 3-1. The load is connected in series between points A and B and will not affect the output current, thus achieving constant current output.

[0037] The above analysis is based on Figure 1 Based on two input voltages with a power-on sequence, the first part of this circuit topology can achieve multi-path expansion, that is, by concatenating the entire VCC2 link below the VCC2 link, and changing VCC2 to VCC3 at one point, and changing VCC1 of the relay to VCC2. For example... Figure 5 As shown, the other multiple paths follow the same logic, and the analysis will not be repeated. With this topology, the power-on sequence of VCC1→VCC2→VCC3→……→VCCn (n is the number of paths) can be achieved.

[0038] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and not to limit them. Although this application has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of this application. Any modifications or equivalent substitutions that do not depart from the spirit and scope of this application should be covered within the protection scope of the claims of this application.

Claims

1. A multi-channel input voltage adjustable constant current topology circuit with power-on sequence, characterized in that, It includes a multi-input voltage topology circuit and an adjustable constant current topology circuit; the multi-input voltage topology circuit includes a first input voltage topology circuit to the Mth input voltage topology circuit; the input terminal of the Kth input voltage topology circuit is connected to the Kth power supply terminal and the (K-1)th power supply terminal, and the output terminal is the input terminal of the adjustable constant current topology circuit, used to power the adjustable constant current topology circuit; the output terminal of the adjustable constant current topology circuit is connected to the load, used to provide a constant current source for the load; the value of K ranges from 1 to M; K is a positive integer greater than 1; when the first input voltage topology circuit to the Mth input voltage topology circuit are powered simultaneously, if the first input voltage topology circuit is selected to power the adjustable constant current topology circuit, then the input voltage topology circuits other than the first input voltage topology circuit in the multi-input voltage topology circuit are all in an open circuit state.

2. The multi-input voltage adjustable constant current topology circuit with power-on sequence according to claim 1, characterized in that, The first input voltage topology circuit includes a first resistor, a second resistor, a first light-emitting diode, a first NMOS transistor, a fifth Zener diode, a sixth Zener diode, and a third PMOS transistor; One end of the first resistor, one end of the second resistor, the cathode of the fifth Zener diode, the cathode of the sixth Zener diode, and the source of the third PMOS transistor are all connected to the first power supply terminal; the other end of the first resistor is connected to the gate of the first NMOS transistor through the first light-emitting diode; the other end of the second resistor and the anode of the fifth Zener diode are grounded sequentially through the drain and source of the first NMOS transistor; the anode of the sixth Zener diode is grounded sequentially through the drain and source of the sixth PMOS transistor and the drain and source of the second NMOS transistor in the second input voltage topology circuit.

3. The multi-input voltage adjustable constant current topology circuit with power-on sequence according to claim 2, characterized in that, The second input voltage topology circuit includes a third resistor, a second light-emitting diode, a second NMOS transistor, a fourth resistor, a fifth PMOS transistor, a sixth PMOS transistor, an eleventh resistor, a relay, a fourth light-emitting diode, and a first capacitor; In the second input voltage topology circuit, one end of the third resistor, one end of the fourth resistor, and the source of the fifth PMOS transistor are all connected to the second power supply terminal; the other end of the third resistor is connected to the first terminal of the relay through the second light-emitting diode; the other end of the fourth resistor is grounded through the drain and source of the second NMOS transistor. The gate of the fifth PMOS transistor and the other end of the fourth resistor are connected through the drain and source of the sixth PMOS transistor; the gate of the second NMOS transistor is connected to the second terminal of the relay; the anode of the fourth light-emitting diode is connected to the first power supply terminal, and the cathode is connected to the first terminal of the relay coil; one end of the first capacitor is connected to the first power supply terminal, and the other end is connected to the second terminal of the relay coil; the second terminal of the relay coil is grounded.

4. The multi-input voltage adjustable constant current topology circuit with power-on sequence according to any one of claims 1-3, characterized in that, The circuit structure and working principle of the second input voltage topology circuit to the Mth input voltage topology circuit are the same; the output terminal of the second input voltage topology circuit is the drain of the fifth PMOS transistor and the drain of the sixth PMOS transistor; the drain of the fifth PMOS transistor is connected to the source of the third PMOS transistor, and the drain of the sixth PMOS transistor is connected to the gate of the third PMOS transistor; the connection relationship between the output terminal of the third input voltage topology circuit to the Mth input voltage topology circuit and the third PMOS transistor is the same as the connection relationship between the output terminal of the second input voltage topology circuit and the third PMOS transistor.

5. The multi-input voltage adjustable constant current topology circuit with power-on sequence according to claim 3, characterized in that, When the first input voltage topology circuit to the Mth input voltage topology circuit are powered simultaneously, the first input voltage topology circuit works normally. When the relay in the second input voltage topology circuit is energized, it exerts a pulling force on its first and second terminals, causing the first and second terminals to disconnect. This results in the second power supply terminal being unable to supply power to the gate of the second NMOS transistor. Consequently, the fifth and sixth PMOS transistors are in an open-circuit state, meaning they cannot provide gate voltage to the third PMOS transistor and cannot supply power to the input terminal of the adjustable constant current topology circuit.

6. The multi-input voltage adjustable constant current topology circuit with power-on sequence according to claim 2, characterized in that, The fifth and sixth Zener diodes are connected in parallel to the first power supply terminal and the ground terminal to protect the voltage drop difference between the gate and source of the third PMOS transistor from exceeding the specified maximum withstand voltage.

7. The multi-input voltage adjustable constant current topology circuit with power-on sequence according to claim 1, characterized in that, The adjustable constant current topology circuit includes a fifth resistor, a third light-emitting diode, a second capacitor, a third capacitor, a sixth resistor, a fourth Zener diode, a potentiometer, an operational amplifier, a fourth NMOS transistor, and an eighth resistor. The fifth resistor and the third LED are connected in series between the output terminal and the ground terminal of the multi-input voltage topology circuit; the second capacitor and the third capacitor are connected in parallel between the output terminal and the ground terminal of the multi-input voltage topology circuit; the sixth resistor and the fourth Zener diode are connected in series between the output terminal and the ground terminal of the multi-input voltage topology circuit; the potentiometer is connected in parallel with the fourth Zener diode; the non-inverting input terminal of the operational amplifier is connected to the sliding terminal of the potentiometer, the inverting input terminal is grounded through the eighth resistor, the output terminal is connected to the gate of the fourth NMOS transistor, and the power supply terminal is connected to the zeroth power supply terminal; the drain of the fourth NMOS transistor and the output terminal of the multi-input voltage topology circuit are connected across the load to provide a constant current to the load; the source of the fourth NMOS transistor is grounded through the eighth resistor.

8. The multi-input voltage adjustable constant current topology circuit with power-on sequence according to claim 7, characterized in that, The zero power supply terminal is connected to the output terminal of the multi-input voltage topology circuit, or the output terminal of the multi-input voltage topology circuit is divided and then connected to the zero power supply terminal.

9. The multi-input voltage adjustable constant current topology circuit with power-on sequence according to claim 7, characterized in that, The third LED indicates whether the circuit containing the fifth resistor is energized; If the adjustable constant current topology circuit is working normally, the third LED will be constantly lit; if the third LED is not lit, check if the third PMOS transistor is working normally. If the third PMOS transistor is normal, then check whether the components connected to the third PMOS transistor are faulty.

10. The multi-input voltage adjustable constant current topology circuit with power-on sequence according to claim 7, characterized in that, When the value of the eighth resistor is fixed, an adjustable constant current can be achieved by adjusting the resistance of the potentiometer.

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