Data storage method of gddr memory, gpu, device and medium

Abstract

The application discloses a data storage method of GDDR memory, a GPU, a device and a medium, and is applied to the field of data storage. The method comprises the following steps: in the process of storing compressed data by using the GDDR memory, if it is detected that the utilization rate of the row storage unit meets the optimization condition, the address remapping function is triggered to be started; after the address remapping function is started, according to the compression rate of each piece of compressed data to be stored and the size of the column storage unit in the storage body, the effective data in each piece of compressed data is stored in the row storage unit of the storage body. The technical scheme of the embodiment of the application achieves the technical effect that each compressed data block in multiple pieces of compressed data is stored in the page to the maximum extent, the utilization rate of the page in the GDDR memory is improved, the time delay of the GPU accessing the GDDR memory is shortened, and the performance of the GDDR memory can be effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data storage, and in particular to a data storage method of GDDR memory, a GPU, a device and a medium. BACKGROUND

[0002] In the interaction scene of GPU (Graphics Processing Unit) and GDDR (Graphics Double Data Rate) memory, data compression technology is widely used to improve bandwidth utilization.

[0003] In the GDDR memory, a plurality of BG (Bank Group) are contained, and each BG further contains a plurality of banks (which can also be referred to as Bank). When compressed data needs to be stored in a certain bank, a row storage unit (which can also be referred to as a page) in the bank needs to be opened first, and then the compressed data blocks in the compressed data are stored in one or more column storage units under the page.

[0004] The inventor found in the process of implementing the present application that, in order to realize the aligned storage of data, the prior art needs to introduce a blank storage placeholder in the page, which will cause the discontinuous storage of the compressed data blocks in the page, reduce the utilization rate of the page, and further increase the latency of the GPU accessing the GDDR memory to a certain extent, thereby limiting the performance of the GDDR memory. SUMMARY

[0005] The embodiments of the present application provide a data storage method of GDDR memory, a GPU, a device and a medium to improve the utilization rate of the page in the GDDR memory and shorten the latency of the GPU accessing the GDDR memory.

[0006] According to an aspect of the embodiments of the present application, a data storage method of GDDR memory is provided, which is executed by a controller of the GDDR memory, the GDDR memory includes N1 bank groups, each bank group includes N2 banks, N1 and N2 are both integers greater than 2, and the method includes:

[0007] In the process of storing compressed data using the GDDR memory, if it is detected that the utilization rate of the row storage unit meets the optimization condition, the address remapping function is triggered to be opened;

[0008] After the address remapping function is opened, the valid data in each piece of compressed data is stored in the row storage unit of the bank according to the compression rate of each piece of compressed data to be stored and the size of the column storage unit in the bank.

[0009] According to another aspect of the embodiments of the present application, there is also provided a data storage apparatus of a GDDR memory, configured in a controller of the GDDR memory, the GDDR memory comprising N1 memory banks, each of the memory banks comprising N2 memory banks, N1 and N2 are integers greater than 2, the apparatus comprising:

[0010] an address remapping function enabling module, configured to, in a process of storing compressed data using the GDDR memory, if it is detected that a utilization rate of the row storage units meets an optimization condition, trigger enabling of an address remapping function;

[0011] an aggregated storage module, configured to, after the address remapping function is enabled, according to a compression rate of each piece of compressed data to be stored and a size of the column storage units in the memory banks, aggregate and store the valid data in each piece of compressed data in the row storage units of the memory banks.

[0012] According to another aspect of the embodiments of the present application, there is also provided a graphics processor, comprising: a GDDR memory and a controller of the GDDR memory, the GDDR memory comprising N1 memory banks, each of the memory banks comprising N2 memory banks, N1 and N2 are integers greater than 2, wherein:

[0013] the controller of the GDDR memory is configured to perform the data storage method of the GDDR memory according to any of the embodiments of the present application.

[0014] According to another aspect of the embodiments of the present application, there is also provided an electronic device, the electronic device comprising:

[0015] at least one graphics processor; and a memory connected in communication with the at least one graphics processor; wherein,

[0016] the memory stores a computer program executable by the at least one graphics processor, the computer program is executed by the at least one graphics processor to enable the at least one graphics processor to perform the data storage method of the GDDR memory according to any of the embodiments of the present application.

[0017] According to another aspect of the embodiments of the present application, there is also provided a computer readable storage medium, the computer readable storage medium storing computer instructions, the computer instructions being used to enable a graphics processor to perform the data storage method of the GDDR memory according to any of the embodiments of the present application when the graphics processor executes the computer instructions.

[0018] According to another aspect of the embodiments of the present application, there is also provided a computer program product, comprising a computer program, the computer program being executed by a graphics processor to implement the steps of the data storage method of the GDDR memory according to any of the embodiments of the present application.

[0019] The technical scheme of the embodiment of the present application, in the process of storing compressed data using the GDDR memory, if it is detected that the utilization rate of the row storage unit meets the optimization condition, the address remapping function is triggered to be started; after the address remapping function is started, according to the compression rate of each piece of compressed data to be stored and the size of the column storage unit in the memory bank, the effective data in each piece of compressed data is stored in the row storage unit of the memory bank in a gathering manner, when it is detected that the page in the GDDR memory appears discontinuous storage, the address remapping function is started in time to remap the physical address of each piece of compressed data, so as to effectively reduce the blank storage space in the page, achieve the technical effect that each piece of compressed data in multiple pieces of compressed data is stored in the page in a gathering manner to the maximum extent, improve the utilization rate of the page in the GDDR memory, shorten the time delay of the GPU accessing the GDDR memory, and effectively improve the performance of the GDDR memory.

[0020] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent through the following description. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical scheme in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0022] Figure 1 is a storage diagram of compressed data in a GDDR memory when the memory bank group rotation function is enabled in the prior art;

[0023] Figure 2 is another storage diagram of compressed data in a GDDR memory when the memory bank group rotation function is not enabled in the prior art;

[0024] Figure 3 is a flowchart of a data storage method of a GDDR memory according to the first embodiment of the present application;

[0025] Figure 4 is a flowchart of another data storage method of a GDDR memory according to the second embodiment of the present application;

[0026] Figure 5is a storage schematic of compressed data in a GDDR memory when the bank rotation function is enabled after the address remapping function of each embodiment of the present application is applied;

[0027] Figure 6 is a storage schematic of compressed data in a GDDR memory when the bank rotation function is not enabled after the address remapping function of each embodiment of the present application is applied;

[0028] Figure 7 is a contrast schematic of two kinds of address mapping relations when the bank rotation function is enabled before and after the address remapping function of each embodiment of the present application is applied;

[0029] Figure 8 is a contrast schematic of two kinds of address mapping relations when the bank rotation function is not enabled before and after the address remapping function of each embodiment of the present application is applied;

[0030] Figure 9 is a structural schematic of a data storage device of a GDDR memory according to the third embodiment of the present application;

[0031] Figure 10 is a structural schematic of a graphic processor according to the fourth embodiment of the present application;

[0032] Figure 11 is a structural schematic of an electronic device for implementing a data storage method of a GDDR memory of the present application. DETAILED DESCRIPTION

[0033] In order to make the personnel in the technical field better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the personnel in the field without creative labor should belong to the protection scope of the present application.

[0034] It is to be understood that the terms "first", "second", and the like, used in the description and the claims of the application, as well as the above-described drawings, are used to distinguish similar objects, and are not necessarily used to describe a particular sequential or chronological order. It should be understood that the data thus used can be interchanged, where appropriate, so that the embodiments of the application described herein can be carried out in other than the order shown or described herein. Furthermore, the terms "comprise" and "have", and any variations thereof, are intended to cover a non-exclusive inclusion, for example, a process, method, system, product, or apparatus that comprises a list of steps or units is not necessarily limited to those steps or units that are clearly listed, but can include other steps or units that are not clearly listed or inherent to such processes, methods, products, or apparatuses.

[0035] In order to more clearly describe the technical solutions of the embodiments of the application, the reasons why the utilization rate of pages is not high when the prior art uses GDDR memory to store compressed data will be simply analyzed as follows.

[0036] In the existing memory management mechanism, due to the limitation of the memory address access demand of the GDDR memory, the starting storage address of each piece of compressed data needs to be an integer multiple of the preset data length, so as to facilitate the access of data in the storage space, which is called data alignment. Further, the data size of each piece of compressed data is generally the bit number of the above-mentioned data alignment, which can also be called the compression granularity.

[0037] Taking a compression granularity of 2kbits as an example, the specific implementation logic of the existing compression scheme is as follows: the data compressor compresses each piece of 2kbits data to be stored into n compression data blocks of a set data block size and then writes the n compression data blocks into the GDDR memory; during the compression process, a compression threshold is set, if the total size of the compressed data exceeds the compression threshold, it is determined that the compression fails, and the original 2kbits data is directly written into the GDDR memory; otherwise, the n compression data blocks are stored.

[0038] Taking a data block size of 256bits as an example, the value range of n is 1 to 6 (including 1 and 6). It should be noted that although the physical storage space occupied by the 2kbits data in the GDDR memory after compression is often less than or equal to 2kbits, in order to meet the alignment constraint condition of 2kbits data, each compression data block in each piece of compressed data will still occupy 2kbits of storage space in the GDDR memory, and only the front effective data (such as the first 1kbits) in the 2kbits of storage space is operated in the actual read-write process.

[0039] Since each BG in GDDR memory can read and write data independently, in order to effectively improve the bandwidth utilization, the prior art often uses the memory bank group rotation (also known as Bank Group Rotate) function to realize the reading and writing of each piece of compressed data. When the above memory bank group rotation mechanism is applied to the reading and writing of compressed data, taking the example of compressing each 2kbits of data into 3 pieces of 256bits (compression ratio is 3:8) compressed data block stored in the GDDR memory, the first 256bits of compressed data block in each 2kbits of data will be stored in BA0 (also known as Bank0) of BG0, the second 256bits of compressed data block will be stored in BA0 of BG1, and the third 256bits of compressed data block will be stored in BA0 of BG0 again, and so on.

[0040] Among them, the bank can be understood as a two-dimensional storage array composed of row storage units (Row) and column storage units (Column). A bank activates a row storage unit (also known as a page) in the two-dimensional storage array for reading and writing operation at a time, and in the page, a large number of column storage units are contained, and each column storage unit is addressed in the corresponding row storage unit through column address. In fact, a compressed data block is finally stored in a specific column storage unit in a specific row storage unit in a specific bank.

[0041] Specifically, in Figure 1 a storage diagram of compressed data in the GDDR memory when the bank group rotation function is enabled is shown.

[0042] As Figure 1As shown, when the memory bank group rotation function is enabled, the compressed data blocks in each 2kbits data are alternately stored in page 0 of BA0 in BG0 and page 0 of BA0 in BG1. When the compression ratio of the first compressed data (1st 2kbits) is 4:8, it means that the first compressed data contains only four actually valid 256-bit compressed data blocks, namely d0-d3. The remaining d4-d7 are invalid data (also called grayed-out data), used to achieve 2kbits data alignment. Accordingly, d0, d2, d4, and d6 are stored in page 0 of BA0 in BG0, and d1, d3, d5, and d7 are stored in page 0 of BA0 in BG1. Obviously, the column storage cells where d4-d7 are located do not store valid data, but only serve as blank storage placeholders for data alignment. When the second batch of compressed data with a compression ratio of 4:8 (2nd 2kbits) arrives, it needs to skip the blank placeholders (d4-d7) from the first batch of compressed data before continuing storage. Therefore, while valid data within the same batch of compressed data (e.g., d0 and d2, d1 and d3) can be stored contiguously in one page, valid data from different batches of compressed data (e.g., d0 and d2 from the first batch versus d0 and d2 from the second batch) cannot be stored contiguously in one page. Furthermore, the lower the compression ratio, the greater the degree of discontinuity between the two batches of compressed data.

[0043] Similarly, in Figure 2 The diagram illustrates another method for storing compressed data in GDDR memory when the memory bank group rotation function is disabled, as applicable to the prior art. Figure 2 As shown, when the memory bank group rotation function is not enabled, each compressed data block in multiple 2kbits compressed data is stored in page 0 of BA0 in BG0. The first four valid data d0-d3 in the first compressed data (1st 2kbits) are stored consecutively, while the column storage cells containing d4-d7 are left empty as blank storage places. When the second compressed data (not shown in the figure) arrives, storage begins from the column storage cell following the grayed-out d7. This storage method also results in valid data from different compressed data being stored intermittently within a single page.

[0044] Clearly, the aforementioned fragmented storage method for pages reduces page utilization. When accessing the same amount of data, this storage method requires more pages, and the activation and switching operations of pages introduce significant latency overhead, impacting the performance of GDDR memory. The embodiments of this invention are technical improvements proposed based on the aforementioned problems in the prior art.

[0045] Example 1

[0046] Figure 3 A flow chart of a data storage method of a GDDR memory provided for Embodiment One of the present application, the embodiment can be applicable to the case of storing compressed data blocks in a GDDR memory as much as possible in one or more pages, the method can be executed by a data storage device of the GDDR memory, the device can be realized in the form of hardware, and generally can be configured in the controller of the GDDR memory. Wherein, the GDDR memory includes N1 memory bank groups, each memory bank group includes N2 memory banks, and N1 and N2 are both integers greater than 2.

[0047] Correspondingly, as shown in Figure 3 , the method includes:

[0048] S310, in the process of storing compressed data using the GDDR memory, if it is detected that the utilization rate of the row storage unit meets the optimization condition, the address remapping function is triggered to be started.

[0049] As described above, the row storage unit specifically refers to a page in a memory bank. And the utilization rate of the row storage unit meets the optimization condition specifically refers to that the discontinuity of each compressed data block stored in the page is relatively high, and the blank storage space between the compressed blocks of adjacent two compressed data is relatively large, etc.

[0050] It can be understood that as long as the compressed data is stored in the row storage unit, the blank storage space will appear, and the problem is only the number. Correspondingly, in an optional implementation manner of the embodiment, detecting that the utilization rate of the row storage unit meets the optimization condition can include: when it is determined that the data is successfully compressed according to the data amount of the compressed data, it is determined that the utilization rate of the row storage unit meets the optimization condition.

[0051] Further, the inventors consider that the technical solutions of the embodiments of the present application need to introduce an address remapping operation in the implementation manner of the prior art, and this newly introduced operation also has a certain implementation cost, therefore, when it is predicted that the utilization rate of the page is lower than a preset utilization rate threshold, it can be determined that the utilization rate of the row storage unit meets the optimization condition, at this time, the address remapping function can be triggered to be started accordingly.

[0052] Correspondingly, in another optional implementation manner of the embodiment, detecting that the utilization rate of the row storage unit meets the optimization condition can include:

[0053] When it is detected that the data amount of the compressed data is less than or equal to half of the data amount of the data before compression, it is determined that the utilization rate of the row storage unit meets the optimization condition.

[0054] As mentioned above, when the data volume of compressed data is less than or equal to half of the data volume of data before compression, it indicates that the utilization rate of the row storage unit will be less than or equal to 1 / 2. That is, in a page, the number of blank storage placeholders is equivalent to or more than the physical storage space occupied by valid data. At this time, the address remapping function can be triggered to start to realize efficient optimization of the row storage unit (page).

[0055] In the prior art, various data processed by the GPU is first stored in a virtual address space in a continuous manner according to logical addresses. The various data is mapped from the virtual address space to an actual physical storage space through a preset mapping relationship between the logical addresses and the physical addresses, and the physical storage space can be understood as a set column storage unit under a set row storage unit in a set bank in a set bank group in a GDDR memory. When the utilization rate of the row storage unit meets the optimization condition, it essentially indicates that the mapping relationship between the logical addresses and the physical addresses is no longer suitable for the current compressed data storage scenario, and therefore, at this time, the address remapping function needs to be started to fine-tune the mapping relationship between the currently used logical addresses and the physical addresses, so as to effectively improve the page utilization rate in the GDDR memory.

[0056] S320, after the address remapping function is started, the valid data in each piece of compressed data is stored in the row storage unit of the bank according to the compression rate of each piece of compressed data to be stored and the size of the column storage unit in the bank.

[0057] Specifically, the compression rate can be a ratio of the data volume after compression to the data volume before compression, which is used to reflect the degree of data compression. As mentioned above, for the scenario of each piece of compressed data including n set data block sizes of compressed data blocks, the compression rate can be represented as n:N, N being the compression granularity divided by the set data block size. In a specific example, if the compression granularity is 2kbits and the size of each data block is 256bits, the compression rate can be represented as n:8. Further, if each piece of 2kbits data is compressed into 3 compressed data blocks of 256bits, the compression rate is 3:8.

[0058] The compression ratio of each piece of compressed data is matched with the compression ratio of the data compressor to reflect the compression degree of each piece of data. The compression ratio can be determined in combination with the data amount of the compressed data, the preset compression granularity, and the size of the single data block. In a specific example, if the data amount of a piece of compressed data sent by the data compressor is 1 kbits, the compression granularity is 2 kbits, and the size of each compressed data block is 256 bits, the compression ratio of the piece of compressed data is 4:8. Further, if the data amount of a piece of compressed data sent by the data compressor is 1.5 kbits and exceeds the preset compression data amount threshold, the data compression fails, and the controller of the GDDR memory directly obtains the original 2 kbits of uncompressed data and stores the uncompressed data in the GDDR memory.

[0059] As described above, each compressed data block of each piece of compressed data is finally stored in a column storage unit in a page. Accordingly, the size of the compressed data block is generally selected to be the size of the column storage unit, that is, 256 bits as described above.

[0060] The correspondence between the logical address and the physical address can be fine-tuned according to the compression ratio of each piece of compressed data to be stored and the size of the column storage unit in the storage bank to achieve the effect of storing the valid data in each piece of compressed data in the row storage unit of the storage bank.

[0061] It should be noted that the storage aggregation described herein is not necessarily that the page does not have any blank storage placeholder at all, and all the compressed data blocks are continuously stored in the page. In fact, the storage aggregation effect of the embodiments of the present application is closely related to the specific compression ratio and whether the storage bank group rotation function is currently used. In some optimistic scenarios, the blank storage placeholder can be completely eliminated. Even in some less optimistic scenarios, compared with the prior art, the number of blank storage placeholders in the page can be effectively reduced, and the utilization rate of the page can be improved.

[0062] In an optional embodiment of the present embodiment, according to the compression ratio of each piece of compressed data to be stored and the size of the column storage unit in the storage bank, the valid data in each piece of compressed data is stored in the row storage unit of the storage bank, which can include:

[0063] S3201, determining a split logical address bit for identifying the split position of the valid data and the invalid data in each piece of compressed data according to the compression ratio of each piece of compressed data to be stored and the size of the column storage unit in the storage bank.

[0064] The data amount of each piece of compressed data is a compression granularity, and one or more column storage unit sizes of compressed data blocks can be contained in the compression granularity. After the compression rate is determined, the data amount of the compressed data blocks contained in the piece of compressed data can be known. The above data amount is the data amount of the effective data in the piece of compressed data, and the data amount of the invalid data is the compression granularity minus the data amount of the effective data.

[0065] After the data amount of the effective data in the piece of compressed data is obtained, when the storage of the compressed data blocks is performed according to the logical addresses of each compressed data block in the piece of compressed data, it can be determined that when a logical address bit of the logical address changes (from 1 to 0 or from 0 to 1), the storage of all the effective data in the piece of compressed data is completed. The logical address bit that changes is the split logical address bit. That is, the split logical address bit is an address bit in the logical address for identifying the split position of the effective data and the invalid data in each piece of compressed data.

[0066] S3202, constructing a storage bank inter-mapping relationship matching the split logical address bit according to the state of whether the storage bank group rotation function is enabled.

[0067] In the embodiment, considering that the storage form of each compressed data block in each piece of compressed data is different when the storage bank group rotation function is in the enabled or disabled state, the storage bank inter-mapping relationship constructed is also different for different storage forms of the compressed data blocks. Further, the new storage bank inter-mapping relationship needs to be determined in combination with the state of whether the storage bank group rotation function is enabled and the split logical address bit.

[0068] First, the target of each embodiment of the application is to reduce the storage blank placeholder introduced by the GDDR memory when storing the compressed data as much as possible. Based on this, the inventor creatively proposes an implementation manner of storing the effective data and the invalid data in each piece of compressed data in hot and cold pages respectively.

[0069] In a specific example, when the storage bank group rotation function is not enabled, each piece of compressed data is stored in only one page A in one storage bank A. At this time, a new page B can be started in a new storage bank B, and the effective data in each piece of compressed data is stored in the page A (hot page), and the invalid data is stored in the page B (cold page). When the GPU needs to access each piece of compressed data, only the page A needs to be activated, and the page B does not need to be activated. Through the above setting, more compressed data blocks can be put into the page A, and the utilization rate of the page A is improved.

[0070] Further, when the memory bank group rotation function is enabled, each piece of compressed data is alternately stored in a page A1 of a memory bank A1 and a page A2 of another memory bank A2. At this time, a new page B1 can be opened in a new memory bank B1 corresponding to the memory bank A1, and a new page B2 can be opened in a new memory bank B2 corresponding to the memory bank A2. Further, the valid data in each piece of compressed data can be alternately stored in the page A1 and the page A2 (hot page), and the invalid data can be alternately stored in the page B1 and the page B2 (cold page).

[0071] Since the split logical address bit can be used to split the valid data and the invalid data in a piece of compressed data, further, the inter-memory bank mapping relationship for implementing memory bank switching can be constructed in combination with the split logical address bit.

[0072] S3203, according to the split logical address bit and the inter-memory bank mapping relationship, the valid data in each piece of compressed data is stored in the row storage unit of the memory bank.

[0073] In the embodiment, when actually storing each compressed data block in each piece of compressed data, the logical address of the compressed data block can be acquired first, the binary value under the split logical address bit can be acquired from the logical address, and the memory bank for storing the compressed data block can be determined based on the binary value and the constructed inter-memory bank mapping relationship, so as to realize the aggregated storage of the valid data in the page of the memory bank.

[0074] The technical scheme of the embodiment of the application, in the process of storing compressed data using the GDDR memory, if it is detected that the utilization rate of the row storage unit meets the optimization condition, the address remapping function is triggered to be opened; after the address remapping function is opened, according to the compression rate of each piece of compressed data to be stored and the size of the column storage unit in the memory bank, the valid data in each piece of compressed data is aggregated and stored in the row storage unit of the memory bank. When it is detected that the page in the GDDR memory appears discontinuous storage, the address remapping function is timely opened to remap the physical address of each compressed data, so as to effectively reduce the blank storage occupancy in the page, achieve the technical effect that each compressed data block in multiple pieces of compressed data is maximally aggregated and stored in the page, improve the utilization rate of the page in the GDDR memory, shorten the time delay of the GPU accessing the GDDR memory, and effectively improve the performance of the GDDR memory.

[0075] Embodiment two

[0076] Figure 4A flow chart of another data storage method of a GDDR memory provided by the second embodiment of the present application is shown in FIG. 4, which is optimized based on the above embodiments. In this embodiment, the implementation of "according to the compression rate of each piece of compressed data and the size of the column storage unit in the storage bank, the valid data in each piece of compressed data is stored in the row storage unit of the storage bank in an aggregated manner" is further specified.

[0077] Accordingly, as shown in FIG. 5, the method can include: Figure 4

[0078] S410, during the storage of compressed data using the GDDR memory, if it is detected that the utilization rate of the row storage unit meets the optimization condition, the address remapping function is triggered to be enabled.

[0079] S420, after the address remapping function is enabled, according to the compression rate of each piece of compressed data, the number of compressed data blocks included in each piece of compressed data is obtained.

[0080] As mentioned above, for a compression rate in the form of n:N, n is the number of compressed data blocks included in each piece of compressed data. For example, if the compression rate of a piece of compressed data is 4:8, the number of compressed data blocks included in this piece of compressed data is 4.

[0081] S430, the product value of the number of blocks and the size of the column storage unit is calculated, and according to the product value and the data storage form in the virtual address space, the split logical address bits are determined.

[0082] As mentioned above, the size of the column storage unit is generally the data size of the compressed data block, and the product value of the number of blocks and the size of the column storage unit is the data amount of the valid data in a piece of compressed data. For example, if the number of blocks is 4 and the size of the column storage unit is 256 bits, the data amount of the valid data in a piece of compressed data is 4*256 bits=1kbits.

[0083] Generally, the data storage form in the virtual address space is generally in units of bytes, while the data amount of the valid data is in units of bits. Accordingly, the split logical address bits can be calculated according to the formula: split logical address bits = data amount of valid data / data storage form in virtual address space.

[0084] Continuing the previous example, when the data amount of the valid data is 4*256 bits=1kbits, the split logical address bits determined are 10-3=7, that is, the 7th bit A7 of the logical address of each compressed data block in a piece of compressed data is used to distinguish whether the data stored at the logical address is valid data.

[0085] ​​S440, detecting whether the bank group rotation function is in an enabled state: if yes, executing S450, otherwise, executing S480.

[0086] S450, acquiring a first bank in a first bank group and a second bank in a second bank group for alternately storing compressed data, and executing S460.

[0087] When the bank group rotation function is in the enabled state, each piece of compressed data is alternately stored in two banks in two different bank groups, and accordingly, a first bank in a first bank group and a second bank in a second bank group for alternately storing compressed data can be acquired.

[0088] S460, selecting a first joint bank in each bank remaining in the first bank group, and selecting a second joint bank in each bank remaining in the second bank group, and executing S470.

[0089] In combination Figure 1 As can be known from the description of the foregoing embodiment, the existing compressed data alternately storage manner makes each compressed data block of different pieces of compressed data discontinuously stored in the respective banks in the two bank groups. Further, a new bank can be opened in each of the two bank groups for storing invalid data (i.e., blank storage placeholder) originally stored in the bank, at which time the valid data in the original bank can be stored as much as possible.

[0090] Accordingly, a first joint bank can be selected in each bank remaining in the first bank group, and a second joint bank can be selected in each bank remaining in the second bank group. In combination Figure 1 of the foregoing embodiment, a new BA1 can be selected in BG0 and a new BA1 can be selected in BG1 as the first joint bank and the second joint bank for storing invalid data, respectively.

[0091] S470, constructing a bank-to-bank mapping relationship using the split logical address bits for selecting in the first bank and the first joint bank, and a bank-to-bank mapping relationship using the split logical address bits for selecting in the second bank and the second joint bank, and executing S4110.

[0092] As described previously, since the split logical address bits are used to distinguish valid data and invalid data, further, the bank-to-bank mapping relationship for selecting in the first bank and the first joint bank and the bank-to-bank mapping relationship for selecting in the second bank and the second joint bank can be constructed according to the split logical address bits.

[0093] In one specific example, A7 in the logical address is used as a split logical address bit, A7 is 0, the data under the logical address is valid data, A7 is 1, and blank storage placeholder needs to be performed. Further, when the data in a specific logical address in a piece of compressed data needs to be stored in BG0, when A7 in the specific logical address is 1, the data needs to be stored in BA1 of BG0, that is, a column storage unit size of blank storage placeholder is performed in BA1 of BG0.

[0094] S480, a third memory bank in a third memory bank group used for storing the compressed data independently is acquired, and S490 is performed.

[0095] Similarly, when the memory bank group rotation function is in the disabled state, each piece of compressed data is independently stored in a specific memory bank in a specific memory bank group, and accordingly, a third memory bank in a third memory bank group used for storing the compressed data independently needs to be acquired.

[0096] S490, a third joint memory bank is selected from the remaining memory banks in the third memory bank group, and S4100 is performed.

[0097] S4100, a memory bank-to-memory bank mapping relationship using the split logical address bit to select the third joint memory bank is constructed, and S4110 is performed.

[0098] S4110, according to the split logical address bit and the memory bank-to-memory bank mapping relationship, valid data in each piece of compressed data is stored in a row storage unit of a memory bank.

[0099] On the basis of the above embodiments, according to the split logical address bit and the memory bank-to-memory bank mapping relationship, valid data in each piece of compressed data is stored in a row storage unit of a memory bank, which can include:

[0100] S41101, when a target compressed data block in a piece of compressed data needs to be stored, a target logical address matching the target compressed data block is acquired.

[0101] In this embodiment, after triggering the address remapping function to be started, address remapping needs to be performed before each piece of compressed data is stored in an actual physical address. Further, a target logical address of a target compressed data block in a piece of compressed data currently to be stored needs to be acquired first for address remapping processing.

[0102] S41102, according to a standard address mapping relationship constructed in advance, a first bit of data in a memory bank group identification address bit in the target logical address is determined, and a target memory bank group is determined according to the first bit of data.

[0103] As mentioned above, the remapping manner of each embodiment of the present application is to establish a new memory bank in the same memory bank group, and the invalid data in the opened page is stored in the memory bank. Therefore, the technical solution of each embodiment of the present application does not need to modify the memory bank group mapping manner of the prior art, and still uses the memory bank group mapping relationship of the prior art, that is, the standard address mapping relationship is used to determine the target memory bank group for storing the target compressed data block.

[0104] The memory bank group identification address bit can be understood as a logical address bit defined by the standard address mapping relationship and used to determine the specific memory bank group where the data is stored. The logical address bit can be one bit or multiple bits, and the embodiment does not limit this. When the first bit data in the memory bank group identification address bit in the target logical address is obtained, the target memory bank group for storing the target compressed data block can be obtained based on the standard address mapping relationship.

[0105] S41103, determining the second bit data in the split logical address bit in the target logical address, and determining the target memory bank in the target memory bank group according to the second bit data and the inter-memory bank mapping relationship.

[0106] S41104, storing the target compressed data block into the target memory bank in the target memory bank group.

[0107] Specifically, in Figure 5 the storage of compressed data in the GDDR memory when the memory bank group rotation function is enabled after the address remapping function of each embodiment of the present application is applied is shown. As Figure 5 shown, when the memory bank group rotation function is enabled, BA1 needs to be used jointly in BG0, and BA1 needs to be used jointly in BG1 to jointly store the invalid data in each piece of compressed data.

[0108] At this time, for the compression ratio of 4:8, the invalid data d4-d7 in each piece of compressed data identified by the split logical address bit can be alternately stored in page0 in BA1 in BG0 and page0 in BA1 in BG1. Since the compression ratio of 4:8 is a relatively optimistic data compression scenario, at this time, the blank storage placeholder can be completely eliminated in page0 in BA0 in BG0 and page0 in BA0 in BG1. However, in some other compression ratio scenarios, a few blank storage placeholders may appear in the hot page, but compared with the prior art, the utilization rate of these hot pages can also be increased, and the performance of the GDDR memory can be effectively improved.

[0109] Similarly, in Figure 6The diagram illustrates the storage of compressed data in GDDR memory when the memory bank rotation function is not enabled after applying the address remapping function of various embodiments of the present invention. Figure 6 As shown, for a compression ratio of 4:8, the invalid data d4-d7 identified by the segmentation logical address bits in each compressed data can be stored separately in page0 of BA1 in BG0, so that the valid data d0-d3 in each compressed data can be stored tightly in page0 of BA0 in BG0.

[0110] To clarify the relationship between the address remapping proposed in each embodiment of the present invention and the existing mapping relationship between logical and physical addresses, Figure 7 The diagram illustrates a comparison of two address mapping relationships before and after applying the address remapping function of various embodiments of the present invention, when enabling the memory bank group rotation function, and also shows a comparison of two address mapping relationships. Figure 8 The diagram shows a comparison of two address mapping relationships before and after applying the address remapping function of the various embodiments of the present invention, when the memory bank group rotation function is not enabled.

[0111] like Figure 7 As shown, the data row corresponding to the "before improvement" field describes the mapping relationship between logical addresses and physical addresses in the prior art. Specifically, bits 15 (A15) and 14 (A14) in the logical address are used to select from four memory banks BA[1:0]. For example, when A15A14 = "00" in the logical address of a compressed data block, BA

[00] is selected to store the compressed data block. In addition, bits A13 and A5 in the logical address are used to select from four memory bank groups BG[1:0], bit A12 in the logical address is used to select from two set column memory units Col[6], and bits A[11:6] in the logical address are used to select from multiple set column memory units Col[5:0].

[0112] In contrast, the data row corresponding to the "Improved" field describes the new mapping relationship between logical addresses and physical addresses after applying the address remapping function of various embodiments of the present invention. Specifically, taking the determination of A7 in the logical address as the separator between valid and invalid data as an example, it is necessary to change the original A14 in the mapping relationship for memory bank BA[1:0] to A7. Since the function of A7 has changed and A14 is no longer used in the memory bank mapping relationship, the mapping relationship associated with A7 and A14 needs to be adaptively adjusted as a whole. Figure 8 The situation is similar to that shown in the example, and will not be described in detail in this embodiment.

[0113] It needs to be emphasized again that, although the embodiments of the present application focus on the specific data aggregation storage mode from the implementation logic of the method, the method of each embodiment is mainly implemented in hardware, for example, by combining various programmable logic gate arrays.

[0114] The technical solution of the embodiment of the present application aims at the core contradiction that the utilization rate of the page in the GDDR memory is not high and the page loss (also known as Miss) increases when using the GDDR memory to store compressed numbers in the prior art. The problem source in the scene where the BG Rotate function is enabled or not enabled is accurately located. The core idea is "effective data aggregation plus invalid data isolation". The mapping relationship between the logical address and the page is redefined through the address remapping technology. The dual effects of efficient utilization of hot pages and isolation of cold pages are achieved. By aggregating the effective compressed data blocks to the hot page and storing the invalid compressed data blocks to the cold page, only the hot page is activated when the GPU accesses the data, and the aggregated effective data is read, which can effectively improve the page utilization rate and reduce the page loss.

[0115] In addition, the technical solution of each embodiment of the present application can be compatible with the dual scenes of enabling and not enabling the BG Rotate function at the same time. Without modifying the physical structure of the GDDR memory, only by optimizing the address mapping logic in the controller of the GDDR memory, the compressed data access scene can be effectively adapted, the goal of "reducing the total number of activated pages" is focused, the page loss and access delay are reduced from the root, and the performance of the GPU accessing the GDDR memory is improved.

[0116] Embodiment three

[0117] Figure 9 A structural schematic diagram of a data storage device of a GDDR memory is provided for the third embodiment of the present application. The device is configured in the controller of the GDDR memory. The GDDR memory includes N1 memory banks, and each memory bank includes N2 memory banks. N1 and N2 are integers greater than 2, such as Figure 9 As shown, the device includes an address remapping function starting module 910 and an aggregation storage module 920, wherein:

[0118] The address remapping function starting module 910 is used to start the address remapping function if it is detected that the utilization rate of the row storage unit meets the optimization condition during the storage process of the compressed data using the GDDR memory;

[0119] The aggregation storage module 920 is configured to, after the address remapping function is enabled, aggregate and store the valid data in each piece of compressed data in the row storage unit of the storage bank according to the compression rate of each piece of compressed data to be stored and the size of the column storage unit in the storage bank.

[0120] In the storage process of the compressed data using the GDDR memory, if it is detected that the utilization rate of the row storage unit meets the optimization condition, the address remapping function is triggered to be enabled; after the address remapping function is enabled, the valid data in each piece of compressed data is aggregated and stored in the row storage unit of the storage bank according to the compression rate of each piece of compressed data to be stored and the size of the column storage unit in the storage bank. When it is detected that the page in the GDDR memory appears discontinuous storage, the address remapping function can be enabled in time to remap the physical address of each piece of compressed data, so as to effectively reduce the blank storage occupancy in the page, achieve the technical effect that each piece of compressed data block in multiple pieces of compressed data is maximally aggregated and stored in the page, improve the utilization rate of the page in the GDDR memory, shorten the time delay of the GPU accessing the GDDR memory, and effectively improve the performance of the GDDR memory.

[0121] On the basis of the above-mentioned embodiments, the address remapping function enabling module 910 can be specifically configured to:

[0122] When it is detected that the data amount of the compressed data is less than or equal to half of the data amount of the data before compression, it is determined that the utilization rate of the row storage unit meets the optimization condition.

[0123] On the basis of the above-mentioned embodiments, the aggregation storage module 920 can specifically include:

[0124] The split logical address bit determination unit is configured to determine a split logical address bit used for identifying the split position of the valid data and the invalid data in each piece of compressed data according to the compression rate of each piece of compressed data to be stored and the size of the column storage unit in the storage bank.

[0125] The inter-bank mapping relationship construction unit is configured to construct an inter-bank mapping relationship matched with the split logical address bit according to the state of whether the storage bank group rotation function is enabled.

[0126] The row aggregation unit is configured to aggregate and store the valid data in each piece of compressed data in the row storage unit of the storage bank according to the split logical address bit and the inter-bank mapping relationship.

[0127] On the basis of the above-mentioned embodiments, the split logical address bit determination unit can be specifically configured to:

[0128] The product value of the block number and the column storage unit size is calculated, and a split logical address bit is determined according to the product value and a data storage form in a virtual address space.

[0129] On the basis of the above embodiments, the inter-bank mapping relationship construction unit can be specifically used for:

[0130] If the bank group rotation function is in an enabled state, a first bank in a first bank group and a second bank in a second bank group used for alternately storing compressed data are acquired;

[0131] A first joint bank is selected from the remaining banks in the first bank group, and a second joint bank is selected from the remaining banks in the second bank group;

[0132] An inter-bank mapping relationship using the split logical address bit to select the first bank and the first joint bank is constructed, and an inter-bank mapping relationship using the split logical address bit to select the second bank and the second joint bank is constructed.

[0133] On the basis of the above embodiments, the inter-bank mapping relationship construction unit can be specifically used for:

[0134] If the bank group rotation function is in a disabled state, a third bank in a third bank group used for independently storing compressed data is acquired;

[0135] A third joint bank is selected from the remaining banks in the third bank group;

[0136] An inter-bank mapping relationship using the split logical address bit to select the third bank and the third joint bank is constructed.

[0137] On the basis of the above embodiments, the row aggregation unit can be specifically used for:

[0138] When a target compressed data block in a piece of compressed data needs to be stored, a target logical address matched with the target compressed data block is acquired;

[0139] According to a pre-constructed standard address mapping relationship, a first bit data in a bank group identification address bit in the target logical address is determined, and a target bank group is determined according to the first bit data;

[0140] A second bit data in the split logical address bit in the target logical address is determined, and a target bank in the target bank group is determined according to the second bit data and an inter-bank mapping relationship;

[0141] The target compressed data block is stored into the target bank in the target bank group.

[0142] The data storage device of the GDDR memory provided in the embodiments of the present invention can execute the data storage method of the GDDR memory provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of executing the method.

[0143] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0144] Example 4

[0145] Figure 10 This is a schematic diagram of the structure of a graphics processor provided in Embodiment 4 of the present invention. Figure 10 As shown, the graphics processor includes: GDDR memory 1010 and a GDDR memory controller 1020. Figure 10 The GDDR memory 1010 (referred to as the GDDR controller in Chinese) includes N1 memory bank groups (not shown in the figure), and each memory bank group includes N2 memory banks (not shown in the figure), where N1 and N2 are both integers greater than 2.

[0146] The controller 1020 of the GDDR memory is used to execute the data storage method of the GDDR memory as described in any embodiment of the present invention.

[0147] Example 5

[0148] Figure 11 A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0149] like Figure 11As shown, the electronic device 10 includes at least one graphics processor 11, and a memory, such as a read-only memory 12, a random access memory 13, etc., communicatively connected to the at least one graphics processor 11, wherein the memory stores a computer program executable by the at least one graphics processor 11, and the graphics processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory 12 or loaded from the storage unit 18 into the random access memory 13. Various programs and data required for the operation of the electronic device 10 can also be stored in the random access memory 13. The graphics processor 11, the read-only memory 12, and the random access memory 13 are connected to each other through a bus 14. An input / output interface 15 is also connected to the bus 14.

[0150] Various components in the electronic device 10 are connected to the input / output interface 15, including an input unit 16, such as a keyboard, a mouse, etc., an output unit 17, such as various types of displays, a speaker, etc., a storage unit 18, such as a magnetic disk, an optical disk, etc., and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.

[0151] The graphics processor 11 can be a dedicated graphics processing component with processing and computing capabilities. The graphics processor 11 performs various methods and processes described above, such as performing the data storage method of the GDDR memory as described in any embodiment of the present application.

[0152] In some embodiments, the data storage method of the GDDR memory as described in any embodiment of the present application can be implemented as a computer program tangibly embodied in a computer readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 10 via the read-only memory 12 and / or the communication unit 19. When the computer program is loaded into the random access memory 13 and executed by the graphics processor 11, one or more steps of the data storage method of the GDDR memory as described in any embodiment of the present application can be performed. Alternatively, in other embodiments, the graphics processor 11 can be configured to perform the data storage method of the GDDR memory as described in any embodiment of the present application by any other appropriate means, such as by means of firmware.

[0153] That is, during the storage of compressed data using the GDDR memory, if it is detected that the utilization rate of the row storage unit satisfies the optimization condition, the address remapping function is triggered to be enabled;

[0154] After the address remapping function is enabled, according to the compression rate of each piece of compressed data to be stored and the size of the column storage unit in the storage bank, the valid data in each piece of compressed data is stored in the row storage unit of the storage bank in an aggregated manner.

[0155] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, specially designed application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0156] Computer programs implementing methods of the present application can be written in any combination of one or more programming languages. These computer programs can be provided to a programmable apparatus, such as a general purpose computer, a special purpose computer, or other programmable data processing apparatus to produce a machine, such that the computer program running on the machine implements the functions / acts specified in the flowcharts and / or block diagrams. The computer program can be executed entirely on a machine, partially on a machine, partially on a machine as part of a standalone software package, or entirely on a remote machine or server.

[0157] In the context of the present application, a computer-readable storage medium can be a tangible medium that can contain or store computer programs for use by or in connection with an instruction execution system, apparatus, or device. Computer-readable storage media can include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of the machine-readable storage medium will include one or more lines of a program of instructions in a transitory signal, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0158] To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0159] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0160] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. A server can be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system, to solve the defects of large management difficulty and weak business scalability in traditional physical host and VPS service.

[0161] It should be understood that the various forms of flow shown above can be re-ordered, added to, or deleted from without departing from the scope of the present disclosure. For example, the steps recited in the present disclosure can be executed in parallel, executed in sequence, or executed in a different order, as long as the desired results of the present disclosure are achieved, and the present disclosure is not limited herein.

[0162] The specific embodiments described above are not intended to be limiting, and persons skilled in the art will appreciate that various modifications, combinations, sub-combinations and alternatives can be made to the specific embodiments without departing from the spirit and principles of the disclosure. Accordingly, the disclosure is not limited to the specific embodiments described above, but only by the scope of the appended claims.

Claims

1. A data storage method for a GDDR memory, characterized in that, The method, executed by a controller of a graphics double data rate (GDDR) memory, comprising N1 memory bank groups, each memory bank group comprising N2 memory banks, where N1 and N2 are both integers greater than 2, includes: During the storage of compressed data using the GDDR memory, if the utilization rate of the row storage unit is detected to meet the optimization conditions, the address remapping function is triggered. After the address remapping function is enabled, the effective data in each compressed data is aggregated and stored in the row storage unit of the storage body according to the compression ratio of each compressed data to be stored and the size of the column storage unit in the storage body. Specifically, based on the compression ratio of each compressed data item to be stored and the size of the column storage units in the storage body, the effective data in each compressed data item is aggregated and stored in the row storage units of the storage body, including: Based on the compression ratio of each compressed data item to be stored and the size of the column storage unit in the storage body, determine the segmentation logical address bits used to identify the segmentation positions of valid and invalid data in each compressed data item; Based on whether the memory bank group rotation function is enabled, construct a mapping relationship between memory banks that matches the segmented logical address bits; Based on the segmentation logical address bits and the mapping relationship between the storage units, the valid data in each compressed data is aggregated and stored in the row storage unit of the storage unit.

2. The method according to claim 1, characterized in that, The utilization rate of row storage units was detected to meet optimization conditions, including: When the amount of compressed data is less than or equal to half the amount of data before compression, the utilization rate of the row storage unit is determined to meet the optimization condition.

3. The method according to claim 1, characterized in that, Based on the compression ratio of each compressed data entry to be stored and the size of the column storage unit in the storage bank, determine the segmentation logical address bits used to identify the splitting positions of valid and invalid data in each compressed data entry, including: Based on the compression ratio of each compressed data, obtain the number of compressed data blocks included in each compressed data; Calculate the product of the number of blocks and the size of the column storage unit, and determine the segmented logical address bits based on the product and the data storage format in the virtual address space.

4. The method according to claim 1, characterized in that, Based on the enabled / disabled state of the memory bank group rotation function, a memory bank mapping relationship matching the segmented logical address bits is constructed, including: If the storage bank group rotation function is enabled, the first storage bank in the first storage bank group and the second storage bank in the second storage bank group are retrieved for alternating storage of compressed data. In the remaining memory banks in the first memory bank group, select the first combined memory bank, and in the remaining memory banks in the second memory bank group, select the second combined memory bank. Construct a memory bank mapping relationship for selecting between the first memory bank and the first combined memory bank using the segmented logical address bits, and construct a memory bank mapping relationship for selecting between the second memory bank and the second combined memory bank using the segmented logical address bits.

5. The method according to claim 1, characterized in that, Based on the enabled / disabled state of the memory bank group rotation function, a memory bank mapping relationship matching the segmented logical address bits is constructed, including: If the storage bank group rotation function is disabled, then the third storage bank in the third storage bank group used for independent storage of compressed data is obtained; Among the remaining memory banks in the third memory bank group, select the third combined memory bank; Construct a mapping relationship between memory banks that are selected between the third memory bank and the third combined memory bank using the segmented logical address bits.

6. The method according to claim 4 or 5, characterized in that, Based on the segmentation logical address bits and the mapping relationship between storage units, the valid data in each compressed data item is aggregated and stored in the row storage unit of the storage unit, including: When it is necessary to store a target compressed data block in a compressed data set, obtain the target logical address that matches the target compressed data block; Based on the pre-built standard address mapping relationship, the first bit of data in the memory bank group identification address bit is determined in the target logical address, and the target memory bank group is determined based on the first bit of data; The second bit data in the segmented logical address is determined in the target logical address, and the target memory is determined in the target memory group based on the second bit data and the mapping relationship between memory banks. Store the target compressed data block into the target storage of the target storage group.

7. A graphics processing unit (GPU), characterized in that, include: GDDR memory and its controller. The GDDR memory comprises N1 memory bank groups, each containing N2 memory banks, where N1 and N2 are both integers greater than 2. The controller of the GDDR memory is configured to execute the data storage method of the GDDR memory as described in any one of claims 1-6.

8. An electronic device, characterized in that, The electronic device includes: At least one graphics processor; and a memory communicatively connected to said at least one graphics processor; wherein... The memory stores a computer program that can be executed by the at least one graphics processor, the computer program being executed by the at least one graphics processor to enable the at least one graphics processor to perform the data storage method of the GDDR memory according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a graphics processor, implement the data storage method of the GDDR memory according to any one of claims 1-6.

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