High-bandwidth low-delay data transmission chip design method

Abstract

The invention relates to the technical field of integrated circuit design, in particular to a high-bandwidth low-delay data transmission chip design method, which comprises the following steps of: integrating a plurality of processor cores provided with local memory controllers, vertical access controllers and transverse communication controllers on a logic chip, and constructing a transverse full internet by virtue of a silicon intermediate layer; an exclusive parallel data transmission channel is established for each pair of processor cores, resource allocation is coordinated through a global flow control and arbitration unit, and single-hop direct communication and efficient memory access between the processor cores are realized in combination with a three-dimensional stacked shared memory space and an intelligent prefetching mechanism. The problems of high data access delay and limited bandwidth caused by relying on network-on-chip multi-hop transmission and arbitration are effectively solved, the communication delay is remarkably reduced, and the concurrent bandwidth and data throughput efficiency of the system are greatly improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a design method for a high-bandwidth, low-latency data transmission chip. Background Technology

[0002] With the rapid development of applications such as artificial intelligence, big data analytics, and cloud computing, processing units such as CPUs and GPUs are placing unprecedented demands on the bandwidth and latency of memory systems. In traditional two-dimensional planar chip architectures, the long data transfer paths and limited bandwidth between the processor and memory have become a major bottleneck in improving overall system performance.

[0003] To overcome this limitation, three-dimensional stacking technology emerged, which significantly shortens interconnect distances by vertically stacking dynamic random access memory (DRAM) chips on top of logic chips, providing a physical basis for high-bandwidth and low-latency access. Patent document CN120144534B discloses a chip design method and chip system that integrates local, global, and shared DRAM controllers on each processor core, and interconnects the local controllers of each core through a network on-chip (NoC), aiming to optimize data exchange efficiency through distributed management and direct connection paths.

[0004] However, the aforementioned chip design methods and chip systems heavily rely on the NoC (No-Creator) architecture to enable collaborative work and data exchange between local DRAM controllers of multiple processor cores. When multiple processor cores concurrently access shared memory resources or need to exchange data between cores, data packets must hop through multiple routing nodes within the NoC. Each hop introduces significant transmission latency and arbitration overhead, leading to an increase in the actual latency of the data path. Simultaneously, the NoC itself can become a bottleneck for bandwidth contention under high loads, thus limiting the peak bandwidth and real-time response capabilities achievable by the system in data-intensive applications. Summary of the Invention

[0005] The purpose of this invention is to provide a high-bandwidth, low-latency data transmission chip design method, which solves the problems of high data access latency and limited bandwidth caused by multi-hop transmission and arbitration of on-chip networks (NoC) in existing three-dimensional stacked chip architectures.

[0006] To achieve the above objectives, the present invention provides a high-bandwidth, low-latency data transmission chip design method, comprising the following steps: Multiple processor cores are integrated on a logic chip, and each processor core integrates a local memory controller, a vertical access controller, and a lateral communication controller. A silicon interposer is provided, and a logic chip integrating the processor core is flip-chip bonded onto the silicon interposer. At least one dynamic random access memory chip is vertically integrated onto the logic chip using three-dimensional stacking technology to form a shared memory space; A lateral fully interconnected network is constructed inside the silicon interposer layer to establish a dedicated parallel data transmission channel between the lateral communication controllers of each pair of processor cores; A global flow control and arbitration unit is integrated on the logic chip to coordinate resource allocation in the horizontal fully interconnected network; Direct data communication between processor cores is achieved through the lateral communication controller, and single-hop communication is achieved using a dedicated parallel data transmission channel; The vertical access controller manages the processor core's direct access to the shared memory space.

[0007] Specifically, direct data communication between processor cores is achieved through the lateral communication controller, and single-hop communication is implemented using a dedicated parallel data transmission channel, including: Through the data packing / unpacking module and protocol processing unit integrated within the horizontal communication controller, independent of the computing unit of the processor core, it can directly perform data transfer operations between other horizontal communication controllers.

[0008] Specifically, a global flow control and arbitration unit is integrated on the logic chip to coordinate resource allocation in the horizontal fully interconnected network, including: Real-time monitoring of the traffic status of each dedicated parallel data transmission channel; When a large-scale data transfer is detected between a pair of processor cores, multiple idle physical channels are dynamically bound to the lateral communication controller of that pair of processor cores to form a temporary aggregated communication link.

[0009] Specifically, a lateral fully interconnect network is constructed within the silicon interposer layer to establish a dedicated parallel data transmission channel between the lateral communication controllers of each pair of processor cores, including: Two physical channels are configured in the horizontally interconnected network: a high-bandwidth parallel data channel, which adopts a low-voltage swing parallel differential signal transmission mechanism for transmitting batch data; and a low-latency control channel, which adopts an independent broadcast or ring topology for transmitting communication synchronization signals and buffer consistency control messages.

[0010] Specifically, managing the processor core's direct access to the shared memory space through the vertical access controller includes: The shared memory space is divided into multiple memory partitions at the logical address level, and each memory partition is associated with a specific data access mode. The intelligent prefetch engine integrated within the vertical access controller learns and identifies the memory access characteristic patterns of the currently executing thread. Memory access requests are dynamically mapped to the most matching memory partition, and the data that will be accessed later is prefetched into the local cache of the processor core according to the preset prefetch strategy of that memory partition.

[0011] Specifically, managing the processor core's direct access to the shared memory space through the vertical access controller further includes: Establish communication connections between the global flow control and arbitration unit and each intelligent prefetching engine; The global flow control and arbitration unit collaboratively optimizes the data prefetching strategy and the allocation and scheduling of lateral communication resources.

[0012] Specifically, a lateral fully interconnect network is constructed within the silicon interposer layer to establish a dedicated parallel data transmission channel between the lateral communication controllers of each pair of processor cores, further including: A dedicated parallel data transmission channel is implemented using a metal layer copper interconnect process, and the channel width is configured between 128 bits and 512 bits.

[0013] Specifically, at least one dynamic random access memory (DRAM) chip is vertically integrated onto the logic chip using three-dimensional stacking technology to form a shared memory space, including: The physical connection between the vertical access controller and the shared memory space is achieved through hybrid bonding technology.

[0014] This invention discloses a high-bandwidth, low-latency data transmission chip design method. By integrating multiple processor cores equipped with local memory controllers, vertical access controllers, and lateral communication controllers onto a logic chip, and constructing a lateral fully interconnected network using a silicon interposer, a dedicated parallel data transmission channel is established for each pair of processor cores. Simultaneously, resource allocation is coordinated through global flow control and arbitration units. Combined with a three-dimensional stacked shared memory space and intelligent prefetching mechanism, single-hop direct communication and efficient memory access between processor cores are achieved. This effectively solves the problems of high data access latency and limited bandwidth caused by reliance on multi-hop transmission and arbitration via on-chip networks (NoC), significantly reducing communication latency and greatly improving system concurrent bandwidth and data throughput efficiency. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0016] Figure 1 This is a flowchart illustrating the steps of the high-bandwidth, low-latency data transmission chip design method of the present invention. Detailed Implementation

[0017] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, but should not be construed as limiting the present invention.

[0018] Please see Figure 1 ,in, Figure 1 This is a flowchart illustrating the steps of the high-bandwidth, low-latency data transmission chip design method of the present invention.

[0019] This invention provides a high-bandwidth, low-latency data transmission chip design method, comprising the following steps: S101: Multiple processor cores are integrated on a logic chip, and each processor core integrates a local memory controller, a vertical access controller and a horizontal communication controller. Specifically, within each processor core integrated on the logic chip, a heterogeneous integration architecture is used to construct three specialized controller units, forming a collaborative control subsystem. The local memory controller manages the processor core's access requests to its own private memory space, handling routine read / write operations and maintaining cache coherency. The vertical access controller is specifically designed for handling direct communication with the memory chips above through a three-dimensional stacked structure. This controller integrates high-speed interface circuitry and timing control logic, enabling direct access to shared memory space via through-silicon vias (TSVs) or vertical interconnects formed by hybrid bonding. The horizontal communication controller serves as a dedicated data path interface between processor cores. It integrates a complete data link layer processing module, including data packing / unpacking units and lightweight protocol processing units, enabling data transfer operations independently of the processor core's computational units. These three controllers are interconnected within the processor core via a dedicated on-chip bus, forming a well-defined yet tightly coordinated control network. The local memory controller acts as the basic memory access unit, the vertical access controller handles vertical storage expansion, and the horizontal communication controller is specifically responsible for horizontal inter-core collaboration. Together, they form the hardware foundation supporting high-bandwidth, low-latency data transmission. This architectural design laid a solid hardware foundation for the subsequent construction of fully interconnected networks and the implementation of single-hop communication.

[0020] S102: Provide a silicon interposer layer, and flip-chip bond the logic chip integrating the processor core onto the silicon interposer layer; Specifically, after integrating the processor core and various controllers on the logic chip, a physical carrier supporting high-speed interconnects is constructed. High-purity silicon is selected as the substrate material for the interposer, whose coefficient of thermal expansion matches that of the logic chip, ensuring structural stability in subsequent packaging processes. Multiple redistribution layers are fabricated within the interposer using semiconductor front-end processes, forming a high-density wiring network through copper interconnects. These metal wiring layers achieve vertical electrical connections through through-silicon vias (TSVs).

[0021] The pad area on the interposer surface utilizes micro-bump technology to form an array of interconnect points. The spacing of these interconnect points is controlled at the micrometer level to meet the requirements of high-density interconnection. During flip-chip bonding, a corresponding array of solder balls is first fabricated on the active surface of the logic chip. Then, a precise alignment device is used to align the logic chip with the silicon interposer, and thermoforming is performed under a controlled atmosphere. This process requires strict control of the temperature profile and pressure parameters to ensure adequate solder wetting while avoiding thermal damage to the internal circuitry of the chip.

[0022] After soldering, an underfill adhesive is filled into the gap between the logic chip and the silicon interposer. This polymer material, after curing, effectively disperses mechanical stress, improving the reliability and lifespan of the connection structure. Through this flip-chip soldering method, the lateral communication controller of each processor core on the logic chip can establish direct connections with other cores via dedicated wiring channels within the silicon interposer, laying the physical foundation for building a fully interconnected network. This packaging structure not only provides a high-bandwidth path for data transmission between chips but also significantly reduces signal transmission latency by shortening the interconnect distance.

[0023] S103: At least one dynamic random access memory chip is vertically integrated onto the logic chip using three-dimensional stacking technology to form a shared memory space; Specifically, after completing the flip-chip bonding of the logic chips to the silicon interposer, the next step is to implement three-dimensional stacked memory integration. High-density dynamic random-access memory (DRAM) chips are selected as the stacking targets, and vertical interconnect pathways are formed inside the DRAM chips using through-silicon vias (TSVs). These TSVs not only handle data transmission but also integrate power management and signal synchronization circuitry, ensuring maximum input / output bandwidth within a limited area.

[0024] In the bonding process, a hybrid bonding technique is used to directly connect DRAM chips and logic chips. First, copper bonding pads are fabricated in the vertical access controller region of the logic chip and the corresponding location on the DRAM chip. Chemical mechanical polishing ensures atomic-level surface flatness. Under strictly controlled environmental conditions, surface activation technology is used to achieve molecular-level bonding between the chips, forming a vertical interconnect structure with low parasitic parameters and high connection density. This hybrid bonding process creates a connection density of tens of thousands per square millimeter, significantly exceeding the connection capabilities of traditional microbump technology.

[0025] To ensure the reliability of the three-dimensional stacked structure, a high-efficiency heat dissipation structure is integrated on the back of the DRAM chip, using thermal interface materials to conduct heat generated by the chip to an external heat dissipation device. Simultaneously, dielectric materials are filled between the stacked layers, providing both mechanical support and enhanced electrical insulation. This vertically integrated shared memory space allows each processor core to directly access unified storage resources through a dedicated vertical access controller, achieving the shortest possible connection between storage and computing units and providing the physical basis for high-bandwidth data access. This three-dimensional stacked architecture not only significantly increases storage capacity and access bandwidth but also effectively reduces access latency by minimizing data transmission paths.

[0026] S104: Construct a lateral full interconnect network inside the silicon interposer layer to establish a dedicated parallel data transmission channel between the lateral communication controllers of each pair of processor cores; Specifically, after completing the integration of the 3D stacked memory, the next step is to build a lateral full interconnect network inside the silicon interposer. Based on the multi-layer copper interconnect structure already formed by the silicon interposer, a fully custom routing strategy is used to establish dedicated physical channels between the lateral communication controllers of each pair of processor cores. These channels adopt a parallel bus architecture, with each channel containing 128-bit to 512-bit wide data lines and equipped with independent clock and control signal lines, ensuring point-to-point direct connection without the need for routing forwarding.

[0027] At the circuit design level, these dedicated channels employ current-mode logic and differential signal transmission technology. Through impedance matching control and timing optimization, they achieve signal transmission rates of tens of gigabits per second. Each channel integrates an adaptive equalization circuit to compensate for signal integrity losses caused by transmission distance and process variations. Simultaneously, shielding and grounding isolation are implemented between adjacent channels to effectively suppress crosstalk noise during parallel transmission.

[0028] The physical implementation of the channels relies on advanced packaging technology of silicon interposers, utilizing their high-density redistribution layers to achieve complex wiring topologies. For a system containing N processor cores, N×(N-1) / 2 bidirectional transmission channels are precisely arranged in the full interconnect network to form a complete mesh connection architecture. These channels are organized hierarchically within the silicon interposer and connected in three dimensions through an array of vias between metal layers, ensuring both the shortest signal paths and minimizing wiring congestion.

[0029] This fully interconnected network directly interfaces with the lateral communication controller within the processor core. The controller's data interface is specially optimized to match the electrical characteristics of the channels. Through this deeply integrated design, data transmission between any two processor cores can be completed in a single hop via a dedicated channel, completely avoiding the multi-hop latency problem of traditional on-chip networks and providing the system with extremely high internal communication bandwidth and extremely low transmission latency.

[0030] S105: A global flow control and arbitration unit is integrated on the logic chip to coordinate resource allocation in the horizontal fully interconnected network; Specifically, after constructing the horizontal fully interconnected network within the silicon interposer, a global flow control and arbitration unit is integrated on the logic chip to coordinate network resource allocation. This unit adopts a distributed architecture design, including a master arbitrator and multiple slave arbitrators, where the slave arbitrators are directly connected to the horizontal communication controller of each processor core, forming a hierarchical control system.

[0031] The global flow control and arbitration unit collects real-time operational status data of the entire interconnected network through dedicated monitoring circuits, including key parameters such as traffic load, data transmission latency, and error rate for each dedicated channel. Monitoring data is transmitted to the arbitration logic via an independent low-latency control channel, ensuring the real-time nature and accuracy of the status information. The integrated dynamic decision-making module calculates the optimal resource allocation scheme based on preset optimization objectives, including minimizing transmission latency, balancing network load, and maximizing throughput.

[0032] When multiple transmission requests are detected competing for the same resource, the arbitration unit makes a comprehensive decision based on multiple factors, including priority weight, data urgency, and channel availability. For large-scale data transmission tasks, the unit can initiate a dynamic channel binding mechanism to temporarily aggregate multiple idle physical channels into a high-bandwidth link. Simultaneously, the unit maintains close collaboration with the lateral communication controllers of each processor core, using pre-configured flow control protocols to prevent data overflow and congestion propagation.

[0033] To achieve fine-grained timing control, the arbitration unit integrates a global clock synchronization module, using phase-locked loop (PLL) technology to ensure consistent timing across all distributed components. This unit also possesses adaptive learning capabilities, enabling it to optimize the arbitration strategy based on historical transmission patterns, gradually improving overall system performance. Through deep integration with the fully interconnected network, the global flow control and arbitration unit achieves efficient utilization and fair allocation of network resources while maintaining low latency in single-hop communication.

[0034] S106: Direct data communication between processor cores is realized through the horizontal communication controller, and single-hop communication is realized using a dedicated parallel data transmission channel; Specifically, based on the resource coordination and channel allocation completed by the global flow control and arbitration unit, data communication between processor cores is achieved through the collaborative work of the lateral communication controller and dedicated parallel data transmission channels. When a processor core needs to transmit data to another core, its internal lateral communication controller first receives the data transmission instruction from the computing unit. The controller's data packing and unpacking module then formats the data to be transmitted, adding necessary header information and checksum sequences to form a data frame conforming to the channel transmission protocol.

[0035] Simultaneously, the protocol processing unit of the lateral communication controller establishes a handshake communication with the global flow control and arbitration unit to obtain the real-time status information of the target channel. Once the channel is confirmed to be ready, the controller immediately initiates the data transmission process, sending the encapsulated data frame directly to the lateral communication controller of the target processor core through a dedicated parallel data transmission channel. The entire transmission process is completed entirely at the hardware level, without the intervention of the processor core's computing unit or any intermediate routing nodes.

[0036] During data transmission, the horizontal communication controller continuously monitors the transmission quality of the channel, ensures signal synchronization through a built-in clock data recovery circuit, and guarantees data integrity using a forward error correction mechanism. After acquiring the data frame, the receiver controller first performs error detection and correction, then unpacks and extracts the payload data, and finally sends the data to the designated storage area of ​​the target core via the internal bus.

[0037] This single-hop communication mechanism completely avoids the multi-level routing and arbitration overhead of traditional on-chip networks, enabling data transmission between any two processor cores to be completed on the shortest path. Through a dedicated channel parallel architecture and hardware-level protocol processing, it achieves microsecond-level end-to-end transmission latency and terabyte-per-second aggregated communication bandwidth, providing an efficient data exchange foundation for large-scale parallel computing tasks.

[0038] S107: The vertical access controller manages the processor core's direct access to the shared memory space.

[0039] Specifically, while achieving efficient lateral communication between processor cores, a vertical access controller establishes a direct access channel between each processor core and the shared memory space of the three-dimensional stack. When a processor core issues a memory access request, the vertical access controller first intelligently resolves and remaps the requested address, directing it to a specific memory partition in the shared memory space that has been optimized and configured.

[0040] The intelligent prefetch engine integrated within the vertical access controller continuously analyzes the processor's access patterns, identifying spatiotemporal locality characteristics of data access through machine learning algorithms. When a regular access sequence is detected, the prefetch engine loads potentially accessed data blocks from shared memory into the processor's local cache in advance. This process runs in parallel with the processor's computation operations, achieving temporal overlap between computation and data movement.

[0041] At the physical connectivity level, the vertical access controller is directly connected to the DRAM memory chips above via tens of thousands of vertical interconnect channels formed by hybrid bonding. These channels employ a grouped parallel architecture, supporting multiple read and write operations simultaneously. The controller integrates advanced memory scheduling algorithms that can reorder and merge access requests from different processors, maximizing the utilization of DRAM's line buffering capabilities and significantly improving effective bandwidth.

[0042] In particular, the vertical access controller works closely with the global flow control and arbitration unit. During large-scale data processing, the global flow control unit coordinates the prefetching strategy of the vertical access controller and the data transmission of the lateral communication controller based on the data demand patterns of each processor, achieving global optimization of memory access and inter-core communication. This collaborative mechanism ensures the orderly flow of data between the storage tier and the computing units, avoiding access conflicts and minimizing memory access latency.

[0043] This refined vertical memory access management enables efficient utilization of three-dimensional stacked memory resources, allowing multiple processor cores to concurrently access the shared memory space with extremely low latency, providing balanced memory access performance for data-intensive applications.

[0044] It effectively solves the problems of high data access latency and limited bandwidth caused by reliance on multi-hop transmission and arbitration of on-chip network (NoC), significantly reduces communication latency, and greatly improves system concurrent bandwidth and data throughput efficiency.

[0045] The above-disclosed embodiments are merely one or more preferred embodiments of this application and should not be construed as limiting the scope of this application. Those skilled in the art can understand that all or part of the processes for implementing the above embodiments and equivalent changes made in accordance with the claims of this application still fall within the scope of this application.

Claims

1. A method for designing a high-bandwidth, low-latency data transmission chip, characterized in that, Includes the following steps: Multiple processor cores are integrated on a logic chip, and each processor core integrates a local memory controller, a vertical access controller, and a lateral communication controller. A silicon interposer is provided, and a logic chip integrating the processor core is flip-chip bonded onto the silicon interposer. At least one dynamic random access memory chip is vertically integrated onto the logic chip using three-dimensional stacking technology to form a shared memory space; A lateral fully interconnected network is constructed inside the silicon interposer layer to establish a dedicated parallel data transmission channel between the lateral communication controllers of each pair of processor cores; A global flow control and arbitration unit is integrated on the logic chip to coordinate resource allocation in the horizontal fully interconnected network; Direct data communication between processor cores is achieved through the lateral communication controller, and single-hop communication is achieved using a dedicated parallel data transmission channel; The vertical access controller manages the processor core's direct access to the shared memory space.

2. The high-bandwidth, low-latency data transmission chip design method as described in claim 1, characterized in that, Direct data communication between processor cores is achieved through the lateral communication controller, and single-hop communication is implemented using a dedicated parallel data transmission channel, specifically including: Through the data packing / unpacking module and protocol processing unit integrated within the horizontal communication controller, independent of the computing unit of the processor core, it can directly perform data transfer operations between other horizontal communication controllers.

3. The high-bandwidth, low-latency data transmission chip design method as described in claim 2, characterized in that, A global flow control and arbitration unit is integrated on the logic chip to coordinate resource allocation in the horizontal fully interconnected network, specifically including: Real-time monitoring of the traffic status of each dedicated parallel data transmission channel; When a large-scale data transfer is detected between a pair of processor cores, multiple idle physical channels are dynamically bound to the lateral communication controller of that pair of processor cores to form a temporary aggregated communication link.

4. The high-bandwidth, low-latency data transmission chip design method as described in claim 3, characterized in that, A lateral fully interconnect network is constructed within the silicon interposer layer to establish a dedicated parallel data transmission channel between the lateral communication controllers of each pair of processor cores, specifically including: Two physical channels are configured in the horizontally interconnected network: a high-bandwidth parallel data channel, which adopts a low-voltage swing parallel differential signal transmission mechanism for transmitting batch data; and a low-latency control channel, which adopts an independent broadcast or ring topology for transmitting communication synchronization signals and buffer consistency control messages.

5. The high-bandwidth, low-latency data transmission chip design method as described in claim 4, characterized in that, The vertical access controller manages the processor core's direct access to the shared memory space, specifically including: The shared memory space is divided into multiple memory partitions at the logical address level, and each memory partition is associated with a specific data access mode. The intelligent prefetch engine integrated within the vertical access controller learns and identifies the memory access characteristic patterns of the currently executing thread. Memory access requests are dynamically mapped to the most suitable memory partition, and the data that will be accessed later is prefetched into the local cache of the processor core according to the preset prefetch strategy of that memory partition.

6. The high-bandwidth, low-latency data transmission chip design method as described in claim 5, characterized in that, The vertical access controller manages the processor core's direct access to the shared memory space, specifically including: Establish communication connections between the global flow control and arbitration unit and each intelligent prefetching engine; The global flow control and arbitration unit collaboratively optimizes the data prefetching strategy and the allocation and scheduling of lateral communication resources.

7. The high-bandwidth, low-latency data transmission chip design method as described in claim 6, characterized in that, A lateral fully interconnect network is constructed within the silicon interposer layer to establish a dedicated parallel data transmission channel between the lateral communication controllers of each pair of processor cores, specifically including: A dedicated parallel data transmission channel is implemented using a metal layer copper interconnect process, and the channel width is configured between 128 bits and 512 bits.

8. The high-bandwidth, low-latency data transmission chip design method as described in claim 7, characterized in that, At least one dynamic random access memory (DRAM) chip is vertically integrated onto the logic chip using a three-dimensional stacking technique to form a shared memory space, specifically including: The physical connection between the vertical access controller and the shared memory space is achieved through hybrid bonding technology.

Images