A resource scheduling and computing control system of a computing memory HAM

Abstract

The application provides a resource scheduling and computing control system of a computing type memory HAM, relates to the field of electric digital data processing, and comprises an intelligent resource allocation module, a heterogeneous computing cooperation module, a safety and reliability guarantee module and a self-adaptive optimization and monitoring module.The intelligent resource allocation module is responsible for the dynamic management and optimized allocation of internal resources of the HAM.The heterogeneous computing cooperation module is responsible for realizing intelligent decomposition, distribution and result synchronization of tasks.The safety and reliability guarantee module is used for providing encryption calculation, error correction detection and access control functions.The self-adaptive optimization and monitoring module is responsible for real-time monitoring and self-adaptive optimization of the system running state.The system fully gives play to the cooperative advantages of the DPU and the mixed storage in the HAM architecture, improves the computing efficiency, the energy efficiency ratio and the safety of the system, and is especially suitable for edge computing and mobile device scenes.

Description

Technical Field

[0001] This invention relates to the field of electronic digital data processing, and more specifically to a resource scheduling and computing control system for a computational memory HAM. Background Technology

[0002] With the rapid development of artificial intelligence and edge computing applications, the demands of computing systems for memory bandwidth, computing power, and energy efficiency continue to grow. Traditional computing architectures separate the processor and memory, and the frequent data transfer between the processor and memory has become a major bottleneck for system performance. To address this issue, various new computing architectures have emerged in recent years, among which computational memory chips with built-in data processing units (DPUs) have attracted widespread attention due to their ability to perform data processing directly on the memory side. These architectures typically use DDR dynamic random access memory as a cache, combined with NAND flash memory to form a hybrid storage system, balancing performance, capacity, and cost.

[0003] In this hybrid storage architecture, how to efficiently schedule data migration between DDR and NAND, how to rationally allocate memory resources between external processors and the built-in DPU, and how to coordinate their computing tasks become key issues affecting the overall system performance. Existing technologies have various memory controller scheduling algorithms and hybrid storage management methods, but most of these methods are designed for traditional single-processor architectures and do not fully consider the special needs of the DPU working collaboratively with external processors.

[0004] The commonly used memory scheduling algorithms in existing technologies mainly include the following three types. The first is the priority-based First-Come, First-Served (FCFS) scheduling algorithm. This algorithm serves memory access requests according to their arrival time, is simple to implement and has good fairness, but cannot distinguish the importance of different requests, easily leading to high-priority tasks being blocked by low-priority tasks, resulting in low overall system throughput. The second is the page hit rate-optimized FR-FCFS scheduling algorithm. This algorithm prioritizes requests that can hit already opened memory pages to reduce page switching overhead. Compared to the FCFS algorithm, it can significantly improve memory bandwidth utilization, but in multi-core systems, it can easily lead to some cores' requests not being served for a long time, resulting in poor fairness, and this algorithm does not consider the service quality requirements of different applications. The third is the ATLAS adaptive scheduling algorithm. This algorithm maintains statistics on the amount of service received for each thread, prioritizing the thread with the least service received. It can achieve a good balance between performance and fairness in multi-memory controller systems, but this algorithm requires complex coordination and information exchange between multiple memory controllers, resulting in high hardware implementation overhead, and it is not optimized for heterogeneous processors and hybrid storage. All three algorithms primarily focus on the access scheduling problem of a single type of memory, lacking comprehensive consideration of data migration timing, migration priority, and residency strategies in DDR-NAND hybrid storage systems, and also failing to address resource allocation and task coordination between external processors and DPUs.

[0005] In terms of patented technology, US Patent 11303472B2 discloses a data processing unit for compute nodes and storage nodes. This patent describes how the memory controller in the DPU can transfer ownership of cache segments among multiple processing cores, achieving data sharing between cores by refreshing cache segments and providing messages when there are no pending write operations. This patent mainly focuses on cache consistency management among multiple cores within the DPU, using message passing and cache refresh mechanisms to coordinate data access between cores. However, this solution only addresses cache management within the DPU and does not address the dynamic allocation of memory resources between the DPU and external processors, nor does it consider data migration scheduling strategies between DDR and NAND hybrid storage. Furthermore, it does not provide differentiated resource management methods for different computing task types such as inference computing and cryptographic computing. Therefore, it is difficult to apply to computing memory systems that require external processors and built-in DPUs to work together and employ a hybrid storage architecture.

[0006] Chinese patent WO2015010646A1 discloses a data access method for hybrid memory. This patent proposes adding a serial module to a hybrid memory system composed of DRAM and NVM, using an ECC error interrupt mechanism to migrate data from NVM to DRAM. When the memory controller accesses data that is not present in NRAM, the serial module intercepts the access request and triggers data migration. After migration, the access request is resent. This scheme avoids modifying the operating system code by utilizing the side effects of the ECC check mechanism to trigger data migration. However, this method is a passive, reactive data migration mechanism, only triggering migration when an access miss occurs. It lacks proactive access pattern prediction and preloading functions, failing to migrate potentially accessed data to DRAM in advance, resulting in high initial access latency. This patent does not consider the characteristics of dual-source access from external processors and the built-in DPU, and cannot perform targeted scheduling optimization based on the different access patterns and priority requirements of both. Furthermore, this scheme does not provide a mechanism for determining the residence time of data in DRAM or an eviction strategy based on access value, which can easily lead to frequent back-and-forth migrations and degrade system performance. Furthermore, the patent does not address the allocation of computing tasks between the external processor and the DPU, nor the resource isolation and security mechanisms for special computing tasks such as encrypted computing and error correction computing. Therefore, it is difficult to meet the comprehensive requirements of computing memory systems for resource scheduling, computing collaboration, and security and reliability. Summary of the Invention

[0007] The purpose of this invention is to address the shortcomings by proposing a resource scheduling and computing control system for a computational memory HAM.

[0008] The present invention adopts the following technical solution:

[0009] A resource scheduling and computing control system for a computational memory HAM includes an intelligent resource allocation module, a heterogeneous computing collaboration module, a security and reliability assurance module, and an adaptive optimization and monitoring module;

[0010] The intelligent resource allocation module is responsible for the dynamic management and optimized allocation of resources within the HAM; the heterogeneous computing collaboration module is responsible for the intelligent decomposition, distribution and result synchronization of tasks; the security and reliability assurance module is used to provide encrypted computing, error correction detection and access control functions; and the adaptive optimization and monitoring module is responsible for real-time monitoring and adaptive optimization of the system's operating status.

[0011] The intelligent resource allocation module includes a memory region dynamic partitioning unit, a DDR-NAND hybrid storage scheduling unit, and a load balancing and priority arbitration unit. The memory region dynamic partitioning unit adjusts the allocation ratio of DDR memory between the external processor and the DPU in real time according to the activation status of the DPU. The DDR-NAND hybrid storage scheduling unit is used to realize automatic data swapping between DDR and NAND. The load balancing and priority arbitration unit monitors the real-time load status of the external processor and the DPU.

[0012] The heterogeneous computing collaboration module includes a task decomposition and distribution unit, a computation result synchronization unit, and an instruction set extension interface unit. The task decomposition and distribution unit parses the composite computation tasks sent by the external processor. The computation result synchronization unit manages the timing of the return of DPU computation results to the external processor. The instruction set extension interface unit provides decoding and execution control of the DPU's dedicated instruction set.

[0013] The security and reliability assurance module includes an encrypted computing control unit, an error correction detection and repair unit, and an isolation and access control unit. The encrypted computing control unit receives external security instructions and schedules the security module to perform data encryption and decryption operations. The error correction detection and repair unit performs error correction code detection and repair on a specified address range according to external instructions. The isolation and access control unit is used to implement memory access permission isolation between the DPU and the external processor.

[0014] The adaptive optimization and monitoring module includes a performance monitoring and statistics unit, a power consumption management and energy saving unit, and a self-learning and strategy optimization unit. The performance monitoring and statistics unit collects performance indicators in real time and statistically analyzes the execution time and energy consumption data of different computing task types. The power consumption management and energy saving unit dynamically adjusts the operating frequency and voltage of the DPU according to the load. The self-learning and strategy optimization unit is used to automatically identify application characteristics and adjust the preloading strategy.

[0015] Furthermore, the DDR-NAND hybrid storage scheduling unit includes an access pattern prediction processor, a data migration processor, and a cache management processor. The access pattern prediction processor predicts future data access patterns by analyzing historical access sequences and generates preloading suggestions. The data migration processor moves data blocks between DDR and NAND and manages data consistency based on the prediction results and cache replacement algorithm. The cache management processor maintains hot data tags in DDR and determines the data residence time based on access frequency and timeliness.

[0016] Furthermore, the access pattern prediction processor calculates the overall access heat H(i) of data block i according to the following formula:

[0017] ;

[0018] in, This indicates the frequency at which data block i is accessed by an external processor. This indicates the frequency at which data block i is accessed by the DPU. Let i be the time interval since the last access to data block i. The time decay coefficient, This indicates the length of the sequential access sequence in which data block i participates. This is the sequential access gain coefficient. and The coefficient of coordination;

[0019] The access pattern prediction processor sorts all data blocks in NAND in descending order of access popularity H(i). When H(i) exceeds a preset preloading threshold, the data block is marked as a preloading candidate and a preloading suggestion list is generated and passed to the data migration processor.

[0020] Furthermore, the data migration processor calculates the migration benefit value G(i) of data block i according to the following formula:

[0021] ;

[0022] in, Indicates the average access latency of NAND. S(i) represents the average access latency of DDR, and S(i) represents the size of data block i. For memory bus bandwidth, This indicates the maximum tolerable migration time window. This indicates that DDR utilizes an adjustment function. For DDR utilization;

[0023] The data migration processor sorts the candidate data blocks in descending order of migration benefit G(i) and performs migration operations sequentially if DDR space allows. When DDR space is insufficient, it triggers the cache management processor to make an eviction decision to free up space.

[0024] Furthermore, the cache management processor calculates the retention value V(i) of data block i in DDR according to the following formula:

[0025] ;

[0026] in, This represents the cumulative amount of data in data block i that participated in the DPU computation. This indicates the total amount of data processed by the DPU. The contribution weighting coefficient is calculated for the DPU, where I(i) is the correlation between data block i and other data blocks in DDR. This is the correlation weighting coefficient;

[0027] When data needs to be evicted, the cache management processor prioritizes migrating the lowest-value data blocks back to NAND.

[0028] The beneficial effects achieved by this invention are:

[0029] This system calculates the overall access heat of data blocks using a dual-source weighted prediction algorithm. It adopts a power product approach, simultaneously considering the access frequencies of the external processor and the DPU, and combines this with a time decay factor and sequential access sequence length. This allows it to accurately identify the most valuable preloaded candidate data blocks. Compared to traditional single access frequency statistical methods, this effectively reduces cache miss rates. The data migration scheduling strategy based on migration benefit values ​​comprehensively considers latency improvement factors, migration time penalty factors, and DDR utilization adjustment functions. It can dynamically adjust migration decisions under different DDR load conditions, avoiding performance degradation caused by blind migration when DDR utilization is high. By maintaining value calculation, it introduces two dimensions: DPU computational contribution and data block correlation. Eviction decisions not only consider access heat but also the importance of data blocks in the computation graph, avoiding the negative impact of frequent evictions on DPU computational performance.

[0030] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the overall structural framework of the present invention;

[0032] Figure 2 This is a schematic diagram of the DDR-NAND hybrid storage scheduling process of the present invention;

[0033] Figure 3 This is a schematic diagram of the task decomposition and distribution mechanism of the present invention;

[0034] Figure 4 This is a schematic diagram illustrating the collaborative encryption and migration pipeline of the present invention;

[0035] Figure 5 This is a schematic diagram of the dynamic security domain switching of the present invention;

[0036] Figure 6 This is a schematic diagram comparing the average access latency of the present invention with other solutions;

[0037] Figure 7 This diagram illustrates a comparison of the DPU computational throughput of this invention with other solutions. Detailed Implementation

[0038] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention. Furthermore, the accompanying drawings of the present invention are for simple illustrative purposes only and are not depictions of actual dimensions; this is stated beforehand. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of protection of the present invention.

[0039] Example 1: This example provides a resource scheduling and computing control system for a computing-based memory HAM, including an intelligent resource allocation module, a heterogeneous computing collaboration module, a security and reliability assurance module, and an adaptive optimization and monitoring module;

[0040] The intelligent resource allocation module is responsible for the dynamic management and optimized allocation of resources within the HAM; the heterogeneous computing collaboration module is responsible for the intelligent decomposition, distribution and result synchronization of tasks; the security and reliability assurance module is used to provide encrypted computing, error correction detection and access control functions; and the adaptive optimization and monitoring module is responsible for real-time monitoring and adaptive optimization of the system's operating status.

[0041] The intelligent resource allocation module includes a memory region dynamic partitioning unit, a DDR-NAND hybrid storage scheduling unit, and a load balancing and priority arbitration unit. The memory region dynamic partitioning unit adjusts the allocation ratio of DDR memory between the external processor and the DPU in real time according to the activation status of the DPU. The DDR-NAND hybrid storage scheduling unit is used to realize automatic data swapping between DDR and NAND. The load balancing and priority arbitration unit monitors the real-time load status of the external processor and the DPU.

[0042] The heterogeneous computing collaboration module includes a task decomposition and distribution unit, a computation result synchronization unit, and an instruction set extension interface unit. The task decomposition and distribution unit parses the composite computation tasks sent by the external processor. The computation result synchronization unit manages the timing of the return of DPU computation results to the external processor. The instruction set extension interface unit provides decoding and execution control of the DPU's dedicated instruction set.

[0043] The security and reliability assurance module includes an encrypted computing control unit, an error correction detection and repair unit, and an isolation and access control unit. The encrypted computing control unit receives external security instructions and schedules the security module to perform data encryption and decryption operations. The error correction detection and repair unit performs error correction code detection and repair on a specified address range according to external instructions. The isolation and access control unit is used to implement memory access permission isolation between the DPU and the external processor.

[0044] The adaptive optimization and monitoring module includes a performance monitoring and statistics unit, a power consumption management and energy saving unit, and a self-learning and strategy optimization unit. The performance monitoring and statistics unit collects performance indicators in real time and statistically analyzes the execution time and energy consumption data of different computing task types. The power consumption management and energy saving unit dynamically adjusts the operating frequency and voltage of the DPU according to the load. The self-learning and strategy optimization unit is used to automatically identify application characteristics and adjust the preloading strategy.

[0045] The DDR-NAND hybrid storage scheduling unit includes an access pattern prediction processor, a data migration processor, and a cache management processor. The access pattern prediction processor predicts future data access patterns by analyzing historical access sequences and generates preloading suggestions. The data migration processor moves data blocks between DDR and NAND and manages data consistency based on the prediction results and cache replacement algorithm. The cache management processor maintains hot data tags in DDR and determines the data residence time based on access frequency and timeliness.

[0046] The access pattern prediction processor calculates the overall access heat H(i) of data block i according to the following formula:

[0047] ;

[0048] in, This indicates the frequency at which data block i is accessed by an external processor. This indicates the frequency at which data block i is accessed by the DPU. Let i be the time interval since the last access to data block i. The time decay coefficient, This indicates the length of the sequential access sequence in which data block i participates. This is the sequential access gain coefficient. and The coefficient of coordination;

[0049] The access pattern prediction processor sorts all data blocks in NAND in descending order of access popularity H(i). When H(i) exceeds a preset preloading threshold, the data block is marked as a preloading candidate and a preloading suggestion list is generated and passed to the data migration processor.

[0050] The data migration processor calculates the migration benefit value G(i) of data block i according to the following formula:

[0051] ;

[0052] in, Indicates the average access latency of NAND. S(i) represents the average access latency of DDR, and S(i) represents the size of data block i. For memory bus bandwidth, This indicates the maximum tolerable migration time window. This indicates that DDR utilizes an adjustment function. For DDR utilization;

[0053] The data migration processor sorts the candidate data blocks in descending order of migration benefit G(i) and performs migration operations sequentially if DDR space allows. When DDR space is insufficient, it triggers the cache management processor to make an eviction decision to free up space.

[0054] The cache management processor calculates the retention value V(i) of data block i in DDR according to the following formula:

[0055] ;

[0056] in, This represents the cumulative amount of data in data block i that participated in the DPU computation. This indicates the total amount of data processed by the DPU. The contribution weighting coefficient is calculated for the DPU, where I(i) is the correlation between data block i and other data blocks in DDR. This is the correlation weighting coefficient;

[0057] When data needs to be evicted, the cache management processor prioritizes migrating the lowest-value data blocks back to NAND.

[0058] Example 2: This example includes all the contents of Example 1, and provides a resource scheduling and computing control system for a computing-based memory HAM, including an intelligent resource allocation module, a heterogeneous computing collaboration module, a security and reliability assurance module, and an adaptive optimization and monitoring module;

[0059] The intelligent resource allocation module is responsible for the dynamic management and optimized allocation of resources within the HAM; the heterogeneous computing collaboration module is responsible for the intelligent decomposition, distribution and result synchronization of tasks; the security and reliability assurance module is used to provide encrypted computing, error correction detection and access control functions; and the adaptive optimization and monitoring module is responsible for real-time monitoring and adaptive optimization of the system's operating status.

[0060] The intelligent resource allocation module includes a memory region dynamic partitioning unit, a DDR-NAND hybrid storage scheduling unit, and a load balancing and priority arbitration unit. The memory region dynamic partitioning unit adjusts the allocation ratio of DDR memory between the external processor and the DPU in real time according to the activation status of the DPU. The DDR-NAND hybrid storage scheduling unit is used to intelligently predict data access patterns and realize automatic data swapping between DDR and NAND. The load balancing and priority arbitration unit monitors the real-time load status of the external processor and the DPU and arbitrates bus bandwidth and computing resources when multiple tasks are concurrent.

[0061] The heterogeneous computing collaboration module includes a task decomposition and distribution unit, a computation result synchronization unit, and an instruction set extension interface unit. The task decomposition and distribution unit parses the composite computing tasks sent by the external processor, identifies the computation parts that can be offloaded to the DPU, and automatically routes them to the corresponding computing units according to the task characteristics. The computation result synchronization unit manages the timing of the return of DPU computation results to the external processor and implements an interrupt or polling notification mechanism for the computation completion status. The instruction set extension interface unit provides decoding and execution control of the DPU-specific instruction set, realizing instruction-level pipeline optimization and parallelism control.

[0062] The security and reliability assurance module includes an encrypted computing control unit, an error correction detection and repair unit, and an isolation and access control unit. The encrypted computing control unit receives external security instructions and schedules the security module to perform data encryption and decryption operations. It supports dynamic switching of multiple encryption algorithms and implements key management and security state machine control. The error correction detection and repair unit performs error correction code detection and repair on a specified address range according to external instructions and monitors the data integrity of DDR and NAND in real time. The isolation and access control unit is used to implement memory access permission isolation between the DPU and the external processor.

[0063] The adaptive optimization and monitoring module includes a performance monitoring and statistics unit, a power consumption management and energy saving unit, and a self-learning and strategy optimization unit. The performance monitoring and statistics unit collects performance indicators in real time and counts the execution time and energy consumption data of different computing task types. The power consumption management and energy saving unit dynamically adjusts the working frequency and voltage of the DPU according to the load. The self-learning and strategy optimization unit optimizes resource allocation and scheduling strategies based on historical running data, automatically identifies application characteristics, and adjusts the preloading strategy.

[0064] The memory region dynamic partitioning unit includes an allocation strategy processor, an address mapping processor, and a defragmentation processor. The allocation strategy processor calculates the memory allocation ratio and generates an allocation scheme based on the DPU activation state and application scenario requirements. The address mapping processor dynamically maps physical memory addresses to the logical address spaces of external processors and DPUs and maintains an address translation table. The defragmentation processor detects the degree of memory fragmentation and performs memory region defragmentation and migration operations when the system is idle.

[0065] The DDR-NAND hybrid storage scheduling unit includes an access pattern prediction processor, a data migration processor, and a cache management processor. The access pattern prediction processor predicts future data access patterns by analyzing historical access sequences and generates preloading suggestions. The data migration processor moves data blocks between DDR and NAND and manages data consistency based on the prediction results and cache replacement algorithm. The cache management processor maintains hot data tags in DDR and determines the data residence time based on access frequency and timeliness.

[0066] The access pattern prediction processor calculates the overall access heat H(i) of data block i according to the following formula:

[0067] ;

[0068] in, This indicates the frequency at which data block i is accessed by an external processor. This indicates the frequency at which data block i is accessed by the DPU. Let i be the time interval since the last access to data block i. The time decay coefficient, This indicates the length of the sequential access sequence in which data block i participates. This is the sequential access gain coefficient. and The coefficient of coordination;

[0069] The access pattern prediction processor sorts all data blocks in NAND in descending order of access popularity H(i). When H(i) exceeds the preset preloading threshold, the data block is marked as a preloading candidate and a preloading suggestion list is generated and passed to the data migration processor.

[0070] The data migration processor calculates the migration benefit value G(i) of data block i according to the following formula:

[0071] ;

[0072] in, Indicates the average access latency of NAND. S(i) represents the average access latency of DDR, and S(i) represents the size of data block i. For memory bus bandwidth, This indicates the maximum tolerable migration time window. This indicates that DDR utilizes an adjustment function. For DDR utilization;

[0073] The data migration processor arranges the candidate data blocks in descending order according to the migration benefit G(i), and performs migration operations in sequence as long as DDR space allows. When DDR space is insufficient, the cache management processor is triggered to make an eviction decision to free up space.

[0074] The cache management processor calculates the retention value V(i) of data block i in DDR according to the following formula:

[0075] ;

[0076] in, This represents the cumulative amount of data in data block i that participated in the DPU computation. This indicates the total amount of data processed by the DPU. The contribution weighting coefficient is calculated for the DPU, where I(i) is the correlation between data block i and other data blocks in DDR. This is the correlation weighting coefficient;

[0077] When data needs to be evicted, the cache management processor prioritizes migrating the lowest-value data blocks back to NAND.

[0078] Combination Figure 2 It describes the scheduling process for DDR-NAND hybrid storage;

[0079] The load balancing and priority arbitration unit includes a load monitoring processor, a bandwidth arbitration processor, and a service quality management processor. The load monitoring processor collects load indicators such as task queue length, computing utilization, and bus occupancy of external processors and DPUs in real time. The bandwidth arbitration processor allocates memory bus bandwidth and schedules access times according to priority and fairness principles when multiple access requests compete. The service quality management processor sets minimum resource guarantees for critical tasks and preempts resource quotas for low-priority tasks when resources are scarce.

[0080] The task decomposition and distribution unit includes a task parsing processor, an unloadability determination processor, and a task routing processor. The task parsing processor receives a task description sent by an external processor and decomposes the composite task into multiple sub-task units. The unloadability determination processor determines whether the sub-tasks are suitable for unloading to the DPU for execution based on their computational characteristics and evaluates the unloading benefits. The task routing processor distributes the unloadable sub-tasks to the inference, encryption, or error correction units of the DPU according to their type and manages task dependencies.

[0081] Combination Figure 3 The task decomposition and distribution unit has an intelligent computing path selection mechanism. This mechanism dynamically determines whether to execute the task directly on an external processor, completely offload it to the DPU, or adopt a collaborative execution mode based on the task characteristics. The task decomposition and distribution unit maintains a task characteristic database, which records the execution efficiency ratio, energy consumption ratio, and latency characteristics of different types of computing tasks on external processors and DPUs. When a new task is received, the task parsing processor first extracts characteristic parameters such as the task's computational density, data dependencies, and memory access patterns. Then, the offloadability determination processor calculates the comprehensive benefit score of the task under the three execution modes by querying the task characteristic database and combining it with the current system load status, and selects the execution mode with the highest score. For tasks adopting the collaborative execution mode, the task routing processor decomposes the task into multiple subtasks, where computationally intensive subtasks are offloaded to the DPU for execution, while control-intensive subtasks are retained for execution on the external processor. A pipeline scheduling mechanism is used to enable both to work in parallel to hide data transmission latency.

[0082] The calculation result synchronization unit includes a result buffer processor, a transmission scheduling processor, and a notification mechanism processor. The result buffer processor allocates a buffer for the DPU calculation results and manages the temporary storage and queuing of result data. The transmission scheduling processor arranges the return timing of result data according to the receiving capability of the external processor and the available bus bandwidth and supports streaming transmission. The notification mechanism processor notifies the external processor and provides the address information of the result data through an interrupt signal or status register when the calculation is completed.

[0083] The instruction set extension interface unit includes an instruction decoding processor, an operator loading processor, and a pipeline control processor. The instruction decoding processor identifies the opcodes in the DPU-specific instruction set and parses the instruction parameters and operand addresses. The operator loading processor supports the dynamic loading of custom operators and maps the operators to the hardware execution units of the DPU. The pipeline control processor manages the pipeline stages of instruction execution and improves instruction throughput through out-of-order execution and parallel scheduling.

[0084] The instruction set extension interface unit supports dynamic instruction fusion optimization technology. When decoding the DPU instruction stream, the instruction decoding processor maintains a sliding window to detect consecutive instruction patterns. When a fusionable instruction sequence is detected, the pipeline control processor merges these instructions into a fusion instruction atomic operation and directly schedules it to the DPU's hardware execution unit for parallel execution. The operator loading processor also supports user-defined fusion rules, allowing for the customization of dedicated instruction fusion modes for specific application scenarios. These predefined rules are loaded into the instruction set extension interface unit in the form of configuration files and take effect dynamically at runtime.

[0085] Combination Figure 4 The encryption computing control unit includes a security instruction parsing processor, an encryption engine scheduling processor, and a key management processor. The security instruction parsing processor receives and parses externally sent security instructions and determines the type and parameters of the encryption operation. The encryption engine scheduling processor selects an appropriate encryption algorithm according to the instruction requirements and schedules the hardware encryption module to perform encryption or decryption operations. The key management processor securely stores and manages encryption keys and controls the lifecycle and access permissions of the keys.

[0086] The error correction detection and repair unit includes an error correction code calculation processor, an error location processor, and a data repair processor. The error correction code calculation processor calculates an error correction check code for data within a specified address range and compares it with a stored check code. When an error is detected, the error location processor locates the specific position of the error bit and determines the repairability of the error. The data repair processor performs bit flipping repair on repairable errors and writes the repaired data back to memory or marks bad blocks for data migration.

[0087] Combination Figure 5 The isolation and access control unit includes a permission verification processor, a security domain partitioning processor, and an access monitoring processor. The permission verification processor checks the identity and permissions of the access source during each memory access and rejects unauthorized access requests. The security domain partitioning processor divides the memory space into multiple security domains and sets access control policies and isolation boundaries for each security domain. The access monitoring processor records all memory access behaviors and triggers security alarms when abnormal access patterns are detected.

[0088] The performance monitoring and statistics unit includes a performance counter, a data acquisition processor, and a report generation processor. The performance counter records the values ​​of key performance indicators such as DPU computing throughput, memory bandwidth utilization, and cache hit rate in real time. The data acquisition processor periodically reads the data from the performance counter and classifies and statistically analyzes the execution time and energy consumption of different computing task types. The report generation processor analyzes and visualizes the collected performance data and generates a performance report for external software tuning reference.

[0089] The power management and energy-saving unit includes a load assessment processor, a dynamic voltage and frequency adjustment processor, and a low-power mode controller. The load assessment processor calculates the optimal operating frequency and voltage level required by the DPU based on the current task load and performance requirements. The dynamic voltage and frequency adjustment processor adjusts the power supply voltage and clock frequency of the DPU in real time based on the assessment results and balances performance and power consumption. When the system is detected to be idle, the low-power mode controller switches the DPU and DDR to a low-power state and adjusts the DDR refresh rate to reduce standby power consumption.

[0090] The self-learning and strategy optimization unit includes a historical data analysis processor, a feature recognition processor, and a strategy adjustment processor. The historical data analysis processor collects and analyzes the historical performance data and resource usage patterns of the system. The feature recognition processor extracts application features from the historical data and identifies the access patterns and computing characteristics of different application scenarios. The strategy adjustment processor automatically optimizes resource allocation strategies, adjusts preload parameters, and supports manual fine-tuning based on user feedback based on the identified features.

[0091] The 'i' mentioned above is an ordinal number used to represent the sequence number and has no actual meaning;

[0092] To verify the beneficial effects of this invention, an experimental platform based on a computationally oriented memory-based HAM prototype system was built for comparative testing. The experimental platform uses a HAM chip with a built-in DPU as the core computing unit. This chip integrates 8GB of DDR4 memory and 800GB of NAND flash memory to form a hybrid storage system. The DPU contains 16 inference computing cores, and the external processor uses a quad-core ARM Cortex-A78 architecture. The system operates at a frequency of 2.0GHz, and the memory bus bandwidth is 32GB / s. Deep learning inference tasks were selected as the typical workload for the experiments, using two classic neural network models: ResNet-50 and MobileNet-v2. The test dataset contained 10,000 image samples. Each experiment ran continuously for one hour, and the average performance metrics were recorded.

[0093] First, a pure DDR system was configured as a control group without hybrid storage, with an average access latency of 280 nanoseconds. Then, a hybrid storage scheme based on passive migration was implemented, where data migration from NAND to DDR was triggered only when an access miss occurred, resulting in an average latency of 195 nanoseconds. Finally, the active prediction and migration benefit evaluation scheduling scheme of this invention was deployed, with an average latency of 112 nanoseconds. Experimental results show that the proposed scheme reduces latency by 60% compared to the system without hybrid storage and by 43% compared to the passive migration scheme. The significant reduction in latency stems from the fact that the calculation of the migration benefit value G(i) comprehensively considers the latency improvement factor, migration time penalty factor, and DDR utilization adjustment function, enabling dynamic adjustment of migration decisions under different load conditions and avoiding performance degradation caused by blind migration.

[0094] First, a simple FIFO (First-In, First-Out) eviction policy was implemented as a baseline, achieving a DPU inference throughput of 3.2 TOPS. Then, an access frequency-based eviction policy was implemented, prioritizing the eviction of low-frequency access data, achieving a throughput of 3.8 TOPS. Finally, the eviction decision mechanism based on the preservation value V(j) of this invention was deployed, achieving a throughput of 4.6 TOPS. Experimental results show that the method of this invention improves throughput by 44% compared to the simple eviction policy and by 21% compared to frequency-based eviction. The key to the performance improvement lies in the fact that the preservation value calculation not only considers access frequency but also introduces two dimensions: DPU computational contribution and data block correlation. This avoids the negative impact of frequent evictions on DPU computational performance, allowing data blocks in critical positions in the computation graph to continuously reside in DDR.

[0095] The data was organized and obtained Figure 6 and Figure 7 ;

[0096] Example 3: This example provides a resource scheduling and computing control system for a computational memory HAM, applied to mobile edge computing server scenarios. The hardware platform in this example uses a QC-HAM-5000 HAM chip with a built-in DPU. This chip integrates 16GB LPDDR5-6400 memory with a working frequency of 6400MHz and a bandwidth of 51.2GB / s, and 1.6TB of enterprise-grade 3D NAND flash memory, model Micron B47R, using a PCIe 4.0x4 interface with a sequential read speed of 7000MB / s. The DPU adopts a 32-core architecture, with each core containing 256 INT8 operation units and 64 FP16 operation units, achieving a peak computing power of 128 TOPS, and integrating 4MB of L2 cache. The external processor is an Intel Xeon Silver 4314 processor with 16 cores and 32 threads, a base frequency of 2.4GHz, and 24MB of L3 cache. The system runs on CentOS 8, uses ONNX Runtime version 1.12 as the deep learning inference framework, and Intel IPP Cryptography 2021.5 as the encryption library.

[0097] The memory region dynamic partitioning unit in the intelligent resource allocation module adopts a page table mapping-based implementation. The allocation strategy processor maintains a 16,384-entry address mapping table, each corresponding to a 4KB physical page, covering a total of 64GB of virtual address space. This mapping table uses a two-level page table structure, with 1,024 entries in the first-level page table, each pointing to a second-level page table with 16 entries, achieving fast address translation. The address mapping processor marks a page as belonging to the external processor access domain, DPU access domain, or shared access domain by modifying the attribute bits of the page table entries. The page table switching latency is controlled within 50 nanoseconds, and the most recent 256 page table entries are cached through the TLB, achieving a hit rate of up to 95%. When the DPU switches from an inactive state to an active state, the allocation strategy processor allocates 16GB of DDR according to the ratio of 8GB for the external processor, 6GB for the DPU, and 2GB for the shared area. The address mapping processor completes the page table remapping operation within 200 microseconds. The defragmentation processor employs a background compression migration algorithm, automatically starting when system load is below 30% and triggering defragmentation when fragmentation exceeds 20%. The migration speed is approximately 1GB / s. The defragmentation process utilizes copy-on-write technology to ensure that currently accessed pages are unaffected. During testing of the BERT-Large model inference task, the external processor handled tokenization, consuming 2.3GB of memory, while the DPU handled Transformer layer computations, consuming 5.8GB of memory. Dynamic adjustments increased memory utilization from a fixed allocation of 72% to 91%.

[0098] The DDR-NAND hybrid storage scheduling unit employs a multi-level cache architecture. The access pattern prediction processor uses a Bloom filter and a minimum count sketch to statistically analyze access frequency. The Bloom filter is 64KB in size, uses three hash functions, and has a false positive rate below 1%. The minimum count sketch uses four rows, each with 8192 counters, each counter being 16 bits. The prediction processor scans once per second, extracting data blocks with access counts exceeding a threshold to generate a preload candidate list of 1024 items sorted by access frequency. For identified sequential access patterns, the prediction processor automatically triggers a prefetch operation, preloading the weighted data of the subsequent three layers. The prefetch window size is 12MB, and the measured prefetch hit rate reaches 83%. The data migration processor implements a priority queue scheduling mechanism, maintaining three priority queues (high, medium, and low). Each queue is organized using a red-black tree structure and sorted according to migration benefit value. The migration processor is equipped with four DMA channels, each capable of independently performing NAND-to-DDR data transfer. A single channel has a bandwidth of 1.75GB / s, and the total bandwidth reaches 7GB / s when all four channels are running concurrently. DMA transfer employs a scatter-gather mode, supporting the transfer of data blocks scattered across multiple physical pages in a single transaction. CRC32 checksums are used during transfer to ensure data integrity, with a measured migration time of approximately 600 microseconds for a 4MB data block. The cache management processor implements a partitioned LRU algorithm, dividing the DDR cache space into eight 2GB partitions, each maintaining its own independent LRU list to avoid global lock contention. During eviction, a candidate data block is selected from the tail of each of the eight partitions' LRU lists, its retention value is calculated, and the block with the lowest value is evicted, with eviction decision latency controlled within 5 microseconds. In the YOLO-v5 object detection task, the cache management processor sets the retention value of feature map data in the detection backbone network as high priority for residing in DDR, while setting temporary calculation results as low priority for eviction, resulting in a 33% improvement in detection throughput from 24 FPS to 32 FPS.

[0099] As a variation of the implementation, the dynamic memory region partitioning unit can adopt a segmented memory management approach instead of paged management, dividing the memory into several logical segments, each with a variable size. The advantage is that the segment size can be flexibly adjusted, reducing internal fragmentation. The disadvantage is that external fragmentation may occur, requiring more frequent defragmentation. The access pattern prediction processor can use an LSTM neural network-based prediction model instead of statistical methods. It uses a two-layer LSTM with 128 hidden units per layer. The input is the access sequence of the most recent 32 time steps, and the output is the top 100 data blocks most likely to be accessed in the next time step. The model's inference latency on the DPU is approximately 2 milliseconds, and the prediction accuracy can reach 92%, which is 3 percentage points higher than statistical methods. The disadvantage is that it requires pre-training and occupies approximately 8MB of memory.

[0100] The task decomposition and distribution unit in the heterogeneous computing collaboration module is optimized for large language models based on the Transformer architecture. The task parsing processor can identify standard modules such as multi-head attention layers, feedforward neural network layers, and normalization layers. For the GPT-3 175B parameter model, the task parsing processor decomposes it into 96 Transformer blocks, totaling 192 subtasks. The offloadability determination processor maintains a task feature database that records the execution time and energy consumption of each subtask on the external processor and DPU. For example, the multi-head attention subtask requires 45 milliseconds and 8 watts of power to execute on the external processor, while it requires 12 milliseconds and 5 watts of power to execute on the DPU. The determination processor calculates the offloading benefit based on the database query results. If the offloading benefit is positive, it determines to offload the subtask; if it is negative, it is retained for execution on the external processor. For the GPT-3 model, 96% of the subtasks are determined to be suitable for offloading to the DPU for execution, while only 4% of the normalization and control logic subtasks are retained on the external processor. The task routing processor uses a directed acyclic graph (DAG) to represent the dependencies between tasks, performs topological sorting on the DAG to determine the task execution order, and implements a critical path analysis algorithm to prioritize scheduling tasks on the critical path. In actual testing, the GPT-3 inference latency using the cooperative execution mode is 980 milliseconds, a 69% reduction compared to 3200 milliseconds for all-CPU execution and a 15% reduction compared to 1150 milliseconds for all-DPU execution. The task feature database uses an embedded SQLite 3.36 database with a storage capacity of approximately 120MB, containing performance feature data for 50 common neural network operations. The query latency is approximately 100 microseconds, and B-tree indexes are used to accelerate queries. Online updates are supported, triggered when the actual execution time deviates from the database record by more than 20%.

[0101] The result synchronization unit employs a circular buffer for efficient result transmission. The result buffer processor allocates a dedicated 16MB circular buffer to each DPU core, capable of holding approximately 200 medium-sized computation results. The circular buffer uses a producer-consumer model, with the DPU acting as the producer writing results and the external processor as the consumer reading them. Lock-free synchronization is achieved through atomic read / write pointer operations, avoiding the performance overhead of mutex locks. In actual testing, the circular buffer achieved a throughput of up to 8GB / s under high load, with a latency of approximately 150 nanoseconds. The transmission scheduling processor implements a priority-based bandwidth allocation mechanism, dividing computation results into three categories: urgent, normal, and low priority. A weighted fair queue (WFQ) algorithm is used to allocate bandwidth with a weight ratio of 5:3:2. In actual testing under mixed load, the latency for urgent results remained at 4.2 milliseconds, while the latencies for normal and low-priority results were 18 milliseconds and 85 milliseconds, respectively. The notification mechanism processor supports both interrupt and polling modes. In interrupt mode, the latency is approximately 500 nanoseconds, suitable for low-latency scenarios, but frequent interrupts incur context switching overhead, with each switch taking approximately 2 microseconds. In polling mode, the period can be configured from 1 millisecond to 100 milliseconds, with a polling overhead of approximately 100 nanoseconds, but this may increase result latency. Actual testing shows that for object detection tasks, the end-to-end latency in interrupt mode is 25 milliseconds, while the latency in polling mode is 33 milliseconds.

[0102] The instruction set extension interface unit implements a DPU instruction set architecture containing 128 dedicated instructions. The instruction format uses 32-bit fixed-length encoding, with the first 8 bits being the opcode, the middle 16 bits being the operand address, and the last 8 bits being flag bits. The instruction decoding processor adopts a two-stage pipeline design, with a decoding throughput of 2 instructions per cycle, maintaining a 128-entry instruction decoding table, and a table lookup latency of 1 clock cycle. The operator loading processor supports loading custom operators via dynamic link libraries. User-written operator code is compiled into shared library files in .so format. The operator loading processor calls the dlopen function to load the shared library and uses the dlsym function to obtain function pointers and register them in the operator table. Actual measurements show that the call overhead for custom operators is approximately 500 nanoseconds. The dynamic instruction fusion optimization technology implements a fusion pattern matching engine, maintaining 32 predefined fusion patterns. Each pattern is described in regular expression form, such as the CONV-BN-RELU pattern. The matching engine uses a sliding window algorithm with a window size of 8 instructions, moving one instruction in each scan to match the fusion pattern. In actual testing, the execution time of the CONV-BN-RELU fusion instruction is 62% of that of the standard three instructions, saving 38% of the execution cycle. This is mainly due to the elimination of intermediate result write-back and re-read overhead (approximately 25%) and instruction scheduling overhead (approximately 13%). Users can add custom fusion modes through a JSON format configuration file, and the operator loading processor parses the configuration file and registers the new fusion mode at startup.

[0103] As a modified implementation, the computation result synchronization unit can replace the circular buffer with a zero-copy transfer method based on shared memory. The DPU and the external processor share the same physical memory region. The DPU writes the computation results directly to the shared memory, and the external processor accesses the result data through memory mapping without data copying. This method has a lower latency of approximately 50 nanoseconds, but requires a more complex synchronization mechanism and is suitable for scenarios with large amounts of result data. The instruction set extension interface unit can replace the standard RISC instruction set with a VLIW (Very Long Instruction Word) architecture. VLIW instructions contain multiple opcodes that can control multiple execution units simultaneously. The advantage is higher instruction-level parallelism and throughput can be increased by 50%. The disadvantage is increased compiler complexity, making it suitable for computationally intensive applications with fewer dependencies between instructions.

[0104] The encryption computing control unit in the security and reliability assurance module integrates the Intel AES-NI instruction set and the national cryptographic SM4 algorithm hardware accelerator. The security instruction parsing processor supports six encryption instructions, including AES-128 encryption, AES-128 decryption, AES-256 encryption, AES-256 decryption, SM4 encryption, and SM4 decryption. Each instruction supports three modes: ECB, CBC, and CTR. The instruction format is 64-bit, including an 8-bit opcode, an 8-bit mode code, a 32-bit data address, and a 16-bit length field. The encryption engine scheduling processor manages four hardware encryption engines: two AES engines and two SM4 engines. The AES engines are implemented based on Intel AES-NI, with a single-engine throughput of approximately 10GB / s and a latency of approximately 100 nanoseconds. The SM4 engines have a single-engine throughput of approximately 6GB / s and a latency of approximately 150 nanoseconds. The scheduling processor uses a round-robin scheduling algorithm to allocate encryption tasks sequentially to idle engines. In actual testing under mixed encryption loads, the concurrent throughput of the four engines reached 32GB / s, with a utilization rate of 94%. The key management processor implements a hierarchical key system. The root key is stored in a one-time programmable eFuse inside the chip; this 128-bit key cannot be changed or read after being programmed. Working keys are stored in a key storage area protected by the root key, which is 8KB of on-chip SRAM and cannot be directly accessed externally. Key lifecycle management includes key generation, key distribution, key rotation (automatic replacement every 7 days), and key destruction. Actual key loading operations take approximately 2 milliseconds, and key rotation operations take approximately 50 milliseconds. In the specific implementation of the pipelined collaborative mechanism, when the migration processor initiates NAND to DDR transfer, it sends the data block identifier and address information to the parsing processor. The parsing processor queries the encryption attribute table of the data block; if decryption is required, it configures a hardware decryption path, inserting an AES or SM4 engine into the data path of the memory bus. After data is read from NAND, it is sent to the decryption engine via the DMA controller. The decryption engine uses an 8-stage pipeline structure, processing 16 bytes of data per stage, achieving a throughput of 32GB / s. The measured migration encryption and decryption time for a 4MB encrypted data block is 650 microseconds, which is only 50 microseconds more than the standard migration time of 600 microseconds, representing an increase of about 8% overhead.

[0105] The error correction and repair unit employs two schemes: BCH error correction code and LDPC low-density parity-check code. The error correction code calculation processor uses BCH(128,120,2) code for DDR data, capable of correcting 2-bit errors and detecting 3-bit errors. For NAND data, it uses LDPC(4096,3584) code, capable of correcting up to 256-bit errors. The error location processor implements a synodal decoding algorithm. For BCH code, it calculates the synodal expression of the received codeword, solves the error location polynomial, and uses the Qian search algorithm to find the error location. The calculation delay is approximately 50 nanoseconds, with a maximum of 128 Qian search iterations and a worst-case delay of approximately 2 microseconds. For LDPC code, it uses a belief propagation BP decoding algorithm, with a maximum of 20 iterations and a decoding delay of approximately 100 microseconds. The data repair processor implements a multi-level repair strategy. For correctable errors detected in DDR, it immediately performs bit-flip repair, writes the correct data back to DDR, and updates the ECC code. For uncorrectable errors, it marks the page as a bad page, prohibits its reuse, and allocates a new page from the redundant area for data reconstruction. For errors detected in NAND, LDPC decoding and repair are first attempted. If the repair is successful, the data is migrated to a new physical block, and the original physical block is marked as a bad block. In actual tests of manually injected errors, the DDR single-bit error rate is approximately 0.8 times per GB per hour, and the system can automatically repair 100%. The NAND page error rate is approximately 2.3 times per TB per hour, with a repair success rate of 99.7%.

[0106] The isolation and access control unit implements a capability-based access control mechanism. The permission verification processor assigns a capability token to each access request. The capability token is a 128-bit data structure containing a 32-bit subject identifier, a 32-bit object identifier, a 32-bit permission bitmap, a 16-bit expiration timestamp, and a 16-bit signature verification code. Access requests must include a valid capability token. The permission verification processor verifies the signature verification code, checks the expiration date and permission bitmap, with a verification latency of approximately 300 nanoseconds. In actual testing under high concurrency, approximately 3.3 million capability token verification requests are processed per second. The security domain partitioning processor divides the 16GB DDR into eight security domains, each 2GB. Domain 0 is a system reserved domain, domain 1 is an external processor user space domain, domains 2 through 4 are DPU inference computing domains, domain 5 is an encryption computing domain, domain 6 is an error correction computing domain, and domain 7 is a shared domain. Each domain has an independent Access Control List (ACL). Security domains are isolated through hardware. The Memory Management Unit (MMU) is configured in domain-aware mode; cross-domain access is hardware-blocked and triggers an access violation exception. Domain switching operations are executed via the privileged instruction SET_DOMAIN, with a latency of approximately 5 microseconds. In real-world testing, under scenarios involving frequent switching between inference, encryption, and error correction tasks, the domain switching overhead accounts for only 0.8% of the total execution time, having a negligible impact on system performance. The access monitoring processor is equipped with a 16MB circular log buffer, recording all memory access events. Log entries include timestamps, source addresses, destination addresses, access types, and results. Log recording is implemented using a lock-free queue, with a log write latency of approximately 50 nanoseconds. The anomaly detection module analyzes the log stream to identify suspicious access patterns, employing a sliding window statistical algorithm with a 1-second window size. A security alarm is triggered when the access failure rate exceeds a 5% threshold. In attack simulation tests, the system can detect brute-force attacks within 1 second, with an average detection latency of approximately 600 milliseconds.

[0107] The performance monitoring and statistics unit in the adaptive optimization and monitoring module combines hardware performance counters and software acquisition agents. Each computing core of the DPU is equipped with eight programmable counters, capable of monitoring performance events such as the number of executed instructions, clock cycles, cache hits, and memory accesses. The external processor is also equipped with an Intel Performance Monitoring Unit (PMU), supporting the monitoring of approximately 200 performance events; this system selects 12 key events. The data acquisition processor runs on a dedicated core of the external processor, periodically reading the performance counters. The default reading cycle is 100 milliseconds. The raw data is stored in a 512MB circular buffer, capable of storing approximately one hour of detailed performance data. In actual testing on the ResNet-50 inference task, the DPU achieved an average IPC of 2.3, an L2 cache hit rate of 92%, and a memory bandwidth utilization of 68%. The report generation processor generates a performance report hourly, including time-series graphs, hotspot analysis graphs, resource utilization distribution graphs, and task type statistics graphs. The report is in HTML format, includes interactive charts, and is approximately 2MB in size. Generating one report takes approximately 15 seconds.

[0108] The power management and energy-saving unit implements two energy-saving technologies: Dynamic Voltage and Frequency Scaling (DVFS) and power gating. The load assessment processor evaluates the system load every 50 milliseconds, collecting data on the task queue length, current instruction execution rate, and the predicted task load for the next second. The assessment algorithm uses an exponentially weighted moving average (EWMA) to predict future load and calculates the required operating frequency and voltage based on the predicted load. The DPU supports five frequency levels: 800MHz, 1.2GHz, 1.6GHz, 2.0GHz, and 2.4GHz, corresponding to voltages of 0.8V, 0.9V, 1.0V, 1.1V, and 1.2V. The dynamic voltage and frequency scaling processor sends frequency and voltage adjustment commands to the power management integrated circuit (PMIC), model TI TPS65987, based on the assessment results. The entire adjustment process takes approximately 800 microseconds. In actual testing under light load conditions, when the DPU frequency is reduced to 1.2GHz, power consumption decreases from the nominal 18 watts to 7 watts, a reduction of approximately 61%, while performance only decreases by about 40%. The low-power mode controller implements four power-saving modes: Mode 0 is the normal operating mode; Mode 1 is a light power-saving mode where idle cores enter a clock-gated state and can be woken up within 1 microsecond; Mode 2 is a medium power-saving mode where idle cores enter a power-gated state and require 10 microseconds to wake up; and Mode 3 is a deep sleep mode where the entire DPU subsystem requires 1 millisecond to wake up after a power outage. In actual testing, DPU power consumption decreased from 18 watts to 12 watts in Mode 1, to 5 watts in Mode 2, and to 0.5 watts in Mode 3. In practical applications, the video stream inference task frame interval is approximately 33 milliseconds. The DPU works for approximately 15 milliseconds within a frame, and enters Mode 2 power-saving mode for the remaining 18 milliseconds. The average DPU power consumption decreases from 18 watts to 9 watts, a 50% reduction in energy consumption.

[0109] The self-learning and strategy optimization unit continuously optimizes system strategies using online learning. The historical data analysis processor maintains a time-series database storing system operation data for the past 30 days. This database uses the InfluxDB 2.1 open-source time-series database engine and stores performance metrics time-series, resource utilization time-series, and task execution records. The total database capacity is approximately 50GB, containing about 43 million records. The feature recognition processor implements a clustering-based application scenario identification algorithm. It extracts application feature vectors from historical data, each containing 12 dimensions. The K-means clustering algorithm is used to cluster historical application scenarios into 8 typical scenarios. The clustering algorithm is trained offline on historical data, using 10,000 samples from the past 30 days, with a training time of approximately 5 minutes. During online operation, the feature recognition processor extracts the current application features every minute, calculates its Euclidean distance to the 8 scenario templates, and selects the closest template as the current scenario identifier. The strategy adjustment processor maintains eight sets of optimized strategy parameters, each corresponding to an application scenario. The strategy parameters include 20 parameters such as memory allocation ratio, data prefetch window size, and the number of DDR cache partitions. Each set of strategy parameters is optimized offline through reinforcement learning, using the near-end strategy optimization (PPO) algorithm, and converges to the optimal strategy after approximately 100,000 iterations. In actual scenario switching tests, when the system switched from an inference-intensive scenario to a hybrid task scenario, the overall task completion rate improved by approximately 25% after the strategy adjustment.

[0110] As a modified implementation, the performance monitoring unit can use sampling-based profiling technology instead of full monitoring. Sampling profiling records performance data once every 100 operations, with a sampling rate of 1%, reducing monitoring overhead from approximately 5% to 0.05%, but slightly decreasing statistical accuracy. The power management unit can use a model predictive control (MPC)-based frequency modulation strategy instead of rule-based frequency modulation. The MPC algorithm establishes a power performance model of the system, predicts the load in the next N time steps, optimizes the weighted objective function of future power consumption and performance, and solves for the optimal frequency-voltage sequence. This approach can better handle load fluctuations, but has higher computational complexity and increases decision latency to approximately 5 milliseconds.

[0111] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of protection of the present invention. Therefore, all equivalent technical changes made based on the content of the present invention specification and drawings are included within the scope of protection of the present invention. Furthermore, the elements therein can be updated as technology develops.

Claims

1. A resource scheduling and computing control system of a computing memory HAM, characterized in that, The intelligent resource allocation module, the heterogeneous computing cooperation module, the security and reliability guarantee module, and the adaptive optimization and monitoring module are included. The intelligent resource allocation module is responsible for dynamic management and optimized allocation of internal resources of the HAM, the heterogeneous computing cooperation module is responsible for intelligent decomposition, distribution and result synchronization of tasks, the security and reliability guarantee module is used for providing encryption calculation, error correction detection and access control functions, and the adaptive optimization and monitoring module is responsible for real-time monitoring and adaptive optimization of system running states. The intelligent resource allocation module includes a memory area dynamic division unit, a DDR-NAND hybrid storage scheduling unit and a load balancing and priority arbitration unit, the memory area dynamic division unit adjusts the allocation proportion of the DDR memory between the external processor and the DPU in real time according to the activation state of the DPU, the DDR-NAND hybrid storage scheduling unit is used for realizing automatic swap-in and swap-out of data between the DDR and the NAND, and the load balancing and priority arbitration unit monitors the real-time load state of the external processor and the DPU. The heterogeneous computing cooperation module includes a task decomposition and distribution unit, a computing result synchronization unit and an instruction set extension interface unit, the task decomposition and distribution unit analyzes the composite computing task sent by the external processor, the computing result synchronization unit manages the return time sequence of the DPU computing result to the external processor, and the instruction set extension interface unit provides decoding and execution control of the DPU special instruction set. The security and reliability guarantee module includes an encryption calculation control unit, an error correction detection and repair unit and an isolation and access control unit, the encryption calculation control unit receives external security instructions and schedules the security module to perform data encryption and decryption operations, the error correction detection and repair unit detects and repairs error correction codes in the specified address range according to external instructions, and the isolation and access control unit is used to realize memory access permission isolation between the DPU and the external processor. The adaptive optimization and monitoring module includes a performance monitoring and statistics unit, a power consumption management and energy saving unit and a self-learning and strategy optimization unit, the performance monitoring and statistics unit collects performance indicators in real time, and statistics the execution time and energy consumption data of different computing task types, the power consumption management and energy saving unit dynamically adjusts the working frequency and voltage of the DPU according to the load, and the self-learning and strategy optimization unit is used to automatically identify application characteristics and adjust the preloading strategy.

2. The resource scheduling and computing control system of claim 1, wherein, The DDR-NAND hybrid storage scheduling unit includes an access mode prediction processor, a data migration processor and a cache management processor, the access mode prediction processor predicts future data access mode by analyzing historical access sequence and generates preloading suggestions, the data migration processor moves data blocks between the DDR and the NAND according to the prediction result and cache replacement algorithm and manages data consistency, and the cache management processor maintains hot data tags in the DDR and decides the residence duration of data according to access frequency and timeliness.

3. The resource scheduling and computing control system of claim 2, wherein, The access mode prediction processor calculates the comprehensive access heat H(i) of data block i according to the following formula: ； wherein, represents the frequency of data block i being accessed by an external processor, represents the frequency of data block i being accessed by a DPU, is the time interval since data block i was last accessed, is a time decay coefficient, represents the length of sequential access sequences in which data block i participates, is a sequential access gain coefficient, and is a synergy coefficient; The access pattern prediction processor arranges all data blocks in the NAND in descending order of access heat H(i), and when H(i) exceeds a preset preloading threshold, marks the data block as a preloading candidate and generates a preloading suggestion list to pass to the data migration processor.

4. The resource scheduling and computing control system of claim 3, wherein, The data migration processor calculates a migration benefit value G(i) of the data block i according to the following formula: ； wherein, denotes the average access latency of NAND, denotes the average access latency of DDR, S(i) denotes the size of data bin i, is the memory bus bandwidth, denotes the maximum tolerable migration time window, denotes the DDR utilization with the adjustment function, is the DDR utilization; The data migration processor arranges the candidate data blocks in descending order of migration benefit G(i), and when the DDR space is sufficient, executes the migration operation in sequence, and when the DDR space is insufficient, triggers the cache management processor to make an eviction decision to free up space.

5. The resource scheduling and computing control system of claim 4, wherein, The cache management processor calculates a retention value V(i) of the data block i in the DDR according to the following formula: ； wherein, represents the cumulative data volume of data block i participating in DPU calculation, represents the total data volume processed by the DPU, is a contribution weight coefficient for DPU calculation, and I(i) is the correlation degree of data block i with other data blocks in the DDR, is a correlation weight coefficient; When data needs to be evicted, the cache management processor preferentially selects a data block with the lowest retention value to migrate back to the NAND.

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