Controller, host, operation method of controller and operation method of host

Abstract

The invention provides a controller, a host, an operation method of the controller and an operation method of the host, and is applied to the technical field of semiconductors. The controller includes an interface circuit and a buffer. The interface circuit and the buffer are coupled. Wherein the buffer is configured to cache log information generated during firmware running. The interface circuit is configured to obtain log information generated during firmware runtime from the buffer. And outputting the log information. According to the embodiment, the log information is output under the condition that IO performance is not affected.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a controller, a host, a method of operating the controller, and a method of operating the host. Background Technology

[0002] Firmware (FW) is the program code embedded in a Solid State Drive (SSD) that controls the SSD's basic functions and its interaction with the host (Host 11000). Debugging the SSD FW is a crucial step to ensure stable, reliable, and efficient SSD operation. During FW debugging, a large amount of firmware-generated log information needs to be recorded on the input / output (IO) paths. This log information is then output via serial port for problem reproduction and localization. However, outputting log information via serial port significantly degrades IO performance, potentially making timing-related issues difficult to reproduce. Summary of the Invention

[0003] The embodiments of this disclosure provide a controller, a host, a method for operating the controller, and a method for operating the host, so as to output log information without affecting IO performance.

[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0005] In a first aspect, embodiments of this disclosure provide a controller including an interface circuit and a buffer. The interface circuit and the buffer are coupled. The buffer is configured to cache log information generated during firmware runtime. The interface circuit is configured to: obtain the log information generated during firmware runtime from the buffer; and output the log information.

[0006] In some possible implementations, the interface circuitry includes PCIe interface circuitry.

[0007] In some possible implementations, the buffer includes at least one of the following: volatile memory and non-volatile memory.

[0008] In some possible implementations, the buffer includes at least one of the following: a controller memory buffer (CMB) and a persistent memory region (PMR).

[0009] In some possible implementations, the controller memory buffer (CMB) and persistent memory region (PMR) are direct memory access regions.

[0010] In some possible implementations, the controller includes multiple kernels. Each kernel is coupled to a buffer. The kernels are configured to cache log information generated during firmware runtime to the buffers.

[0011] In some possible implementations, different kernels correspond to different storage areas in the buffer. Multiple kernels are configured to cache log information generated during firmware runtime to their respective storage areas.

[0012] In some possible implementations, the buffer includes multiple storage addresses that indicate the locations where log information is written and read. At any given time, the same storage address is used for at most one of the following: writing log information and reading log information.

[0013] In some possible implementations, the controller further includes a controller processor. The controller processor is coupled to the interface circuitry and the buffer. The controller processor is configured to output control commands in response to a received log retrieval request. The log retrieval request includes a preset number of log messages to be retrieved. The control commands are used to control the buffer to output a number of log messages less than or equal to the preset number.

[0014] In some possible implementations, the log information includes identification information and log data information. The identification information is used to indicate the bits occupied by the log data.

[0015] Secondly, embodiments of this disclosure provide a host computer, which includes a host processor and a storage device. The host processor and the storage device are coupled together. The host computer is coupled to a controller. The host processor is configured to: retrieve log information from a buffer in the controller based on a target address. The target address is the storage address of the log information in the buffer. The log information is then stored in the storage device.

[0016] In some possible implementations, the log information includes identification information and log data information. The identification information is used to indicate the bits occupied by the log data. The host processor is also configured to obtain the log data based on the identification information and the log data information.

[0017] In some possible implementations, the buffer includes at least one of the following: a controller memory buffer (CMB) and a persistent memory region (PMR).

[0018] In some possible implementations, the controller memory buffer (CMB) and persistent memory region (PMR) are direct memory access regions.

[0019] Thirdly, embodiments of this disclosure provide a method for operating a controller, the method comprising: obtaining log information generated during firmware runtime from a buffer; the log information generated during firmware runtime being cached in the controller's buffer; and outputting the log information.

[0020] In some possible implementations, the controller includes multiple kernels. The controller's operation also includes the multiple kernels caching log information generated during firmware runtime into buffers.

[0021] In some possible implementations, different kernels correspond to different storage areas in the buffer. Multiple kernels cache log information generated during firmware runtime to the buffer, including: multiple kernels caching log information generated during firmware runtime to corresponding storage areas.

[0022] In some possible implementations, the buffer includes multiple storage addresses, which indicate the location where log information is written or read. At any given time, the same storage address is used only for writing or reading log information.

[0023] In some possible implementations, the method further includes: responding to a received log retrieval request by outputting a control command. The log retrieval request includes a preset number of log messages to be retrieved. The control command is used to control the buffer to output a number of log messages that is less than or equal to the preset number.

[0024] In some possible implementations, the log information includes identification information and log data information. The identification information is used to indicate the bits occupied by the log data.

[0025] Fourthly, embodiments of this disclosure provide a method for operating a host, including: retrieving log information from a buffer of a controller based on a target address. The target address is the storage address of the log information in the buffer. The log information is then stored in a storage device.

[0026] In some possible implementations, the log information includes identification information and log data information. The identification information is used to indicate the bits occupied by the log data. The host's operation method further includes: obtaining the log data based on the identification information and the log data information.

[0027] Fifthly, embodiments of this disclosure provide a storage system including a memory and any of the controllers described in the first aspect. The controller and the memory are coupled.

[0028] Sixthly, embodiments of this disclosure provide a system including a server and a storage system. The server and the storage system are coupled.

[0029] In some possible implementations, the server includes a cloud server.

[0030] In a seventh aspect, embodiments of this disclosure provide an electronic device including any controller of the first aspect and any host of the second aspect. The host and the controller are coupled.

[0031] Eighthly, embodiments of this disclosure provide a computer-readable storage medium including instructions. When executed on a processor, the instructions cause the processor to perform an operation method of any controller in the third aspect and / or an operation method of any host in the fourth aspect. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0033] Figure 1 A schematic diagram of a module of an electronic device according to some embodiments. Figure 1 ;

[0034] Figure 2 A schematic diagram of a module of an electronic device according to some embodiments. Figure 2 ;

[0035] Figure 3 A schematic diagram of a module of an electronic device according to some embodiments. Figure 3 ;

[0036] Figure 4 A schematic diagram of a module of an electronic device according to some embodiments. Figure 4 ;

[0037] Figure 5 This is a schematic diagram of a PCIe layered structure according to some embodiments;

[0038] Figure 6 This is a schematic diagram illustrating the structural relationship between NVMe and PCIe according to some embodiments;

[0039] Figure 7 This is a schematic diagram of a queue structure according to some embodiments;

[0040] Figure 8 This is a schematic diagram of a queue producer / consumer model according to some embodiments;

[0041] Figure 9 This is a schematic diagram of command execution in an electronic device according to some embodiments of a queue. Figure 1;

[0042] Figure 10 This is a schematic diagram of command execution in an electronic device according to some embodiments of a queue. Figure 2 ;

[0043] Figure 11 This is a schematic diagram of command execution in an electronic device according to some embodiments of a queue. Figure 3 ;

[0044] Figure 12 This is a schematic diagram of command execution in an electronic device according to some embodiments of a queue. Figure 4 ;

[0045] Figure 13 This is a schematic diagram of command execution in an electronic device according to some embodiments of a queue. Figure 5 ;

[0046] Figure 14 A schematic diagram of a module of an electronic device according to some embodiments. Figure 5 ;

[0047] Figure 15 A schematic diagram of a module of an electronic device according to some embodiments. Figure 6 ;

[0048] Figure 16 A schematic diagram of a module of an electronic device according to some embodiments. Figure 7 ;

[0049] Figure 17 A schematic diagram of a module of an electronic device according to some embodiments. Figure 8 ;

[0050] Figure 18 A schematic diagram of a module of an electronic device according to some embodiments. Figure 9 ;

[0051] Figure 19 This is a schematic diagram of a ring-shaped buffer structure according to some embodiments;

[0052] Figure 20 A schematic diagram of a module of an electronic device according to some embodiments. Figure 10 ;

[0053] Figure 21 This is a schematic diagram illustrating a method of organizing log information according to some embodiments;

[0054] Figure 22 This is a schematic diagram of a system module according to some embodiments;

[0055] Figure 23 This is a flowchart illustrating an operation method according to some embodiments. Figure 1 ;

[0056] Figure 24 This is a flowchart illustrating an operation method according to some embodiments. Figure 2 ;

[0057] Figure 25 This is a schematic diagram of a memory card module according to some embodiments;

[0058] Figure 26 This is a schematic diagram of a solid-state drive module according to some embodiments;

[0059] Figure 27 A schematic diagram of a memory module according to some embodiments. Figure 1 ;

[0060] Figure 28 A schematic diagram of a memory module according to some embodiments. Figure 2 . Detailed Implementation

[0061] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0062] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0063] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0064] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0065] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0066] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0067] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0068] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0069] Firmware (FW) is the program code embedded in a storage system, such as a solid-state drive (SSD). It controls the basic functions of the storage system and its interaction with external devices (such as the host of electronic devices). Debugging the FW is a crucial step in ensuring the stable, reliable, and efficient operation of the storage system. During FW debugging, it is necessary to record a large amount of log data generated by the FW operation along the input / output (IO) path (the IO path refers to the entire process from data request generation to the final data being written to or read from the storage system) to reproduce and locate problems.

[0070] To preserve the log data generated by these firewalls for problem reproduction and localization, embodiments of this disclosure provide an electronic device, such as... Figure 1As shown, electronic device 10000 includes a host 11000 and a storage system 12000, which are coupled together. Storage system 12000 includes a controller 12100 and a memory 12200, which are coupled together. Controller 12100 includes an interface circuit 12110, a controller processor 12120, and a buffer 12130. The interface circuit 12110 (i.e., the I / O interface), controller processor 12120, and buffer 12130 are mutually coupled. Interface circuit 12110 can use serial transmission for data transmission. For simple, stable, and low-power data transmission, interface circuit 12110 can use a Universal Asynchronous Receiver / Transmitter (UART) to implement serial communication between devices. Figure 2 As shown, the FW generates log data during operation, and then actively transmits it to the host 11000 for storage or parsing in real time through the serial interface circuit 12110, such as UART.

[0071] In such Figure 2 In the illustrated implementation, the serial port transmission rate (e.g., the common 115200bps) is significantly lower than the random read / write performance of the storage system 12000 (e.g., several hundred KIOPS), where IOPS represents Input / Output Operations Per Second. This means that actively outputting large amounts of log data in real-time via the serial port will consume significant resources of the controller processor 12120 and system time, leading to a substantial decrease in the serial port performance of the storage system 12000's interface circuit 12110. This can result in slow system response, slow data transmission speed, and application lag. To avoid the technical problem of a significant decrease in the serial port performance of the storage system 12000's interface circuit 12110 due to the mismatch between the low serial port transmission rate and the random read / write rate of the storage system 12000, the implementation of this measure is not recommended.

[0072] In some possible implementations, log data can be temporarily stored in memory 12200. For example... Figure 3As shown, the FW generates a series of log data, which may contain detailed information about the operation, errors, and performance of the storage system 12000. In some scenarios, because the log data may grow rapidly and be large in quantity, while the writing speed to the memory 12200 is slow, the log data can be cached in the buffer 12130 first, and then written from the buffer 12130 to the memory 12200, such as to the NAND SPB (Super Block, a management method for blocks in NAND, with an SPB capacity of approximately tens of gigabytes), to ensure the integrity of the log data and improve the efficiency of log data transmission. When the storage system 12000 encounters problems or anomalies, it is necessary to examine this log data temporarily stored in the memory 12200 to diagnose the problem. The host 11000 can export the log data from the memory 12200 for parsing through the interface circuit 12110. The interface circuit 12110 can include, but is not limited to, UART, and can also include a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) interface, etc., without limitation.

[0073] In some examples, such as interface circuit 12110 including UART, host 11000 can trigger the export operation of log data through UART commands.

[0074] In other examples, such as interface circuit 12110 including a PCIe interface, for instance... Figure 4 As shown, the interface circuit 12110 may include a PCIe controller 12111 and a Non-Volatile Memory Express (NVMe) controller 12112. NVMe is a non-volatile memory host controller interface specification, specifically designed to provide a communication interface for various non-volatile memory (NVM) systems, such as solid-state drives (SSDs), flash memory, and storage class memory (SCM). PCIe, as a high-speed serial computer expansion bus standard, boasts high-speed data transfer capabilities and flexibility as its main advantages, connecting the host 11000 and the storage system 12000 in the electronic device. Commands and data are transmitted between the host 11000 and the storage system 12000 via the front-side bus of the PCIe interface. Figure 5As shown, PCIe adopts a layered architecture, including the Transaction Layer, Data Link Layer, and Physical Layer. The Physical Layer further comprises logical and electrical sub-modules. Each layer has its specific function, but overall, the lower layers provide services to the upper layers.

[0075] The NVMe protocol runs on the PCIe bus, such as Figure 6 As shown, its architecture sits on top of PCIe. Therefore, NVMe devices (such as NVMe SSDs) need to use the PCIe interface to communicate with the host system. The NVMe protocol defines the command set for communication between the host 11000 and the NVMe device, as well as the execution method of the commands. Specifically, taking the NVMe device as storage system 12000 as an example, NVMe includes two main types of commands: Admin commands and I / O commands. Admin commands are used to help the host 11000 manage and control the storage system 12000, while I / O commands are used to transfer data between the host 11000 and the storage system 12000.

[0076] In its implementation, NVMe communicates with host 11000 through a Submission Queue (SQ), a Completion Queue (CQ), and a Doorbell Register (DB). The SQ resides in host 11000's memory. When host 11000 needs to send a command, it first places the prepared command in the SQ and then notifies storage system 12000 to retrieve it. The CQ also resides in host 11000's memory. Upon completion of a command, regardless of success or failure, storage system 12000 always writes the command completion status to the CQ. Host 11000 notifies storage system 12000 by writing to the DB register on the storage system's side. The relationship between SQ and CQ can be one-to-one or many-to-one, but regardless, they are always paired; that is, the existence of an SQ necessarily implies the existence of a CQ. Admin SQ / CQ and I / O SQ / CQ each have their own functions. Admin commands cannot be placed in an I / O SQ, and similarly, I / O commands cannot be placed in an Admin SQ. I / O SQ / CQs are created using Admin commands. There is only one pair of Admin SQ / CQs on host 11000, and they are in a one-to-one correspondence. However, there are multiple pairs of I / O SQ / CQs.

[0077] Both SQ and CQ are queue structures, and logically, they are circular queue structures. SQ stores multiple Submission Queue Entry (SQE) entries; that is, an SQE is the basic building block of an SQ, and an SQ is composed of multiple SQEs. In the NVMe protocol, each IO SQ (submission queue used to execute I / O commands) corresponds to a set of SQEs. When host 11000 needs to issue an I / O command, it writes the SQ containing the command information into the SQ. Host 11000 can issue I / O commands by writing SQEs into the SQ. In the NVMe protocol, the SQE is the basic unit for submitting I / O requests. It contains all the information needed to perform the I / O operation, such as data address, length, and command type. Similarly, CQ stores multiple Completion Queue Entry (CQE) entries. When host 11000 submits I / O commands to the NVMe device, these commands are placed in the Submission Queue (SQ). Once the NVMe device has processed these commands, it generates a corresponding CQE in the CQ to notify the host 11000 of the command completion status. The CQE is the basic building block of the CQ. A CQ consists of multiple CQEs, each corresponding to a completed I / O command. The CQE is the smallest unit in the NVMe protocol used to store I / O command completion information. It contains the status, result, and other relevant information about the completed I / O command.

[0078] like Figure 7 As shown, a queue has several elements, including queue depth, queue contents, and a head and a tail. The head of the queue represents items being served or waiting to be served; once service is complete, it leaves the queue. Therefore, the head and tail of the queue are crucial; the head determines which items will be served immediately, and the tail determines the position of new writes. The database (DB) is used to record the head and tail of a sorted queue (SQ) or sorted queue (CQ). Each SQ or CQ has two corresponding DBs: a head DB and a tail DB. The DB is a register at the 12000 end of the storage system, recording the head and tail positions of the SQ and CQ.

[0079] like Figure 8The diagram illustrates a queue producer / consumer model. The producer writes content to the tail of the queue, and the consumer retrieves content from the head. For a queue (SQ), the producer is host 11000, which writes commands to the tail of the SQ, and the consumer is storage system 12000, which removes commands from the head of the SQ and executes them. For a queue (CQ), the opposite is true: the producer is storage system 12000, which writes command completion information to the tail of the CQ, and the consumer is host 11000, which retrieves command completion information from the head of the CQ.

[0080] In one example, such as Figure 9 As shown, in the initial state, SQ1 and CQ1 are empty, and Head = Tail = 0. Figure 10 As shown, host 11000 writes three commands to SQ1, changing SQ1's Tail to 3. After writing the three commands, host 11000 updates the value of the SQ1Tail DB register on controller 12100 to 3. By updating this register, host 11000 is also informing controller 12100 that a new command has arrived and should retrieve and execute it. Figure 11 As shown, after receiving the notification, controller 12100 retrieves all three commands from SQ1 and executes them. Storage system 12000 consumes all three commands from SQ1, and the SQ1 Head is adjusted to 3. Controller 12100 then writes this Head value to its local SQ1 Head DB register. Figure 12 As shown, after executing two commands, storage system 12000 writes two command completion messages to CQ1 and updates the value of the Tail DB register corresponding to CQ1 to 2. Simultaneously, it sends a message to host 11000. (The rest of the text appears to be unrelated and possibly machine-generated.) Figure 13 As shown, host 11000 receives a notification (interrupt information) from storage system 12000 and retrieves two completion messages from CQ1. After processing, host 11000 updates the Head value of CQ1 in the CQ1 Head DB register to 2.

[0081] In the command processing flow, the database (DB) remembers the head and tail of both the sorted queue (SQ) and the command queue (CQ). For SQ, storage system 12000 is the consumer, interacting directly with the head of the queue and knowing exactly where the SQ head is; therefore, the SQ Head DB is maintained by storage system 12000 itself. However, it doesn't know the queue length, the tail, or how many commands are waiting to be executed. In contrast, host 11000 does, so the SQ Tail DB is updated by host 11000. By combining the head and tail of the SQ, storage system 12000 knows how many commands are still waiting to be executed in the SQ. For CQ, storage system 12000 is the producer, knowing exactly where the CQ tail is; therefore, it updates its own CQ Tail DB. However, storage system 12000 doesn't know how many command completion messages host 11000 has processed; this information needs to be provided by host 11000. Therefore, the CQ Head DB is updated by host 11000. Based on the CQ header and tail, storage system 12000 knows whether the CQ can still receive and how many command completion information it can accept. The database also serves a notification function: when host 11000 updates the SQ Tail database, it also informs storage system 12000 that there are new commands to process. When host 11000 updates the CQ Head database, it also informs storage system 12000 that the returned command completion status information has been processed.

[0082] The NVMe protocol allows users to configure specific commands to meet the needs of specific application scenarios. For example, in this implementation, host 11000 can trigger log data export operations using NVMe-based Vendor Unique (VU) commands. NVMe VU Commands are an optional feature in the NVMe protocol that gives manufacturers of electronic devices 10000 the ability to define unique command sets for their specific storage systems 12000, sent via SQ and returned via CQ. These commands execute in NVMe devices in a similar manner and process to standard commands, but their specific content and behavior are defined by the vendor. This mechanism allows device manufacturers to customize functionality for their devices to differentiate them from SSDs that only use the standard NVMe command set. Almost all NVMe controllers support this VUCommand mechanism, meaning that using NVMe VU Commands has broad applicability in terms of hardware compatibility. Device manufacturers can leverage NVMe VU Commands to extend the functionality of storage systems to meet their specific needs or application scenarios. For example, some advanced functions, performance optimizations, or special management functions may only be implemented through these unique commands. The specific format and definition of VU Commands are entirely determined by the device manufacturer and detailed in their device's NVMe specification. These commands generally follow the basic structure and syntax of the NVMe command set, but may include additional fields or parameters to achieve specific functionalities. From the perspective of host 11000, exporting log data using NVMe VU Commands is relatively simple, requiring only the addition of an NVMe VU Command to the firmware (FW), as this process does not require special hardware support or specific memory regions. This flexibility allows device manufacturers to easily extend and customize the functionality of their storage systems through software updates. Once storage system 12000 receives the export command, its FW reads the log data temporarily stored in memory 12200 and sends it to host 11000 for storage or parsing.

[0083] In some examples, due to the limited capacity of memory 12200 and the potential rapid growth of log data, the firmware can compress the log data before storing it in memory 12200. This reduces storage space usage and improves storage efficiency. The compressed log data is temporarily stored in memory 12200, awaiting subsequent export and saving or export parsing. When storage system 12000 encounters problems or malfunctions, developers or technical support personnel may need to review these temporarily stored logs to diagnose the issue.

[0084] In such Figure 3 and Figure 4 In the illustrated embodiment, the log data processing mechanism of the storage system 12000 employs a strategy of temporarily storing log data in the memory 12200. This design triggers the log data export operation via UART commands or NVMe VU Commands, aiming to avoid the performance overhead of serial communication. By reducing the real-time requirements of serial communication, it avoids the mismatch between its low transmission rate and the high random read / write rate of the storage system 12000, thereby preventing the interface circuit 12110 from significantly degrading due to serial port performance bottlenecks. Furthermore, this strategy ensures that the actual performance of the storage system is not masked or altered during debugging due to additional latency from serial communication and increased load on the controller processor 12120. This is particularly important for debugging serial port performance-sensitive issues, preventing technical problems where performance-sensitive issues cannot be reproduced. However, the limited capacity of the memory 12200 (one SPB is approximately tens of gigabytes) poses a challenge. In long-term or high-intensity testing environments, the rapid accumulation of log data may quickly exhaust its storage space, thus affecting the normal operation of the storage system 12000. At the same time, the limited storage space restricts the retention time of log data (e.g., about two hours can fill up the 12200 memory). Especially when it is necessary to trace long-term anomalies, the development process of the problem may not be fully presented due to data truncation, which brings difficulties to the tracing, location and resolution of the problem.

[0085] In order to quickly store large amounts of log data, in some possible implementations, compared to... Figure 4 The embodiments shown are as follows: Figure 14 As shown, the log data generated by the controller 12100 running the FW can be... Figure 14 Log information (including log data) is temporarily stored in buffer 12130, meaning that the log data generated by the FW is not stored according to... Figure 2 The embodiment shown directly and actively transmits data to the host 11000 via the serial port interface circuit 12110, and does not follow the procedure described above. Figure 3 and Figure 4 The illustrated implementation is temporarily stored in memory 12200. Host 11000 can trigger the log data export operation through NVMe VU Command to export the log data from buffer 12130 to host 11000 for storage or parsing through interface circuit 12110 (including PCIe controller 12111 and NVMe controller 12112).

[0086] In some examples, Figure 15As shown, host 11000 includes host processor 11100 and first storage device 11200. Host 11000 also includes an interface circuit (not shown) that matches the interface circuit 12110 in storage system 12000. Host processor 11100 and first storage device 11200 are coupled. Host processor 11100 triggers log data export operations or log extraction requests via NVMe VU Command. The log extraction request includes a preset quantity of log information to be extracted (such as all or part). In response to the received log extraction request, controller processor 12120 outputs a control command to buffer 12130. The control command controls buffer 12130 to output less than or equal to the preset quantity of log information. Then, host 11000 obtains log data from buffer 12130 of controller 12100 and stores the log data in first storage device 11200 to achieve long-term storage of log data for subsequent analysis and diagnosis. The first storage device 11200 may include, but is not limited to, hard disks (such as mechanical hard disks and solid-state hard disks), cloud storage and cloud disks, or any physical or virtual device with data storage function, without any restrictions.

[0087] For example, such as Figure 16 As shown, at least one second storage device A can be set outside the host 11000. The second storage device A is similar to the first storage device 11200 and can further increase the storage space for cached log data.

[0088] In some examples, buffer 12130 may include, but is not limited to, at least one of the following: volatile memories such as Static Random-Access Memory (SRAM) and Dynamic Random-Access Memory (DRAM), and non-volatile memories such as SCMs like Phase-Change Memory (PCM), Ferroelectric Random Access Memory (FeRAM), and NAND flash memory; no limitation is made here. Controller 12100 may choose to use SRAM or DRAM depending on storage speed and size requirements. SRAM is generally faster than DRAM, but it is also more expensive and has a smaller capacity. DRAM, on the other hand, has a higher capacity and a lower cost. If fast writing of large amounts of data is required, SRAM may be chosen. If long-term storage of large amounts of data is required, DRAM may be chosen. Figure 17 As shown, the buffer 12130 includes a buffer controller 12131, an SRAM 12132, and a DRAM 12133.

[0089] In such Figure 14 In the implementation shown, although the implementation of NVMe VU Command is relatively simple, since NVMe VU Command requires FW to parse and implement the command, some additional processing is still required from FW, which may increase some additional processing time and performance overhead.

[0090] To further improve the rate of storing large volumes of log data, the storage system 12000 can be optimized via its controller 12100 as follows: the controller 12100 can configure some or all of the general-purpose buffers of the storage system's internal buffer 12130 as controller memory buffers (CMB) and / or persistent memory regions (PMR), and map these resources to the host 11000, thereby allowing the host 11000 to use these CMBs or PMRs to cache log data.

[0091] In its implementation, the NVMe protocol allows controller 12100 to map the general-purpose cache within storage system 12000 to host 11000, enabling host 11000 to access it via PCIe memory read / write (a data transfer method based on the PCIe bus). For example, the general-purpose cache (such as DRAM) of buffer 12130 within storage system 12000 can be configured as CMB and / or PMR for host 11000 use. CMB (or PMR) can be used to store various NVMe queues (such as SQ and CQ) or NVMe data (such as log data). The SQ and CQ established in CMB and PMR use the same queue method as those established in host 11000 memory.

[0092] In some examples, NVMe SQ and CQ are built on CMB. A portion of the general-purpose cache (such as DRAM or SRAM) within the storage system 12000's internal buffer 12130 is configured as CMB. For example... Figure 18As shown, a portion of the general-purpose cache area of ​​the DRAM inside the storage system 12000 is configured as a CMB. CMB is an important feature of the NVMe protocol, significantly improving data transfer efficiency and performance by establishing the NVMe Submission Queue (SQ) on the CMB. Under the CMB architecture, the SQs and CQs required for NVMe I / O commands can reside directly in the general-purpose cache area (such as DRAM) of the internal buffer 12130 of the storage system 12000, instead of being placed in the host 11000's memory. This design reduces the command interaction latency between the host 11000 and the storage system 12000 because the host 11000 no longer needs to go through the PCIe bus when writing SQ entries (SQE). Through the CMB, the controller 12100 can map the general-purpose buffer inside the storage system 12000 to the address space of the host 11000. Once the mapping is complete, the host 11000 can directly read and write to the CMB inside the controller 12100 via the PCIe interface, just like accessing its own memory. Because CMB allows direct access, this mechanism avoids data transfer bottlenecks based on the PCIe bus (such as bus bandwidth limitations; while the PCIe bus provides high-speed data transfer capabilities, its bandwidth is still limited), thus significantly reducing data transfer latency. Direct access to host memory or the controller's internal memory greatly improves data transfer efficiency and further enhances the overall performance of the storage device. CMB not only optimizes data transfer latency but also enhances the storage system's response speed and throughput. Furthermore, direct access to the controller's internal memory significantly improves data transfer efficiency, thereby enhancing the overall performance of the storage device.

[0093] Because the CMB (Memory Buffer Block) function requires hardware support at the controller 12100 level, not all storage systems 12000 have this feature; only those storage systems 12000 with controller 12100 designs supporting CMB can use it. Therefore, in its implementation, the controller 12100 uses two registers—Controller Memory Buffer Location (CMBLOC) and Controller Memory Buffer Size (CMBSZ)—to describe basic CMB information, including its location and size. The host 11000 uses CMB by enabling the CMBLOC and CMBSZ registers. CMBSZ is read-only for the host 11000. It determines the size of the storage system 12000's internal buffer available for CMB, as well as the minimum granularity, where Size refers to the length of available space within the CMB. CMBSZ indicates whether SQ and CQ creation within the CMB is supported. During CMB initialization, the server (FW) needs to set appropriate CMB attributes, such as the Completion Queue Size (CQS) and Submission Queue Size (SQS) in CMBSZ, to ensure correct CMB usage. If the FW sets CQS and SQS to 1 in CMBSZ during initialization, it instructs controller 12100 to support the creation of Admin SQ / CQ and I / O SQ / CQ within the CMB. If the FW sets CQS and SQS to 0 in CMBSZ during initialization, it instructs controller 12100 not to support the creation of Admin SQ / CQ and I / O SQ / CQ within the CMB. CMBLOC indicates the PCIe address range corresponding to the CMB on host 11000. After controller 12100 enables CMB and restarts host 11000, and host 11000 enables the CMBLOC and CMBSZ registers, controller 12100's CMB function is enabled. Controller 12100 then allocates a buffer segment in buffer 12130 as CMB. To cache log data in CMB and ensure that CMB is used for caching log data and not for establishing NVMe SQ and CQ, the firmware needs to set relevant attributes (such as CQS and SQS in CMBSZ) to 0 during initialization. This tells the driver that CMB is ready to store log data and will not be used for other purposes.

[0094] In one example, taking the caching of log data in the CMB as an example, after the controller 12100 enables the CMB and restarts the host 11000, and the host 11000 enables the CMBLOC and CMBSSZ registers, the controller 12100's CMB function is enabled. The controller 12100 then allocates an internal memory buffer as the CMB. For example, using `lspci -vv` (a standard tool in Linux systems used to display detailed information about all PCIe bus devices or devices connected to the bus), one can observe that a new region has been added to the PCIe network, indicating its starting address and size. This information provides the specific range and size of the CMB mapped address. An 8MB address space starting from 0x840000 has been allocated to the CMB. This CMB memory is then mapped to a specific address space in the host 11000's PCI Base Address Register (BAR). The host 11000 can access the data in the CMB through this address range. When host 11000 attempts to access storage system 12000, if the accessed PCIe address falls within the address range configured for CMB, the SSD will translate the memory read / write request for that PCIe address into a CMB read / write request. The PCI BAR space is a part of the PCIe device configuration space, used to describe the memory space mapped to the device's memory. Each PCIe device can have multiple BARs, each corresponding to a segment of storage space on the device. Once CMB is mapped to the address space of any PCI BAR, host 11000 can interact with CMB by accessing that specific address.

[0095] For example, host processor 11100 retrieves log data from buffer 12130 based on a target address, which is the storage address of log data in buffer 12130. The log data is then stored in first storage device 11200 and / or second storage device A.

[0096] In some examples, since the CMB is a shared resource between host 11000 and FW, it's necessary to ensure that host 11000 and FW cannot simultaneously read from, modify, or write to the same address in the CMB. To avoid the problem of host 11000 and FW writing to the same address in the CMB at the same time, the buffer in the CMB can be set as a logical ring buffer. A ring buffer is a data structure that allows data producers (such as FW) and data consumers (such as host 11000) to write and read data from different locations without needing to move other data. Figure 19As shown, the Ring Buffer has two key pointers: the Write Position and the Read Position. The Firewall (FW) modifies the Write Position to indicate where new data is written (the memory address corresponds to the buffer in the CMB), while the Host 11000 modifies the Read Position to read the written data. The CMB includes multiple memory addresses, which indicate the locations for writing and reading log data. At any given time, the same memory address is used for at most one of the following: writing log data and reading log data.

[0097] In one example, given that most controllers 12100 include multiple cores, these cores (e.g., core 0, core 1, and core 2) cache log data generated during the Fireworks (FW) runtime to the Central Management Block (CMB). The allocation of the CMB among these cores becomes particularly important, with different cores corresponding to different buffers within the CMB. To ensure data consistency and performance, the buffer segments in the CMB need to be allocated according to the specific architecture of the Fireworks. Taking mirrored cores as an example (meaning each core has the same functionality, is independent, and can run the Fireworks in parallel), such as... Figure 20 As shown, the CMB can be evenly distributed among all cores. For example, the CMB can be divided into three buffers: buffer 0, buffer 1, and buffer 2. Buffer 0 can be allocated to kernel 0, buffer 1 to kernel 1, and buffer 2 to kernel 2. This means each core has its own CMB segment and interacts with host 11000 through its own Ring Buffer. This approach reduces contention and conflicts between cores, improving overall system performance. Each core interacts with host 11000 using its Ring Buffer, such as... Figure 20 As shown in the diagram, the allocation of CMB, the structure of the Ring Buffer, and the interaction flow between the host 11000 and the server (FW) are illustrated. The diagram demonstrates the usage of the CMB Buffer and Ring Buffer in a multi-core controller 12100. In a non-mirrored core scenario, CMB can be allocated to each core according to its specific function, with at least two cores having different CMB buffer sizes.

[0098] In one example, to minimize the space occupied by a single log entry, the server (FW) can define the log entry structure according to the actual situation. Generally, a log entry consists of an identifier (tag) and log data (data). The tag indicates the number of bits occupied by the data. To ensure data alignment, the size can be defined as 32 bits or 64 bits. This effectively compresses the log. Figure 21 As shown, taking a 32-bit Log Entry as an example, the high 16 bits are the Tag, and the low 16 bits are the data. Two 32-bit log data sets, Data0 and Data1, need to be stored, with sizes of 0x23784500 and 0x89671299 respectively. To distinguish between Data0 and Data1, Tag 0x0001 and Tag 0x0002 represent the high and low 16 bits of Data0, respectively. 0x0007 and 0x0008 represent the high and low 16 bits of Data1. Therefore, the data stored in memory is as follows: Figure 21 As shown, the log information organization method only requires one identifier and log data, which can reduce the log information storage space.

[0099] In some examples, NVMe SQ and CQ are built on PMR. PMR is also a buffer provided by controller 12100 for host 11000. PMR space can provide a storage area with memory-level read / write speeds and data retention after power failure, meaning data can still be retained when the power is off. Data retention after power failure can be achieved in at least two ways: First, PMR can be implemented using non-volatile memory such as SCM, PCM, FeRAM, and NAND, mainly due to the non-volatile nature of the storage medium used in PMR. Second, a portion of DRAM or SRAM within storage system 12000 can be allocated to the PMR area, and the entire storage system 12000 is protected by a power failure protection design. Combining these two features, plus a certain amount of conventional NAND flash memory, PMR can be implemented. For example, storage system 12000 has dedicated power failure protection capacitors, which can safely flush data in PMR to flash memory in the event of an unexpected power failure. When storage system 12000 loses power, the contents of PMR will be automatically written to flash memory. When host system 11000 is powered on again, host 11000 can request storage system 12000 to reload the contents of PMR. The way PMR uses queues and retrieves log data is similar to CMB, and will not be described in detail here.

[0100] In this embodiment, CMB and PMR allow the host 11000 to perform Direct Memory Access (DMA), treating it as an accessible buffer for read and write operations. DMA technology enables the controller 12100 to directly transfer data with the host 11000 without the intervention of the controller processor 12120. This design significantly reduces the involvement of the controller processor 12120 in the data transfer process, thereby greatly improving the speed and flexibility of data transfer, and also enhancing the overall system performance. Through this optimization strategy, the number of memory interactions between the storage system 12000 and the host 11000 is reduced, the data transfer process is optimized, and system performance is significantly improved. This further improves the efficiency of tasks such as firmware debugging, performance analysis, and troubleshooting, providing users with a superior user experience.

[0101] Embodiments of this disclosure provide a system, such as Figure 22 As shown, system 20000 includes server 21000 and storage system 22000 (e.g., storage system 12000 as described above), and server 21000 and storage system 22000 are coupled together. Server 21000 may be, but is not limited to, a cloud server, or a host 11000 as described above; no limitation is made here. The cloud server is used to store log information (which includes identification information and log data) and to parse the log information for problem reproduction and localization.

[0102] Based on the foregoing Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 20 The electronic device, host, storage system, or controller shown can achieve the following: Figure 23 The operation method shown includes the following steps S100-S300, and the specific steps include:

[0103] S100: External devices retrieve log information from the controller's buffer based on the target address.

[0104] In some examples, external devices may include, but are not limited to, such as Figure 1 , Figure 2 , Figure 3 , Figure 4, Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 20 The host computer in the electronic device shown may also include, for example: Figure 22 The server in the system shown. The target address is the storage address of the log information in the buffer. For example... Figure 21 As shown, the log information includes identification information and log data information. The identification information indicates the bits occupied by the log data. For details, please refer to the above example. Figure 21 The explanation of the embodiments shown will not be repeated here.

[0105] S200: The controller obtains log information generated during firmware runtime from the buffer and outputs the log information to external devices.

[0106] In some examples, such as Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 20 In the illustrated embodiment, the buffer is configured to cache log information generated during firmware runtime. External devices, such as a host, can retrieve log information from the controller's buffer via methods such as... Figure 14 , Figure 15 and Figure 16 The NVMe VU Command in the illustrated embodiment can also be accessed via, as shown in the example below. Figure 17 , Figure 18 and Figure 20 The illustrated embodiment demonstrates direct memory access to the CMB or PMR. For detailed procedures, please refer to the above description. Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 20 The explanation of the embodiments shown will not be repeated here.

[0107] S300 and external devices store log information in storage devices.

[0108] In some examples, such as Figure 23 As shown, log information can be stored in, for example... Figure 15 In the first storage device shown, it is also possible to... Figure 24 As shown, log information is stored in such a way as Figure 16 The second storage device is shown above. For details, please refer to the above description. Figure 15 and Figure 16 The explanation of the embodiments shown will not be repeated here.

[0109] This disclosure provides embodiments of a controller, a host, a method for operating the controller, and a method for operating the host. The method primarily involves temporarily storing firmware-generated log information in a buffer of the controller, and retrieving this log information from the host via a high-speed interface circuit. Specifically, the log information is first temporarily stored in the controller's buffer (such as SRAM or DRAM). This avoids accelerated memory wear caused by frequent writing of log information to memory, thus preventing a shortened lifespan of the entire storage system. Then, the host retrieves this log information from the controller's memory using specific commands (such as NVMe VU Commands) or mechanisms (such as CMB or PMR) via a high-speed interface circuit (such as a PCIe interface circuit). During the temporary storage process, the log information is first placed in the CMB (Common Management Block) or PMR (Persistent Memory Region). The size of the CMB or PMR is dynamically allocated by the controller based on the buffer distribution to ensure that the speed at which the firmware stores log data is not affected by the performance of the interface circuit. Once the log information is extracted, it can be stored in the host's internal first storage device (such as the host's built-in hard drive or SSD) or an external second storage device (such as an externally connected hard drive or network storage). This storage method allows the size of the log information to be no longer limited by the controller's own storage space, but rather depends on the storage space of the storage device attached to the host, thereby greatly increasing the amount of log information that can be stored and achieving the goal of long-term log information preservation, providing strong support for subsequent analysis and diagnosis.

[0110] Embodiments of this disclosure also provide a computer storage medium that includes instructions. When the instructions are executed on the electronic device, host, storage system, or controller described in the above embodiments, the storage system causes the storage system to perform the data processing method described in the above embodiments (e.g., Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 20 , Figure 23 and Figure 24 (The electronic device, host, storage system, controller, and data processing method shown).

[0111] The embodiments provided in this disclosure are as follows: Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 20 The electronic device 10000 shown may include, but is not limited to, mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices (e.g., smartwatches, smart bracelets, smart glasses, etc.), smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein. In this context, the host 11000 in electronic device 10000 can be the processor of electronic device 10000. For example, the processor can be a chip, specifically a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system-on-chip (SoC), a central processing unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), an application processor (AP), or other integrated chips.

[0112] According to some embodiments, controller 12100 is coupled to memory 12200 and host 11000 and is configured to control memory 12200. Controller 12100 can manage data stored in memory 12200 and communicate with host 11000. In some embodiments, controller 12100 is designed to operate in a low duty cycle environment, such as Secure Digital (SD) cards, Compact Flash Cards (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, controller 12100 is designed to operate in a high duty cycle environment, such as Solid State Drives (SSDs) or Embedded MultiMedia Cards (eMMCs), which are used as data storage devices for mobile electronic devices such as smartphones, tablets, personal computers, etc., and for enterprise storage arrays. Controller 12100 can be configured to manage data stored in memory 12200 and communicate with external devices (e.g., a host computer). It controls the operation of memory 12200, such as read, erase, and program operations. In some embodiments, controller 12100 can also be configured to manage various functions related to data stored or to be stored in memory 12200, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 12100 is also configured to process error correction codes (ECC) related to data read from or written to memory 12200. Controller 12100 can also perform any other appropriate functions, such as formatting memory 12200. Controller 12100 can communicate with external devices (e.g., host computer 11000) according to a specific communication protocol.For example, the controller 12100 can communicate with external devices through at least one of various interface protocols, such as USB, MultiMediaCard (MMC), Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Device Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0113] Of course, controller 12100 can also perform any other suitable functions, such as formatting memory 12200. For example, controller 12100 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0114] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0115] The controller 12100 and one or more memories 12200 can be integrated into various types of storage systems, for example, included in the same package, such as an embedded multimedia card (eMMC), universal flash storage (UFS) package, an embedded multi-chip package (eMCP) package, or a UFS-based multi-chip package (uMCP) package. eMMC uses a unified MMC standard interface, encapsulating high-density NAND and the MMC controller in a single ball grid array (BGA) package chip. UFS is an advanced version of eMMC, also an array-type storage module composed of multiple flash memory chips and a controller. UFS overcomes the limitation of eMMC, which only supports half-duplex operation (read and write operations must be performed separately), enabling full-duplex operation and thus doubling performance. eMCP is a package that integrates volatile memory, such as Static Random-Access Memory (SRAM) or Dynamic Random-Access Memory (DRAM), on eMMC. In a specific implementation, the DRAM can be Low Power Double Data Rate Synchronous Dynamic Random-Access Memory (LPDDR). uMCP is a package that integrates volatile memory (such as SRAM or DRAM) on UFS, offering high performance and large capacity. In a specific implementation, the DRAM can be LPDDR. In other words, the storage system 12000 can be implemented and packaged into different types of end electronic devices. For example... Figure 25 In one example shown, controller 12100 and a single memory 12200 can be integrated into memory card 400. Memory card 400 may include PC card (PCMCIA, Personal Computer Memory Card International Association), CF card, Smart Media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 400 may also include memory card connector 410 that couples memory card 400 to a host (e.g., host 11000). Figure 26In another example shown, controller 12100 and multiple memories 12200 may be integrated into SSD 500. SSD 500 may also include SSD connector 510 that couples SSD 500 to a host (e.g., host 11000). In some implementations, the storage capacity and / or operating speed of SSD 500 is higher than that of memory card 400.

[0116] Figure 27 A schematic circuit diagram of an exemplary memory 600, including peripheral circuitry 602, is shown according to some aspects of this disclosure. The memory 600 may be... Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 20 An example of memory 12200 is shown. Memory 600 may include a memory cell array 601 and peripheral circuitry 602 coupled to the memory cell array 601. The memory cell array 601 may be a NAND flash memory cell array, wherein memory cells 606 are provided in the form of an array of NAND memory strings 608, all extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 608 includes a plurality of memory cells 606 coupled in series and stacked vertically. Each memory cell 606 is capable of holding a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 606. Each memory cell 606 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0117] In some implementations, each storage cell 606 is a single-level cell (SLC) having two possible storage states (levels) and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a threshold voltage within a first range, and a second storage state "1" may correspond to a threshold voltage within a second range. In some implementations, each storage cell 606 is an xLC capable of storing more than one bit of data in four or more storage states (levels). For example, an xLC may be capable of storing two bits per cell (Multi-Level Cell, MLC), three bits per cell (Triple-Level Cell, TLC), or four bits per cell (Quad-Level Cell, QLC). Each xLC may be programmed to assume a range of possible nominal storage values ​​(i.e., 2N segments of N-bit data, such as Gray code). In one example, an MLC can be programmed from an erase state to assume one of three possible programming levels by writing one of the three possible nominal storage values ​​into the cell. A fourth nominal storage value may be used for the erase state.

[0118] like Figure 27 As shown, each NAND flash memory string 608 may further include a source select gate (SSG) transistor 610 at its source end and a drain select gate (DSG) transistor 612 at its drain end. The SSG transistor 610 and DSG transistor 612 can be configured to activate the selected NAND flash memory string 608 (column of the array) during read and program operations. In some embodiments, the sources of the NAND flash memory strings 608 in the same block 604 are coupled through the same source line (SL) 614 (e.g., common SL). In other words, according to some embodiments, all NAND flash memory strings 608 in the same block 604 have an array common source (ACS). According to some embodiments, the drain of each NAND flash memory string 608 is coupled to a corresponding bit line 616, enabling data to be read from or written to the corresponding bit line 616 via an output bus (not shown). In some implementations, each NAND memory string 608 is configured to be selected or deselected by applying a selection or deselection voltage to the gate of the corresponding DSG transistor 612 via one or more DSG lines 613 and / or by applying a selection or deselection voltage to the gate of the corresponding SSG transistor 610 via one or more SSG lines 615.

[0119] like Figure 27As shown, NAND memory strings 608 can be organized into multiple blocks 604, each of which may have a common source line 614, for example, coupled to the ACS. In some embodiments, each block 604 is the basic data unit for erase operations, i.e., all memory cells 606 on the same block 604 are erased simultaneously. To erase memory cells 606 in a selected block 604, the source lines 614 coupled to the selected block 604 and unselected blocks 604 in the same plane as the selected block 604 can be biased with an erase voltage (Vers), such as a high positive bias voltage (e.g., 20V or higher). Memory cells 606 of adjacent NAND memory strings 608 can be coupled via word lines (WL) 618, which selects which row of memory cells 606 is affected by read and program operations. Peripheral circuitry 602 can be coupled to memory cell array 601 via bit line (BL) 616, word line 618, source line 614, SSG line 615, and DSG line 613. Peripheral circuitry 602 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory cell array 601 by applying and sensing voltage and / or current signals to and from each target memory cell 606 via bit line 616, word line 618, source line 614, SSG line 615, and DSG line 613. Peripheral circuitry 602 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 28 Some exemplary peripheral circuitry is shown, including a page buffer / sensor amplifier 704, a column decoder / bit line driver 706, a row decoder / word line driver 708, a voltage generator 710, a control logic unit 712, a register 714, an interface (I / F) 716 (representing the interface circuitry for communication between the controller 12100 and the memory 12200), and a data bus 718. It should be understood that additional peripheral circuitry may be included. Figure 28 Additional peripheral circuitry not shown.

[0120] Page buffer / sensor amplifier 704 can be configured to read and program (write) data from and to memory cell array 601 according to control signals from control logic unit 712. In one example, page buffer / sensor amplifier 704 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 606 coupled to selected word line 618. In yet another example, page buffer / sensor amplifier 704 can also sense a low-power signal representing a data bit stored in memory cell 606 from bit line 616 during a read operation and amplify a small voltage swing to a recognizable logic level. As detailed below and consistent with the scope of this disclosure, during a programming operation, page buffer / sensor amplifier 704 may include a storage module (e.g., latch, cache, register, etc.) for temporarily storing a segment of N-bit data (e.g., in Gray code form) received from data bus 718 and using 2 N -2 N In each programming pass of the multi-pass programming operation, the N-bit data segment is provided to the corresponding target storage unit 606 via the corresponding bit line 616.

[0121] The column decoder / bit line driver 706 can be configured to be controlled by the control logic unit 712 and to select one or more NAND memory strings 608 by applying bit line voltages generated by the voltage generator 710. The row decoder / word line driver 708 can be configured to be controlled by the control logic unit 712 and to select / deselect block 604 of the memory cell array 601 and to select / deselect word lines 618 of block 604. The row decoder / word line driver 708 can also be configured to drive word lines 618 using word line voltages generated by the voltage generator 710. In some embodiments, the row decoder / word line driver 708 can also select / deselect and drive SSG lines 615 and DSG lines 613. The voltage generator 710 can be configured to be controlled by the control logic unit 712 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be provided to the memory cell array 601.

[0122] Control logic unit 712 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 714 can be coupled to control logic unit 712 and includes a status register, a command register, and an address register for storing status information, command operation code (OP), and command address for controlling the operation of each peripheral circuit. Interface circuit 716 can be coupled to control logic unit 712 and acts as a control buffer to buffer control commands received from the host (e.g., host 11000) and forward them to control logic unit 712, and buffer status information received from control logic unit 712 and forward it to the host. Interface circuit 716 can also be coupled to column decoder / bit line driver 706 via data bus 718 and acts as a data input / output (I / O) interface and data buffer to buffer and forward data to and from memory cell array 601.

[0123] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A controller, characterized in that, The controller includes an interface circuit and a buffer; the interface circuit and the buffer are coupled; wherein... The buffer is configured to cache log information generated during firmware runtime; The interface circuit is configured as follows: Obtain log information generated during firmware runtime from the buffer; Output the log information.

2. The controller according to claim 1, characterized in that, The interface circuit includes a PCIe interface circuit.

3. The controller according to claim 1, characterized in that, The buffer includes at least one of the following: volatile memory and non-volatile memory.

4. The controller according to claim 1, characterized in that, The buffer includes at least one of the following: a controller memory buffer (CMB) and a persistent memory region (PMR).

5. The controller according to claim 4, characterized in that, The controller memory buffer (CMB) and the persistent memory region (PMR) are direct memory access regions.

6. The controller according to claim 1, characterized in that, The controller includes multiple kernels; each of the multiple kernels is coupled to the buffer. The multiple kernels are configured to cache log information generated during firmware runtime to the buffer.

7. The controller according to claim 6, characterized in that, Different kernels correspond to different storage regions in the buffer; The multiple kernels are configured to cache log information generated during firmware runtime to the corresponding storage areas.

8. The controller according to claim 1, characterized in that, The buffer includes multiple storage addresses, which are used to indicate the locations for writing and reading the log information; at any given time, the same storage address is used for at most one of the following: writing the log information and reading the log information.

9. The controller according to claim 1, characterized in that, The controller further includes a controller processor; the controller processor is coupled to the interface circuit and the buffer; The controller processor is configured to: output a control command in response to a received log extraction request; the log extraction request includes a preset number of log information to be extracted; the control command is used to control the buffer to output a number of log information less than or equal to the preset number.

10. The controller according to any one of claims 1-9, characterized in that, The log information includes identification information and log data information; the identification information is used to indicate the bits occupied by the log data.

11. A host computer, characterized in that, The host includes a host processor and a storage device; the host processor and the storage device are coupled together; the host is coupled to a controller; The host processor is configured to retrieve log information from the controller's buffer based on the target address; The target address is the storage address of the log information in the buffer; The log information is stored in the storage device.

12. The host computer according to claim 11, characterized in that, The log information includes identification information and log data information; the identification information is used to indicate the bits occupied by the log data. The host processor is further configured to obtain log data based on the identification information and the log data information.

13. The host computer according to claim 11, characterized in that, The buffer includes at least one of the following: a controller memory buffer (CMB) and a persistent memory region (PMR).

14. The host computer according to claim 13, characterized in that, The controller memory buffer (CMB) and the persistent memory region (PMR) are direct memory access regions.

15. A method for operating a controller, characterized in that, The operation method of the controller includes: Log information generated during firmware runtime is obtained from the buffer; the log information generated during firmware runtime is cached in the buffer of the controller. Output the log information.

16. The method of operating the controller according to claim 15, characterized in that, The controller includes multiple kernels; the operation method of the controller further includes: The multiple kernels cache the log information generated during the firmware runtime to the buffer.

17. The method of operating the controller according to claim 16, characterized in that, Different kernels correspond to different storage regions in the buffer; The multiple kernels cache the log information generated during firmware runtime to the buffer, including: The multiple kernels cache the log information generated during firmware runtime to the corresponding storage area.

18. The method of operating the controller according to claim 15, characterized in that, The buffer includes multiple storage addresses, which are used to indicate the location where the log information is written or read; at any given time, the same storage address is used only for writing or reading the log information.

19. The method of operating the controller according to claim 15, characterized in that, The operation method of the controller also includes: In response to a received log extraction request, a control instruction is output; the log extraction request includes a preset number of log information to be extracted; the control instruction is used to control the buffer to output a number of log information that is less than or equal to the preset number.

20. The method of operating the controller according to any one of claims 15-19, characterized in that, The log information includes identification information and log data information; the identification information is used to indicate the bits occupied by the log data.

21. A method for operating a host computer, characterized in that, The operation method of the host includes: Log information is retrieved from the controller's buffer based on the target address; the target address is the storage address of the log information in the buffer. The log information is stored in the storage device.

22. The method of operating the host according to claim 21, characterized in that, The log information includes identification information and log data information; The identification information is used to indicate the bits occupied by the log data; The operation method of the host also includes: Log data is obtained based on the identification information and the log data information.

23. A storage system, characterized in that, The storage system includes a memory and a controller as described in any one of claims 1-10; the controller and the memory are coupled.

24. A system, characterized in that, The system includes a server and a storage system as described in claim 23; the server and the storage system are coupled together.

25. The system according to claim 24, characterized in that, The server includes a cloud server.

26. An electronic device, characterized in that, The electronic device includes a controller as described in any one of claims 1-10 and a host as described in any one of claims 11-14; the host and the controller are coupled together.

27. A computer storage medium, characterized in that, The computer-readable storage medium includes instructions; when the instructions are executed on a processor, the processor causes the processor to perform the operation method of the controller as claimed in any one of claims 15-20 and / or the operation method of the host as claimed in any one of claims 21-22.

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