An integrated chip, a data access method, an electronic device, and a storage medium

Abstract

Embodiments of the present disclosure provide a memory-compute integrated chip, a data access method, an electronic device, and a storage medium. The memory-compute integrated chip includes a memory unit, a compute core, a first interface, and a memory driving circuit. The memory unit is configured to store data. The compute core is configured to perform a compute operation related to the data in the memory unit in a memory-compute integrated mode. The first interface is configured to communicate with a device outside the memory-compute integrated chip. The memory driving circuit is configured to drive the memory unit, and in response to the memory-compute integrated mode being enabled, the compute core is communicatively connected to the memory unit to access the memory unit, or in response to the memory-compute integrated mode being disabled, the first interface is communicatively connected to the memory unit to access the memory unit. The memory-compute integrated chip can greatly improve the utilization and applicability of hardware resources.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of computer technology, specifically to a memory computing chip, a data access method, an electronic device, and a storage medium. Background Technology

[0002] With the rapid development of artificial intelligence and big data, the demand for computing power and energy efficiency has surged. The separation of storage and computation in the von Neumann architecture leads to frequent data movement, limiting system performance. In-memory computing technology can embed computing functions into storage units, enabling in-situ computation, significantly reducing data movement, and substantially improving energy efficiency and computing density. Summary of the Invention

[0003] This disclosure provides at least one embodiment of an in-memory computing chip, comprising: a storage unit, a computing core, a first interface, and a storage driver circuit. The storage unit is configured to store data; the computing core is configured to perform computational operations related to the data in the storage unit in an in-memory computing mode; the first interface is configured to communicate with a device outside the in-memory computing chip; the storage driver circuit is configured to drive the storage unit, and in response to the in-memory computing mode being enabled, enables the computing core to communicate with the storage unit to access the storage unit, or in response to the in-memory computing mode being disabled, enables the first interface to communicate with the storage unit to access the storage unit.

[0004] In at least one embodiment of the in-memory computing chip provided in this disclosure, the in-memory computing chip further includes a storage controller. The storage controller is configured to control the communication connection between the storage unit and the computing core in response to the in-memory computing mode being enabled.

[0005] In at least one embodiment of the in-memory computing chip provided in this disclosure, the in-memory computing chip further includes a mode register. The mode register is configured to record the selective enabling or disabling of the in-memory computing mode.

[0006] In at least one embodiment of the in-memory computing chip provided in this disclosure, the in-memory computing chip further includes a timing calibrator. The timing calibrator is configured to perform timing optimization on the communication signals between the first interface and the memory driver circuit in response to the in-memory computing mode being disabled.

[0007] In at least one embodiment of the in-memory computing chip provided in this disclosure, the first interface is further configured to receive data read / write instructions issued by the device, perform data conversion on the data read / write instructions to obtain a first data read / write instruction; the timing calibrator is further configured to perform timing optimization on the first data read / write instructions to form a second data read / write instruction; and the storage driver circuit is further configured to perform quality optimization on the second data read / write instructions to form a third data read / write instruction, and provide the third data read / write instruction to the storage unit.

[0008] In at least one embodiment of the in-memory computing chip provided in this disclosure, the first interface is further configured to perform a data conversion operation on the data write instruction in response to receiving a data write instruction issued by the device, so as to form a first data write instruction; the timing calibrator is further configured to perform timing optimization on the first data write instruction, so as to form a second data write instruction; the storage driver circuit is further configured to perform quality optimization on the second data write instruction, so as to form a third data write instruction; and the storage unit is configured to perform a data write operation in response to receiving the third data write instruction.

[0009] In at least one embodiment of the in-memory computing chip provided in this disclosure, the data conversion operation of the data write instruction includes: performing signal conversion, voltage conversion and instruction parsing processing on the data write instruction to form a first data write instruction.

[0010] In at least one embodiment of the in-memory computing chip provided in this disclosure, the timing optimization of the first data write instruction includes: performing signal equalization processing, clock recovery processing, and data retiming processing on the first data write instruction to form a second data write instruction.

[0011] In at least one embodiment of the in-memory computing chip provided in this disclosure, the quality optimization of the second data write instruction includes: shaping, noise reduction and rate adaptation processing of the second data write instruction, and converting the optimized signal based on the storage protocol to form a third data write instruction.

[0012] In at least one embodiment of the in-memory computing chip provided in this disclosure, the first interface is further configured to perform a data conversion operation on the data read instruction received from the device to form a first data read instruction; the timing calibrator is further configured to perform timing optimization on the first data read instruction to form a second data read instruction; the storage driver circuit is further configured to perform quality optimization on the second data read instruction to form a third data read instruction; and the storage unit is configured to perform a data read operation in response to receiving the third data read instruction and provide the first data information corresponding to the third data read instruction to the device.

[0013] In at least one embodiment of the in-memory computing chip provided in this disclosure, the storage unit is further configured to receive the third data read instruction and provide the first data information to the storage driver circuit; the storage driver circuit is further configured to perform quality optimization processing on the first data information to form second data information; the timing calibrator is further configured to perform timing optimization on the second data information to form third data information; and the first interface is further configured to perform data conversion operation on the third data information based on the memory protocol corresponding to the device, and provide the converted data information to the device.

[0014] In at least one embodiment of the in-memory computing chip provided in this disclosure, the storage controller is further configured to initiate a data read request to the storage unit in response to receiving a computing operation instruction issued by the computing core; the storage unit is further configured to provide second data corresponding to the data read request to the storage driver circuit in response to receiving the data read request; the storage driver circuit is further configured to perform quality optimization on the second data to form third data; and the storage controller is further configured to provide the third data to the computing core.

[0015] This disclosure provides at least one embodiment of a data access method, wherein the data access method is applied to an in-memory computing chip, the in-memory computing chip including: a storage unit, a computing core, a first interface, and a storage driver circuit. The storage unit is configured to store data; the computing core is configured to perform computational operations related to the data in the storage unit in an in-memory computing mode; the first interface is configured to communicate with a device outside the in-memory computing chip; and the storage driver circuit is configured to drive the storage unit. The data access method includes: in response to the in-memory computing mode being enabled, the computing core communicatingly connecting to the storage unit via the storage driver circuit to access the storage unit; or, in response to the in-memory computing mode being disabled, the first interface communicatingly connecting to the storage unit via the storage driver circuit to access the storage unit.

[0016] At least one embodiment of this disclosure provides an electronic device, wherein the electronic device includes a memory computing chip provided in any embodiment of this disclosure.

[0017] At least one embodiment of this disclosure provides an electronic device, wherein the electronic device includes at least one processor and at least one memory, wherein the at least one memory stores at least one computer program, and when the at least one computer program is executed by the at least one processor, it implements the data access method provided in any embodiment of this disclosure.

[0018] At least one embodiment of this disclosure provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium is used to non-transitory store computer-readable instructions, which, when executed by a computer, implement the data access method provided in any embodiment of this disclosure.

[0019] In at least one embodiment of this disclosure, the dynamic configuration of the storage driver circuit under different operating modes enables the same hardware to switch between in-memory computing mode and standard storage mode. This effectively improves the resource utilization of the chip during non-computing tasks, avoiding idle storage units and computing cores; at the same time, it also enhances the flexibility of the system, allowing the chip to switch between the roles of dedicated computing accelerator and general-purpose storage resource according to actual needs; in addition, by following standardized memory protocols through the first interface, the in-memory computing chip can be recognized and accessed by various external devices when used as a storage resource, reducing system integration complexity and further broadening application scenarios. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0021] Figure 1 A schematic block diagram of a memory computing chip provided in at least one embodiment of the present disclosure is shown.

[0022] Figure 2 A schematic block diagram of another in-memory computing chip provided in at least one embodiment of the present disclosure is shown.

[0023] Figure 3 A flowchart of a data access method provided by at least one embodiment of the present disclosure is shown.

[0024] Figure 4 A flowchart of another data access method provided by at least one embodiment of the present disclosure is shown.

[0025] Figure 5 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure is shown.

[0026] Figure 6 A schematic block diagram of another electronic device provided in at least one embodiment of the present disclosure is shown.

[0027] Figure 7 A schematic block diagram of a non-transitory computer-readable storage medium provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0029] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. The terms “comprising” or similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0030] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0031] With the rapid development of technologies such as artificial intelligence and big data, unprecedented demands have been placed on the computing power and energy efficiency of computing systems. The von Neumann architecture employs a design that physically separates storage units from computing units. Under the von Neumann architecture, executing computing tasks requires frequent data transfer between storage units (such as DRAM and hard drives) and computing units (such as CPUs and GPUs). This frequent data transfer leads to significant performance bottlenecks and power consumption, specifically manifested as: the "memory wall" problem, where processor performance is limited due to waiting for data; the "power wall" problem, where data transfer operations themselves consume a huge amount of energy, accounting for a high proportion of the total power consumption of the processing system; and the "computing power wall" problem, where the data supply speed cannot match the processor's computing speed.

[0032] To overcome the technical bottlenecks of the von Neumann architecture, in-memory computing technology has emerged. In-memory computing architecture embeds computing functions within or deeply integrates with storage units, performing computational operations at the location where data is stored. This significantly reduces the need for data movement and demonstrates enormous potential in improving computing energy efficiency and computing density.

[0033] For example, near-memory computing technology uses advanced packaging processes such as 2.5D and 3D stacking to physically integrate computing chips (such as GPUs and ASICs) with high-bandwidth memory (HBM) to shorten interconnect distances and thus achieve extremely high memory access bandwidth. However, in-memory computing chips are typically highly optimized for specific computing tasks (such as image recognition, speech processing, or neural network training).

[0034] The inventors of this disclosure have noted that, for example, when an in-memory computing chip is not performing its assigned computing tasks, the computing cores and storage resources within the chip will be idle. For instance, an in-memory computing accelerator card in an artificial intelligence (AI) training server will be completely idle during non-training periods, unable to provide value to other parts of the system, resulting in a significant waste of hardware resources and an increase in total cost of ownership. This also severely restricts the economic benefits and flexibility of in-memory computing technology in practical commercial deployments.

[0035] Therefore, there is an urgent need for an in-memory computing chip architecture that can effectively solve the problem of idle chip resources in non-computing task scenarios while retaining the advantages of high energy efficiency and high computing power of in-memory computing, thereby greatly improving the utilization rate and applicability of hardware resources.

[0036] Based on at least one of the above, at least one embodiment of this disclosure provides a memory computing chip, a data access method, an electronic device, and a non-transitory computer-readable storage medium. The memory computing chip includes a storage unit, a computing core, a first interface, and a storage driver circuit; wherein the storage unit is configured to store data; the computing core is configured to perform computational operations related to the data in the storage unit in a memory computing mode; the first interface is configured to communicate with a device outside the memory computing chip; the storage driver circuit is configured to drive the storage unit, and in response to the memory computing mode being enabled, enables the computing core to communicate with the storage unit to access the storage unit, or in response to the memory computing mode being disabled, enables the first interface to communicate with the storage unit to access the storage unit. This memory computing chip can effectively solve the problem of resource idleness in non-computing task scenarios while retaining the high energy efficiency and high computing power advantages of memory computing, thereby significantly improving the utilization and applicability of hardware resources.

[0037] Figure 1 and Figure 2 A schematic block diagram of a memory computing chip provided in at least one embodiment of the present disclosure is shown.

[0038] like Figure 1 and Figure 2As shown, the in-memory computing chip 3000 includes a storage unit 300, a computing core 310, a storage driver circuit 320, and a first interface 330.

[0039] Storage unit 300 is configured to store data.

[0040] The computing core 310 is configured to perform computational operations related to the data in the storage unit 300 in in-memory computing mode.

[0041] The first interface 330 is configured to communicate with a device 2000 outside the in-memory computing chip.

[0042] The storage driver circuit 320 is configured to drive the storage unit 300. Furthermore, the storage driver circuit 320 is also configured to, in response to the in-memory computing mode being enabled, enable the computing core 310 to communicate with the storage unit 300 to access the storage unit 300, or, in response to the in-memory computing mode being disabled, enable the first interface 330 to communicate with the storage unit 300 to access the storage unit 300.

[0043] For example, such as Figure 1 As shown, in in-memory computing mode, when in-memory computing mode is enabled, the storage driver circuit 320 can configure internal paths to establish a communication connection between the computing core 310 and the storage unit 300. In in-memory computing mode, the computing core 310 can directly and at high speed access the data in the storage unit 300 and perform calculations.

[0044] For example, such as Figure 2 As shown, when the in-memory computing mode is disabled (i.e., standard storage mode), the storage drive circuit 320 can be configured to switch internal paths, enabling the first interface 330 to establish a communication connection with the storage unit 300. At this time, the external device 2000 can access the storage unit 300 via the second interface 200 and the first interface 330 using the standard memory protocol.

[0045] For example, storage unit 300 is the data storage carrier of in-memory computing chip 3000, used to store all data that needs to be processed or has been processed. In in-memory computing mode, storage unit 300 can store model parameters, input data and intermediate results required by computing core 310; in standard storage mode, storage unit 300 can provide general data storage space for device 2000.

[0046] The internal structure of memory cell 300 may include one or more memory arrays. The memory array is the main structure of memory cell 300, consisting of a two-dimensional grid composed of a large number of memory cell circuits arranged in rows and columns. Each memory cell circuit is a basic unit capable of storing one bit of data (e.g., representing logic '0' or '1' through the charge of a capacitor or the threshold voltage of a transistor). By activating specific word lines and bit lines, read or write operations can be performed on the memory cell circuit at a specific address in the memory array.

[0047] For example, the storage unit 300 may include an HBM storage unit, an RRAM storage unit, a DRAM storage unit, or a PCM storage unit, etc., and the embodiments disclosed herein are not limited thereto.

[0048] For example, the compute core 310 is the computing engine of the in-memory computing chip when performing in-memory computing tasks. The compute core 310 can be configured to perform specific computationally intensive operations, such as various calculations in the field of artificial intelligence.

[0049] For example, the computing core 310 may include a central processing unit (CPU) or other types of processors, such as an artificial intelligence (AI) processor, a graphics processing unit, etc., and may include one or more multiply-accumulate units, parallel processing units, or tensor processing units to efficiently execute algorithms such as matrix multiplication and convolution operations.

[0050] For example, the microarchitecture of the compute core 310 can be designed as a single instruction multiple data stream or multiple instruction multiple data stream to support the processing of tasks with different degrees of parallelism.

[0051] For example, the computing core 310 can be configured to be activated in in-memory computing mode and establish a data path with the storage unit 300.

[0052] For example, the first interface 330 is a protocol converter for the in-memory computing chip in standard storage mode. The first interface 330 can be configured to realize bidirectional conversion between the internal storage unit protocol of the in-memory computing chip and the external standard memory protocol, so that the external device 2000 can access the internal storage resources of the in-memory computing chip using standardized commands through the second interface 200.

[0053] For example, in one alternative implementation, the first interface 330 can be implemented as a low-power double data rate synchronous dynamic random access memory (DRAM) at the physical layer. For example, external to the in-memory computing chip, the first interface 330 can communicate with the LPDDR master PHY of device 2000 (e.g., system-on-a-chip (SoC), direct memory (DMA) controller, etc.) via a signal and command set conforming to the JEDEC LPDDR standard. For example, internal to the in-memory computing chip, the first interface 330 can convert received standard LPDDR read / write commands into a signal format that can be processed by internal circuitry; the first interface 330 can also convert data received internally into LPDDR standard-compliant signal waveforms and send them to the external device 2000.

[0054] For example, the first interface 330 can also be configured to support other standard memory protocols from the physical layer, such as GDDR PHY or DDR PHY.

[0055] For example, the storage drive circuit 320 can be configured to drive the storage cell 300, i.e., provide signals that meet the electrical characteristics and timing requirements of the storage cell 300; and as a configurable data path switch to switch internal connections according to the operating mode.

[0056] For example, in one alternative implementation, the memory driver circuit 320 can be configured as a customized HBM physical layer circuit, such as an interface circuit between the digital controller and the analog memory medium, for handling signal integrity, timing, and protocols.

[0057] For example, when the in-memory computing mode is enabled, the storage drive circuit 320 serves as a dedicated high-speed channel between the computing core 310 and the HBM storage unit 300, enabling data to be transmitted in a high-speed parallel manner as required by the HBM protocol.

[0058] For example, when the in-memory computing mode is disabled, the storage driver circuit 320 switches to "standard storage mode". In this mode, its HBM protocol processing logic can be bypassed while retaining signal quality processing functions (such as equalization, amplification, etc., which are not limited in the embodiments of this disclosure).

[0059] For example, the memory driver circuit 320 may be a custom physical layer circuit designed specifically to drive a particular type of memory cell (such as HBM, HMC, RRAM, etc.) and has a configurable data path.

[0060] For example, device 2000 can be the service object and data interaction subject of in-memory computing chip 3000 in standard storage mode.

[0061] For example, device 2000 can be any system host device that requires storage resources, such as a central processing unit, graphics processing unit, system-on-a-chip, or dedicated accelerator. These devices access the in-memory computing chip 3000 through their internally integrated master physical layer (e.g., LPDDR Master PHY, DDR Master PHY, etc.) that is compatible with the protocol of the first interface 330.

[0062] In at least one embodiment of this disclosure, the dynamic configuration of the storage driver circuit under different operating modes enables the same hardware to switch between in-memory computing mode and standard storage mode. This effectively improves the resource utilization of the chip during non-computing tasks, avoiding idle storage units and computing cores; at the same time, it also enhances the flexibility of the system, allowing the chip to switch between the roles of dedicated computing accelerator and general-purpose storage resource according to actual needs; in addition, by following standardized memory protocols through the first interface, the in-memory computing chip can be recognized and accessed by various external devices when used as a storage resource, reducing system integration complexity and further broadening application scenarios.

[0063] In some embodiments of this disclosure, such as Figure 1 As shown, the in-memory computing chip 3000 may also include a storage controller 340.

[0064] The storage controller 340 can be configured to control the communication connection between the storage unit and the computing core in response to the activation of the in-memory computing mode.

[0065] For example, the storage controller 340 can be implemented as a dedicated digital logic unit, which can serve as a data scheduling hub between the computing core 310 and the storage unit 300.

[0066] For example, the storage controller 340 can be configured to receive data access requests from the computing core 310 (e.g., reading a weight matrix block or writing a computation result), and to translate task-logic-based virtual address or data block requests issued by the computing core 310 into physical address sequences and specific operation commands that the storage unit 300 can recognize and that conform to its physical architecture.

[0067] For example, as mentioned above, the storage unit 300 (such as HBM) is composed of multiple parallel storage channels and storage banks. The storage controller 340 can cleverly map consecutive logical addresses to different storage banks and channels through a corresponding address mapping algorithm, so that access to consecutive data can be evenly distributed across multiple physical units. When the computing core 310 initiates multiple data access requests simultaneously, the arbitration logic contained in the storage controller 340 can schedule and sort these requests according to preset strategies (such as priority, timing urgency, etc., which are not limited in the embodiments of this disclosure), and issue the optimal command sequence to the storage unit 300 to hide access latency and maintain the continuity of the data flow.

[0068] For example, since accessing storage cell 300 involves complex timing parameters, such as row activation, precharge, and column read / write, the storage controller 340 can further integrate a timing state machine to generate all control signals (such as RAS, CAS, WE) that conform to the timing specifications of storage cell 300, ensuring that each read / write operation is executed correctly and efficiently.

[0069] In an alternative implementation, such as in in-memory computing mode, the computing core 310, due to computational needs, sends a request to the memory controller 340 to "read data from address A to address B". The memory controller 340 can decompose this request into a set of specific DRAM operation commands (such as ACTIVATE, READ) for different memory banks and channels, and optimize their execution order. These commands can be converted into HBM-compliant electrical signals by the memory driver circuit 320, driving the memory cell 300 to perform the corresponding read operation. The data read by the memory cell 300 is returned to the memory controller 340 through the memory driver circuit 320. The memory controller 340 then performs buffering and reassembly processing on the returned data, and distributes the data to the computing core 310 for computation according to the format and timing required by the computing core 310.

[0070] In at least one embodiment of this disclosure, the storage controller provides centralized and efficient scheduling management for data access in in-memory computing mode. This helps optimize data transmission timing and bandwidth utilization between the computing core and storage units. Through mechanisms such as address interleaving and command arbitration, the storage controller can significantly improve the data supply efficiency and processing throughput of in-memory computing tasks, while also enhancing operational reliability and stability under complex access timings.

[0071] In some embodiments of this disclosure, the in-memory computing chip 3000 may also include a mode register (not shown in the figure).

[0072] The mode register can be configured to record the selective enabling or disabling of in-memory computing modes, thereby allowing the in-memory computing chip to operate in different modes.

[0073] For example, the mode register can be implemented as a storage unit configured by software or hardware logic, and the value of a specific bit stored therein can directly determine the global operating state of the in-memory computing chip 3000.

[0074] For example, the mode register can include at least one mode selection bit.

[0075] For example, when the mode selection bit is set to "1", it indicates that the in-memory computing mode is enabled; when the mode selection bit is set to "0", it indicates that the in-memory computing mode is disabled (i.e., the standard storage mode is enabled).

[0076] For example, the mode register can be implemented as a multi-bit register to record more configuration information. For example, the configuration information may include a low-power mode enable bit, a specific LPDDR rate configuration field in memory mode, or a computing core operating frequency classification in in-memory computing mode, etc. The embodiments of this disclosure do not limit this, thereby achieving more refined control.

[0077] For example, the mode register can be connected to control entities inside or outside the in-memory computing chip 3000 through a configuration interface. This interface can be a standard low-speed serial peripheral interface, an integrated circuit built-in bus, or a memory-mapped register accessed via a top-level pin of the chip; the embodiments disclosed herein are not limited to this. For example, system software (such as a device driver or operating system kernel) can use this configuration interface to dynamically write to the mode register according to a global task scheduling policy, thereby initiating a switch in the operating mode.

[0078] For example, the output of the mode register can be connected to the control terminals of multiple related modules within the in-memory computing chip 3000. When its output value changes, a global mode switching signal can be generated. This signal can directly control the switching of the internal data path of the memory driver circuit 320 and, as an enable signal, control the activation and sleep states of modules such as the memory controller 340, computing core 310, timing calibrator 350, and first interface 330 according to the current mode. For example, in in-memory computing mode, the mode switching signal can activate the clock and power supply of the memory controller 340 and computing core 310, while simultaneously putting the timing calibrator 350 and first interface 330 into a low-power state; in standard memory mode, the opposite operation is performed.

[0079] In one alternative implementation, for example, the system software determines that the in-memory computing chip 3000 needs to be switched from in-memory computing mode to standard storage mode. The system software can write a specific value representing "standard storage mode" to the mode register via the configuration bus (e.g., clearing the mode selection bit to "0"). Once the mode register value is updated, a corresponding mode switching signal is immediately generated. Upon receiving this signal, the modules within the in-memory computing chip 3000 begin coordinated switching actions. For example, the computing core 310 can enter sleep mode after completing its current task, and the storage controller 340 will stop working; the first interface 330 and the timing calibrator are activated and initialized. The storage driver circuit 320 can, based on this signal, reconfigure its internal data path from being connected to the storage controller 340 to being connected to the timing calibrator. For example, after the mode switch is complete, the in-memory computing chip 3000 operates fully in standard storage mode, waiting for the device 2000 to initiate storage access through the first interface 330.

[0080] In at least one embodiment of this disclosure, a stable and software-configurable hardware control mechanism is provided for switching operating modes by setting a mode register. This makes the mode switching operation flexible, reliable, and easy to integrate into system-level resource management strategies. The system software can easily adjust the working role of the in-memory computing chip according to the dynamic changes in computing load, just like configuring a standard peripheral, thereby realizing intelligent dynamic management and optimization of hardware resources from the system level, greatly improving the adaptability and efficiency of the entire computing system.

[0081] The inventors of this disclosure have noted that, in standard memory mode, data needs to be transferred between a memory driver circuit 320 following an internal custom protocol and a first interface 330 following an external standard protocol. These two protocols (e.g., a protocol for HBM and a protocol for LPDDR) differ fundamentally in clock architecture, timing parameters (such as setup / hold time), signal edge rates, etc. Direct connection would result in severe signal timing violations, causing data transmission errors.

[0082] Based on this, in some embodiments of this disclosure, such as Figure 1 As shown, the in-memory computing chip 3000 may also include a timing calibrator 350. The timing calibrator 350 can be configured to perform timing optimization on the communication signals between the first interface and the memory driver circuitry in response to the in-memory computing mode being disabled.

[0083] For example, timing calibrator 350 can be configured to perform timing alignment and signal retiming operations on communication signals between the first interface and the storage driver circuit.

[0084] For example, timing calibrator 350 can be configured to compensate for clock skew and data delay of signals on the transmission path, so that the data signal and its corresponding clock or strobe signal meet the precise timing relationship required by the target protocol when they arrive at the target module (first interface 330 or storage driver circuit 320).

[0085] For example, the timing calibrator 350 can be configured to reshape signals that suffer from inter-symbol interference due to channel loss, restore their sharp edges, and reduce the bit error rate.

[0086] For example, timing calibrator 350 may include a delay phase-locked loop or phase-locked loop circuit that can generate a precise and controllable delay, which can be used to perform bit-by-bit delay adjustment of the data signal until it is aligned with the clock edge.

[0087] For example, the timing calibrator 350 may also include a variable delay line for coarse and fine adjustment of the delay of the overall signal path.

[0088] In an alternative implementation, for example, in standard storage mode, for the data write path, the first interface 330 can be configured to receive LPDDR-compliant signals from an external device 2000. These signals, after being converted into digital data streams, can be passed to the storage driver circuit 320. However, due to protocol differences, their timing model does not meet the requirements of the HBM interface. The timing calibrator 350 can be configured to retime the data and clock signals, adjusting their relative delays to generate a set of signals that timing-compliant with the expected input requirements of the storage driver circuit 320 in "standard storage mode." The optimized signals can then be fed into the storage driver circuit 320, thereby driving the storage cell 300 to complete the write operation.

[0089] In an alternative implementation, for example, in standard storage mode, for the data read path, storage unit 300 can output data through storage driver circuit 320, where the signal timing is based on HBM physical layer characteristics. Before entering the first interface 330 for protocol conversion, the signal is processed by timing calibrator 350. Timing calibrator 350 can adjust the timing of these signals to meet the setup and hold time requirements of the LPDDR Slave PHY for input signals. Subsequently, the first interface 330 can convert these signals into standard LPDDR signals and send them to device 2000.

[0090] In at least one embodiment of this disclosure, a timing calibrator is used to resolve the timing matching issue between the output signal of the storage driver circuit and the first interface standard protocol in standard storage mode. This effectively ensures the signal integrity and timing accuracy of the in-memory computing chip 3000 when it is used as a general-purpose memory for high-speed communication with external host devices. Precise calibration of the clock and data relationships significantly reduces the bit error rate of data transmission, improves communication stability and system compatibility, and enhances the reliability of the storage mode functionality.

[0091] In some embodiments of this disclosure, such as Figure 1 As shown, the first interface 330 can be further configured to receive data read / write instructions from the device, perform data conversion on the data read / write instructions to obtain a first data read / write instruction. The timing calibrator 350 can be further configured to perform timing optimization on the first data read / write instruction to form a second data read / write instruction. The storage driver circuit 320 can be further configured to perform quality optimization on the second data read / write instruction to form a third data read / write instruction, and provide the third data read / write instruction to the storage unit.

[0092] For example, in standard storage mode, the first interface 330 can be configured to convert external standard protocols into signals that can be processed by internal circuitry. For example, the first interface 330 can receive raw data read / write commands and related data from device 2000 that conform to standard protocols (such as LPDDR) through its I / O circuitry. These signals include complete commands, addresses, and information.

[0093] For example, the first interface 330 can be configured to perform preliminary data conversion on the received signal. This conversion process may include, for example, the following:

[0094] Serial-to-parallel conversion: Converts high-speed serially transmitted data streams into parallel data formats required for internal processing;

[0095] Signal level conversion: Converts the signal level of the external interface voltage domain (e.g., 1.2V) to the core voltage domain of the chip (e.g., 0.9V).

[0096] Analysis: The commands of the standard protocol are decoded to extract core information such as operation type (read / write) and target address, forming a more general intermediate instruction format that is decoupled from specific external protocols.

[0097] After the above conversion process, a first data read / write instruction can be obtained. This first data read / write instruction is logically defined, but its signal timing characteristics are not yet adapted to the subsequent memory drive circuit. Therefore, the timing calibrator 350 can perform timing integration so that instructions and data can be sampled at precise moments.

[0098] For example, the timing calibrator 350 can be configured to receive a first data read / write instruction from the first interface 330 and perform precise timing optimization on the first data read / write instruction.

[0099] For example, the timing optimization process may include:

[0100] Clock data recovery and alignment: Recover the accurate clock signal from the data stream and use DLL or PLL circuits to apply an adjustable delay to each bit of data so that the center of the effective window of the data signal is strictly aligned with the clock edge.

[0101] Deskipation: Compensates for the slight delay (skip) between command, address, and data signals in an instruction due to path differences, so that they arrive synchronously.

[0102] After the timing optimization process described above, the second data read / write instruction is generated. At this point, the timing relationship of the second data read / write instruction has been adjusted to meet the ideal state of the input requirements of the memory driver circuit 320.

[0103] For example, the storage driver circuit 320 can be configured to receive a second data read / write instruction from the timing calibrator 350 and perform quality optimization on the second data read / write instruction.

[0104] For example, quality optimization processes may include:

[0105] Signal shaping: Reshaping waveforms that have attenuated due to transmission to restore their steep edges;

[0106] Amplification: Amplifying the signal voltage / current amplitude to a level sufficient to drive a high-load memory cell array;

[0107] Pre-emphasis / equalization: Pre-emphasis is applied to compensate for high-frequency losses, so that the signal remains clear when it is transmitted over long lines to the storage unit 300;

[0108] Protocol generation: The optimized signal is used to form a third data read / write instruction according to the electrical interface requirements of the storage unit 300 (such as HBM).

[0109] After the above quality optimization process, a third data read / write instruction is generated. The storage driver circuit 320 provides the third data read / write instruction to the storage unit 300, thereby realizing the physical read / write operation on the storage unit 300.

[0110] In at least one embodiment of this disclosure, by explicitly defining the data read / write instructions in standard storage mode, a complete, robust, and high-performance data path is constructed through sequential processing steps such as protocol conversion, timing optimization, and quality optimization. This modular and staged processing approach enables standard instructions from external devices to be accurately and reliably converted and transmitted to the customized storage unit. It effectively solves the compatibility problem between different protocol domains, ensures operational reliability through timing optimization, and improves signal integrity through quality optimization, thereby realizing the complete functionality and performance of the in-memory computing chip as a general-purpose memory.

[0111] In some embodiments of this disclosure, such as Figure 1 As shown, the first interface 330 can be further configured to perform a data conversion operation on the data write command received from the device to form a first data write command. The timing calibrator 350 can be further configured to perform timing optimization on the first data write command to form a second data write command. The storage driver circuit 320 can be further configured to perform quality optimization on the second data write command to form a third data write command. The storage unit 300 can be configured to perform a data write operation in response to receiving the third data write command.

[0112] This embodiment further describes the collaborative workflow of the various modules inside the in-memory computing chip 3000 when the device 2000 initiates a data write to the in-memory computing chip 3000, so that external data can be accurately and reliably stored in the storage unit 300.

[0113] For example, the first interface 330 can be configured to respond to receiving a data write command conforming to a standard memory protocol (such as LPDDR) from an external device 2000. For example, the data write command may include a write command, a target address, and the data to be written.

[0114] For example, the first interface 330 can be configured to perform data conversion operations on the data write command and the accompanying data.

[0115] For example, the first interface 330 can be configured to receive physical layer signals (such as converting differential signals to single-ended signals), perform serial-to-parallel conversion (converting high-speed serial data streams into wide-bit parallel data), perform level conversion (converting signals in the interface voltage domain to the chip's internal voltage domain), and perform preliminary parsing and decoding of command packets.

[0116] For example, after data conversion, a first data write instruction is formed. For example, the first data write instruction may include explicit write operation semantics, target address information, and parallel data to be written, but its electrical characteristics and timing do not yet meet the direct access requirements of the storage unit 300.

[0117] For example, timing calibrator 350 can be configured to perform timing optimization on the first data write instruction after receiving a first data write command from the first interface 330.

[0118] For example, the timing calibrator 350 can be configured to precisely adjust the delay and clock data alignment of the command, address, and data bus signals in the instruction through its internal delay-locked loop, variable delay line, and other circuits. This ensures that all signals meet their setup and hold time requirements when reaching the next stage, generating a timing-corrected second data write instruction. At this point, the instruction content remains unchanged, but the timing relationship of all its signals has been adjusted to match the optimal state that matches the input timing model of the memory driver circuit 320.

[0119] For example, the storage driver circuit 320 can be configured to receive a second data write instruction from the timing calibrator 350 and perform quality optimization on the second data write instruction.

[0120] For example, the storage driver circuit 320 can be configured to perform signal shaping (repairing waveform edges), signal amplification (to meet drive capability requirements), or apply pre-emphasis or equalization techniques to compensate for high-frequency losses on the second data write instruction, in order to generate a third data write instruction. For example, the storage driver circuit 320 can also perform final formatting of the quality-optimized signal according to the electrical interface specifications of the storage cell 300.

[0121] For example, the generated third data write instruction can be directly used to drive memory cell 300. For example, memory cell 300 can be configured to initiate its internal operation sequence in response to receiving a third data write instruction from memory driver circuit 320. For example, memory cell 300 can be configured to decode and activate the corresponding memory bank, word line, and bit line according to the target address in the instruction; then, write the data to be written carried in the instruction to the designated memory cell circuit. This completes the operation of persistently storing external data in the chip's internal memory array.

[0122] In at least one embodiment of this disclosure, a highly reliable data write channel from an external standard interface to an internal custom storage unit is constructed by clearly defining consecutive and well-defined processing stages in the data write path. This architecture enables write commands and data from different protocol domains (such as LPDDR) to be accurately written into high-performance storage units (such as HBM) after precise protocol conversion, timing reshaping, and signal quality enhancement. It not only solves the compatibility challenges between heterogeneous protocol interfaces but also ensures data integrity under high-speed operation through multi-level signal conditioning, thus providing crucial support for realizing complete and stable data write functionality in standard storage modes for in-memory computing chips.

[0123] In some embodiments of this disclosure, a data conversion operation is performed on the data write instruction, including: signal conversion, voltage conversion, and instruction parsing processing of the data write instruction to form a first data write instruction. This step can be performed, for example, by the first interface 330.

[0124] For example, in signal conversion, the input / interface circuit of the first interface 330 can convert external electrical signals received from physical pins into signals that can be processed by internal digital logic.

[0125] For example, the first interface 330 can be configured to convert differential signals (such as CK_t / CK_c) into single-ended signals to enhance noise immunity and simplify subsequent processing; at the same time, it can perform high-speed serial-to-parallel conversion, reorganizing the serial data stream into wide-bit parallel data to accommodate the internal processing bandwidth.

[0126] For example, voltage conversion can be achieved by a level shifter circuit included in the first interface 330. Since the operating voltage (e.g., 1.2V) of an external memory interface (such as LPDDR) may differ from the internal logic voltage (e.g., 0.8V or 0.9V) of the in-memory computing chip 3000, direct connection could lead to device damage or logic errors. Therefore, it is necessary to safely and accurately convert the levels of all signals received from the outside (e.g., commands, addresses, data, etc.) from the interface voltage domain to the internal voltage domain.

[0127] For example, instruction parsing can be performed by a logic control unit or finite state machine included in the first interface 330, decoding the received and preliminarily converted digital signal stream. For instance, it can identify the command encoding of a standard protocol (such as LPDDR) (e.g., determine whether it's a write or read command) and extract key information such as the target memory bank, row and column addresses, and the write data mask. This process can "unpack" data packets encapsulated by external standard protocols, forming an internally unified intermediate instruction format decoupled from specific external protocols.

[0128] In at least one embodiment of this disclosure, the first interface 330 can be configured to process external complex signals into internally usable instructions, enabling the in-memory computing chip to securely and correctly receive and understand write commands from a variety of possible standard interfaces, thereby improving the compatibility and robustness of the architecture.

[0129] In some embodiments of this disclosure, timing optimization of the first data write instruction includes: performing signal equalization processing, clock recovery processing, and data retiming processing on the first data write instruction to form a second data write instruction. This step can be performed, for example, by a timing calibrator 350.

[0130] For example, signal equalization processing is used to compensate for inter-symbol interference caused by high-frequency losses during signal transmission on the PCB board or inside the 3000 in-memory computing chip.

[0131] For example, this can be achieved using a continuous-time linear equalizer (CTLE) or a decision feedback equalizer (DFE) in the timing calibrator 350. For example, a continuous-time linear equalizer can correct attenuated waveforms by boosting high-frequency components; for example, a decision feedback equalizer can use the decision results of previous bits to cancel out interference in the current bit, thereby opening up the originally closed data eye diagram.

[0132] For example, clock recovery processing can be performed by the clock data recovery circuit (CDR) in the timing calibrator 350. For instance, in a source-synchronous interface, the clock data recovery circuit can extract a clean, low-jitter clock signal from the strobe signal accompanying the data, or from the data stream itself in some embedded clock systems. This recovered clock can serve as a reference for subsequent data retiming to determine the corresponding phase relationship between the sampled clock and the data.

[0133] For example, in data retiming processing, the equalized data and command signals can be resampled and latched using a clock recovered by a clock data recovery circuit or an adjusted reference clock. For instance, a delay-locked loop (DLL) or a phase-locked loop (PLL) can be used to control the variable delay line, finely adjusting the delay of each signal path and ultimately aligning all signals to the effective edge of the clock. This process eliminates skew between different signal lines, ensuring that the signals meet the setup and hold time requirements of the storage driver circuit 320 input.

[0134] In at least one embodiment of this disclosure, timing optimization includes signal processing procedures such as equalization, clock recovery, and retiming, which solves the problem of timing mismatch in high-speed signals, improves signal integrity, and enables the command, address, and data buses to maintain precise synchronization under high-speed operation, greatly improving the timing tolerance of data transmission and the reliability of the overall system.

[0135] In some embodiments of this disclosure, the quality optimization of the second data write instruction includes: shaping, noise reduction, and rate adaptation of the second data write instruction, and converting the optimized signal based on the storage protocol to form a third data write instruction. This step can be performed, for example, by the storage driver circuit 320.

[0136] For example, for data shaping, waveform shapers or output drivers can be used to shape signals to restore the rounded edges caused by the resistance and capacitance effects of the transmission path, making them steeper and more regular, thereby reducing switching time and improving timing.

[0137] For example, noise reduction techniques can be used to reduce noise in a signal through filtering and power supply noise suppression. This can include using decoupling capacitors in the driver's power domain and filtering circuits on the signal path to suppress power supply noise and coupling noise, thereby improving the signal-to-noise ratio.

[0138] For example, in rate matching processing, since there may be a difference between the external interface rate and the operating rate of the storage unit 300, the rate matching problem can be solved by using an asynchronous FIFO or a flexible buffer. An asynchronous FIFO or flexible buffer acts as a buffer to smooth data flow between different clock domains, preventing data overflow or underflow.

[0139] For example, the memory driver circuit 320 can be configured to convert the aforementioned optimized general-purpose digital signal into a signal conforming to the physical layer protocol of the memory cell 300 (such as HBM). This may include generating HBM-specific command codes, driving the command / address bus and data bus according to HBM timing requirements, and meeting its specific electrical specifications (such as drive strength, SSTL, or POD levels).

[0140] In at least one embodiment of this disclosure, the quality optimization stage may include, for example, processing steps such as shaping, noise reduction, rate adaptation, and final protocol conversion. This series of processes can ensure that instructions and data have sufficient signal quality, purity, and protocol correctness when they arrive at the storage unit.

[0141] In some embodiments of this disclosure, such as Figure 1As shown, the first interface 330 can be further configured to perform a data conversion operation on the data read instruction received from the device 2000 to form a first data read instruction. The timing calibrator 350 can be further configured to perform timing optimization on the first data read instruction to form a second data read instruction. The storage driver circuit 320 can be further configured to perform quality optimization on the second data read instruction to form a third data read instruction. The storage unit 300 can be configured to perform a data read operation in response to receiving the third data read instruction and provide the first data information corresponding to the third data read instruction to the device.

[0142] This embodiment further describes how the modules inside the in-memory computing chip 3000 work together to reliably read and transmit the data in the storage unit 300 to the device 2000 when the device 2000 initiates a data read request to the in-memory computing chip.

[0143] For example, the first interface 330 can be configured to respond to receiving a data read instruction conforming to a standard memory protocol (such as LPDDR) from the device 2000. For example, the data read instruction may include a read command and source address information.

[0144] For example, the first interface 330 can be configured to perform data conversion operations on the data read command. This process is similar to the initial stage of the write path, and may include, for example, physical layer signal reception, level conversion, and preliminary parsing and decoding of the command packet. For example, after data conversion, an internally unified first data read command is formed.

[0145] For example, timing calibrator 350 can be configured to receive a first data read instruction from first interface 330. For example, timing calibrator 350 can be configured to perform timing optimization on the first data read instruction. For example, through its internal DLL, PLL, and variable delay line circuits, it can precisely adjust the delay and clock alignment of the command and address signals in the first data read instruction to generate a timing-corrected second data read instruction, so that it can arrive at memory driver circuit 320 with the correct timing.

[0146] For example, the memory driver circuit 320 can be configured to receive a second data read instruction from the timing calibrator 350. For example, the memory driver circuit 320 can be configured to optimize the quality of the second data read instruction, such as by performing signal shaping or amplification operations, to improve the physical quality of the instruction signal and generate a third data read instruction that can be used to drive the memory cell 300.

[0147] For example, memory cell 300 can be configured to initiate its internal read sequence in response to receiving a third data read instruction from memory drive circuit 320. For example, based on the source address in the instruction, the corresponding memory bank, word line, and bit line can be decoded and activated to sense, amplify, and latch the data in the target memory cell.

[0148] For example, storage unit 300 can be configured to complete a read operation and output the first data information corresponding to the third data read instruction. Here, "first data information" refers to the raw data signal read from the storage array without subsequent path optimization.

[0149] For example, storage unit 300 can be configured to provide first data information to storage driver circuit 320, thereby opening a data return path. Subsequent processes will involve the storage driver circuit, timing calibrator, and the first interface performing reverse processing on the read data so that it can be received by device 2000 in a form conforming to external protocols.

[0150] In at least one embodiment of this disclosure, a reliable channel is constructed from receiving an external read command to successfully reading data from the internal storage unit through a data read command reception, conversion, and execution path. In standard storage mode, the in-memory computing chip can correctly parse the external read request and, after precise timing reshaping and signal quality enhancement, accurately transmit the request to the storage unit to trigger the read operation. This improves the accuracy and timeliness of end-to-end read command transmission.

[0151] In some embodiments of this disclosure, such as Figure 1 As shown, the storage unit 300 can be further configured to receive a third data read instruction and provide the first data information to the storage driver circuit. The storage driver circuit 320 can be further configured to perform quality optimization processing on the first data information to form second data information. The timing calibrator 350 can be further configured to perform timing optimization on the second data information to form third data information. The first interface 330 can be further configured to perform data conversion operations on the third data information based on the memory protocol corresponding to the device 2000, and provide the converted data information to the device 2000.

[0152] This embodiment further describes the complete return path of how data read from storage unit 300 is processed and returned to device 2000 during the data reading operation, which together with the aforementioned embodiment constitutes a closed-loop data reading workflow.

[0153] For example, memory cell 300 can be configured to read data stored at a specified address after successfully executing a third data read instruction, forming first data information. Here, the first data information is the raw electrical signal directly sensed and amplified from the memory array. Although the data content is correct, its signal quality may be attenuated due to long-distance transmission and load within the memory cell, and its timing and electrical characteristics are based on a custom protocol (such as HBM) within the chip. Memory cell 300 can be configured to provide the first data information to memory driver circuit 320.

[0154] For example, the storage driver circuit 320 can be configured to receive first data information from the storage cell 300. The storage driver circuit 320 can be configured to perform quality optimization processing on the first data information to improve the signal quality of the raw data output from the storage cell, preparing for subsequent long-path transmission and protocol conversion. For example, the storage driver circuit 320 can be configured to perform operations such as signal amplification, waveform shaping, or pre-emphasis (to pre-compensate for high-frequency losses in subsequent transmission paths), forming second data information after optimization. At this point, the data signal of the second data information has been improved in amplitude and shape, making it more suitable for transmission.

[0155] For example, timing calibrator 350 can be configured to receive second data information from memory driver circuitry 320. For example, timing calibrator 350 can be configured to perform timing optimization on the second data information. For example, timing calibrator 350 can be configured to retime the data signal using its internal timing adjustment circuitry (such as a DLL or variable delay line) so that the data signal and the clock / strobe signal to be sent to an external device meet the setup and hold times required by the target protocol (such as LPDDR), generating timing-calibrated third data information. At this point, the relative timing relationship between the data and its clock signal has been adjusted to meet the transmission requirements of the first interface 330.

[0156] For example, the first interface 330 can be configured to receive third data information from the timing calibrator 350. For example, the first interface 330 can be configured to perform data conversion operations on the third data information based on the memory protocol (such as LPDDR) corresponding to the device 2000. For example, the first interface 330 can be configured to perform parallel-to-serial conversion, level conversion, and other operations, as well as generate correct data strobe signals according to the specifications of the target standard protocol, and output the data and strobe signals synchronously.

[0157] For example, the first interface 330 can be configured to send converted data information conforming to the standard protocol to the device 2000, thereby completing the response to the entire data read request.

[0158] In at least one embodiment of this disclosure, a highly reliable data return channel from the internal storage unit to the external standard interface is constructed through the data return path processing stage. This allows the raw data read from the storage unit to undergo signal quality enhancement, precise timing calibration, and final protocol encapsulation sequentially, ensuring it conforms to external standards and possesses good signal integrity before being accurately received by the external device. This solves the problem of protocol, timing, and signal quality compatibility between customized storage units and standardized external devices in the data output direction under standard storage mode, improving the integrity and high performance of the data read function when the in-memory computing chip is used as a general-purpose memory.

[0159] In some embodiments of this disclosure, the storage controller 340 may be further configured to initiate a data read request to the storage unit in response to receiving a computing operation instruction from the computing core. The storage unit 300 may be further configured to provide second data corresponding to the data read request to the storage driver circuit 320 in response to receiving the data read request. The storage driver circuit 320 may be further configured to perform quality optimization on the second data to form third data. The storage controller 340 may be further configured to provide the third data to the computing core 310.

[0160] like Figure 2 As shown, this embodiment further describes how the storage controller 340 coordinates the data supply process from the storage unit 300 to the computing core 310 in a storage-computing mode.

[0161] For example, in initiating and converting computation requests, the storage controller 340 can be configured to respond to receiving computation operation instructions from the computation core 310. These computation operation instructions may include, for example, the logical address or data block identifier of the data required by the computation task.

[0162] For example, the storage controller 340, acting as a scheduling hub, can translate the computing request into a physical operation that the storage unit 300 can perform.

[0163] For example, the storage controller 340 can be configured to map virtual or logical addresses issued by the computing core 310 to physical addresses within the storage cell 300 (e.g., channel, bank, row, and column addresses). For example, the storage controller 340 can generate a series of efficient DRAM operation commands (e.g., row activation commands, column read commands) according to the timing specifications of the storage cell 300, and optimize their scheduling to hide access latency.

[0164] For example, storage cell 300 can be configured to initiate its internal read timing in response to receiving a data read request from storage controller 340. For example, storage cell 300 can activate the corresponding word line based on the physical address in the data read request, amplify the data in the storage cell circuit, and latch the data via bit lines. For example, storage cell 300 can provide the second data corresponding to this data read request (i.e., the original data signal read from the storage array) to storage driver circuit 320.

[0165] For example, in in-memory computing mode, the storage driver circuit 320 can receive second data from the storage cell 300. For example, the storage driver circuit 320 can optimize the quality of the second data by performing operations such as signal amplification, waveform shaping, or equalization to generate third data with optimized quality, thereby enabling the data read from the storage cell to be transmitted to the storage controller with good signal quality.

[0166] For example, the storage controller 340 can be configured to receive third data from the storage drive circuitry 320. For example, the storage controller 340 can be configured to temporarily buffer the data to handle minor differences between potential burst transfers and the computing core's consumption rate.

[0167] For example, the storage controller 340 can be configured to provide third data to the computing core 310 according to the timing and data format required by the computing core 310, so that it can perform computational operations (such as matrix multiplication and addition, activation functions, etc.).

[0168] In at least one embodiment of this disclosure, a high-bandwidth, low-latency, and highly reliable data channel is provided to the computing core through the internal data reading path in the in-memory computing mode. This data channel enables the computing core to continuously obtain high-quality data streams, allowing it to focus on the computing task itself and maximizing the energy efficiency advantages and performance potential of the in-memory computing architecture.

[0169] For example, in embodiments of this disclosure, such as Figure 1 and Figure 2As shown, the storage unit 300, computing core 310, storage driver circuit 320, storage controller 340, timing calibrator 350, first interface 330, and second interface 200, etc., can be implemented by hardware, software, firmware, and any feasible combination thereof. For example, the storage unit 300, computing core 310, storage driver circuit 320, storage controller 340, timing calibrator 350, first interface 330, and second interface 200, etc., can be dedicated or general-purpose circuits, chips, or devices, or can be a combination of a processor and memory. The embodiments of this disclosure do not limit the specific implementation of the above modules.

[0170] It should be noted that, in the embodiments of this disclosure, Figure 1 and Figure 2 The modules of the in-memory computing chip shown can correspond to the steps of the data access method (described below) provided in this disclosure. The above... Figure 1 and Figure 2 The components and structure of the in-memory computing chip 3000 shown are merely exemplary and not limiting. The in-memory computing chip 3000 may also include other components and structures as needed.

[0171] Figure 3 A flowchart of a data access method provided by at least one embodiment of the present disclosure is shown.

[0172] like Figure 3 As shown, the data access method includes step S410. For example, this data access method can be applied to in-memory computing chips and electronic devices provided in any embodiment of this disclosure.

[0173] Step S410: In response to the in-memory computing mode being enabled, the computing core is made to communicate with the storage unit through the storage driver circuit to access the storage unit; or, in response to the in-memory computing mode being disabled, the first interface is made to communicate with the storage unit through the storage driver circuit to access the storage unit.

[0174] For example, step S410 can be applied to the memory driver circuit 320 provided in the foregoing embodiments of this disclosure.

[0175] In some embodiments of this disclosure, the data access method may further include step S420.

[0176] Step S420: In response to the in-memory computing mode being enabled, control the communication connection between the storage unit and the computing core.

[0177] For example, S420 can be applied to the storage controller 340 provided in the foregoing embodiments of this disclosure.

[0178] In some embodiments of this disclosure, the data access method may further include step S430.

[0179] Step S430: Record the selective enabling or disabling of the in-memory computing mode.

[0180] For example, step S430 can be applied to the mode register provided in the foregoing embodiments of this disclosure.

[0181] In some embodiments of this disclosure, the data access method may further include step S440.

[0182] Step S440: In response to the in-memory computing mode being disabled, timing optimization is performed on the communication signals between the first interface and the memory driver circuit.

[0183] For example, step S440 can be applied to the timing calibrator 350 provided in the foregoing embodiments of this disclosure.

[0184] Figure 4 A flowchart of another data access method provided by at least one embodiment of the present disclosure is shown.

[0185] like Figure 4 As shown, in some embodiments of this disclosure, the data access method may include steps S500 to S520.

[0186] Step S500: Receive data read / write instructions from the device, and perform data conversion on the data read / write instructions to obtain a first data read / write instruction. For example, step S500 can be applied to the first interface 330 provided in the foregoing embodiments of this disclosure.

[0187] Step S510: Optimize the timing of the first data read / write instruction to form a second data read / write instruction. For example, step S510 can be applied to the timing calibrator 350 provided in the foregoing embodiments of this disclosure.

[0188] Step S520: Optimize the quality of the second data read / write instruction to form a third data read / write instruction, and provide the third data read / write instruction to the storage unit. For example, step S520 can be applied to the storage driver circuit 320 provided in the foregoing embodiments of this disclosure.

[0189] In some embodiments of this disclosure, step S500 may further include step S501, step S510 may further include step S511, step S520 may further include step S521, and the data access method may further include step S530.

[0190] Step S501: In response to receiving a data write command from the device, perform a data conversion operation on the data write command to form a first data write command.

[0191] Step S511: Optimize the timing of the first data write instruction to form the second data write instruction.

[0192] Step S521: Optimize the quality of the second data write instruction to form the third data write instruction.

[0193] Step S530: In response to receiving a third data write instruction, a data write operation is performed. For example, step S530 can be applied to the storage unit 300 provided in the foregoing embodiments of this disclosure.

[0194] In some embodiments of this disclosure, step S501 may further include step S5011.

[0195] Step S5011: Perform signal conversion, voltage conversion, and instruction parsing on the data write instruction to form the first data write instruction.

[0196] In some embodiments of this disclosure, step S511 may further include step S5111.

[0197] Step S5111: Perform signal equalization processing, clock recovery processing, and data retiming processing on the first data write instruction to form the second data write instruction.

[0198] In some embodiments of this disclosure, step S521 may further include step S5211.

[0199] Step S5211: The second data write instruction is shaped, noise-reduced, and rate-adapted, and the optimized signal is converted based on the storage protocol to form the third data write instruction.

[0200] In some embodiments of this disclosure, step S500 may further include step S502, step S510 may further include step S512, step S520 may further include step S522, and step S530 may further include step S531.

[0201] Step S502: In response to receiving a data read instruction from the device, perform a data conversion operation on the data read instruction to form a first data read instruction.

[0202] Step S512: Optimize the timing of the first data read instruction to form the second data read instruction.

[0203] Step S522: Optimize the quality of the second data read instruction to form the third data read instruction.

[0204] Step S531: In response to receiving a third data read instruction, perform a data read operation and provide the first data information corresponding to the third data read instruction to the device.

[0205] In some embodiments of this disclosure, step S500 may further include step S503, step S510 may further include step S513, step S520 may further include step S523, and step S530 may further include step S532.

[0206] Step S532: Upon receiving the third data read instruction, the first data information is provided to the storage driver circuit.

[0207] Step S523: Perform quality optimization processing on the first data information to form the second data information.

[0208] Step S513: Perform timing optimization on the second data information to form the third data information.

[0209] Step S503: Based on the memory protocol corresponding to the device, perform data conversion operation on the third data information and provide the converted data information to the device.

[0210] In some embodiments of this disclosure, the data access method may include steps S540-S570. For example, steps S540-S570 may be applied when in-memory computing mode is enabled.

[0211] Step S540: In response to receiving a computing operation instruction from the computing core, a data read request is initiated to the storage unit. For example, step S540 can be applied to the storage controller 340 provided in the foregoing embodiments of this disclosure.

[0212] Step S550: In response to receiving a data read request, the second data corresponding to the data read request is provided to the storage driver circuit. For example, step S550 can be applied to the storage unit 300 provided in the foregoing embodiments of this disclosure.

[0213] Step S560: Optimize the quality of the second data to form the third data. For example, step S560 can be applied to the memory driver circuit 320 provided in the foregoing embodiments of this disclosure.

[0214] Step S570: Provide the third data to the computing core. For example, step S570 can be applied to the storage controller 340 provided in the foregoing embodiments of this disclosure.

[0215] It should be noted that the specific functions and beneficial effects of each step in the data access method provided in any embodiment of this disclosure can be referred to the relevant descriptions of the in-memory computing chip embodiments above, and will not be repeated here.

[0216] Figure 5 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0217] For example, such as Figure 5 As shown, the electronic device 700 includes at least one processor 701 and at least one memory 702. The at least one memory 702 includes one or more computer program modules. These computer program modules are stored in the memory 702 and configured to be executed by the at least one processor 701. The one or more computer program modules include instructions for performing the data access method described above. When executed by the at least one processor 701, they can perform one or more steps of the data access method provided in at least one embodiment of this disclosure. The memory 702 and the processor 701 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0218] For example, processor 701 can be a central processing unit (CPU), digital signal processor (DSP), graphics processing unit (GPU), general-purpose graphics processing unit (GPGPU), artificial intelligence (AI) accelerator, or other processing unit with data processing and / or program execution capabilities, such as a field-programmable gate array (FPGA). For example, the CPU can employ instruction set architectures such as x86, ARM, or RISC-V. Processor 701 can be a general-purpose processor or a special-purpose processor, capable of controlling other components in electronic device 700 to perform desired functions.

[0219] For example, memory 702 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc.

[0220] Figure 6 This is a schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0221] The electronic devices in at least one embodiment of this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (PADs), portable multimedia players (PMPs), in-vehicle terminals (e.g., in-vehicle navigation terminals), wearable electronic devices, and fixed terminals such as digital TVs and desktop computers. Figure 6 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0222] The electronic device includes at least one processor and a memory. The processor may be referred to as processing device 801 as described below, and the memory may include at least one of ROM 802, RAM 803, and storage device 808 as described below. The memory is used to store programs for performing the methods described in the various method embodiments above; the processor is configured to execute the programs stored in the memory. The processor may include a central processing unit (CPU) or other forms of processing unit having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0223] like Figure 6 As shown, the electronic device 800 may include a processing unit 801 (e.g., a central processing unit (CPU), digital signal processor (DSP), image processor (GPU), general-purpose graphics processor (GPGPU), artificial intelligence (AI) accelerator, or other forms of processing unit with data processing and / or program execution capabilities), which can perform various appropriate actions and processes according to a program stored in ROM 802 or a program loaded from storage device 808 into RAM 803. RAM 803 also stores various programs and data required for the operation of the electronic device 800. The processing unit 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interfaces are also connected to bus 804.

[0224] Typically, the following devices can be connected to I / O interface 805: input devices 806 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 807 including, for example, displays, speakers, vibrators, etc.; storage devices 808 including, for example, magnetic tapes, hard disks, etc.; and communication devices 809. Communication device 809 allows electronic device 800 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 6An electronic device 800 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0225] In particular, according to at least one embodiment of this disclosure, the process described above with reference to the flowchart can be implemented as a computer software program.

[0226] For example, at least one embodiment of this disclosure includes a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program including program code for performing the methods shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device 809, or installed from a storage device 808, or installed from a ROM 802. When the computer program is executed by a processing device 801, it performs the functions defined in the methods of at least one embodiment of this disclosure.

[0227] It should be noted that the computer-readable medium described above in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0228] In at least one embodiment of this disclosure, a computer-readable storage medium can be any tangible medium that includes or stores a program that can be used or combined with an instruction execution system, apparatus, or device. In at least one embodiment of this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or combined with an instruction execution system, apparatus, or device. The program code included on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, radio frequency (RF), etc., or any suitable combination thereof.

[0229] The aforementioned computer-readable medium may be included in the aforementioned electronic device 800; or it may exist independently and not assembled into the electronic device 800.

[0230] Figure 7 This is a schematic block diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure.

[0231] For example, such as Figure 7 As shown, a non-transitory computer-readable storage medium 900 stores computer-readable instructions 901, which, when executed by at least one processor, perform one or more steps of the data access method described above.

[0232] For example, the storage medium may include a memory card for a smartphone, a storage component for a tablet computer, a hard drive for a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), flash memory, or any combination of the above storage media, or other suitable storage media. For example, the readable storage medium may also be... Figure 5 The memory 702 in the memory is described in the foregoing content and will not be repeated here.

[0233] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the inventive concept of the present disclosure are within the scope of protection claimed by the present disclosure.

[0234] The following points should be noted regarding this disclosure:

[0235] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0236] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0237] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0238] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A memory computing chip, characterized in that, The in-memory computing chip includes: Storage units are configured to store data; The computing core is configured to perform computational operations related to the data in the storage unit in a storage-computing mode. The first interface is configured to communicate with devices outside the in-memory computing chip; and A storage driver circuit is configured to drive the storage unit and, in response to the in-memory computing mode being enabled, enable the computing core to communicate with the storage unit to access the storage unit, or, in response to the in-memory computing mode being disabled, enable the first interface to communicate with the storage unit to access the storage unit. The in-memory computing chip further includes a mode register configured to record the selective enabling or disabling of the in-memory computing mode. The mode register includes at least one mode selection bit. When the mode selection bit is set to a first value, it indicates that the in-memory computing mode is enabled. When the mode selection bit is set to a second value, it indicates that the in-memory computing mode is disabled.

2. The in-memory computing chip according to claim 1, characterized in that, The in-memory computing chip also includes: The storage controller is configured to control the communication connection between the storage unit and the computing core in response to the activation of the in-memory computing mode.

3. The in-memory computing chip according to any one of claims 1-2, characterized in that, The in-memory computing chip also includes: A timing calibrator is configured to perform timing optimization on the communication signals between the first interface and the memory driver circuit in response to the in-memory computing mode being disabled.

4. The in-memory computing chip according to claim 3, characterized in that, The first interface is further configured to receive data read / write instructions issued by the device, and to perform data conversion on the data read / write instructions to obtain a first data read / write instruction; The timing calibrator is further configured to perform timing optimization on the first data read / write instruction to form a second data read / write instruction; and The storage driver circuit is further configured to perform quality optimization on the second data read / write instruction to form a third data read / write instruction, and to provide the third data read / write instruction to the storage unit.

5. The in-memory computing chip according to claim 4, characterized in that, The first interface is further configured to, in response to receiving a data write instruction from the device, perform a data conversion operation on the data write instruction to form a first data write instruction; The timing calibrator is further configured to perform timing optimization on the first data write instruction to form a second data write instruction; The storage driver circuit is further configured to perform quality optimization on the second data write instruction to form a third data write instruction; as well as The storage unit is configured to perform a data write operation in response to receiving the third data write instruction.

6. The in-memory computing chip according to claim 5, characterized in that, The data conversion operation for the data writing instruction includes: The data write instruction is processed by signal conversion, voltage conversion, and instruction parsing to form a first data write instruction.

7. The in-memory computing chip according to claim 5, characterized in that, The timing optimization of the first data write instruction includes: The first data write instruction is processed by signal equalization, clock recovery, and data retiming to form the second data write instruction.

8. The in-memory computing chip according to claim 5, characterized in that, The quality optimization of the second data write instruction includes: The second data write instruction is shaped, noise-reduced, and rate-adapted. The optimized signal is then converted based on the storage protocol to form the third data write instruction.

9. The in-memory computing chip according to claim 4, characterized in that, The first interface is further configured to, in response to receiving a data read instruction from the device, perform a data conversion operation on the data read instruction to form a first data read instruction; The timing calibrator is further configured to perform timing optimization on the first data read instruction to form a second data read instruction; The storage drive circuit is further configured to optimize the quality of the second data read instruction to form a third data read instruction; as well as The storage unit is further configured to perform a data reading operation in response to receiving the third data reading instruction, and to provide the first data information corresponding to the third data reading instruction to the device.

10. The in-memory computing chip according to claim 9, characterized in that, The storage unit is further configured to, upon receiving the third data read instruction, provide the first data information to the storage drive circuit; The storage drive circuit is further configured to perform quality optimization processing on the first data information to form the second data information; The timing calibrator is further configured to perform timing optimization on the second data information to form the third data information; as well as The first interface is further configured to perform a data conversion operation on the third data information based on the memory protocol corresponding to the device, and provide the converted data information to the device.

11. The in-memory computing chip according to claim 2, characterized in that, The storage controller is further configured to initiate a data read request to the storage unit in response to receiving a computing operation instruction from the computing core; The storage unit is further configured to provide the second data corresponding to the data read request to the storage driver circuit in response to receiving the data read request; The storage driver circuit is further configured to optimize the quality of the second data to form third data; and The storage controller is further configured to provide the third data to the computing core.

12. A data access method, characterized in that, Applied to in-memory computing chips, The in-memory computing chip includes: Storage units are configured to store data; The computing core is configured to perform computational operations related to the data in the storage unit in a storage-computing mode. The first interface is configured to communicate with devices outside the in-memory computing chip; and A storage driver circuit is configured to drive the storage cell; The data access method includes: In response to the activation of the in-memory computing mode, the computing core is communicatively connected to the storage unit via the storage driver circuit to access the storage unit; or... In response to the in-memory computing mode being disabled, the first interface is made to communicate with the storage unit through the storage driver circuit to access the storage unit; The in-memory computing chip further includes a mode register configured to record selective enabling or disabling of the in-memory computing mode; wherein the mode register includes at least one mode selection bit, wherein setting the mode selection bit to a first value indicates enabling the in-memory computing mode, and setting the mode selection bit to a second value indicates disabling the in-memory computing mode.

13. An electronic device, characterized in that, The electronic device includes a memory computing chip as described in any one of claims 1-11.

14. An electronic device, characterized in that, The electronic device includes: At least one processor; and At least one memory, wherein the at least one memory stores at least one computer program that, when executed by the at least one processor, implements the data access method of claim 12.

15. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium is used to non-transitory store computer-readable instructions that, when executed by a computer, implement the data access method of claim 12.

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