A functional eco automatic partition correction method

Abstract

The application provides an ECO improvement method for a large-scale netlist, receives an original netlist and a target netlist as inputs, dynamically divides an error output port set into several subsets with controllable sizes based on a calculation complexity evaluation, adopts an Auto Partition correction strategy, selects one subset each time for prior processing, generates a corresponding function patch and merges the function patch into the original netlist, re-evaluates the remaining error set based on an updated netlist state, and repeats the above process until all errors are completely eliminated; the method decomposes a global correction task into multiple sub-problems which can be efficiently solved, significantly improves the processing capacity of an ECO algorithm for a large-scale netlist, and realizes comprehensive performance optimization in terms of patch quality and operation efficiency, so that a large-scale design which cannot be successfully corrected in the past can be implemented by ECO.

Description

Technical Field

[0001] This invention belongs to the field of ECO technology, specifically relating to a functional ECO automatic partition correction method. Background Technology

[0002] When modifying RTL code after the layout has been generated, without a dedicated tool (such as the ECO tool), the entire process must be re-executed from scratch. However, using the ECO (Engineering Change Order) tool is equivalent to applying a patch directly to the existing layout (i.e., the executable file), eliminating the need to redo the entire process and thus saving significant time and resources.

[0003] One of the core metrics of ECO technology in the current EDA field is patch size; smaller patches generally indicate more efficient algorithms. Traditional ECO algorithms suffer from the following technical problems when processing large-scale netlists: patch size is too large to meet practical application requirements; runtime is too long to complete corrections within a reasonable timeframe; the algorithm is prone to failure when the number of error output ports (POs) is large, making it impossible to guarantee the generation of effective patches; and for large-scale netlists, the computational complexity and memory consumption of traditional algorithms increase exponentially, severely impacting processing efficiency. Summary of the Invention

[0004] This invention provides a functional ECO automatic partition correction method, which aims to solve the problems of low processing efficiency and high resource consumption caused by the large netlist size of traditional ECO algorithms.

[0005] The solution of the present invention is as follows:

[0006] An automatic partition correction method for functional ECO is provided to reduce the patch size of large-scale netlist ECOs and achieve fast ECOs for large-scale netlists. The method includes the following steps:

[0007] Step S1: Receive the original netlist and target netlist input by the user, compare the original netlist and target netlist through logical equivalence check, and identify the set of erroneous POs of the output ports in the original netlist.

[0008] Step S2: Attempt to perform a one-time ECO correction on the set of erroneous POs. If the correction is successful, the process ends; if the correction fails, proceed to step S3.

[0009] Step S3: Select a subset of error POs of manageable size from the set of error POs according to the preset computing resource constraints.

[0010] Step S4: Generate functional patches for the selected subset of error POs.

[0011] Step S5: Merge the functional patch into the current original netlist to generate an updated netlist.

[0012] Step S6: Perform a logical equivalence check again based on the updated netlist to obtain the remaining set of error POs; determine whether the termination condition is met. If it is met, the process ends; otherwise, proceed to step S7.

[0013] Step S7: Using the updated netlist as the new original netlist and the remaining set of error POs as the new set of error POs, repeat steps S3 to S6.

[0014] Furthermore, within the set of erroneous POs, the logical relationships between erroneous POs are analyzed, the computational resources required to correct each subset of erroneous POs are calculated, and subsets of erroneous POs that simultaneously meet the screening criteria are selected to obtain the erroneous PO subset with controllable size.

[0015] The filtering conditions include: the number of erroneous POs in the subset does not exceed a preset threshold; the erroneous POs in the subset meet a logical correlation threshold; and the computing resources required to correct the subset do not exceed the currently available computing resources.

[0016] Furthermore, the logic equivalence check in step S1 adopts a combinational equivalence check. The combinational equivalence check is carried out by constructing a mixer Miter circuit, performing an XOR operation on the corresponding outputs of the original netlist and the target netlist, and using the SAT solver to determine whether the XOR result is always 0.

[0017] Furthermore, the specific steps for generating a feature patch are as follows:

[0018] Step S4.1: Construct a local netlist model based on the selected subset of erroneous POs. The MFFC (maximum fanout free cone) of the erroneous PO subset is defined as follows: The MFFC of a node n or a gate g refers to a subset of the fanout cone of that gate g. This subset contains nodes that satisfy the condition that every path from these nodes to the final output PO must pass through that gate g or that node n. Only a subset of such a fanout cone can be called an MFFC. That is, if a node is removed and some of its leading nodes cannot reach the PO, then the set of these leading nodes is the MFFC.

[0019] Step S4.2: Use a matching algorithm to analyze the logical differences between the erroneous PO subset and the corresponding part of the target netlist. The matching algorithm uses binary decision graph (BDD) or non-graph (AIG) for function representation and comparison.

[0020] Step S4.3: Generate a minimal functional patch that can eliminate the logic differences through logic synthesis. The functional patch includes input ports, output ports, and internal logic gates.

[0021] Furthermore, the functional patch must correct the logical function of at least one faulty PO within the subset; and must not change the logical behavior of other correct POs in the original netlist; the input port of the patch is connected to the internal signal node of the original netlist, and the output port replaces the corresponding faulty PO.

[0022] The number of logic gates in the functional patch is generally no more than 1.5 times the number of logic gates corresponding to the original erroneous PO subset, in order to control area overhead. If area overhead is not considered and only logical correctness is required, then there is no upper limit to the number of logic gates. Finally, the task with the best result among multiple tasks will be selected as the final result.

[0023] Furthermore, the function patch merging operation in step S5 includes: establishing a connection between the input port of the function patch and the corresponding signal node in the original netlist; replacing the corresponding error PO in the original netlist with the output port of the function patch; and updating the topology and signal propagation relationship of the netlist to ensure the integrity and consistency of the netlist.

[0024] Furthermore, based on the updated netlist, a logical equivalence check is performed again to obtain the set of remaining error POs. When the set of remaining error POs is empty, or the remaining error POs cannot form a subset that satisfies the computing resource constraints, or the number of AutoPartitions reaches the preset maximum number of AutoPartitions, it is determined that the termination condition is met and the process ends.

[0025] Furthermore, the preset maximum number of Auto Partitions is 1-12.

[0026] Furthermore, the computing resource constraints include: memory usage constraints, computation time constraints, logic gate count constraints, and netlist size constraints;

[0027] The memory usage of a single ECO operation shall not exceed 60% of the total system memory; the computation time of a single ECO operation shall not exceed a preset time limit, which is 30 minutes to 2 hours; the number of logic gates contained in a single functional patch shall not exceed 1,000 to 5,000; and the size of the local netlist corresponding to the subset of erroneous POs processed in a single operation shall not exceed 20% of the size of the original netlist.

[0028] Compared with the prior art, the beneficial effects of this invention are:

[0029] This invention divides a large-scale netlist into multiple sub-problems of controllable size, enabling successful correction of previously unmanageable large-scale designs. Through the Auto Partition processing method, the global correction task is decomposed into multiple efficient and solvable sub-stages, significantly reducing the computational complexity and memory consumption of a single solution. Compared with traditional methods, it can generate smaller-scale and higher-quality functional patches, improve the ECO correction effect, and enable the ECO algorithm to adapt to larger-scale modern chip designs, exhibiting good scalability. Attached Figure Description

[0030] Figure 1 This is a flowchart of a functional ECO automatic partition correction method according to the present invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0032] Example

[0033] like Figure 1 The diagram shown is a flowchart of a functional ECO automatic partition correction method according to the present invention. The method includes the following steps:

[0034] Step S1: Receive the original netlist and target netlist input by the user, compare the original netlist and target netlist through logical equivalence check, and identify the set of output port errors (POs) in the original netlist.

[0035] The original netlist is the Old Netlist, which represents the chip version for which the physical design has been completed; the target netlist is the New Netlist, which represents the ideal chip version that is expected to be achieved.

[0036] In this embodiment, the logic equivalence check employs a combinational equivalence check. This check involves constructing a mixer Miter circuit, performing an XOR operation on the corresponding outputs of the original and target netlists, and using the SAT solver to determine if the XOR result is consistently zero. Specifically, for each output port... Construct an XOR gate When the XOR result is 1, it indicates that there is a logical difference at the output port.

[0037] Step S2: Attempt to perform a one-time ECO correction on the set of erroneous POs. If the correction is successful, the process ends; if the correction fails, proceed to step S3.

[0038] First, we try the traditional global correction method to obtain a relatively good correction result (global correction is not necessarily optimal). Global correction can take into account the logical relationship between all erroneous POs and can theoretically generate the smallest functional patch. However, when there are many erroneous POs or complex logical relationships are involved, global correction often fails due to excessive computational complexity.

[0039] In this embodiment, the failure criteria for global ECO correction include: the estimated memory requirement exceeds 60% of the available system memory; the estimated calculation time exceeds the preset time limit (30 minutes to 2 hours); the SAT solver fails to converge within the preset time; when any of the failure criteria is met, the algorithm automatically switches to Auto Partition correction mode.

[0040] Step S3: Select a subset of error POs of manageable size from the set of error POs according to the preset computing resource constraints.

[0041] It should be noted that traditional ECO methods often fail directly when faced with large-scale error sets, while this invention decomposes complex problems into multiple solvable subproblems through an intelligent partitioning strategy.

[0042] In the set of erroneous POs, the logical relationships between erroneous POs are analyzed, the computational resources required to correct each subset of erroneous POs are calculated, and the subset of erroneous POs that simultaneously meets the screening criteria are selected to obtain the erroneous PO subset with controllable size.

[0043] The filtering conditions include: the number of erroneous POs in the subset does not exceed a preset threshold, which is 8-20; the erroneous POs in the subset meet a logical correlation threshold, which is 0.3-0.8; and the computing resources required to correct the subset do not exceed the currently available computing resources.

[0044] Based on logical correlation analysis, the algorithm adopts a greedy strategy to select a subset of erroneous POs. Specifically, it first selects the erroneous PO with the highest correlation as the seed node, and then gradually adds other erroneous POs that have high correlation with the selected node and meet resource constraints, until a subset that meets the screening conditions is formed.

[0045] The logical correlation between the erroneous POs is determined based on the topological distance between the erroneous POs in the netlist. The specific calculation method is as follows: for any two erroneous POs... and Calculate the shortest path distance between them in the directed graph of the netlist. Define logical relationships: ,in, This is the distance attenuation coefficient, with a value ranging from 0.1 to 0.5; smaller values ​​are acceptable. A value that mitigates the impact of distance on associativity is suitable for designs with a more dispersed logical structure; a larger value... Values ​​place greater emphasis on local correlations and are suitable for highly modular designs.

[0046] when When it exceeds the logical correlation threshold, it is considered that and They are logically related.

[0047] Step S4: Generate functional patches for the selected subset of error POs.

[0048] The specific steps for generating a feature patch are as follows:

[0049] Step S4.1: Construct a local netlist model based on the selected subset of erroneous POs. The local netlist model includes the fan-in cone of the erroneous PO subset and the MFFC of the erroneous PO subset.

[0050] Step S4.2: Use a matching algorithm to analyze the logical differences between the erroneous PO subset and the corresponding part of the target netlist. The matching algorithm uses binary decision graph (BDD) or non-graph (AIG) for function representation and comparison.

[0051] In this embodiment, the matching algorithm preferentially uses binary decision graph (BDD) for function representation because it has normalization characteristics and can quickly determine the equivalence of functions. The algorithm first constructs the BDD representation of the erroneous PO, and then compares it with the BDD output of the target netlist. The logical difference function is directly obtained through BDD operations (XOR, simplification). For complex functions, the AND-NOT graph (AIG) is used as an auxiliary representation, and its structured characteristics are used to locate the difference.

[0052] Step S4.3: Generate a minimal functional patch that can eliminate the logic differences through logic synthesis. The functional patch includes input ports, output ports, and internal logic gates.

[0053] The number of input ports is determined by the number of supporting variables of the difference function, and the number of output ports is equal to the number of error POs in the subset.

[0054] It is important to note that feature patches are allowed to make partial corrections, at least one faulty Product Object (PO) needs to be corrected; patches cannot change the logical behavior of other correct POs in the original netlist, and formal verification is used to ensure there are no side effects.

[0055] Step S5: Merge the functional patch into the current original netlist to generate an updated netlist.

[0056] Feature patch merging operations include:

[0057] First, establish connections between the patch input port and the signal nodes within the original netlist. The selection of connection points is based on the analysis results from the patch generation phase, ensuring the logical semantics of the signals are correct. During the connection process, the signal's driving capability needs to be considered, and buffers should be inserted if necessary to meet load requirements.

[0058] Secondly, replace the corresponding faulty PO in the original netlist with the output port of the patch; the replacement process requires updating all related signal references, including internal wiring and external interface definitions; to avoid naming conflicts, the signal nodes in the patch adopt a unified naming convention, usually adding the "patch" prefix to distinguish them.

[0059] Finally, update the netlist topology and signal propagation relationships. Topology updates include adding nodes, reconstructing connections, and adjusting hierarchical relationships.

[0060] Step S6: Perform a logical equivalence check again based on the updated netlist to obtain the remaining set of error POs; determine whether the termination condition is met. If it is met, the process ends; otherwise, proceed to step S7.

[0061] Based on the updated netlist, a logical equivalence check is performed again to obtain the set of remaining error POs. When the set of remaining error POs is empty, or the remaining error POs cannot form a subset that satisfies the computing resource constraints, or the number of Auto Partitions reaches the preset maximum number of Auto Partitions, it is determined that the termination condition is met and the process ends.

[0062] When the set of remaining error POs is empty, it indicates that all errors have been successfully corrected and the algorithm has reached the optimal termination state. When the remaining error POs cannot form a subset that satisfies the computational resource constraints, it indicates that the remaining errors are too complex or scattered and cannot be processed under the current algorithm parameters. At this time, the algorithm terminates and reports the partial correction results. When the number of Auto Partitions reaches the preset maximum number of Auto Partitions (1-12 times), the algorithm is forcibly terminated to avoid infinite loops.

[0063] The logical equivalence check of the updated netlist uses the same method as in step S1, but focuses on the remaining uncorrected errors. During the check, corrected POs should be completely consistent with the target netlist, while the number and distribution of remaining erroneous POs provide guidance for the next round of Auto Partition.

[0064] The computing resource constraints include: memory usage constraints, computation time constraints, logic gate number constraints, and netlist size constraints; the memory usage of a single ECO operation shall not exceed 60% of the total system memory; the computation time of a single ECO operation shall not exceed a preset time limit, which is 30 minutes to 2 hours; the number of logic gates contained in a single functional patch shall not exceed 1,000 to 5,000; and the size of the local netlist corresponding to a subset of erroneous POs processed in a single operation shall not exceed 20% of the original netlist size.

[0065] Step S7: Using the updated netlist as the new original netlist and the remaining set of error POs as the new set of error POs, repeat steps S3 to S6.

[0066] Before each Auto Partition begins, the algorithm updates global state information, including the current netlist snapshot, remaining error statistics, resource consumption records, and convergence trend analysis.

[0067] To improve the efficiency of Auto Partition, the algorithm adopts an adaptive parameter adjustment strategy: when the error reduction of two consecutive Auto Partitions is less than the threshold, the logical correlation requirement is appropriately relaxed to expand the range of candidate subsets; when a certain type of error occurs repeatedly, its priority is increased to ensure that it is processed first in subsequent Auto Partitions; when resource consumption continues to rise, the subset size limit is tightened to maintain the stability of the algorithm.

[0068] Meanwhile, the algorithm maintains a detailed Auto Partition log, recording the input state, processing procedure, output results, and performance metrics for each Auto Partition.

[0069] To better illustrate the practical application effect of the method of the present invention, a detailed explanation is given below through a specific design case of a digital signal processing unit (DSP unit).

[0070] A company's digital signal processing unit needs a functional upgrade. The original version (version A) implemented basic digital filtering functions, including low-pass, high-pass, and band-pass filters. The target version (version B), while retaining the original filtering functions, adds an adaptive dynamic noise reduction algorithm and optimizes the original filter coefficient calculation logic to improve processing accuracy and reduce power consumption.

[0071] This DSP unit contains approximately 1.5 million logic gates and has 64 main output ports, belonging to the category of large-scale integrated circuit design. After the RTL code modification was completed, the logic equivalence checking tool detected functional inconsistencies in 35 output ports. These errors were distributed in the filter coefficient calculation module, data path control module, and output formatting module.

[0072] The following problems were encountered when using the traditional ECO method to fix these 35 bugs in one go: the computational complexity was too high, with an estimated requirement of 40GB of memory and more than 6 hours of computation time; available resources were limited, with the server configured with 32GB of memory and a single task time limit of 2 hours; and the fix failed, as the traditional ECO tool could not generate a valid feature patch before resources were exhausted.

[0073] In this situation, the design team faces two choices: either upgrade computing resources (which is costly and success is not guaranteed) or redesign from scratch (which is extremely time-consuming).

[0074] The system configuration using the Auto Partition ECO method of this invention is as follows: maximum size of the erroneous PO subset: 20; logical correlation threshold: 0.5; distance decay coefficient. 0.3; Single Auto Partition memory limit: 19GB (60% of total system memory); Single Auto Partition time limit: 1 hour; Maximum number of Auto Partitions: 10.

[0075] In the first round of Auto Partition, the system corrected the filter coefficient module. It initially attempted to perform a one-time ECO correction on all 35 erroneous product objects (POs). Based on resource estimation, the system determined that this operation required approximately 40GB of memory, exceeding the system limit. The correction failed, and the process switched to Auto Partition mode.

[0076] The algorithm performs logical correlation analysis on 35 erroneous product objects (POs). Netlist topology analysis reveals that 17 of these errors are concentrated in the filter coefficient calculation module, exhibiting high logical correlation (average correlation degree 0.65). Based on a greedy selection strategy, the algorithm selects these 17 errors as the first processing subset (Subset_1). Resource assessment shows that processing Subset_1 is expected to require 15GB of memory and 45 minutes of computation time, both within the constraints.

[0077] For Subset_1, the algorithm constructs a local netlist model containing the logic for calculating the filter coefficients, which contains approximately 120,000 logic gates. Analysis using the BDD function matching algorithm reveals that the main logical differences are concentrated in the expansion of coefficient precision (from 16 bits to 24 bits) and the change in rounding method (from truncation to rounding).

[0078] The logic synthesis-generated functional patch patch_1.v contains: 23 input ports (coefficient inputs and control signals connected to the original netlist); 17 output ports (corresponding to error POs in Subset_1); and 1247 internal logic gates (equivalent to 1.35 times the original logic).

[0079] patch_1.v was successfully merged into the original netlist, generating the intermediate netlist ecoed_netlist_v1. Formal verification confirmed that all 17 errors in Subset_1 were corrected, and the logic functionality of other Product Objects remained unaffected. Area increased by approximately 1800 equivalent gates.

[0080] The logical equivalence check was re-executed, and the number of remaining erroneous POs was reduced to 18. The first round of Auto Partition was successfully completed.

[0081] The second round of Auto Partition corrected the data path control module. Based on the remaining 18 errors, the algorithm executed the partitioning strategy again. Analysis revealed that 12 of the errors were located in the data path control module and had a moderate degree of logical correlation (average correlation score of 0.42). These 12 errors were selected as the second processing subset (Subset_2).

[0082] The generated feature patch_2.v primarily corrects the multiplexing logic and pipeline control signals in the data path. Patch size: 956 logic gates, successfully correcting all 12 errors.

[0083] The number of remaining errors in the merged netlist ecoed_netlist_v2 has been reduced to 6.

[0084] The third round of Auto Partition corrects the output formatting module. The remaining 6 errors are distributed in the output formatting module and have low correlation with each other (average correlation of 0.28). However, due to their small number, the algorithm decides to process them all at once.

[0085] The generated feature patch_3.v mainly involves output data bit width adjustment and format conversion logic. Patch size: 342 logic gates, successfully correcting all 6 errors.

[0086] The final netlist ecoed_netlist_v3 is completely identical to the target netlist, with 0 erroneous product objects (POs).

[0087] Through three rounds of Auto Partition, the method of this invention successfully completed the ECO correction of the DSP unit. Traditional methods failed to correct the error and could not generate results. The three rounds of Auto Partition of the method of this invention had a total computation time of 2.3 hours and a peak memory usage of 17GB.

[0088] Total patch size: 3545 logic gates; Area overhead: approximately 2.4% (relative to the original design); Timing impact: Critical path latency increased by 3%, within acceptable limits; Power consumption increase: approximately 1.8%.

[0089] This application example fully demonstrates that through logical correlation analysis, the algorithm can automatically identify errors with strong correlations in the filtering coefficient module and prioritize the processing of these errors to achieve the greatest correction benefit. The three rounds of AutoPartition show a clear convergence trend, with each round significantly reducing the number of remaining errors, verifying the algorithm's convergence. By decomposing a large-scale problem into multiple sub-problems, the previously unmanageable correction task can be completed with limited resources. The generated patch size is reasonable, and the area overhead and timing impact are within acceptable engineering limits, demonstrating the algorithm's effective control over patch quality.

[0090] This application example demonstrates that the Auto Partition ECO method of this invention can effectively solve the resource bottleneck and convergence problems faced by traditional ECO technology in large-scale netlist correction, providing a practical ECO solution for modern large-scale integrated circuit design.

[0091] This invention has been described through specific embodiments. Those skilled in the art will understand that various modifications and equivalent substitutions can be made to this invention without departing from its scope. Furthermore, various modifications can be made to this invention for specific situations or materials without departing from its scope. Therefore, this invention is not limited to the specific embodiments disclosed, but should include all embodiments falling within the scope of the claims.

Claims

1. A functional ECO auto-partitioning correction method for implementing fast ECO of large scale netlist, characterized in that, The method comprises the following steps: Step S1, receiving a user inputted original netlist and target netlist, comparing the original netlist and the target netlist through logical equivalence checking, and identifying a set of output port errors PO in the original netlist; Step S2, attempting to make one-time ECO correction to the set of error POs, and if the correction is successful, ending the process, and if the correction fails, entering step S3; Step S3, selecting a subset of error POs with controllable size from the set of error POs according to preset computing resource constraints; Step S4, generating a function patch for the selected subset of error POs; Step S5, merging the function patch into the current original netlist to generate an updated netlist; Step S6, re-performing logical equivalence checking based on the updated netlist to obtain a set of remaining error POs; determining whether a termination condition is met, and if so, ending the process, and if not, entering step S7; Step S7, taking the updated netlist as a new original netlist, taking the set of remaining error POs as a new set of error POs, and repeating steps S3 to S6.

2. The functional ECO automatic partitioning correction method of claim 1, wherein, In the set of error POs, the logical correlation between error POs is analyzed, the computing resources required for correcting each subset of error POs are calculated, the subset of error POs that meets the filtering condition is selected, and the subset of error POs with controllable size is obtained; The filtering condition includes that the number of error POs in the subset does not exceed a preset number threshold, the error POs in the subset meet a logical correlation threshold, and the computing resources required for correcting the subset do not exceed the current available computing resources.

3. The functional ECO automatic partitioning correction method of claim 2, wherein, The logical equivalence checking in step S1 uses combination equivalence checking, which constructs a mixer Miter circuit, performs an exclusive OR operation on the corresponding outputs of the original netlist and the target netlist, and uses a SAT solver to determine whether the exclusive OR result is always 0.

4. The functional ECO automatic partitioning correction method of claim 3, wherein, The specific steps for generating a function patch are as follows: Step S4.1, constructing a local netlist model based on the selected subset of error POs, the local netlist model including fan-in cones and shared logic of the subset of error POs; Step S4.2, using a matching algorithm to analyze the logical differences between the subset of error POs and the corresponding part of the target netlist, the matching algorithm using binary decision diagram BDD or and-inverter graph AIG for function representation and comparison; Step S4.3, generating a minimum function patch that can eliminate the logical differences through logic synthesis, the function patch including input ports, output ports, and internal logic gates.

5. The functional ECO automatic partitioning correction method of claim 4, wherein, The function patch needs to correct at least the logical function of one error PO itself; and does not change the logical behavior of other correct POs in the original netlist; the input ports of the patch are connected to the internal signal nodes of the original netlist, and the output ports replace the corresponding error POs.

6. The functional ECO automatic partitioning correction method of claim 5, wherein, The function patch merging operation in step S5 includes: establishing a connection between the input ports of the function patch and the corresponding signal nodes in the original netlist; replacing the corresponding error POs in the original netlist with the output ports of the function patch; updating the topology and signal propagation relationship of the netlist to ensure the integrity and consistency of the netlist.

7. The functional ECO automatic partitioning correction method of claim 6, wherein, Re-perform the logic equivalence check based on the updated netlist to obtain a remaining error PO set, and determine that a termination condition is met and end the process when the remaining error PO set is empty, or the remaining error POs cannot form a subset that meets the computing resource constraints, or the number of Auto Partitions reaches a preset maximum number of Auto Partitions.

8. The functional ECO auto-partition revision method of claim 7, wherein, The computing resource constraint conditions include a memory usage constraint, a computing time constraint, a logic gate number constraint, and a netlist size constraint.

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