A delay device and delay control method suitable for a multi-memory test system

Abstract

This invention discloses a delay device and delay control method suitable for multi-memory testing systems, relating to the field of memory testing technology. It includes a first delay register and a second delay register. The first delay register is connected to a data driver on an electronic pin in the multi-memory testing system and is used to adjust the output timing of several data signals in a test vector according to a first delay logic, to compensate for path difference delays between the command / address bus and data bus of several memories under test. The second delay register is connected to a data receiver on an electronic pin in the multi-memory testing system and is used to adjust the timing of the data receiver receiving several expected data signals according to a second delay logic, to compensate for the internal delays of several memories under test. This invention can achieve delay compensation for all signals in the test vector, ensuring effective testing of multiple memories and improving test accuracy.

Description

Technical Field

[0001] This invention relates to the field of memory testing technology, and in particular to a delay device and delay control method suitable for multi-memory testing systems. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] Dynamic Random Access Memory (DRAM) is a widely used semiconductor memory. Its working principle involves using the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0, thus storing data. Currently, various testing devices or systems for DRAM have been proposed to perform aging tests, weak cell tests, and speed tests on packaged DRAM components to ensure the memory components can operate normally.

[0004] For memory testing, compared to test systems for single-memory systems, test systems for multiple memory types have been proposed to improve testing efficiency. For example, the published patent CN118692550B proposes a semiconductor memory test system that achieves unified testing of several DRAMs by setting up a test board for inserting at least one DUT (Device Under Test) and a vector tester (or vector tester). Considering that electronic pins are a key element in the test system, they must operate at high frequency and high timing accuracy to ensure the synchronous transmission and reception of test signals (or test vectors) to guarantee the accuracy of the final test. This is one of the reasons for the high cost of the test system. Currently, in test systems for synchronous testing of multiple memories, the different command / address / data bus designs of multiple DUTs (Device Under Test) on the test board lead to delays in the routing and transmission of signals within the signal pins. These delays cause test errors, affecting the final test results and accuracy. Although delay compensation schemes have been proposed in the existing technology, the existing schemes consider only one factor and ignore the impact of other factors on signal delay. Moreover, they mostly only focus on the delay of signal transmission from the tester to the DUT, without considering the delay conflict of bidirectional transmission. That is, they do not consider the delay conflict problem that exists in the transmission of different signals to the DUT and the feedback transmission from the DUT, resulting in inaccurate delay control and failure to guarantee the accuracy of test results. Summary of the Invention

[0005] To address the shortcomings of the prior art, this invention provides a delay device and delay control method suitable for multi-memory test systems. Considering the delay problem that exists when testing multiple DUTs in parallel, the invention simplifies the electronic pins in the test system (i.e., multi-memory test system) to the greatest extent, optimizes the design of the delay device, and introduces different delay logic for different signals to achieve bidirectional delay compensation for signals in the test vector, thereby ensuring the test accuracy of multiple DUTs.

[0006] In a first aspect, the present invention provides a delay device suitable for multi-memory test systems.

[0007] A delay device suitable for a multi-memory test system, the delay device comprising a first delay register and a second delay register;

[0008] The first delay register is connected to the data driver of the electronic pin in the multi-memory test system. It is used to adjust the output timing of several data signals in the test vector by the data driver according to the first delay logic, so as to compensate for the path difference delay between the command / address bus and the data bus of several memories under test.

[0009] The second delay register is connected to the data receiver of the electronic pin in the multi-memory test system. It is used to adjust the timing of the data receiver receiving several expected data signals according to the second delay logic in order to compensate for the internal delay of several memories under test.

[0010] A further technical solution is that the multi-memory testing system includes a test board and a tester;

[0011] The test board is provided with several slots for inserting the memory under test. Each row of slots is connected to the same command / address bus, and the slots in the corresponding columns of each row are connected to the same data bus.

[0012] The tester includes a controller, electronic pins, and a delay unit. The controller is used to generate test vectors according to the downloaded long vector test mode. The electronic pins are provided with a command driver, an address driver, a data driver, and a data receiver. The command driver and the address driver are connected to the command / address bus, and the data driver and the data receiver are connected to the data bus.

[0013] The test vector includes command, address, and data signals for testing the memory under test. The test vector is driven by the driver in the electronic pin and transmitted to the memory under test in the test board slot through the command / address bus and data bus. The memory under test feeds back data signals and transmits them to the data receiver in the electronic pin through the data bus, thereby realizing the testing of the memory under test.

[0014] Further technical solutions for data drivers include at least an input signal DI, an output signal DO, and a control signal DC.

[0015] In each test cycle, the data signal DD facing several different locations of the memory under test in the test vector is used as the input signal DI and input to the data driver. At the same time, the clock signal clk is used as the control signal DC after being delayed by the first delay register and input to the data driver. The data driver controls the output signal DO according to the control signal DC, so that several memory under test receive the data signal synchronously and the data signal and command signal are matched in time.

[0016] A further technical solution involves adjusting the delay in the first delay register according to a first delay logic, which is as follows:

[0017] The path delay between the command / address bus and the data bus of the nearest memory under test is used as the baseline DUT path delay. The path delay of each memory under test is calculated based on the physical path distance of the command / address bus between several other memories under test located at different locations and the nearest memory under test.

[0018] Based on the path delay of each memory under test, the output time of the corresponding memory under test is adjusted so that all memory under test receive the data signal synchronously, and the reception time of the data signal matches that of the command signal.

[0019] A further technical solution is that the path delay is related to the test temperature, as shown in the formula:

[0020] ;

[0021] In the above formula, This represents the path delay of the target DUT. This represents the path delay of the reference DUT measured at standard temperature. This represents the temperature compensation coefficient, which is the rate of change of path delay caused by a unit change in temperature. This represents the difference between the current temperature and the reference temperature. This indicates the difference in the physical path length of the command / address bus between the target DUT and the reference DUT; Indicates the signal propagation speed at the reference temperature. At the speed of light, is the dielectric constant.

[0022] Further technical solutions, for data receivers, include at least an input signal RI, an output signal RO, and a control signal RC;

[0023] In each test cycle, the expected data signals fed back by the memory under test at several different locations are used as the input signal RI of the data receiver and are input to the data receiver. At the same time, the clock signal clk is adjusted by the delay of the second delay register and is used as the control signal RC and input to the data receiver. The data receiver controls the output of the output signal RO according to the control signal RC, so that the expected output signals fed back by the several memory under test are synchronized.

[0024] In a further technical solution, during each test cycle, the data signal RR of the memory under test facing several different locations in the test vector is input to the comparator as the original signal, and the synchronous output signal RO output by the data receiver is also input to the comparator. The comparator compares the original signal and the output signal RO to obtain the test result, and stores the test result in a set bit position in the test vector.

[0025] A further technical solution involves adjusting the delay in the second delay register according to a second delay logic, which is as follows:

[0026] The internal latency of different memory devices under test is obtained; the internal latency is the CL value, which is the time required from receiving a command to reading data from the memory.

[0027] Based on the internal delay of each memory under test, the expected data signal reception time of the corresponding memory under test is adjusted to synchronize the signal reception of all memory under test.

[0028] A further technical solution involves storing the data signals of the memory under test at several different locations in the test vector at the same bit position in each test cycle, and storing the synchronous output signal RO of the data receiver at the same bit position in the test vector, or directly at a set bit position.

[0029] Secondly, the present invention provides a delay control method suitable for multi-memory test systems.

[0030] A delay control method suitable for multi-memory test systems includes:

[0031] Using the first delay register and according to the first delay logic, the output timing of several data signals in the test vector by the data driver is adjusted to compensate for the path difference delay between the command / address bus and the data bus of several memory under test.

[0032] Using the second delay register, the timing of the data receiver receiving several expected data signals is adjusted according to the second delay logic to compensate for the internal delay of several memories under test.

[0033] The above one or more technical solutions have the following beneficial effects:

[0034] 1. This invention provides a delay device and delay control method suitable for multi-memory test systems. Considering the delay issues present in parallel testing of multiple DUTs, it simplifies the electronic pins in the test system to the greatest extent, optimizes the delay device design, and introduces different delay logic for different signals to achieve bidirectional delay compensation for all signals in the test vector, ensuring the testing accuracy of multiple DUTs. Specifically, through a first delay register, the path delay of other DUTs is calculated based on the path delay of the nearest DUT, and the output time of the data signal is adjusted accordingly. This ensures that all DUTs receive data signals synchronously and match the reception time of command signals, resolving the signal asynchrony problem caused by differences in the command / address bus and data bus paths, and avoiding test misjudgments. Through a second delay register, the timing of the data receiver receiving the expected data signal is adjusted according to the internal delay of different DUTs, synchronizing the signals fed back by each DUT, ensuring the accuracy of subsequent signal comparisons, and further improving test accuracy.

[0035] 2. By designing a first delay register and a second delay register, this invention integrates the delay compensation function into the electronic pin, eliminating the need for additional complex hardware structures. This simplifies the design of electronic pins in the test system to the greatest extent, reducing system complexity and cost. By integrating the delay unit with the tester's controller, electronic pins, etc., a complete test system is formed, making the system structure more compact and easier to maintain and upgrade.

[0036] 3. In the calculation of path delay, the present invention also considers the temperature factor and corrects the path delay at different temperatures by means of a temperature compensation coefficient, so that the system can accurately compensate for the path delay under different temperature environments, thus ensuring the stability and reliability of the test results.

[0037] 4. In this invention, the test results are stored in a set bit position in the test vector. Alternatively, the synchronous output signal output by the data receiver can be directly stored in the set bit position or the same bit position to facilitate subsequent data processing and analysis. The above design can effectively reduce connection complexity and improve test speed.

[0038] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0039] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0040] Figure 1 This is a schematic diagram of a delay device applicable to a multi-memory test system in an embodiment of the present invention;

[0041] Figure 2 This is a schematic diagram of a delay unit with the comparator omitted in an embodiment of the present invention;

[0042] Figure 3 This is a schematic diagram of a delay unit in an embodiment of the present invention, in which the comparator design is omitted and the storage location is adjusted. Detailed Implementation

[0043] It should be noted that the following detailed descriptions are exemplary and are intended only to describe specific embodiments and to provide further explanation of the invention, and are not intended to limit the scope of exemplary embodiments of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0044] Example 1

[0045] This embodiment provides a delay device suitable for a multi-memory test system, the delay device including a first delay register and a second delay register;

[0046] The first delay register is connected to the data driver of the electronic pin in the multi-memory test system. It is used to adjust the output timing of several data signals in the test vector by the data driver according to the first delay logic, so as to compensate for the path difference delay between the command / address bus and the data bus of several memories under test.

[0047] The second delay register is connected to the data receiver of the electronic pin in the multi-memory test system. It is used to adjust the timing of the data receiver receiving several expected data signals according to the second delay logic in order to compensate for the internal delay of several memories under test.

[0048] The delay device design proposed in this embodiment will be described in more detail below.

[0049] This embodiment relates to a test system for testing multiple memory systems. The system includes a test board and a tester. The test board has several slots for inserting a memory under test (DUT). Each row of slots is connected to the same command / address bus, and slots in corresponding columns of each row are connected to the same data bus. The tester includes a controller, electronic pins, and delay units. The controller generates test vectors based on a downloaded Long Vector (LV) test mode. These test vectors include command, address, and data signals for testing the DUT. The electronic pins have a command driver (CMD pin), an address driver (Addr pin), a DQ / DQS data driver (DQ / DQS pin), and a data receiver. The command driver and address driver are connected to the command / address bus, and the DQ / DQS data driver and data receiver are connected to the data bus. Additionally, the electronic pins have a power pin for supplying power. Based on this configuration, the test vectors are driven by the drivers in the electronic pins and transmitted to the DUT in the test board slots via the command / address bus and data bus. The DUT then feeds back data signals, which are transmitted to the data receiver in the electronic pins via the data bus, thus completing the testing of the DUT.

[0050] The CMD signal serves as a command interaction signal, used to transmit control commands or respond to the host. This CMD signal is transmitted via the Command / Address Bus, sending control instructions to the DUT, such as opening a page, closing a page, reading, and writing. Specifically, operations like "Open Page 1" and "Issue Read Command x2" are triggered by the CMD signal. The DQ / DQS signals, responsible for data transmission (DQ) and data strobing (DQS), are separate from the CMD signal. Considering that all DUTs are arranged along the long Command / Address Bus and all DUTs along the short Data Bus, the greater the distance between the DUTs on this bus, the more severe the mismatch between the command signals received by the DUTs and the DQ bus. If the data signal is driven to the DRAM on the DQ / DQS, it may arrive too early for the command / address signal. Conversely, if the feedback data signal is received from the DRAM on the DQ / DQS, the distance between the DUTs on the command bus will continue to increase. In other words, the arrival time of the CMD signal must be strictly synchronized with the DQ / DQS signals. This requires delaying the data signal (or equivalently advancing the command signal) to match their arrival times, thus avoiding command-data mismatch (such as data arriving too early or too late) caused by bus delay. Furthermore, different DUTs have different internal delays (i.e., CL values). The CL value of a memory is the first parameter of memory timing, representing the CAS latency, which is the time required from receiving a command to reading data from the memory, i.e., the response time of the memory's vertical address pulse. Therefore, the time it takes for the feedback data signal from different DUTs to reach the data receiver is also different. To ensure the final test accuracy, the arrival times of different DUTs also need to be sequentially delayed so that the received DUT feedback data signals can be arranged in the correct timing sequence, ensuring the accuracy of subsequent timing signal comparison tests.

[0051] Therefore, to ensure normal testing and high testing accuracy, the aforementioned signal delay must be compensated for via an electronic pin. To this end, this embodiment proposes a delay device suitable for multi-memory testing systems. This delay device includes programmable delay elements: a first delay register and a second delay register, which can adjust signal timing to compensate for path differences and internal delays within the DUT. Both the first and second delay registers can be implemented using an inverter chain, and the receiver and driver can be implemented using CMOS logic circuits. Other implementation methods can also be chosen, which will not be elaborated upon here.

[0052] like Figure 1 As shown, it provides a typical command sequence for testing DRAM, which displays the typical operation time of 9 clock cycles, i.e., Time1-9, as follows:

[0053] Time1: Open page 1; that is, initiate access to DRAM page 1;

[0054] Time2: Issue read command x1; that is, issue a read command. The command signal is transmitted to the DUT through the command bus. At this time, due to the bus length, there may be an initial delay, and the data needs to go through a delay of 4 clock cycles (assuming the waiting time is 4 clock cycles).

[0055] Time3: Close page 1; that is, close the currently accessed page 1 to free up resources for subsequent operations;

[0056] Time4: Open page 2; that is, open a new page 2. The command bus transmission delay may cause a slight lag in the time when the DUT receives the command. The timing needs to be adjusted through the electronic pin.

[0057] Time5: Issue read command x2; that is, send a new read request to page 2;

[0058] Time6: Data x1 from Time2 begins to arrive; that is, the read data sent by Time2 arrives at this time due to a 4-cycle delay, while the read command Time5 for page 2 is still in transmission and has not yet returned data.

[0059] Time7: Sends a write command (Test Vector) to page 2, while still receiving x1 data from Time2; that is, performs a write operation (write y2) on page 2. However, due to command bus delay, the actual effective time of the write command may be delayed, and it needs to be strictly synchronized with the DQ / DQS signal to avoid conflict.

[0060] Time8: The data x2 of Time5 has arrived; that is, it may be in an intermediate state of data transmission or command execution, such as waiting for the data read from Time5 to return.

[0061] Time9: Data x2 of Time5 continues to arrive; that is, the read data of Time5 returns at this moment. If the write command (Time7) requires data confirmation, additional delay compensation is required to match the timing of the DQ bus.

[0062] As one implementation method, the above command sequence can also be applied similarly to other semiconductors, such as LPDRAM, SRAM, flash memory, etc.

[0063] To ensure that the arrival time of the command / address signal and the DQ / DQS data signal is synchronized, in this embodiment, a first delay register is connected to the DQ / DQS data driver of the electronic pin in the multi-memory test system. The first delay register is used to adjust the output timing of several data signals in the test vector by the data driver according to the first delay logic, so as to compensate for the path difference delay between the command / address bus and the data bus of several memories under test.

[0064] Specifically, for a data driver, there are at least an input signal DI, an output signal DO, and a control signal DC. In each test cycle, the data signal DD facing several different locations of the memory under test in the test vector is used as the input signal DI and input to the data driver. At the same time, the clock signal clk is used as the control signal DC after being delayed by the first delay register and input to the data driver. The data driver controls the output of the output signal DO according to the control signal DC, so that several memory under test receive the data signal synchronously, and the reception time of the data signal matches the command signal.

[0065] The first delay register performs delay adjustment according to the first delay logic, which is as follows:

[0066] First, the path delay between the command / address bus and the data bus corresponding to the nearest memory under test (DUT) is used as the reference DUT path delay. This reference DUT path delay can be preset according to actual conditions (e.g., set to 4 clock cycles), ensuring that the data signal reception time is no earlier than the command / address signal reception time. Preferably, a signal acquisition device can also be used to pre-test the nearest DUT. By performing a synchronous command / address / data signal transmission test on the DUT, the reception time of the command / address signal and the data signal are obtained. Based on the difference between the reception times of the two signals, the reference DUT path delay time is determined. Based on this delay time, the transmission of the data signal is delayed to ensure that the data signal reception time is the same as the command / address signal reception time, thus achieving matching.

[0067] Secondly, the path delay of each memory under test is calculated based on the physical path distance of the command / address bus between several other memories under test located in different locations and the nearest memory under test.

[0068] The path delay mentioned above is related to the test temperature and can be expressed as:

[0069] ;

[0070] In the above formula, This represents the path delay of the target DUT. This represents the path delay of the reference DUT measured at standard temperature. This represents the temperature compensation coefficient, which is the rate of change of path delay caused by a unit change in temperature. This represents the difference between the current temperature and the reference temperature. This indicates the difference in the physical path length of the command / address bus between the target DUT and the reference DUT; Indicates the signal propagation speed at the reference temperature. At the speed of light, is the dielectric constant.

[0071] Finally, based on the path delay of each memory under test, the output time of the corresponding memory under test is adjusted so that all memory under test receive the data signal synchronously, and the reception time of the data signal matches that of the command signal.

[0072] In this embodiment, a second delay register is also provided and connected to the DQ / DQS data receiver of the electronic pin in the multi-memory test system. The second delay register is used to control the timing of the DQ / DQS data receiver to receive several data signals according to the second delay logic, so as to compensate for the internal delay of several memories under test and align the data signals fed back by each memory under test. This process does not include additional path length compensation.

[0073] Specifically, the data receiver has at least an input signal RI, an output signal RO, and a control signal RC. In each test cycle, the expected data signals fed back from several different locations of the memory under test (MDT) serve as the input signal RI to the data receiver. Simultaneously, the clock signal clk, after being delayed and adjusted by the second delay register, serves as the control signal RC and is input to the data receiver. The data receiver controls the output signal RO according to the control signal RC, synchronizing the expected output signals fed back from the several MDTs. Further, in each test cycle, the data signals RR from the test vector facing several different locations of the MDT are input as the original signals to the comparator. The synchronization output signal RO from the data receiver is also input to the comparator. The comparator compares the original signals and the output signal RO to obtain the test result, which is then stored in a designated bit position in the test vector. Additionally, the comparator is activated and controlled to start the comparison by the control signal CC.

[0074] The aforementioned second delay register performs delay adjustment according to the second delay logic, which is as follows:

[0075] First, obtain the internal latency of different memory devices under test. This internal latency is called the CL value. The CL value is the first parameter of memory timing and represents the CAS latency, which is the time required from receiving a command to reading data from memory, that is, the response time of the memory vertical address pulse. Different memory devices have different CL values.

[0076] Secondly, based on the internal delay of each memory under test, the expected data signal reception time of the corresponding memory under test is adjusted to synchronize the signal reception of all memory under test.

[0077] As one implementation method, considering that data comparison takes time and may lead to a decrease in speed, this embodiment directly stores the read information in a test vector file. At this point, it's impossible to determine whether the information is correct or incorrect. In this situation, offline software post-processing of the modified vector file is required to determine whether the read data is correct. That is, as... Figure 2 As shown, in each test cycle, the data signals of the DUT at several different locations in the test vector are all stored at the same bit position in the test vector. The synchronization output signal RO output by the data receiver is directly stored at a set bit position to reduce the required connections and further improve speed. Preferably, the data signals include data signals DD, RR, etc. Data signal DD is used as the driving data output to the DUT, and data signal RR is used as the reference data, i.e., the comparison benchmark for the read-back data. These two types of data are usually placed at different or the same bit positions in the test vector for easy use for driving and result verification, respectively.

[0078] As another implementation method, such as Figure 3 As shown, the synchronization output signal RO output by the data receiver can also be stored in the same bit position of the test vector.

[0079] The design of the first and second delay registers proposed in this embodiment integrates the delay compensation function into the electronic pins, eliminating the need for additional complex hardware structures. This simplifies the design of electronic pins in the test system to the greatest extent, reducing system complexity and cost. Furthermore, through the optimized design of this delay unit, different delay logic is introduced for different signals to achieve bidirectional delay compensation for all signals in the test vector, effectively ensuring the test accuracy of multiple DUTs.

[0080] Example 2

[0081] This embodiment provides a latency control method suitable for multi-memory test systems, specifically including the following steps:

[0082] Using the first delay register and according to the first delay logic, the output timing of several data signals in the test vector by the data driver is adjusted to compensate for the path difference delay between the command / address bus and the data bus of several memory under test.

[0083] Using the second delay register, the timing of the data receiver receiving several expected data signals is adjusted according to the second delay logic to compensate for the internal delay of several memories under test.

[0084] The steps involved in the above embodiment two correspond to those in embodiment one. For specific implementation details, please refer to the relevant description section of embodiment one, which will not be repeated here.

[0085] The above description is only a preferred embodiment of the present invention. Although the specific implementation of the present invention has been described in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that, based on the technical solution of the present invention, various modifications or variations that can be made by those skilled in the art without creative effort are still within the scope of protection of the present invention.

Claims

1. A delay device suitable for multi-memory test systems, characterized in that, The delay unit includes a first delay register and a second delay register; The first delay register is connected to the data driver of the electronic pin in the multi-memory test system. It is used to adjust the output timing of several data signals in the test vector by the data driver according to the first delay logic, so as to compensate for the path difference delay between the command / address bus and the data bus of several memories under test. The second delay register is connected to the data receiver of the electronic pin in the multi-memory test system. It is used to adjust the timing of the data receiver receiving several expected data signals according to the second delay logic in order to compensate for the internal delay of several memories under test. The first delay register adjusts the delay according to the first delay logic, which is as follows: The path delay between the command / address bus and the data bus of the nearest memory under test is used as the baseline DUT path delay. The path delay of each memory under test is calculated based on the physical path distance of the command / address bus between several other memories under test located at different locations and the nearest memory under test. Based on the path delay of each memory under test, the output time of the corresponding memory under test is adjusted so that all memory under test receive the data signal synchronously and the reception time of the data signal matches that of the command signal. The path delay is related to the test temperature, and the formula is: ； In the above formula, This indicates the path delay of the target DUT. This represents the path delay of the reference DUT measured at standard temperature. This represents the temperature compensation coefficient, which is the rate of change of path delay caused by a unit change in temperature. This represents the difference between the current temperature and the reference temperature. This indicates the difference in the physical path length of the command / address bus between the target DUT and the reference DUT; Indicates the signal propagation speed at the reference temperature. At the speed of light, It is the dielectric constant; In each test cycle, the data signal RR of the memory under test facing several different locations in the test vector is input into the comparator as the original signal, and the synchronous output signal RO output by the data receiver is also input into the comparator. The comparator compares the original signal and the output signal RO to obtain the test result, and stores the test result in the set bit position in the test vector. The second delay register adjusts the delay according to the second delay logic, which is as follows: The internal latency of different memory devices under test is obtained; the internal latency is the CL value, which is the time required from receiving a command to reading data from the memory. Based on the internal delay of each memory under test, the expected data signal reception time of the corresponding memory under test is adjusted to synchronize the signal reception of all memory under test.

2. The delay device for a multi-memory test system as described in claim 1, characterized in that, The multi-memory testing system includes a test board and a tester; The test board is provided with several slots for inserting the memory under test. Each row of slots is connected to the same command / address bus, and the slots in the corresponding columns of each row are connected to the same data bus. The tester includes a controller, electronic pins, and a delay unit. The controller is used to generate test vectors according to the downloaded long vector test mode. The electronic pins are provided with a command driver, an address driver, a data driver, and a data receiver. The command driver and the address driver are connected to the command / address bus, and the data driver and the data receiver are connected to the data bus. The test vector includes the command, address, and data signals for testing the memory under test; The test vector is driven by the driver in the electronic pin and transmitted to the memory under test in the test board slot through the command / address bus and data bus. The memory under test feeds back data signals and transmits them to the data receiver in the electronic pin through the data bus, thus realizing the testing of the memory under test.

3. The delay device for a multi-memory test system as described in claim 1, characterized in that, For a data driver, at least an input signal DI, an output signal DO, and a control signal DC are required; In each test cycle, the data signal DD facing several different locations of the memory under test in the test vector is used as the input signal DI and input to the data driver. At the same time, the clock signal clk is used as the control signal DC after being delayed by the first delay register and input to the data driver. The data driver controls the output signal DO according to the control signal DC, so that several memory under test receive the data signal synchronously and the data signal and command signal are matched in time.

4. The delay device for a multi-memory test system as described in claim 1, characterized in that, For a data receiver, it must have at least an input signal RI, an output signal RO, and a control signal RC; In each test cycle, the expected data signals fed back by the memory under test at several different locations are used as the input signal RI of the data receiver and are input to the data receiver. At the same time, the clock signal clk is adjusted by the delay of the second delay register and is used as the control signal RC and input to the data receiver. The data receiver controls the output of the output signal RO according to the control signal RC, so that the expected output signals fed back by the several memory under test are synchronized.

5. The delay device for a multi-memory test system as described in claim 4, characterized in that, In each test cycle, the data signals of the memory under test facing several different locations in the test vector are all stored in the same bit position of the test vector, and the synchronous output signal RO output by the data receiver is also stored in the same bit position of the test vector, or directly stored in a set bit position.

6. A delay control method suitable for multi-memory test systems, characterized in that, The delay device implementation for a multi-memory test system based on any one of claims 1-5 includes: Using the first delay register and according to the first delay logic, the output timing of several data signals in the test vector by the data driver is adjusted to compensate for the path difference delay between the command / address bus and the data bus of several memory under test. Using the second delay register, the timing of the data receiver receiving several expected data signals is adjusted according to the second delay logic to compensate for the internal delay of several memories under test.

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