An Optimized Generation Method for Power Transistor Drive Signals in a Submodule of an SLCC-SVF System

Abstract

This invention discloses an optimized generation method for power transistor drive signals in SLCC-SVF system submodules. Addressing the problem of abnormal switching frequencies, additional losses, and efficiency degradation caused by capacitor voltage sorting-based equalization strategies during operation, this invention proposes a drive signal generation strategy combining synchronous updates and equivalent frequency reduction. This method introduces an adaptive modulation switching mechanism. In normal operating mode, it uses nearest-nearest-level modulation (NLM) combined with a capacitor voltage sorting equalization strategy to generate drive signals. When a submodule switching frequency or temperature exceeds limits, it automatically switches to a carrier phase-shift pulse width modulation (CPS-PWM) module, utilizing its built-in closed-loop voltage equalization algorithm to achieve rapid voltage regulation and anomaly suppression. This strategy effectively suppresses instantaneous switching frequency rises and average frequency fluctuations, achieving coordinated optimization of the power transistor drive signals while balancing voltage equalization and system efficiency.

Description

Technical Field

[0001] This invention belongs to the field of power electronic converter technology, and particularly relates to an optimized generation method for power transistor drive signals of a submodule in an SLCC-SVF system. Background Technology

[0002] The Linear Constant Current Source-Static Var Compensator-Filter (SLCC-SVF) composite system consists of a line commutator converter (LCC) and a static var compensator and filter (SVF) connected in parallel. It combines high-power transmission and dynamic reactive power compensation capabilities and is widely used in high-voltage direct current transmission and power quality control. SVFs typically employ a modular multilevel structure, consisting of multiple full-bridge sub-modules connected in series. Multilevel output and capacitor voltage balance are achieved by controlling the switching of these sub-modules. Existing systems often use a voltage equalization strategy based on capacitor voltage sorting to achieve voltage equalization control. However, this strategy is prone to fluctuations in sub-module switching frequencies during frequent sorting updates, leading to increased switching losses and thermal stress, and decreased system efficiency. Under high harmonic or heavy load conditions, the capacitor voltage and temperature of some sub-modules are prone to exceeding limits, affecting system stability. Therefore, a sub-module drive signal optimization method is needed that can adaptively adjust the switching frequency and temperature while maintaining voltage balance to improve system reliability and operating efficiency. Summary of the Invention

[0003] Purpose of the Invention: The purpose of this invention is to provide an optimized generation method for the power transistor drive signals of a submodule in an SLCC-SVF system. This method achieves adaptive optimization of the submodule drive signals under different operating conditions, thereby balancing voltage balance, frequency suppression, and temperature control, and improving the system's operational stability and overall efficiency.

[0004] Technical Solution: The present invention provides an optimized generation method for the power transistor drive signal of a submodule in an SLCC-SVF system. The method is applied to a linear constant current source-static var compensator and filter composite system SLCC-SVF. The system consists of a line commutator converter (LCC) and a static var compensator and filter (SVF) connected in parallel. The SVF contains multiple full-bridge submodules, each of which consists of four power transistors, anti-parallel diodes, and capacitors. By executing steps A to D, the switching frequency is reduced, thereby optimizing the drive signal.

[0005] Step A. Collect the operational data of each full-bridge submodule in the SLCC-SVF system. The operational data includes capacitor voltage. Real-time switching frequency ,temperature and bridge arm current Based on the sampled capacitor voltage Generate capacitor voltage reference value According to the system's rated DC voltage The theoretical voltage distribution value of each module is calculated according to the number N of sub-modules and the initial input polarity is determined in combination with the sampling current direction; the running quantity is used for subsequent modulation and out-of-limit judgment after A / D conversion;

[0006] Step B. In the normal working mode, the driving signal is generated by using the nearest level modulation strategy NLM in combination with the capacitor voltage sorting equalization strategy, the positive and negative input priorities of the sub-modules are dynamically adjusted by comparing the capacitor voltage reference value with the actual capacitor voltage value in combination with the sorting result, and the capacitor voltage equalization is realized;

[0007] Step C. Calculate the comprehensive index When the comprehensive out-of-limit index of any sub-module is detected Exceeds the set threshold 1, the driving signal generation mode of the sub-module is switched from the NLM modulation mode to the carrier phase shift pulse width modulation CPS-PWM mode;

[0008] Step D. In the CPS-PWM mode, the capacitor voltage of the abnormal module is adjusted by the carrier phase shift and closed-loop voltage equalization algorithm; when the comprehensive index Restores to below 1, the system switches back to the NLM modulation combined with the equalization strategy mode;

[0009] Step E. The driving signals of the normal modules and the out-of-limit modules are selected and output by the gate; when 1, the driving signal generated by the NLM combined with the equalization strategy is output; when 1, the driving signal generated by the CPS-PWM module is output, realizing the cooperative control of the switching frequency and the temperature.

[0010] Further, in step A, the theoretical voltage distribution value of each module is calculated according to the system rated DC voltage And the number N of sub-modules, specifically:

[0011] 。

[0012] Further, in step B, the update condition of the capacitor voltage sorting result Is limited to triggering only when the number of sub-module inputs Changes, so as to avoid the instantaneous switching frequency rise caused by repeated sorting, and the maximum value of the instantaneous switching frequency Is limited to , Indicates the total switching times of Sub-modules in 1 second, Indicates the switching frequency.

[0013] Further, step B specifically includes the following steps:

[0014] Step B1. Two kinds of capacitor voltage input modes are realized according to the direction of bridge arm current , which are positive voltage input mode and negative voltage input mode ; when the sub-module is in positive voltage input mode, current flows through power tube VT1 and anti-parallel diode VD2, and capacitor voltage is output with positive polarity, denoted as ; when the sub-module is in negative voltage input mode, current flows through power tube VT3 and anti-parallel diode VD4, and capacitor voltage is output with negative polarity, denoted as

[0015] Step B2. The number of input sub-modules is calculated by using the nearest level modulation strategy NLM, and the mathematical expression is:

[0016]

[0017] wherein is the capacitor voltage reference value, is the capacitor voltage, is the rounding function; when , input sub-modules output positive level; when , input sub-modules output negative level;

[0018] Step B3. The voltage balancing strategy based on capacitor voltage sorting is used to maintain the balance of capacitor voltage of each sub-module in the system, and the sorting balance control includes four instructions: instruction 1 is to generate the number of input sub-modules according to the NLM modulation strategy ; instruction 2 sorts the capacitor voltage of each sub-module to obtain the sorting result ; instruction 3 is to determine the switching priority according to the polarity of bridge arm current ; instruction 4 is to generate the power tube driving signal of each sub-module in combination with the foregoing calculation results, so as to realize the dynamic balance of capacitor voltage.

[0019] Step B4. After completing the four instructions, the system enters an idle state before the next calculation period starts, and the sorting update rate is constrained by the communication bandwidth and the data frame length, and the rate result is used to determine the change range of the average switching frequency and the instantaneous switching frequency in the upper and lower boundary analysis of frequency.

[0020] Further, in step C, the comprehensive index is calculated, specifically:

[0021] ​

[0022] in, and These are the real-time switching frequency and temperature of the submodule, respectively. and Preset safety thresholds for real-time switching frequency and temperature.

[0023] Further, step D specifically involves: the CPS-PWM module including a carrier generation unit, a phase shift generation unit, a comparison unit, a closed-loop voltage equalization control unit, and a drive gating unit; the carrier generation unit generates N periodic carrier signals with the same frequency, the carrier being a constant-amplitude triangular wave or a sawtooth wave, and the frequency is denoted as . The phase-shifting generation unit shifts the phase of the carrier signal according to the number N sub-modules within a single-phase bridge arm, obtaining the phase shift of the first phase. Road carrier Its phase shift satisfy This achieves an evenly spaced phase staggered distribution of the carrier waves; the comparison unit will divide each phase-shifted carrier wave... With control reference quantity Or the reference value of the capacitor voltage of each submodule The comparison is performed, and the result is processed and used as the first... PWM pulses of submodules; closed-loop voltage equalization control unit based on real-time capacitor voltage of each submodule. With capacitor voltage reference value The deviation is calculated to determine the closed-loop equalization correction, and the correction is fed back to the comparison unit periodically or via event triggering to adjust the comparison threshold or reference; the drive gating unit is then driven to adjust the comparison threshold or reference based on the comprehensive index. The system gating logic determines whether to output the PWM pulse generated by the CPS-PWM module to the switching transistor drive circuit, and state synchronization and edge alignment are used during mode switching.

[0024] Furthermore, the CPS-PWM module also includes a configuration unit for limiting the relationship between the carrier frequency and the closed-loop voltage equalization bandwidth. Through carrier phase shift and closed-loop voltage equalization, the peak-shifting switching of each sub-module is achieved, and the equivalent switching frequency and thermal stress of a single module are reduced.

[0025] Furthermore, to limit the average switching frequency The growth, based on communication bandwidth The data frame length (Data) of the submodule is calculated using the following formula:

[0026]

[0027] Obtain capacitor voltage sorting results Update lower limit frequency ,in, Vdc is the DC side voltage, is the peak current of the bridge arm, C is the sub-module capacitor, and N is the number of sub-modules; when the update frequency is lower than , the system automatically enters the equivalent frequency reduction equalization mode to ensure that the capacitor voltage fluctuation is less than .

[0028] The application also discloses a computer device, including a memory, a processor and a computer program stored on the memory, and the processor executes the computer program to realize the steps of the method of the application.

[0029] The application also discloses a computer readable storage medium, which stores a computer program / instruction, and the computer program / instruction is executed by a processor to realize the steps of the method of the application.

[0030] The application also discloses a computer program product, which includes a computer program / instruction, and the computer program / instruction is executed by a processor to realize the steps of the method of the application.

[0031] Advantages: compared with the prior art, the application has the following remarkable advantages:

[0032] The application can effectively inhibit the problem of abnormal increase of instantaneous switching frequency caused by the capacitor voltage ordering equalization strategy, significantly reduce the fluctuation amplitude of the average switching frequency, and reduce the additional switching action and thermal stress of the sub-module. By adaptively switching the voltage equalization NLM modulation and the CPS-PWM modulation mode under different working conditions, the switching frequency and the temperature are cooperatively controlled, so that the system can maintain good voltage equalization and stable operation. The method can maintain the output power quality while reducing switching loss, improving system efficiency and device reliability, so that the driving signal optimization generation method provided by the application is suitable for high-voltage high-power, multi-level conversion structure power electronic devices, especially in high-voltage direct current transmission (HVDC) converter stations, dynamic reactive power compensation devices and new type of composite converter systems, and has wide application prospect. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is the SLCC main circuit and its SVF topological graph;

[0034] Figure 2 is the optimization generation strategy diagram of the power tube driving signal;

[0035] Figure 3 is the voltage balancing strategy implementation process diagram based on the sorting algorithm;

[0036] Figure 4 is the voltage and current waveform diagram under the equalization mode of the traditional capacitor voltage ordering under the condition that the voltage equalization frequency is 100Hz;

[0037] Figure 5 is the voltage and current waveform diagram under the adaptive modulation switching mode when the equalization frequency is 100 Hz;

[0038] Figure 6 is the voltage and current waveform diagram under the traditional capacitor voltage sequencing equalization mode when the equalization frequency is 500 Hz;

[0039] Figure 7 is the voltage and current waveform diagram under the adaptive modulation switching mode when the equalization frequency is 500 Hz;

[0040] Figure 8 is the voltage and current waveform diagram under the traditional capacitor voltage sequencing equalization mode when the equalization frequency is 1000 Hz;

[0041] Figure 9 is the voltage and current waveform diagram under the adaptive modulation switching mode when the equalization frequency is 1000 Hz. DETAILED DESCRIPTION

[0042] The technical solutions of the present application will be further described below in combination with the drawings.

[0043] As shown in the drawings, the SLCC main circuit and its SVF topology are shown in the drawings. Figure 1 is the system side inductance, is the DC filter inductance, , , is the SVF phase bridge inductance; and are the AC voltage and DC bus voltage, respectively, , , , , are the AC input current, filter branch current and phase bridge current, respectively. The SVF adopts a three-phase cascaded H-bridge structure, each phase is composed of N full-bridge sub-modules in series, and the sub-modules are numbered according to the phase sequence and position as , , , The topology structure of the full-bridge sub-module is adopted: it contains four switching devices ( ) and anti-parallel diodes ( ), and the capacitor voltage in the sub-module is usually denoted as .

[0044] As shown in the drawings, the SLCC main circuit and its SVF topology are shown in the drawings. Figure 2 ​The application discloses a sub-module power tube driving signal optimization generation method based on an SLCC-SVF system, and is applied to a linear constant current source-static reactive compensation and filter composite system (SLCC-SVF). The system is composed of a line commutated converter (LCC) and a static reactive compensation and filter (SVF) in parallel, wherein the SVF comprises a plurality of full-bridge sub-modules, each of which is composed of four power tubes, anti-parallel diodes and a capacitor. The method comprises the following steps A to D to reduce the switching frequency and optimize the driving signal.

[0045] Step A. Real-time collection of key operation quantities of each full-bridge sub-module in the SLCC-SVF system, wherein the operation quantities comprise capacitor voltage , real-time switching frequency , temperature and bridge arm current ; capacitor voltage reference value is generated according to the sampled capacitor voltage ; the theoretical voltage distribution value of each module is calculated according to the system rated DC voltage and the number N of sub-modules according to the following formula:

[0046]

[0047] The initial input polarity is determined in combination with the sampling current direction; the collected capacitor voltage, switching frequency and temperature signals are converted by an A / D converter to serve as the basis for subsequent modulation and out-of-limit judgment; and then step B is entered.

[0048] Step B. In the normal working mode, a nearest level modulation strategy (NLM) is combined with a capacitor voltage sorting and balancing strategy to generate a driving signal. The positive and negative input priorities of the sub-modules are dynamically adjusted by comparing the capacitor voltage reference value with the actual capacitor voltage value in combination with the sorting result, so that the capacitor voltage is balanced. When the comprehensive out-of-limit index of any sub-module exceeds a set threshold value 1, the driving signal generation mode of the sub-module is switched from the NLM modulation mode to a carrier phase shift pulse width modulation (CPS-PWM) mode according to the following formula:

[0049]

[0050] The comprehensive index is obtained, wherein and are the real-time switching frequency and temperature of the sub-module respectively, and are preset safety threshold values; and then step C is entered.

[0051] In practical applications, in step B above, steps B1 to B4 are executed to obtain the nearest level modulation strategy (NLM) combined with the capacitor voltage equalization control module.

[0052] Step B1. Based on the bridge arm current The direction allows for two capacitor voltage input methods: positive voltage input mode and positive voltage input mode. With negative voltage input mode When the submodule is in positive voltage input mode, the current... The current flows through the power transistor VT1 and the anti-parallel diode VD2, and the capacitor voltage is output with positive polarity, denoted as . When the submodule is in negative voltage input mode, current flows through power transistor VT3 and anti-parallel diode VD4, and the capacitor voltage is output with negative polarity, denoted as... Then proceed to step B2;

[0053] Step B2. Calculate the number of submodules to be deployed using the Nearest Level Modulation (NLM) strategy. Its mathematical expression is:

[0054]

[0055] in, This is the reference value for the submodule voltage. This refers to the capacitor voltage of the submodule. This is the integer function (rounding). Therefore, when At that time, invest Each submodule outputs a positive level; when At that time, invest | Each submodule outputs a negative level; then proceed to step B3;

[0056] Step B3. As Figure 3 As shown, a voltage balancing strategy based on capacitor voltage sorting is adopted to maintain the balance of capacitor voltages in each submodule of the system. The sorting and balancing control includes four instructions: Instruction 1 generates the number of submodules to be put into operation according to the NLM modulation strategy. Instruction 2 specifies the capacitor voltage for each submodule. Sort the data to obtain the sorted results. Instruction 3 is based on the bridge arm current. The polarity determines the switching priority; instruction 4 generates the power transistor drive signal for each submodule based on the aforementioned calculation results to achieve dynamic balance of capacitor voltage; then proceed to step B4;

[0057] Step B4. After completing the four instruction segments, the system enters an idle state before the start of the next calculation cycle to prevent instantaneous switching frequency fluctuations caused by repeated updates; the sorting update rate is constrained by the communication bandwidth and data frame length, and the result will be used to determine the system's average switching frequency in the upper and lower frequency boundary analysis. With instantaneous switching frequency The range of variation.

[0058] Step C. In CPS-PWM mode, the capacitor voltage of the abnormal module is quickly adjusted through carrier phase shift and closed-loop voltage equalization algorithm to achieve synchronous control of frequency and temperature; when the comprehensive index After the value recovers to below 1 and remains below 1 for a certain period of time (e.g., 5 switching cycles), the system automatically switches back to the NLM modulation combined with equalization strategy mode; then proceeds to step D.

[0059] In practical applications, step C above involves a carrier phase-shift pulse width modulation module (CPS-PWM module) used to generate the closed-loop voltage equalization PWM drive signal for the sub-module in over-limit mode. The CPS-PWM module includes a carrier generation unit, a phase-shift generation unit, a comparison unit, a closed-loop voltage equalization control unit, and a drive gating unit. The functions of each unit are as follows: the carrier generation unit generates N periodic carrier signals with the same frequency. The carrier is a constant-amplitude triangular wave or a sawtooth wave, and its frequency is denoted as... The phase-shifting generation unit shifts the phase of the carrier signal according to the number N sub-modules within a single-phase bridge arm, obtaining the phase shift of the first phase. Road carrier Its phase shift satisfy This achieves an evenly spaced phase staggered distribution of the carrier waves; the comparison unit will divide each phase-shifted carrier wave... With from Control reference quantity of converter Or the local reference voltage of each submodule The comparison is performed, and the result, after dead-zone processing, is used as the first... PWM pulses of submodules; closed-loop voltage equalization control unit based on real-time capacitor voltage of each submodule. With capacitor voltage reference The deviation is calculated to obtain the closed-loop voltage equalization correction amount, and the correction amount is fed back to the comparison unit in a periodic or event-triggered manner to adjust the comparison threshold or reference, thereby realizing rapid adjustment and equalization of the capacitor voltage of the over-limit submodule; the drive gating unit is driven according to the over-limit evaluation index. The system gating logic determines whether to output the PWM pulse generated by the CPS-PWM module to the switching transistor drive circuit. During mode switching, state synchronization and edge alignment measures are adopted to ensure a smooth transition of the drive signal and avoid transient impacts. The CPS-PWM module also includes a configuration unit for limiting the relationship between the carrier frequency and the closed-loop voltage equalization bandwidth to avoid oscillations caused by excessively wide closed-loop bandwidth and power quality degradation caused by excessively low carrier frequency. Thus, by coordinating carrier phase shift and closed-loop voltage equalization, peak-shifting switching of each sub-module is achieved, and the equivalent switching frequency and thermal stress of a single module are reduced.

[0060] Step D. The drive signals of the normal module and the over-limit module are filtered and output using a selector. For the normal module (S... 1) The output is a drive signal generated by NLM combined with equalization strategy. For the over-limit module (S>1), the output is a drive signal generated by CPS-PWM module to ensure that there is no transient interference during the drive signal switching process, thereby realizing the coordinated control of switching frequency and temperature.

[0061] In practical applications, step D above, such as... Figure 2 As shown, the limit-breaking judgment module uses a real-time digital comparison method to periodically calculate the comprehensive evaluation index of each sub-module. Based on this, threshold judgment and modulation mode switching control are completed without the need for additional equalization time calculation.

[0062] In practical applications, to suppress instantaneous switching frequency To limit the peak value, a synchronous update strategy is introduced into the control logic to restrict the capacitor voltage sorting results. The update condition is only applied to the number of entries in the submodule. Triggered when changes occur Update, thereby making The maximum value is limited to , express Total number of switching cycles per submodule within 1 second , Indicates the switching frequency.

[0063] In practical applications, to limit the average switching frequency The growth, based on communication bandwidth The data frame length (Data) of the submodule is calculated using the following formula:

[0064]

[0065] Obtain capacitor voltage sorting results Update lower limit frequency ,in, DC side voltage Where C is the peak current of the bridge arm, C is the capacitance of the submodule, and N is the number of submodules; when Update frequency is lower than At this time, the system automatically enters the equivalent frequency reduction equalization mode to ensure that the capacitor voltage fluctuation is less than 100%. .

[0066] The aforementioned technical solution proposes an optimized generation method for submodule power transistor drive signals based on an SLCC-SVF system. Targeting the operating characteristics of a linear constant current source-static var compensator-filter composite system (SLCC-SVF), it constructs a drive signal generation mechanism centered on adaptive modulation switching. This method first generates capacitor voltage reference values ​​by real-time acquisition of capacitor voltage, switching frequency, and temperature for each submodule. Under normal operating conditions, it uses nearest-nearest-level modulation (NLM) combined with a capacitor voltage sorting and equalization strategy to generate drive signals, achieving dynamic voltage equalization control. When a submodule is detected to have exceeded its frequency or temperature limits, the system automatically switches to carrier phase-shift pulse width modulation (CPS-PWM) mode, utilizing multi-carrier phase misalignment and closed-loop voltage equalization algorithms to achieve rapid adjustment and thermal stress balance for the over-limited module. A synchronous update algorithm restricts the update conditions of the sorting results, effectively constraining the instantaneous switching frequency peak. Furthermore, it calculates the lower limit frequency for voltage sorting updates based on the communication bandwidth to prevent increased losses due to excessively high average frequencies. This design scheme enables coordinated control of submodule switching frequency and temperature, significantly reducing additional switching losses and voltage fluctuations, improving system operating efficiency and stability, and has wide application value in high voltage DC transmission, dynamic reactive power compensation and multilevel conversion devices.

[0067] A simulation experimental platform was built according to the technical solution of this invention. Experiments were conducted using both the traditional capacitor voltage sorting equalization strategy and the adaptive modulation switching strategy proposed in this invention. The voltage and current waveform curves at their respective LCC voltage equalization frequencies were obtained, as shown below. Figures 4-9 As shown in the figure, the voltage and current waveforms of two control strategies are presented under voltage equalization frequencies of 100Hz, 500Hz, and 1000Hz. It can be seen from the figure that the voltage and current waveforms under the traditional capacitor voltage sorting equalization strategy exhibit significant high-frequency fluctuations and voltage spikes, large bridge arm current distortion, and irregular jumps in instantaneous switching frequency, leading to increased dynamic deviations in the submodule capacitor voltages. However, after adopting the adaptive modulation switching strategy proposed in this invention, the voltage waveform is significantly smoother, the current distortion rate is significantly reduced, and the switching frequency distribution is more uniform, especially at a voltage equalization frequency of 1000Hz. Simulation experiments show that the average switching frequency using the traditional capacitor voltage sorting equalization strategy and the average switching frequency using the improved optimized strategy are shown in Table 1. After adopting the adaptive modulation switching strategy, the average switching frequency decreases significantly. The experimental results verify that this method has excellent dynamic response performance and engineering application value in high-voltage multilevel conversion systems.

[0068] Table 1. Effects of the two methods on the average switching frequency

[0069]

[0070] The embodiments are merely illustrative of the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of this invention.

Claims

1. A method for optimizing the generation of power tube drive signals for SLCC-SVF system sub-modules, characterized in that, The method is applied to a linear constant current source-static reactive compensation and filter composite system SLCC-SVF, the system is composed of a line commutated converter LCC and a static reactive compensation and filter SVF in parallel, wherein the SVF comprises a plurality of full-bridge sub-modules, each of which is composed of four power tubes, anti-parallel diodes and a capacitor, by performing steps A to D, the size of the switching frequency is reduced, and the driving signal is optimized; Step A. Collecting the running quantities of each full-bridge sub-module in the SLCC-SVF system, including the capacitor voltage , real-time switching frequency , temperature and bridge arm current ; According to the sampled capacitor voltage Generating a capacitor voltage reference value ; According to the system rated DC voltage The theoretical voltage distribution value of each module is calculated with the number of sub-modules N, and the initial input polarity is determined in combination with the sampling current direction; The running quantity is converted by A / D after running quantity, which is used for subsequent modulation and out-of-limit judgment; Step B. In the normal working mode, the driving signal is generated by using the nearest level modulation strategy NLM combined with the capacitor voltage sorting equalization strategy, by comparing the capacitor voltage reference value with the actual capacitor voltage value, and dynamically adjusting the positive and negative input priority of the sub-module combined with the sorting result, the capacitor voltage equalization is realized. Step C. Calculate the comprehensive index When the comprehensive index of any submodule is detected When the threshold value exceeds 1, the driving signal generation mode of this submodule will be switched from NLM modulation mode to carrier phase-shift pulse width modulation (CPS-PWM) mode. In step C, the overall index is calculated , in particular: ； wherein, and are the real-time switching frequency and temperature of the sub-modules, respectively, and are preset safety thresholds for the real-time switching frequency and temperature, respectively. Step D. In CPS-PWM mode, the capacitor voltage of the abnormal module is adjusted by carrier phase shift and closed-loop voltage sharing algorithm; when the comprehensive index restores to 1 or below, the system switches back to the NLM modulation combined with equalization strategy mode; Step E. The drive signals of normal module and out-of-limit module are screened and outputted by the gate, when 1, the drive signal generated by NLM combined with equalization strategy is outputted; when 1, the drive signal generated by CPS-PWM module is outputted, realizing the cooperative control of switching frequency and temperature.

2. The method of claim 1, wherein the SLCC-SVF system sub-module power tube drive signal is optimized. In step A, the system rated DC voltage The theoretical voltage distribution value of each module is calculated according to the number N of sub-modules, specifically: 。 3. The method of claim 1, wherein the SLCC-SVF system sub-module power tube drive signal is optimized. In step B, the capacitor voltage ranking result The update condition is limited to only when the number of sub-modules is changed, to avoid the transient switching frequency rise caused by repeated ranking, and limit the maximum value of the transient switching frequency to , represents the total switching times of sub-modules within 1 second, represents the switching frequency.

4. The method of claim 1, wherein the SLCC-SVF system sub-module power tube drive signal is optimized. Step B specifically includes the following steps: Step B1. Two kinds of capacitor voltage input modes are realized according to the direction of bridge arm current , which are positive voltage input mode and negative voltage input mode ; when the sub-module is in positive voltage input mode, current flows through power tube VT1 and anti-parallel diode VD2, capacitor voltage is output with positive polarity, denoted as ; when the sub-module is in negative voltage input mode, current flows through power tube VT3 and anti-parallel diode VD4, capacitor voltage is output with negative polarity, denoted as ; Step B2. Calculate the number of inputs of the sub-module using the recent level modulation strategy NLM The mathematical expression is: ； wherein, is a capacitance voltage reference value, is a capacitance voltage, is a rounding function; when is input a sub-module outputs a positive level; when is input a sub-module outputs a negative level; Step B3. Employ a voltage balancing strategy based on capacitor voltage sorting to maintain the voltage balance of capacitors in each submodule of the system. The sorting and balancing control includes four instructions: Instruction 1 generates the number of submodules to be engaged based on the NLM modulation strategy. Instruction 2 specifies the capacitor voltage for each submodule. Sort the data to obtain the sorted results. Instruction 3 is based on the bridge arm current. The polarity determines the switching priority; Instruction 4 generates the power transistor drive signal for each submodule based on the aforementioned calculation results, so as to achieve dynamic balance of capacitor voltage; Step B4. After completion of the four-segment instruction, the system enters an idle state until the beginning of the next computation cycle. The sequencing update rate is constrained by the communication bandwidth and the data frame length. The resulting rate is analyzed in the upper and lower frequency bound analysis to determine the average switching frequency of the system and the range of variation of the instantaneous switching frequency .

5. The method of claim 1, wherein, The step D specifically comprises: the CPS-PWM module comprises a carrier generating unit, a phase-shifting generating unit, a comparing unit, a closed-loop voltage-sharing control unit and a drive gating unit; the carrier generating unit generates N periodic carrier signals with same frequency, the carrier is equiamplitude triangle wave or sawtooth wave and the frequency is denoted as ; The phase-shifting generation unit shifts the phase of the carrier signal according to the number N sub-modules in a single-phase bridge arm, and obtains the phase shift of the first phase. Road carrier Its phase shift satisfy This achieves an evenly spaced phase staggered distribution of the carrier waves; the comparison unit will divide each phase-shifted carrier wave... With control reference quantity Or the reference value of the capacitor voltage of each submodule The comparison is performed, and the result is processed and used as the first... PWM pulses of submodules; closed-loop voltage equalization control unit based on real-time capacitor voltage of each submodule. With capacitor voltage reference value The deviation is calculated to determine the closed-loop equalization correction, and the correction is fed back to the comparison unit periodically or via event triggering to adjust the comparison threshold or reference; the drive gating unit is then driven to adjust the comparison threshold or reference based on the comprehensive index. The system gating logic determines whether to output the PWM pulse generated by the CPS-PWM module to the switching transistor drive circuit, and state synchronization and edge alignment are used during mode switching.

6. The method of claim 5, wherein the method further comprises: The CPS-PWM module further comprises a configuration unit for limiting the relationship between the carrier frequency and the closed-loop voltage balancing bandwidth, and the peak shifting of each sub-module is realized by the cooperation of the carrier phase shift and the closed-loop voltage balancing, and the equivalent switching frequency and thermal stress of the single module are reduced.

7. A computer apparatus comprising a memory, a processor, and a computer program stored on the memory, wherein the computer program, when executed by the processor, causes the processor to perform the method of any one of claims 1 to 6. The processor executes the computer program to realize the steps of the method of claim 1.

8. A computer readable storage medium having stored thereon computer programs / instructions, characterized in that, The computer program / instruction is executed by the processor to realize the steps of the method of claim 1.

9. A computer program product comprising computer programs / instructions, characterized in that, The computer program / instruction is executed by the processor to realize the steps of the method of claim 1.

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