Duty ratio calibration circuit and differential clock signal generation device

Abstract

According to the duty ratio calibration circuit and the differential clock signal generation device provided by the invention, the duty ratio of an external clock signal can be calibrated to 50% through a collaborative architecture of the common-mode feedback circuit module and the driving circuit module and by adopting a full-analog circuit. A common-mode feedback circuit module collects common-mode levels of differential signals output by a driving circuit in real time, the common-mode levels are directly compared with reference voltage vref to generate a pair of differential control voltages, and then the driving circuit module dynamically corrects input external differential clock signals according to the two signals. The whole process does not need time-consuming links such as ADC analog-to-digital conversion and digital logic operation, the delay problem of a traditional scheme is thoroughly avoided, microsecond-level and even nanosecond-level real-time calibration is finally achieved, the core requirements for rapid initialization when a high-speed system is started and coping with sudden duty ratio deviation in operation can be accurately matched, and the real-time calibration accuracy of the high-speed system is improved. And the overall response efficiency of the system is greatly improved.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and more specifically, to a duty cycle calibration circuit and a differential clock signal generation device. Background Technology

[0002] In recent years, the operating speed of modern integrated circuit devices has significantly improved. Many high-speed integrated circuits rely on a system clock signal with a duty cycle of approximately 50% (i.e., the ratio of pulse duration to pulse period) for synchronous operation. Taking Double Data Rate Synchronous Dynamic Random Access Memory (DDR-SDRAM) as an example, it needs to complete two data transmissions within a single clock cycle, corresponding to the rising and falling edges of the clock. This characteristic requires the clock signal to have a 50% duty cycle to maximize data transmission performance. If the duty cycle of the input clock signal deviates from 50% (greater or less), it will directly affect the operating performance of the integrated circuit device, causing it to be unable to stably complete the preset tasks.

[0003] In digital circuits, the clock pulse signal is the core of sequential logic, used to define the state update timing of logic units. Data changes typically occur when the clock edge arrives. In the field of semiconductor circuits, key modules such as phase-locked loops (PLLs) and clock data recovery circuits (CDRs) also require the output clock signal to have a 50% duty cycle to ensure that data sampling is completed on both the rising and falling edges of the clock. Therefore, correction circuits that convert non-50% duty cycle pulse clock signals to 50% duty cycle have become one of the key research directions.

[0004] Existing duty cycle calibration schemes that correct non-50% duty cycle pulse clock signals to 50% duty cycle require multiple scans, measurements, analog-to-digital conversion (ADC), and digital comparison processes to complete a single calibration. This process is time-consuming and cannot meet the requirements for rapid calibration during the startup or operation of high-speed systems. Summary of the Invention

[0005] The purpose of this application is to provide a duty cycle calibration circuit and a differential clock signal generation device to solve the problem that existing duty cycle calibration schemes are time-consuming and cannot meet the needs of fast calibration during high-speed system startup or operation.

[0006] This application provides a duty cycle calibration circuit, including a common-mode feedback circuit module and a driving circuit module. The output terminal of the driving circuit module is connected to the input terminal of the common-mode feedback circuit module to form a closed-loop feedback path. The first input terminal of the common-mode feedback circuit module receives the ckdcc_i_m signal, the second input terminal of the common-mode feedback circuit module receives the ckdcc_i_p signal, the first output terminal of the common-mode feedback circuit module outputs the vcip signal to the first input terminal of the drive circuit module, and the second output terminal of the common-mode feedback circuit module outputs the vcim signal to the second input terminal of the drive circuit module. The third input terminal of the driver circuit module receives the ck clock signal, the fourth input terminal of the driver circuit module receives the ckn clock signal, the first output terminal of the driver circuit module outputs the ckdcc_i_p signal, and the second output terminal of the driver circuit module outputs the ckdcc_i_m signal. The common-mode feedback circuit module is used to compare the common-mode levels of the ckdcc_i_m and ckdcc_i_p signals with the reference voltage vref to generate the vcip and vcim signals. The driver circuit module is used to adjust the ck clock signal according to the vcip signal to obtain the ckdcc_i_p signal; and to adjust the ckn clock signal according to the vcim signal to obtain the ckdcc_i_m signal.

[0007] In the above technical solution, through the collaborative architecture of the common-mode feedback circuit module and the drive circuit module, and implemented using a fully analog circuit, the duty cycle of the external clock signal can be calibrated to 50%. For differential clock signals, when the duty cycle is 50%, the common-mode level is at an ideal value (e.g., vref); when the duty cycle deviates, the common-mode level will change accordingly, thereby adjusting the duty cycle through feedback.

[0008] Specifically, the common-mode feedback circuit module acquires the common-mode level of the differential signals ckdcc_i_p and ckdcc_i_m output from the driver circuit in real time, directly compares them with the reference voltage vref to generate a pair of differential control voltages (vcip, vcim adjustment signals). The driver circuit module then dynamically corrects the input external differential clock signals (ck signal, ckn signal) based on these two signals. The entire process eliminates the need for time-consuming steps such as ADC analog-to-digital conversion and digital logic operations, completely avoiding the latency problem of traditional solutions. Ultimately, it achieves real-time calibration at the microsecond or even nanosecond level, accurately matching the core requirements of rapid initialization during high-speed system startup and handling sudden duty cycle deviations during operation, significantly improving the overall system response efficiency. The all-analog circuit used in this solution eliminates the reliance on high-precision ADC devices and complex digital processing units, simplifying the circuit topology, reducing the complexity of signal interaction between modules, and significantly reducing the chip area footprint. Furthermore, the closed-loop control mechanism formed by the common-mode feedback circuit module and the drive circuit module can continuously monitor the common-mode level changes of the output differential clock. Once a deviation occurs, it is immediately corrected by adjusting the signal to ensure that ckdcc_i_p and ckdcc_i_m always maintain a stable duty cycle. Compared with the open-loop scheme, it has a stronger ability to resist changes in process, voltage, and temperature (PVT), and significantly improves the robustness of the system under complex operating conditions. The reason is: The duty cycle of an open-loop scheme depends on fixed device parameters, which drift with PVT. The core of a closed-loop scheme, however, lies in real-time monitoring of the output and correction of deviations, regardless of whether these deviations are caused by changes in the input duty cycle or by drift in internal circuit parameters due to PVT variations.

[0009] In some alternative implementations, the common-mode feedback circuit module includes: an operational amplifier module; The operational amplifier module receives the ckdcc_i_m signal at its positive input terminal and the ckdcc_i_p signal at its negative input terminal, used to sample the common-mode level of the ckdcc_i_p and ckdcc_i_m signals; the operational amplifier module receives the bias voltage vb at its bias terminal, used to provide bias for the internal current source of the operational amplifier; the operational amplifier module receives the reference voltage vref at its reference voltage terminal, used to compare with the common-mode level; the operational amplifier module outputs the vcim signal at its positive output terminal and the vcip signal at its negative output terminal.

[0010] In the above technical solution, the operational amplifier module is a differential input, differential output operational amplifier, which forms negative feedback with the driving circuit module to stabilize the output common-mode voltage. The main working principle is to compare the common-mode voltage sampled by the PMOS differential pair with the reference voltage vref. If the common-mode level is higher than the reference value vref, the common-mode level is pulled down through common-mode feedback; conversely, when the output common-mode level is too low, the common-mode level is increased through common-mode feedback until it matches the reference voltage vref. This structure not only achieves high-gain amplification of the differential signal but also effectively suppresses common-mode level drift, improving the linearity and stability of the signal.

[0011] In some optional implementations, the operational amplifier module includes: a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; The sources of the third, fourth, and fifth PMOS transistors are connected to the power supply VDD. The gates of the third, fourth, and fifth PMOS transistors are connected and then connected to the drain of the fifth NMOS transistor. The drain of the fourth PMOS transistor, the source of the sixth, seventh, and eighth PMOS transistors are connected. The drain of the fifth PMOS transistor, the source of the ninth PMOS transistor, and the source of the tenth PMOS transistor are connected. The gate of the sixth PMOS transistor is connected to the reference voltage vref. The drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor. The gates of the seventh and ninth PMOS transistors are connected and serve as the positive input of the operational amplifier module. The eighth and tenth PMOS transistors... The gates of the S-channel transistors are connected and serve as the negative input of the operational amplifier module. The drains of the seventh PMOS transistor, the eighth PMOS transistor, and the seventh NMOS transistor are connected. The drains of the ninth PMOS transistor and the eighth NMOS transistor are connected and serve as the negative output of the operational amplifier module. The drains of the tenth PMOS transistor and the ninth NMOS transistor are connected and serve as the positive output of the operational amplifier module. The sources of the fifth, sixth, seventh, eighth, and ninth NMOS transistors are all grounded. The gate of the fifth NMOS transistor is connected to the bias voltage vb. The gates and drains of the sixth and seventh NMOS transistors are connected. The gates of the seventh, eighth, and ninth NMOS transistors are connected.

[0012] In the above technical solution, a common-mode feedback loop is used to dynamically adjust the common-mode level of the output signal, changing the duration of the high and low levels, thereby optimizing the clock signal duty cycle. First, during power-up, a bias circuit consisting of a resistor divider network and the first and second NMOS transistors generates a reference voltage vref, providing a stable common-mode reference point for the operational amplifier module. The operational amplifier module samples the common-mode component of the output signal in real time and compares it with the reference voltage vref. Through feedback adjustment, the operational amplifier module output generates control signals vcip and vcim, which drive the symmetrical CMOS switches of the first and second PMOS transistors in the subsequent stage, respectively. Based on the deviation of the output waveform, the conduction time of the first and second PMOS transistors is automatically changed, effectively correcting the time ratio between high and low levels of the clock signals ck and ckn. Finally, the signal is buffered and shaped by an inverter stage (INV1~INV4) to form standard clock signals ckdec_i_p and ckdec_i_m with opposite phases, whose duty cycle is closer to the ideal 50%.

[0013] The common-mode level detection refers to using the source potential changes of the seventh and eighth PMOS transistors to reflect the input common-mode level. Specifically: When the common-mode level of the input operational amplifier module is higher than the reference voltage vref, the source-gate voltages of the seventh and eighth PMOS transistors decrease, resulting in a decrease in their on-current. Since the tail current cannot flow completely, the source voltages of the seventh and eighth PMOS transistors rise. The source voltage of the sixth PMOS transistor also rises, leading to an increase in its on-current. Through the current mirror effect, the current in the branches of the eighth and ninth NMOS transistors also increases, causing an increase in the common-mode of the vcim and vcip signals output from the positive and negative output terminals of the operational amplifier module. This, in turn, reduces the current of the PMOS transistors in the driver circuit module, thus reducing the common-mode of the ckdcc_i_p and ckdcc_i_m signals output from the driver circuit module. This achieves a negative feedback regulation process, ultimately stabilizing the common-mode levels of the ckdcc_i_p and ckdcc_i_m signals at the reference voltage vref.

[0014] When the common-mode level of the input operational amplifier module is lower than the reference voltage vref, the source-gate voltages of the seventh and eighth PMOS transistors increase, leading to an increase in their on-current. Since the tail current cannot flow completely, this causes a drop in their source voltage. The source voltage of the sixth PMOS transistor also decreases, resulting in a decrease in its on-current. Through the current mirror effect, the current in the branches of the eighth and ninth NMOS transistors also decreases, leading to a reduction in the common-mode of the vcim and vcip signals output from the positive and negative output terminals of the operational amplifier module. This, in turn, increases the current of the PMOS transistors in the control circuit module, increasing the common-mode of the ckdcc_i_p and ckdcc_i_m signals output from the drive circuit module. This achieves a negative feedback regulation process, ultimately stabilizing the common-mode levels of the ckdcc_i_p and ckdcc_i_m signals at the reference voltage vref.

[0015] In some optional implementations, the common-mode feedback circuit module further includes: a reference power supply module; The output of the reference power supply module is connected to the reference voltage terminal of the operational amplifier module, and the input of the reference power supply module is the PWron signal. When the pwron signal is high, the reference power supply module outputs the reference voltage vref to the operational amplifier module; when the pwron signal is low, the reference power supply module shuts down and stops outputting the reference voltage vref.

[0016] In some alternative implementations, the reference power module includes: a first resistor, a second resistor, a first NMOS transistor, and a second NMOS transistor; The power supply VDD is connected to the drain of the first NMOS transistor through the first resistor. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor and outputs a reference voltage vref. The source of the second NMOS transistor is grounded through the second resistor. The gates of the first and second NMOS transistors are connected and input a pwron signal.

[0017] In the above technical solution, after power-on initialization, the pwron signal is high, the first NMOS transistor and the second NMOS transistor are turned on, the first resistor and the second resistor form a voltage divider resistor, and generate the reference voltage vref required by the operational amplifier module.

[0018] In some alternative implementations, the drive circuit module includes: a first PMOS transistor and a third NMOS transistor; The gate of the first PMOS transistor is input with a Vcip signal to control its conduction state. The source of the first PMOS transistor is connected to the power supply VDD, the drain of the first PMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor is input with a ck clock signal, and the source of the third NMOS transistor is grounded.

[0019] In the above technical solution, the vcip signal generated by the common-mode feedback circuit module controls the conduction of the first PMOS transistor of the drive circuit module, changing the high and low level duration of the input ck clock signal, thereby effectively adjusting the duty cycle of the output signal (ckdcc_i_p signal) waveform.

[0020] In some alternative implementations, the drive circuit module further includes: a first inverter and a second inverter; The drain of the first PMOS transistor is connected to the drain of the third NMOS transistor and is connected to the input of the first inverter. The output of the first inverter is connected to the input of the second inverter, and the output of the second inverter outputs the ckdcc_i_p signal.

[0021] In the above technical solution, the first inverter and the second inverter act as inverting buffers to further shape, delay and buffer the output signal pair, improve the driving capability and ensure that the output ckdcc_i_p signal has clear edges.

[0022] In some alternative implementations, the drive circuit module includes: a second PMOS transistor and a fourth NMOS transistor; The gate of the second PMOS transistor is input with the vcim signal to control its conduction state. The source of the second PMOS transistor is connected to the power supply VDD, and the drain of the second PMOS transistor is connected to the drain of the fourth NMOS transistor. The gate of the fourth NMOS transistor is input with the ckn clock signal, and the source of the fourth NMOS transistor is grounded.

[0023] In the above technical solution, the vcim signal generated by the common-mode feedback circuit module controls the conduction of the second PMOS transistor of the drive circuit module, changing the high and low level duration of the input ckn clock signal, thereby effectively adjusting the duty cycle of the output signal (ckdcc_i_m signal) waveform.

[0024] In some alternative implementations, the drive circuit module further includes: a third inverter and a fourth inverter; The drain of the second PMOS transistor is connected to the drain of the fourth NMOS transistor and then connected to the input of the third inverter. The output of the third inverter is connected to the input of the fourth inverter, and the output of the fourth inverter outputs the ckdcc_i_m signal.

[0025] In the above technical solution, the third and fourth inverters act as inverting buffers to further shape, delay, and buffer the output signal pairs, thereby improving the driving capability and ensuring that the output ckdcc_i_m signal has clear edges.

[0026] This application provides a differential clock signal generation device, comprising: an oscillator and a duty cycle calibration circuit as described in any of the above embodiments. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A functional block diagram of a duty cycle calibration circuit provided in an embodiment of this application; Figure 2 This application provides a common-mode feedback circuit module circuit structure diagram for embodiments of the present application. Figure 3 This is a circuit structure diagram of the driving circuit module provided in the embodiments of this application; Figure 4 The circuit structure diagram of the operational amplifier module provided in the embodiment of this application is shown. Detailed Implementation

[0029] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0030] Please refer to Figure 1 , Figure 1 A functional block diagram of a duty cycle calibration circuit provided in this application embodiment includes: a common-mode feedback circuit module and a drive circuit module; The first input terminal of the common-mode feedback circuit module receives the ckdcc_i_m signal, the second input terminal of the common-mode feedback circuit module receives the ckdcc_i_p signal, the first output terminal of the common-mode feedback circuit module outputs the vcip signal to the first input terminal of the drive circuit module, and the second output terminal of the common-mode feedback circuit module outputs the vcim signal to the second input terminal of the drive circuit module. The third input terminal of the driver circuit module receives the ck clock signal, the fourth input terminal of the driver circuit module receives the ckn clock signal, the first output terminal of the driver circuit module outputs the ckdcc_i_p signal, and the second output terminal of the driver circuit module outputs the ckdcc_i_m signal. The common-mode feedback circuit module is used to compare the common-mode levels of the ckdcc_i_m and ckdcc_i_p signals with the reference voltage vref to generate the vcip and vcim signals. Specifically, the implementation process of the common-mode feedback circuit module includes: using two PMOS transistors to form a differential pair for detecting input common-mode changes, and using the reference voltage vref as a reference, working in conjunction with the tail current source of the differential pair to transmit the common-mode error information to the output stage through the current mirror circuit, and finally amplifying the common-mode error and converting it into control voltage signals (vcip signal and vcim signal).

[0031] The driver circuit module is used to adjust the ck clock signal according to the vcip signal to obtain the ckdcc_i_p signal; and to adjust the ckn clock signal according to the vcim signal to obtain the ckdcc_i_m signal.

[0032] Specifically, the vcip and vcim signals control the gate voltage of the PMOS transistor, changing its conduction state, thereby adjusting the rise and fall times of the output waveform and achieving duty cycle calibration.

[0033] In this embodiment, through a collaborative architecture of the common-mode feedback circuit module and the drive circuit module, and implemented using a fully analog circuit, the duty cycle of the external clock signal can be calibrated to 50%. The common-mode feedback circuit module acquires the common-mode level of the differential signals ckdcc_i_p and ckdcc_i_m output from the drive circuit in real time, directly comparing it with the reference voltage vref to generate a pair of differential control voltages (vcip, vcim adjustment signals). The drive circuit module then dynamically corrects the input external differential clock signals (ck signal, ckn signal) based on these two signals. The entire process eliminates the need for time-consuming steps such as ADC analog-to-digital conversion and digital logic operations, completely avoiding the latency problem of traditional solutions. Ultimately, it achieves real-time calibration at the microsecond or even nanosecond level, accurately matching the core requirements of rapid initialization during high-speed system startup and handling sudden duty cycle deviations during operation, significantly improving the overall system response efficiency. The fully analog circuit used in this solution eliminates the reliance on high-precision ADC devices and complex digital processing units, simplifying the circuit topology, reducing the complexity of signal interaction between modules, and significantly reducing the chip area footprint. Furthermore, the closed-loop control mechanism formed by the common-mode feedback circuit module and the drive circuit module can continuously monitor the common-mode level changes of the output differential clock. Once a deviation occurs, it will be corrected immediately by adjusting the signal to ensure that ckdcc_i_p and ckdcc_i_m always maintain a stable duty cycle. Compared with the open-loop scheme, it has a stronger ability to resist changes in process, voltage, and temperature (PVT) and greatly improves the robustness of the system under complex operating conditions.

[0034] Please refer to Figure 2 , Figure 2 The circuit structure diagram of the common-mode feedback circuit module provided in the embodiments of this application is shown.

[0035] In some alternative implementations, the common-mode feedback circuit module includes: an operational amplifier module; The op-amp module receives the ckdcc_i_m signal at its positive input terminal, the ckdcc_i_p signal at its negative input terminal, the bias voltage vb at its bias terminal, the reference voltage vref at its reference voltage terminal, the vcim signal at its positive output terminal, and the vcip signal at its negative output terminal.

[0036] In this embodiment, the operational amplifier module is a differential input, differential output operational amplifier that forms negative feedback with the driving circuit module to stabilize the output common-mode voltage. The main working principle is to compare the common-mode voltage sampled by the PMOS differential pair with the reference voltage vref. If the common-mode level is higher than the reference value vref, the common-mode level is pulled down through common-mode feedback; conversely, when the output common-mode level is too low, the common-mode level is increased through common-mode feedback until it matches the reference voltage vref. This structure not only achieves high-gain amplification of the differential signal but also effectively suppresses common-mode level drift, improving the linearity and stability of the signal.

[0037] Please refer to Figure 4 , Figure 4 The circuit structure diagram of the operational amplifier module provided in the embodiment of this application is shown.

[0038] In some optional implementations, the operational amplifier module includes: a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, and a ninth NMOS transistor NM9; The sources of the third PMOS transistor PM3, the fourth PMOS transistor PM4, and the fifth PMOS transistor PM5 are connected to the power supply VDD. The gates of the third PMOS transistor PM3, the fourth PMOS transistor PM4, and the fifth PMOS transistor PM5 are connected and then connected to the drain of the fifth NMOS transistor NM5. The drain of the fourth PMOS transistor PM4, the source of the sixth PMOS transistor PM6, the source of the seventh PMOS transistor PM7, and the source of the eighth PMOS transistor PM8 are connected. The drain of the fifth PMOS transistor PM5, the source of the ninth PMOS transistor PM9, and the source of the tenth PMOS transistor PM10 are connected. The gate of the sixth PMOS transistor PM6 is connected to the reference voltage vref. The drain of the sixth PMOS transistor PM6 is connected to the drain of the sixth NMOS transistor NM6. The gates of the seventh PMOS transistor PM7 and the ninth PMOS transistor PM9 are connected and serve as the positive input terminals of the operational amplifier module. The eighth PMOS transistor PM8 and the tenth PMOS transistor PM10 are connected. The gate of transistor PM10 is connected and serves as the negative input terminal of the operational amplifier module. The drains of the seventh PMOS transistor PM7, the eighth PMOS transistor PM8, and the seventh NMOS transistor NM7 are connected. The drains of the ninth PMOS transistor PM9 and the eighth NMOS transistor NM8 are connected and serve as the negative output terminal of the operational amplifier module. The drain of the tenth PMOS transistor PM10 and the drain of the ninth NMOS transistor NM9 are connected and serve as the positive output terminal of the operational amplifier module. The sources of the fifth NMOS transistor NM5, the sixth NMOS transistor NM6, the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, and the ninth NMOS transistor NM9 are all grounded. The gate of the fifth NMOS transistor NM5 is connected to the bias voltage vb. The gates and drains of the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 are connected. The gates of the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, and the ninth NMOS transistor NM9 are connected.

[0039] In this embodiment, a common-mode feedback loop is used to dynamically adjust the common-mode level of the output signal, changing the duration of high and low levels, thereby optimizing the clock signal duty cycle. First, during power-up, a bias circuit composed of a resistor divider network and the first NMOS transistor NM1 and the second NMOS transistor NM2 generates a reference voltage vref, providing a stable common-mode reference point for the operational amplifier module. The operational amplifier module samples the common-mode component of the output signal in real time and compares it with the reference voltage vref. Through feedback adjustment, the operational amplifier module output generates control signals vcip and vcim, which drive the symmetrical CMOS switches of the subsequent stage, corresponding to the first PMOS transistor PM1 and the second PMOS transistor PM2. Based on the deviation of the output waveform, the conduction time of the first PMOS transistor PM1 and the second PMOS transistor PM2 is automatically changed, effectively correcting the time ratio between high and low levels of the clock signals ck and ckn. Finally, the signal is buffered and shaped by the inverter stage (INV1~INV4) to form standard clock signals ckdec_i_p and ckdec_i_m with opposite phases, and their duty cycles are closer to the ideal 50%.

[0040] The common-mode level detection refers to using the source potential changes of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 to reflect the input common-mode level. Specifically: When the common-mode level of the input operational amplifier module is higher than the reference voltage vref, the source-gate voltage of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 decreases, resulting in a decrease in the conduction current of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8. Since the tail current cannot flow completely, the source voltage of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 will rise. The source voltage of the sixth PMOS transistor PM6 also increases, leading to an increase in the on-state current of PM6. Through the current mirror effect, the current in the branches of the eighth NMOS transistor NM8 and the ninth NMOS transistor NM9 also increases, resulting in an increase in the common-mode voltage of the vcim and vcip signals output from the positive and negative output terminals of the operational amplifier module. This, in turn, reduces the current of the PMOS transistors in the drive circuit module, thereby reducing the common-mode voltage of the ckdcc_i_p and ckdcc_i_m signals output from the drive circuit module. This achieves the negative feedback regulation process, ultimately stabilizing the common-mode voltage of the ckdcc_i_p and ckdcc_i_m signals at the reference voltage vref.

[0041] When the common-mode level of the input operational amplifier module is lower than the reference voltage vref, the source-gate voltage of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 increases, which leads to an increase in the conduction current of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8. Since the tail current cannot flow completely, the source voltage of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 will decrease. The source voltage of the sixth PMOS transistor PM6 also decreases, resulting in a decrease in the conduction current of the sixth PMOS transistor PM6. Through the current mirror effect, the current in the branches of the eighth NMOS transistor NM8 and the ninth NMOS transistor NM9 also decreases, causing the common-mode voltage of the vcim and vcip signals output from the positive and negative output terminals of the operational amplifier module to decrease. This, in turn, increases the current of the PMOS transistors in the control circuit module, thereby increasing the common-mode voltage of the ckdcc_i_p and ckdcc_i_m signals output from the drive circuit module. This achieves the negative feedback regulation process, ultimately stabilizing the common-mode voltage of the ckdcc_i_p and ckdcc_i_m signals at the reference voltage vref.

[0042] In some optional implementations, the common-mode feedback circuit module further includes: a reference power supply module; The output of the reference power supply module is connected to the reference voltage terminal of the operational amplifier module, and the input of the reference power supply module is the PWron signal. The pwron signal serves as a power-on reset or enable signal. When the pwron signal is high, the reference power supply module outputs a reference voltage vref to the operational amplifier module; when the pwron signal is low, the reference power supply module does not output a signal to the operational amplifier module.

[0043] In some alternative implementations, the reference power supply module includes: a first resistor R1, a second resistor R2, a first NMOS transistor NM1, and a second NMOS transistor NM2; The power supply VDD is connected to the drain of the first NMOS transistor NM1 through the first resistor R1. The source of the first NMOS transistor NM1 is connected to the drain of the second NMOS transistor NM2 and outputs a reference voltage vref. The source of the second NMOS transistor NM2 is grounded through the second resistor R2. The gate of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2 are connected and input a pwron signal.

[0044] In this embodiment of the application, after power-on initialization, the pwron signal is high, the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned on, the first resistor R1 and the second resistor R2 form a voltage divider resistor, and generate the reference voltage vref required by the operational amplifier module.

[0045] Please refer to Figure 3 , Figure 3The circuit structure diagram of the driving circuit module provided in the embodiment of this application is shown.

[0046] In some alternative implementations, the drive circuit module includes: a first PMOS transistor PM1 and a third NMOS transistor NM3; The gate of the first PMOS transistor PM1 receives the Vcip signal, the source of the first PMOS transistor PM1 is connected to the power supply VDD, the drain of the first PMOS transistor PM1 is connected to the drain of the third NMOS transistor NM3, the gate of the third NMOS transistor NM3 receives the ck clock signal, and the source of the third NMOS transistor NM3 is grounded.

[0047] In this embodiment, the vcip signal generated by the common-mode feedback circuit module controls the conduction of the first PMOS transistor PM1 of the drive circuit module, changing the duration of the high and low levels of the input ck clock signal, thereby effectively adjusting the duty cycle of the output signal (ckdcc_i_p signal) waveform.

[0048] In some alternative implementations, the drive circuit module further includes: a first inverter and a second inverter; The drain of the first PMOS transistor PM1 is connected to the drain of the third NMOS transistor NM3 and is connected to the input of the first inverter. The output of the first inverter is connected to the input of the second inverter, and the output of the second inverter outputs the ckdcc_i_p signal.

[0049] In this embodiment, the first inverter and the second inverter serve as inverting buffers to further shape, delay, and buffer the output signal pair, thereby improving the driving capability and ensuring that the output ckdcc_i_p signal has clear edges.

[0050] In some alternative implementations, the drive circuit module includes: a second PMOS transistor PM2 and a fourth NMOS transistor NM4; The gate of the second PMOS transistor PM2 receives the vcim signal, the source of the second PMOS transistor PM2 is connected to the power supply VDD, the drain of the second PMOS transistor PM2 is connected to the drain of the fourth NMOS transistor NM4, the gate of the fourth NMOS transistor NM4 receives the ckn clock signal, and the source of the fourth NMOS transistor NM4 is grounded.

[0051] In this embodiment, the vcim signal generated by the common-mode feedback circuit module controls the conduction of the second PMOS transistor PM2 of the drive circuit module, changing the duration of the high and low levels of the input ckn clock signal, thereby effectively adjusting the duty cycle of the output signal (ckdcc_i_m signal) waveform.

[0052] In some alternative implementations, the drive circuit module further includes: a third inverter and a fourth inverter; The drain of the second PMOS transistor PM2 is connected to the drain of the fourth NMOS transistor NM4 and is connected to the input of the third inverter. The output of the third inverter is connected to the input of the fourth inverter, and the output of the fourth inverter outputs the ckdcc_i_m signal.

[0053] In this embodiment, the third and fourth inverters act as inverting buffers to further shape, delay, and buffer the output signal pairs, thereby improving the driving capability and ensuring that the output ckdcc_i_m signal has clear edges.

[0054] This application provides a differential clock signal generation device, comprising: an oscillator and a duty cycle calibration circuit as described in any of the above embodiments.

[0055] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0056] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0057] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0058] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0059] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A duty cycle calibration circuit, characterized in that, include: A common-mode feedback circuit module and a drive circuit module are provided, wherein the output terminal of the drive circuit module is connected to the input terminal of the common-mode feedback circuit module to form a closed-loop feedback path; The common-mode feedback circuit module receives the ckdcc_i_m signal at its first input terminal and the ckdcc_i_p signal at its second input terminal. The common-mode feedback circuit module outputs the vcip signal to the first input terminal of the drive circuit module at its first output terminal and the vcim signal to the second input terminal of the drive circuit module at its second output terminal. The third input terminal of the driving circuit module receives the ck clock signal, the fourth input terminal of the driving circuit module receives the ckn clock signal, the first output terminal of the driving circuit module outputs the ckdcc_i_p signal, and the second output terminal of the driving circuit module outputs the ckdcc_i_m signal. The common-mode feedback circuit module is used to compare the common-mode levels of the ckdcc_i_m and ckdcc_i_p signals with the reference voltage vref to generate vcip and vcim signals. The driving circuit module is used to adjust the ck clock signal according to the vcip signal to obtain the ckdcc_i_p signal; and to adjust the ckn clock signal according to the vcim signal to obtain the ckdcc_i_m signal.

2. The circuit as described in claim 1, characterized in that, The common-mode feedback circuit module includes: an operational amplifier module; The operational amplifier module receives the ckdcc_i_m signal at its positive input terminal and the ckdcc_i_p signal at its negative input terminal, used to sample the common-mode level of the ckdcc_i_p and ckdcc_i_m signals; the operational amplifier module receives a bias voltage vb at its bias terminal, used to provide bias for the internal current source of the operational amplifier; the operational amplifier module receives a reference voltage vref at its reference voltage terminal, used to compare with the common-mode level; the operational amplifier module outputs the vcim signal at its positive output terminal and the vcip signal at its negative output terminal.

3. The circuit as described in claim 2, characterized in that, The operational amplifier module includes: a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; The sources of the third, fourth, and fifth PMOS transistors are connected to the power supply VDD. The gates of the third, fourth, and fifth PMOS transistors are connected and then connected to the drain of the fifth NMOS transistor. The drain of the fourth PMOS transistor, the source of the sixth, seventh, and eighth PMOS transistors are connected. The drain of the fifth PMOS transistor, the source of the ninth PMOS transistor, and the source of the tenth PMOS transistor are connected. The gate of the sixth PMOS transistor is connected to the reference voltage vref. The drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor. The gates of the seventh and ninth PMOS transistors are connected and serve as the positive input terminal of the operational amplifier module. The eighth PMOS transistor and the tenth PMOS transistor... The gates of the OS transistors are connected and serve as the negative input terminal of the operational amplifier module. The drains of the seventh PMOS transistor, the eighth PMOS transistor, and the seventh NMOS transistor are connected. The drains of the ninth PMOS transistor and the eighth NMOS transistor are connected and serve as the negative output terminal of the operational amplifier module. The drains of the tenth PMOS transistor and the ninth NMOS transistor are connected and serve as the positive output terminal of the operational amplifier module. The sources of the fifth, sixth, seventh, eighth, and ninth NMOS transistors are all grounded. The gate of the fifth NMOS transistor is connected to the bias voltage vb. The gates and drains of the sixth and seventh NMOS transistors are connected. The gates of the seventh, eighth, and ninth NMOS transistors are connected.

4. The circuit as described in claim 2, characterized in that, The common-mode feedback circuit module further includes: a reference power supply module; The output terminal of the reference power supply module is connected to the reference voltage terminal of the operational amplifier module, and the input terminal of the reference power supply module receives the pwron signal. When the pwron signal is high, the reference power supply module outputs a reference voltage vref to the operational amplifier module; when the pwron signal is low, the reference power supply module is turned off and stops outputting the reference voltage vref.

5. The circuit as described in claim 4, characterized in that, The reference power supply module includes: a first resistor, a second resistor, a first NMOS transistor, and a second NMOS transistor; The power supply VDD is connected to the drain of the first NMOS transistor through the first resistor. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor and outputs a reference voltage vref. The source of the second NMOS transistor is grounded through the second resistor. The gates of the first NMOS transistor and the gates of the second NMOS transistor are connected and input a pwron signal.

6. The circuit as described in claim 1, characterized in that, The driving circuit module includes: a first PMOS transistor and a third NMOS transistor; The gate of the first PMOS transistor is input with a Vcip signal to control its conduction state; the source of the first PMOS transistor is connected to the power supply VDD; the drain of the first PMOS transistor is connected to the drain of the third NMOS transistor; the gate of the third NMOS transistor is input with a ck clock signal; and the source of the third NMOS transistor is grounded.

7. The circuit as described in claim 6, characterized in that, The driving circuit module further includes: a first inverter and a second inverter; The drain of the first PMOS transistor is connected to the drain of the third NMOS transistor and is connected to the input terminal of the first inverter. The output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter outputs the ckdcc_i_p signal.

8. The circuit as described in claim 1, characterized in that, The driving circuit module includes: a second PMOS transistor and a fourth NMOS transistor; The gate of the second PMOS transistor is input with a vcim signal to control the conduction state of the second PMOS transistor; the source of the second PMOS transistor is connected to the power supply VDD, the drain of the second PMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is input with a ckn clock signal, and the source of the fourth NMOS transistor is grounded.

9. The circuit as described in claim 8, characterized in that, The driving circuit module further includes: a third inverter and a fourth inverter; The drain of the second PMOS transistor is connected to the drain of the fourth NMOS transistor and is connected to the input terminal of the third inverter. The output terminal of the third inverter is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter outputs the ckdcc_i_m signal.

10. A differential clock signal generating device, characterized in that, include: An oscillator and a duty cycle calibration circuit as described in any one of claims 1-9.

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