Core board

Abstract

The invention provides a core board, one side of the core board is provided with a first layer of welding spot pins to a fifth layer of welding spot pins composed of a plurality of welding spot pins, and the first layer of welding spot pins to the fifth layer of welding spot pins are sequentially arranged in the direction close to the center of the core board; the first layer of welding spot pins to the fifth layer of welding spot pins are distributed in a square shape, a square formed by the first layer of welding spot pins to the third layer of welding spot pins is provided with an opening at the same vertex angle, and the fourth layer of welding spot pins and the fifth layer of welding spot pins are closed squares. By adopting the scheme, multi-layer pin arrangement can be realized to accommodate sufficient pads, the transmission integrity of high-frequency signals is guaranteed, and meanwhile, the damage risk of the pads during board splitting and turnover is reduced to improve the mechanical reliability.

Description

Technical Field

[0001] This invention relates to the field of embedded technology, and more specifically, to a core board. Background Technology

[0002] In core board application scenarios, as electronic system functions become increasingly complex, higher requirements are placed on the core board's signal transmission speed, wiring capacity, and board stability.

[0003] In existing technologies, the pin layout of core boards generally adopts a single-sided centralized layout, that is, all pins used for signal transmission and power supply are concentrated on one side of the core board. In the early days, this layout method was used to some extent in core board products with simple functions and low pin requirements because the design logic was simple and only a matching interface needed to be designed on the corresponding side of the baseboard to complete the connection between the core board and the baseboard. It can also reduce the difficulty of initial wiring.

[0004] However, research has found that the single-sided centralized arrangement method used in existing technologies has significant drawbacks: First, the space for single-sided arrangement is limited, making it difficult to accommodate a sufficient number of pins (such as hundreds of pins required by complex systems), resulting in the core board being unable to provide enough signal and power paths, thus restricting functional expansion; Second, when transmitting high-frequency signals, the pins on a single side have concentrated signal paths with large differences in length, which easily generates severe parasitic inductance and capacitance, causing signal reflection, attenuation, and crosstalk, and failing to guarantee the integrity of high-frequency signals; Third, single-sided pins concentrate the force on that side when the core board is connected to the baseboard, which can easily lead to solder joint detachment and poor contact after long-term use. In addition, the space occupied by single-sided pins will squeeze the layout of other devices, making it impossible to achieve close-range connection between devices and pins, further affecting power integrity and wiring flexibility. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a core board capable of multi-layer pin arrangement to accommodate sufficient pads, ensuring the integrity of high-frequency signal transmission, while reducing the risk of pad damage during board separation and turnover to improve mechanical reliability.

[0006] This application embodiment provides a core board, the core board comprising: The core board has a first layer of solder pins to a fifth layer of solder pins consisting of multiple solder pins on one side. The first layer of solder pins to the fifth layer of solder pins are arranged sequentially along the direction close to the center of the core board. The solder joint pins from the first layer to the fifth layer are arranged in a square. The square formed by the solder joint pins from the first layer to the third layer has an opening at the same vertex. The solder joint pins of the fourth layer and the fifth layer are closed squares.

[0007] Optionally, each solder joint pin in the first layer is a low-speed pin used to transmit low-speed signals, and each solder joint pin in the second to fifth layers is a high-speed pin used to transmit high-speed signals.

[0008] Optionally, each solder pin in the first layer transmits a low-speed signal below 2.5GHz, and each solder pin in the second to fifth layers transmits a high-speed signal below 10GHz.

[0009] Optionally, in a counterclockwise direction, the edge of the core board includes a first side, a second side, a third side, and a fourth side, and the square formed by the first layer solder pins to the third layer solder pins has an opening at the apex formed by the first side and the fourth side; The first layer of solder joints includes 149 solder joints arranged in a continuous sequence, the second layer of solder joints includes 129 solder joints arranged in a continuous sequence, the third layer of solder joints includes 121 solder joints arranged in a continuous sequence, the fourth layer of solder joints includes 116 solder joints arranged in a continuous sequence, and the fifth layer of solder joints includes 104 solder joints arranged in a continuous sequence. From the first layer of solder joint pins to the fifth layer of solder joint pins, the spacing between any two adjacent pins is equal in the counterclockwise direction; From the first layer of solder joint pins to the fifth layer of solder joint pins, adjacent layers of solder joint pins are arranged at equal intervals, and adjacent layers of solder joint pins are arranged in a staggered manner.

[0010] Optionally, the core board has a size of 50mm × 50mm; The center-to-center spacing between adjacent pins on the same layer, from the first layer to the fifth layer, is 0.8mm-1.5mm. From the first layer of solder joints to the fifth layer of solder joints, the center distance between two adjacent layers of solder joints that are staggered and projected onto the corresponding side is 0.4mm-0.75mm. The center distance between the centers of two adjacent layers of solder joints that are staggered and located on the same side is 1.5mm-2.5mm in the direction perpendicular to that side.

[0011] Optionally, each solder joint pin in the first to fifth layer is circular, with a diameter of 0.5mm-1.2mm.

[0012] Optionally, the distance between the center of each solder joint pin in the first layer and the edge of the core board it is closest to is 0.8mm-1.5mm.

[0013] Optionally, the core board further includes a device area located within the region formed by the solder pins of the fifth layer, wherein active devices and / or passive devices are disposed within the device area.

[0014] Optionally, the distance from the center of the pin on the fifth layer solder joint to the edge of the device area is 1.5mm-2.5mm, and the size of the device area is less than or equal to 30mm×30mm.

[0015] Optionally, the fifth layer solder joint pins may include extension pins.

[0016] The technical solution provided in this application includes, but is not limited to, the following beneficial effects: One side of the core board features a first to fifth layer of solder joint pins, arranged sequentially along the direction closest to the center of the core board. This arrangement fully utilizes the planar space of the core board, enabling a multi-layered solder joint pin layout on one side. It accommodates a sufficient number of solder joint pins within a limited board area, meeting the signal interaction requirements between the complex internal circuitry and external circuits. This avoids the problem of insufficient pin count and inability to cover complex functions due to space limitations in a single or limited layer. Simultaneously, the layered division from the outside in naturally creates a physical signal isolation structure. The transmission paths of outer and inner layer pins are independent, reducing mutual interference between different types of signals during transmission and providing a stable transmission environment for all types of signals, ensuring the overall signal transmission stability of the core board. Furthermore, this arrangement can adapt to the multi-layer design requirements of the core board, further expanding its wiring capacity and providing flexible support for the layout of complex circuits.

[0017] The solder pins from the first to the fifth layer are arranged in a square pattern. The squares formed by the first to third layers of solder pins have an opening at the same vertices. The fourth and fifth layers of solder pins are closed squares. This ensures that the spacing of the solder pins in each layer is uniform and consistent. This facilitates the processing and positioning of the solder pins during the core board production process, reduces dimensional errors during manufacturing, and optimizes the soldering effect. It allows the solder paste to evenly cover the pins during soldering, avoiding solder paste bridging and short circuits between adjacent pins due to uneven spacing, effectively improving the soldering yield. Secondly, the structure with an opening at the same vertices can specifically avoid the risk of mechanical damage during the core board separation process: stress concentration is prone to occur at the board edges during separation. The opening area avoids the direct force connection between the outer layer pins and the board edge, preventing shearing and compressive stresses from acting directly on the outer layer pins during separation, reducing the probability of pin breakage and detachment, and improving the mechanical reliability of the core board. The closed square design maximizes the use of space in the central area of ​​the core board, allowing the inner layer solder pins to be closer to the areas where devices may be placed on the core board. This shortens the connection path between pins and devices, reduces signal or power transmission losses, improves transmission efficiency, avoids wasting space in the central area, and optimizes the overall layout density of the core board.

[0018] In summary, the five-layer square arrangement from the outside in fully utilizes the board's load-bearing capacity, ensures a reasonable number and layout of solder joints and pins, and meets the needs of complex circuits. Layer isolation and regular spacing reduce signal interference, providing a stable environment for various signal transmissions. The outer layer opening design precisely addresses pin damage issues during board separation. The overall structure effectively adapts to the application requirements of the core board in complex electronic systems, providing strong support for the core board's functional expansion and performance stability.

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This diagram illustrates the structure of a core board provided in an embodiment of the present invention. Figure 2 A schematic diagram of the structure of the second type of core board provided in an embodiment of the present invention is shown; Figure 3A schematic diagram of the structure of the third type of core board provided in an embodiment of the present invention is shown; Figure 4 A schematic diagram of the structure of the fourth type of core board provided in an embodiment of the present invention is shown; Figure 5 A schematic diagram of the structure of the fifth type of core board provided in an embodiment of the present invention is shown; Figure 6 A simulation diagram of solder joint pin signal transmission provided by an embodiment of the present invention is shown; Figure 7 A simulation diagram of the second type of solder joint pin signal transmission provided in an embodiment of the present invention is shown; Figure 8 A schematic diagram of the sixth type of core board provided in an embodiment of the present invention is shown. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0023] It should be noted in advance that all pins involved in this application are standard pins. For specific functions, definitions and explanations, please refer to the functions, definitions and explanations of standard pins in the prior art. They will not be described in detail here.

[0024] Example To facilitate understanding of this application, the following is combined with... Figure 1 The schematic diagram of a core board provided in the embodiment of the present invention shown herein will be used to describe the embodiments of this application in detail.

[0025] See Figure 1 As shown, Figure 1 The diagram shows a schematic of a core board provided in an embodiment of the present invention. The core board has a first layer of solder pins to a fifth layer of solder pins, which are composed of a plurality of solder pins. The first layer of solder pins to the fifth layer of solder pins are arranged sequentially in a direction close to the center of the core board.

[0026] Specifically, in this arrangement, the first layer of solder pads corresponds to the outermost pad, and the fifth layer of solder pads corresponds to the innermost pad, with the overall arrangement distributed layer by layer "away from the board edge and close to the center." This layered design from the outside in can, on the one hand, complement the core board's characteristics of "no board thickness limitation and the ability to increase the number of layers," providing space for complex circuit routing; on the other hand, it can achieve signal classification and transmission, and subsequent signal integrity can be satisfied by functional division of outer and inner layer pins (such as outer layers transmitting low-speed signals and inner layers transmitting high-speed signals).

[0027] The solder joint pins from the first layer to the fifth layer are arranged in a square. The square formed by the solder joint pins from the first layer to the third layer has an opening at the same vertex. The solder joint pins of the fourth layer and the fifth layer are closed squares.

[0028] Specifically, the overall distribution of solder pads on each layer is square, with the outer square having an opening and the inner square being closed. The core purpose of the outer open design is to ensure compatibility with older designs; while the inner closed square design is because the inner layer is closer to the center of the core board, where space is relatively compact, and the closed shape maximizes the use of the limited area, increasing the pad density to meet the needs of more high-speed signals.

[0029] In one optional implementation, each solder pin in the first layer is a low-speed pin for transmitting low-speed signals, and each solder pin in the second to fifth layers is a high-speed pin for transmitting high-speed signals.

[0030] Specifically, this optional solution clearly defines the functions of the solder joint pins at different levels: the outer layer (first layer) handles low-speed signal transmission, while the inner layers (second to fifth layers) handle high-speed signal transmission. The underlying logic of this division of labor is that the inner layer solder joint pins adopt a planar array layout, which can significantly shorten the signal transmission path, reduce parasitic inductance and capacitance, reduce signal delay, and better adapt to the stringent requirements of high-speed signal transmission environments; while the outer layer solder joint pins are less sensitive to the signal transmission path length, and using them to transmit low-speed signals can avoid interference between low-speed and high-speed signals in the same area. At the same time, the outer layer pins are also easier to interface with low-speed interfaces (such as ordinary I / O interfaces) on the baseboard.

[0031] In one alternative implementation, each solder pin in the first layer transmits a low-speed signal below 2.5 GHz, and each solder pin in the second to fifth layers transmits a high-speed signal below 10 GHz.

[0032] Specifically, this optional solution further quantifies the signal transmission frequency range of different pin levels: the upper limit for low-speed signals is 2.5GHz, and the upper limit for high-speed signals is 10GHz. The 10GHz frequency limit for high-speed signals was determined based on simulation verification results of the relevant pad layout—under this layout, the signal reflection, crosstalk, attenuation, and other indicators can be controlled within acceptable ranges, ensuring stable high-speed data transmission; while low-speed signals below 2.5GHz have lower requirements for transmission integrity and do not need to rely on the optimized layout of the inner layer. The transmission path of the outer layer pins can fully meet their needs, while also avoiding low-speed signals occupying the high-speed signal resources of the inner layer.

[0033] In an optional implementation, see Figure 2 As shown, Figure 2 A schematic diagram of the structure of a second type of core board provided in an embodiment of the present invention is shown, wherein, along the counterclockwise direction, the edge of the core board includes a first side, a second side, a third side, and a fourth side, and the square formed by the first layer solder pins to the third layer solder pins has an opening at the apex formed by the first side and the fourth side.

[0034] Specifically, this optional solution first defines the four edges of the core board (from the first to the fourth edge) by dividing it counterclockwise, and then precisely locates the position of the square opening of the outer layer solder pad pins (from the first to the third layer) at the apex formed by the first and fourth edges. This apex is chosen because it is usually the main stress point during core board separation, and also a common positioning or fixing area when docking with the baseboard. The opening design effectively prevents the solder pads from breaking due to mechanical stress during separation, and also provides space for the baseboard's positioning posts, fixing screws, and other structures, preventing physical interference with the outer layer solder pads.

[0035] The first layer of solder joints includes 149 solder joints arranged in a continuous sequence, the second layer of solder joints includes 129 solder joints arranged in a continuous sequence, the third layer of solder joints includes 121 solder joints arranged in a continuous sequence, the fourth layer of solder joints includes 116 solder joints arranged in a continuous sequence, and the fifth layer of solder joints includes 104 solder joints arranged in a continuous sequence.

[0036] Specifically, the document provides the precise number of solder pads for each layer. Calculations show that the total number of pins across the five layers is 149 + 129 + 121 + 116 + 104 = 619. This total perfectly matches the 619 LGA pads specified in the UP5 core board design. The number of pins gradually decreases from the outermost to the innermost layer because the inner layers (fourth and fifth layers) are closer to the center of the core board, and their planar area is smaller than that of the outer layers (first and second layers). By reasonably reducing the number of pins, the pin spacing can be kept within the limited space to meet design requirements, avoiding poor soldering or signal interference caused by space congestion. At the same time, the total of 619 pins can fully cover the requirements of complex circuit systems for extracting various signals such as power signals, high-speed differential signals, and control signals.

[0037] From the first layer solder joint pins to the fifth layer solder joint pins, the spacing between any two adjacent pins is equal in the counterclockwise direction.

[0038] Specifically, the description emphasizes the uniformity of the counterclockwise spacing of the solder joint pins within each layer, typically ranging from 0.8mm to 1.5mm. This uniform spacing design offers several advantages: from a soldering perspective, uniform spacing ensures even solder paste application during reflow soldering, preventing short circuits caused by insufficient solder paste due to too small a spacing, or cold solder joints due to insufficient solder paste due to too large a spacing; from a signal transmission perspective, uniform spacing ensures consistent transmission path lengths for signals of the same type within the same layer (such as a group of low-speed signals), reducing signal delay differences and avoiding signal synchronization problems caused by uneven delays, which is especially crucial for low-speed control signals requiring parallel transmission.

[0039] From the first layer of solder joint pins to the fifth layer of solder joint pins, adjacent layers of solder joint pins are arranged at equal intervals, and adjacent layers of solder joint pins are arranged in a staggered manner.

[0040] Specifically, this content clarifies two main arrangement characteristics of adjacent layer solder pads: equal spacing between layers and staggered arrangement between layers. The equal spacing between layers typically ranges from 1.5mm to 2.5mm in the vertical direction. This spacing provides sufficient space for signal fan-out of inner layer pins, avoiding the need for complex pad-to-pad via processes (increasing manufacturing costs) due to excessively small spacing. It also accommodates the layout of grounding vias, providing a good grounding reference for high-speed signals. The staggered arrangement between layers typically has a horizontal spacing of 0.4mm to 0.75mm. This arrangement avoids vertical overlap between adjacent layer pads, reducing interlayer parasitic capacitance and lowering the risk of crosstalk during high-speed signal transmission between layers. It also allows for further increases in pad density within a limited core board area.

[0041] In an optional implementation, see Figure 3 As shown, Figure 3A schematic diagram of the structure of the third type of core board provided in the embodiment of the present invention is shown, wherein the core board has a size of 50mm × 50mm.

[0042] Specifically, the optional solution specifies that the physical size of the core board is a 50mm×50mm square. This size was determined by taking into account a variety of factors: from the perspective of space capacity, the 50mm side length can fully accommodate five layers of solder pins, while also reserving a central area for placing components; from the perspective of application adaptation, the 50mm×50mm size is a miniaturized design that can be flexibly embedded into various devices without limiting the installation scenario due to excessive size, or causing a crowded layout due to excessive size.

[0043] The center-to-center spacing between adjacent pins on the same layer, from the first layer to the fifth layer, is 0.8mm-1.5mm.

[0044] Specifically, this content provides the specific range of center-to-center spacing between adjacent pins within each layer. This range is crucial for balancing "signal density" and "soldering reliability." When the spacing is 1.25mm, a sufficient number of pins (e.g., 149 in the first layer) can be arranged on a 50mm×50mm core board to meet the signal output requirements of complex circuits, while avoiding short circuits caused by solder paste bridging during soldering due to excessively small spacing (e.g., less than 0.8mm). At the same time, under this spacing range, electromagnetic field simulation verification shows that crosstalk between adjacent pins can be controlled within an acceptable range during high-speed signal transmission below 10GHz, without affecting signal integrity. For example, in a 10Gbps high-speed signal transmission scenario, the signal eye diagram will not show significant deterioration.

[0045] From the first layer of solder joints to the fifth layer of solder joints, the center distance between two adjacent layers of solder joints that are staggered and projected onto the corresponding side is 0.4mm-0.75mm. The center distance between the centers of two adjacent layers of solder joints that are staggered and located on the same side is 1.5mm-2.5mm in the direction perpendicular to that side.

[0046] Specifically, this content refines the spacing parameters for staggered adjacent layers. The "horizontal projection center-to-center spacing 0.4mm-0.75mm" and "vertical edge center-to-center spacing 1.5mm-2.5mm" are both proven reasonable ranges. Narrow horizontal spacing allows inner layer signals to be routed through vias from the gaps between outer layer pads without increasing the number of PCB layers. Reasonable vertical spacing ensures sufficient space for grounding vias on inner layer pads; for example, high-speed differential signals can fan out along the direction of the grounding vias, reducing signal interference through grounding references, while also preventing electrical interference between inner and outer layer pads in the vertical direction.

[0047] In an optional implementation, see Figure 4 As shown, Figure 4 The diagram shows a fourth type of core board provided in an embodiment of the present invention, wherein each solder pin in the first layer to the fifth layer is circular, and the diameter of the circle is 0.5mm-1.2mm.

[0048] Specifically, this optional solution specifies that the solder pads are circular in shape, with a defined diameter range. Compared to square or oval pads, circular pads allow for more uniform solder paste flow during soldering, better covering the pad surface and improving soldering reliability. The diameter range of 0.5mm-1.2mm avoids both insufficient contact area between the pad and solder paste (leading to cold solder joints) due to excessively small diameters (e.g., less than 0.5mm) and excessively large diameters (e.g., greater than 1.2mm) which would reduce the spacing between adjacent pads (resulting in a reduced number of pins on the same layer). Taking a 0.8mm diameter as an example, the contact area between the pad and solder paste is moderate, resulting in a high soldering yield, while also allowing for a reasonable arrangement of adjacent pads within the 0.8mm-1.5mm spacing on the same layer, preventing overlap or crowding.

[0049] In an optional implementation, see Figure 5 As shown, Figure 5 A schematic diagram of the structure of the fifth type of core board provided in the embodiment of the present invention is shown, wherein the distance between the center of each solder pin in the first layer and the edge of the core board it is close to is 0.8mm-1.5mm.

[0050] Specifically, this optional solution defines the spacing range between the outermost (first layer) solder pad pins and the edge of the core board. This spacing is crucial for ensuring the mechanical reliability of the core board. A spacing of 1.25mm effectively avoids damage to the solder pads from mechanical stress during the board separation process. If the spacing is too small (e.g., less than 0.8mm), the shearing force during separation will be directly transmitted to the solder pads, easily causing them to break or detach, resulting in board failure. If the spacing is too large (e.g., greater than 1.5mm), it will compress the layout space of the inner layer solder pads, leading to a reduction in the number of inner layer pins, which cannot meet the requirements for high-speed signal extraction. Simultaneously, this spacing also allows space for protective structures (such as edge plating) on ​​the edge of the core board, improving the overall durability of the core board.

[0051] See Figure 6 As shown, Figure 6 This diagram illustrates a simulation of solder joint pin signal transmission according to an embodiment of the present invention. The horizontal axis represents the signal frequency in GHz, ranging from 0 GHz to 20 GHz; the vertical axis represents the return loss of the signal on the transmission channel, i.e., the ratio of the signal reflected from the transmission channel to the incident signal. In this example, the transmission channel refers to the LGA solder joint connecting the core board and the baseboard. The smaller the value, the less loss occurs when the signal passes through the solder joint, and the better the signal quality. The green line represents the SFF-8431 protocol's limit on the return loss of signals below 10 GHz on the transmission channel, requiring that the actual return loss of the transmission channel not exceed this value. The red curve represents the simulated return loss of signals below 10 GHz passing through the half-hole solder joint under a solder joint diameter of 0.8 mm and a solder joint spacing of 1.27 mm. As can be seen from the diagram, the simulated data has a minimum margin of 4.9 dB relative to the protocol limit across the entire frequency range, which meets the requirements.

[0052] See Figure 7 As shown, Figure 7This diagram illustrates a simulation of the second type of solder joint pin signal transmission provided in this embodiment of the invention. The horizontal axis represents the signal frequency in GHz, ranging from 0 GHz to 20 GHz; the vertical axis represents the return loss of the signal on the transmission channel, i.e., the ratio of the signal reflected from the transmission channel to the incident signal. In this example, the transmission channel refers to the solder joint connecting the core board and the baseboard. The smaller the value, the less loss occurs when the signal passes through the solder joint, and the better the signal quality. The green line represents the SFF-8431 protocol's limit on the return loss of signals below 10 GHz on the transmission channel, requiring that the actual return loss of the transmission channel cannot exceed this value. The red curve represents the simulated return loss of signals below 10 GHz passing through the half-hole solder joint under a solder joint diameter of 1 mm and a solder joint spacing of 1.5 mm. As can be seen from the diagram, the simulated data has a minimum margin of 3.8 dB relative to the protocol limit across the entire frequency range. Figure 6 The margin in the signal has decreased, resulting in poorer signal quality. Therefore, it can be concluded that the smaller the solder joint diameter and the smaller the solder joint spacing, the better the signal quality.

[0053] In an optional implementation, the core board further includes a device region located within the area formed by the fifth layer solder pins, wherein active devices and / or passive devices are disposed within the device region.

[0054] Specifically, this optional solution introduces an additional functional area on the core board—the device area, located within the region formed by the solder pins of the innermost (fifth) layer. The core function of this area is to optimize circuit performance. For example, when placing capacitors among passive components, they can be precisely aligned with the processor on the top layer of the core board, minimizing the power signal transmission path from the capacitor to the processor. This effectively reduces power signal delay and fluctuations, ensuring power integrity and preventing voltage instability from affecting the normal operation of the processor. If the platform's functionality is simple and power integrity requirements are not high, this area can be omitted to reduce the core board's manufacturing cost and overall thickness, improving application flexibility. Furthermore, this area can also accommodate small active devices (such as signal amplifier chips) as needed, further integrating core board functionality.

[0055] In an optional implementation, see Figure 8 As shown, Figure 8 A schematic diagram of the sixth type of core board provided in the embodiment of the present invention is shown, wherein the distance from the center of the pin on the fifth layer solder joint to the edge of the device area is 1.5mm-2.5mm, and the size of the device area is less than or equal to 30mm×30mm.

[0056] Specifically, this optional solution specifies the spacing range between the fifth-layer solder joint pins and the edge of the device area, as well as the maximum size limit of the device area. The 1.5mm-2.5mm spacing design ensures sufficient distance between the devices on the bottom of the core board and the corresponding cutouts on the base plate, preventing physical impacts during core board handling and assembly that could damage devices or solder joint pins, thus ensuring product mechanical reliability. This spacing also provides reasonable space for soldering and heat dissipation within the device area, preventing electrical interference caused by excessively close proximity between devices and solder joint pins. The limitation of the device area size not exceeding 30mm×30mm is based on the overall 50mm×50mm size of the core board. This design allows sufficient space in the device area to accommodate passive components (such as capacitors for voltage stabilization) or active components without compressing the layout space of the outer layers (first to fourth layers), ensuring that the number and spacing of the outer layer solder joint pins meet signal transmission requirements and achieving a balanced overall core board structure.

[0057] In an optional implementation, the fifth-layer solder joint pins include extension pins.

[0058] Specifically, this alternative solution proposes setting extension pins in the fifth-layer solder joint pins. The core purpose is to enhance the functional expandability and adaptability flexibility of the core board. As the inner layer closest to the center of the core board, the fifth layer's solder joint pin layout is less affected by interference from outer layer pins and can coordinate with pins in other layers through staggered arrangement, making it suitable for setting extension pins. These extension pins can be flexibly defined as additional power pins, control signal pins, or high-speed auxiliary signal pins according to different platform requirements. For example, in complex platforms, extension pins can increase power paths, further improving power integrity. In scenarios requiring multiple interface expansions, extension pins can serve as backup signal interfaces to meet the docking needs of different external devices. Simultaneously, placing extension pins in the fifth layer does not occupy outer layer pin resources (especially the first to fourth layers which handle low-speed or primarily high-speed signal transmission), thus enhancing the core board's applicability without affecting core signal transmission performance.

[0059] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0060] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. All should be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A core board, characterized in that, The core board includes: The core board has a first layer of solder pins to a fifth layer of solder pins consisting of multiple solder pins on one side. The first layer of solder pins to the fifth layer of solder pins are arranged sequentially along the direction close to the center of the core board. The solder joint pins from the first layer to the fifth layer are arranged in a square. The square formed by the solder joint pins from the first layer to the third layer has an opening at the same vertex. The solder joint pins of the fourth layer and the fifth layer are closed squares.

2. The core board as described in claim 1, characterized in that, Each solder joint pin in the first layer is a low-speed pin used to transmit low-speed signals, and each solder joint pin in the second to fifth layers is a high-speed pin used to transmit high-speed signals.

3. The core board as described in claim 2, characterized in that, Each solder joint pin in the first layer transmits a low-speed signal below 2.5GHz, and each solder joint pin in the second to fifth layers transmits a high-speed signal below 10GHz.

4. The core board as described in claim 1, characterized in that, In a counterclockwise direction, the edge of the core board includes a first side, a second side, a third side, and a fourth side, and the square formed by the first layer solder pins to the third layer solder pins has an opening at the apex formed by the first side and the fourth side; The first layer of solder joints includes 149 solder joints arranged in a continuous sequence, the second layer of solder joints includes 129 solder joints arranged in a continuous sequence, the third layer of solder joints includes 121 solder joints arranged in a continuous sequence, the fourth layer of solder joints includes 116 solder joints arranged in a continuous sequence, and the fifth layer of solder joints includes 104 solder joints arranged in a continuous sequence. From the first layer of solder joint pins to the fifth layer of solder joint pins, the spacing between any two adjacent pins is equal in the counterclockwise direction; From the first layer of solder joint pins to the fifth layer of solder joint pins, adjacent layers of solder joint pins are arranged at equal intervals, and adjacent layers of solder joint pins are arranged in a staggered manner.

5. The core board as described in claim 4, characterized in that, The core board has dimensions of 50mm × 50mm; The center-to-center spacing between adjacent pins on the same layer, from the first layer to the fifth layer, is 0.8mm-1.5mm. From the first layer of solder joints to the fifth layer of solder joints, the center distance between two adjacent layers of solder joints that are staggered and projected onto the corresponding side is 0.4mm-0.75mm. The center distance between the centers of two adjacent layers of solder joints that are staggered and located on the same side is 1.5mm-2.5mm in the direction perpendicular to that side.

6. The core board as described in claim 5, characterized in that, Each solder joint pin from the first layer to the fifth layer is circular, with a diameter of 0.5mm-1.2mm.

7. The core board as described in claim 1, characterized in that, The distance between the center of each solder joint pin in the first layer and the edge of the core board it is closest to is 0.8mm-1.5mm.

8. The core board as described in claim 1, characterized in that, The core board also includes a device area located within the region formed by the solder pins of the fifth layer, wherein active devices and / or passive devices are disposed within the device area.

9. The core board as described in claim 8, characterized in that, The distance from the center of the pin on the fifth layer solder joint to the edge of the device area is 1.5mm-2.5mm, and the size of the device area is less than or equal to 30mm×30mm.

10. The core board as described in claim 1, characterized in that, The fifth layer solder joint pins include extension pins.

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