Dual-interface smart card substrate layer, and dual-interface smart card

Abstract

Provided in the present invention are a dual-interface smart card substrate layer, and a dual-interface smart card. The dual-interface smart card substrate layer comprises: a bearing layer, a first connecting structure, an antenna, and a chip module, wherein the first connecting structure, the antenna and the chip module are all borne by the bearing layer, and both the first connecting structure and the antenna are electrically connected to the chip module; orthographic projection regions of the first connecting structure and the antenna on a normal plane of a target surface of the bearing layer overlap; and orthographic projection regions of the chip module and a strip module mounting region of the bearing layer on the target surface of the bearing layer do not overlap, the target surface of the bearing layer being one of the surfaces having the largest area of the bearing layer, and the normal plane of the target surface referring to a plane where a normal line of the target surface is located. Thus, the mechanical reliability of a chip can be improved, and costs can also be reduced.

Description

A dual-interface smart card substrate layer, a dual-interface smart card Technical Field

[0001] This invention relates to the field of chip devices, and more specifically, to chip devices comprising contact or contactless communication interfaces. Background Technology

[0002] Dual-interface smart cards are multifunctional cards that combine both contact and contactless communication interfaces. Because they combine the ease of use of contactless IC cards with the security and reliability of contact IC cards, dual-interface smart cards have been widely used in urban public transportation, highway toll collection, e-wallets, financial services, e-commerce and other fields.

[0003] Existing dual-interface smart cards assemble the smart card module, antenna, and card body together through lamination, milling, spot welding, and hot pressing. The functional circuits of the dual-interface module are concentrated in the module packaging position, which causes the chip to be subjected to excessive heat, pressure, and deformation during the card sealing process. At the same time, the mechanical reliability of the chip is insufficient, and the cost is too high. Summary of the Invention

[0004] To address the above problems, this invention proposes a dual-interface smart card substrate layer and a dual-interface smart card. Attached Figure Description

[0005] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0006] Figure 1 is one of the top view schematic diagrams of the novel dual-interface smart card substrate structure of a specific embodiment of the present invention.

[0007] Figure 1A is one of the schematic diagrams of the strip module installation area structure of the new dual-interface smart card substrate layer in a specific embodiment of the present invention.

[0008] Figure 1B is a schematic diagram of the strip module structure of the new dual-interface smart card according to a specific embodiment of the present invention.

[0009] Figure 1C is a second schematic diagram of the strip module mounting area structure of the new dual-interface smart card substrate layer in a specific embodiment of the present invention.

[0010] Figure 1D is one of the schematic diagrams of the chip module structure of the novel dual-interface smart card substrate layer in a specific embodiment of the present invention.

[0011] Figure 1E is a second schematic diagram of the chip module structure of the novel dual-interface smart card substrate layer in a specific embodiment of the present invention.

[0012] Figure 1F is one of the schematic diagrams of the cross-sectional structure along the AA direction in Figure 1D.

[0013] Figure 1G is a schematic cross-sectional view of the structure along the AA direction in Figure 1E.

[0014] Figure 2 is a schematic diagram of the preferred position of the substrate layer chip module corresponding to the same-layer antenna full-wrap of the new dual-interface smart card in a specific embodiment of the present invention.

[0015] Figure 2A is a schematic diagram of the preferred positions of the corresponding substrate layer chip module in the same layer of the new dual-interface smart card according to a specific embodiment of the present invention, where the antenna 2 / 3 is wrapped around the same layer.

[0016] Figure 2B is a schematic diagram of the preferred position of the substrate layer chip module in the same layer of the new dual-interface smart card according to a specific embodiment of the present invention, where the antenna 3 / 4 is wrapped around the corresponding layer.

[0017] Figure 3 is one of the schematic diagrams of the substrate layer structure corresponding to the new dual-interface smart card winding-same-layer-antenna half-winding in a specific embodiment of the present invention.

[0018] Figure 3A is a schematic diagram of the preferred positions of the substrate layer chip module corresponding to the new dual-interface smart card winding-same-layer-antenna half-winding in a specific embodiment of the present invention.

[0019] Figure 3B is the second schematic diagram of the substrate layer structure corresponding to the new dual-interface smart card winding-same-layer-antenna half-winding in a specific embodiment of the present invention.

[0020] Figure 3C is the third schematic diagram of the substrate layer structure corresponding to the new dual-interface smart card winding-same-layer-antenna half-winding in a specific embodiment of the present invention.

[0021] Figure 4 is one of the schematic diagrams of the cross-sectional structure along the AA direction in Figure 1.

[0022] Figure 4A is the second schematic diagram of the cross-sectional structure along the AA direction in Figure 1.

[0023] Figure 4B is the third schematic diagram of the cross-sectional structure along the AA direction in Figure 1.

[0024] Figure 4C is the fourth schematic diagram of the cross-sectional structure along the AA direction in Figure 1.

[0025] Figure 4D is the fifth schematic diagram of the cross-sectional structure along the AA direction in Figure 1.

[0026] Figure 4E is the sixth schematic diagram of the cross-sectional structure along the AA direction in Figure 1.

[0027] Figure 4F is the seventh schematic diagram of the cross-sectional structure along the AA direction in Figure 1.

[0028] Figure 4G is the eighth schematic diagram of the cross-sectional structure along the AA direction in Figure 1.

[0029] Figure 4H is the ninth schematic diagram of the cross-sectional structure along the AA direction in Figure 1.

[0030] Figure 4I is the tenth schematic diagram of the cross-sectional structure along the AA direction in Figure 1.

[0031] Figure 4J is the eleventh of the cross-sectional structural diagrams along the AA direction in Figure 1.

[0032] Figure 4K is the twelfth of the cross-sectional structural diagrams along the AA direction in Figure 1.

[0033] Figure 4L is the thirteenth schematic diagram of the cross-sectional structure along the AA direction in Figure 1.

[0034] Figure 4M is one of the distorted top views of Figure 1, and one of the cross-sectional structural schematic diagrams along the AA direction.

[0035] Figure 4N is one of the deformed top views of Figure 1, and the second schematic diagram of the cross-sectional structure along the AA direction.

[0036] Figure 4O is one of the deformed top views of Figure 1, and is a schematic diagram of the cross-sectional structure along the AA direction.

[0037] Figure 4P is one of the deformed top views of Figure 1, and is a schematic diagram of the cross-sectional structure along the AA direction.

[0038] Figure 4Q is one of the deformed top views of Figure 1, and is the fifth schematic diagram of the cross-sectional structure along the AA direction.

[0039] Figure 4R is a cross-sectional view of one of the deformed top views of Figure 1, along the AA direction.

[0040] Figure 4S is one of the deformed top views of Figure 1, and is a schematic diagram of the cross-sectional structure along the AA direction.

[0041] Figure 4T is one of the deformed top views of Figure 1, and is a schematic diagram of the cross-sectional structure along the AA direction.

[0042] Figure 4U is one of the deformed top views of Figure 1, and is a schematic diagram of the cross-sectional structure along the AA direction.

[0043] Figure 4V is one of the deformed top views of Figure 1, and is a cross-sectional structural schematic diagram along the AA direction.

[0044] Figure 4W is one of the top views of a new dual-interface smart card according to a specific embodiment of the present invention.

[0045] Figure 4X is one of the schematic diagrams of the cross-sectional structure of Figure 4W along the AA direction.

[0046] Figure 4Y is the second schematic diagram of the cross-sectional structure along the AA direction of Figure 4W.

[0047] Figure 4Z is a top view of the new dual-interface smart card according to a specific embodiment of the present invention.

[0048] Figure 4Z' is a schematic diagram of the cross-sectional structure of Figure 4Z along the AA direction.

[0049] Figure 5 is the fourteenth of the cross-sectional structural diagrams along the AA direction in Figure 1.

[0050] Figure 5A is one of the distorted top views of Figure 1, and is a schematic cross-sectional view along the AA direction.

[0051] Figure 5B is the fifteenth of the cross-sectional structural diagrams along the AA direction in Figure 1.

[0052] Figure 5C is one of the cross-sectional structural schematic diagrams along the AA direction of the second deformed top view of Figure 1.

[0053] Figure 5D is the second cross-sectional structural schematic diagram along the AA direction of the second deformed top view of Figure 1.

[0054] Figure 5E is one of the distorted top views of Figure 1, and is a cross-sectional structural schematic diagram along the AA direction.

[0055] Figure 5F is the third cross-sectional structural diagram along the AA direction, which is a modified top view of Figure 1.

[0056] Figure 5G is the fourth cross-sectional structural diagram along the AA direction, which is the second of the deformed top view of Figure 1.

[0057] Figure 5H is a thirteenth schematic diagram of the cross-sectional structure along the AA direction, one of the deformed top views of Figure 1.

[0058] Figure 5I is the third schematic diagram of the cross-sectional structure along the AA direction of Figure 4W.

[0059] Figure 5J is the fourth schematic diagram of the cross-sectional structure along the AA direction of Figure 4W.

[0060] Figure 6 is a schematic diagram of the substrate layer strip module mounting area corresponding to the new dual-interface smart card of the present invention.

[0061] Figure 7 is one of the schematic diagrams of the cross-sectional structure along the AA direction in Figure 6.

[0062] Figure 7A is the second schematic diagram of the cross-sectional structure along the AA direction in Figure 6.

[0063] Figure 7B is the third schematic diagram of the cross-sectional structure along the AA direction in Figure 6.

[0064] Figure 7C is the fourth schematic diagram of the cross-sectional structure along the AA direction in Figure 6.

[0065] Figure 7D is the fifth of the cross-sectional structural diagrams along the AA direction in Figure 6.

[0066] Figure 7E is the sixth of the cross-sectional structural diagrams along the AA direction in Figure 6.

[0067] Figure 8 is the seventh schematic diagram of the cross-sectional structure along the AA direction in Figure 6.

[0068] Figure 8A is the eighth of the cross-sectional structural diagrams along the AA direction in Figure 6.

[0069] Figure 8B is the ninth schematic diagram of the cross-sectional structure along the AA direction in Figure 6.

[0070] Figure 8C is the tenth schematic diagram of the cross-sectional structure along the AA direction in Figure 6.

[0071] Figure 8D is the eleventh of the cross-sectional structural diagrams along the AA direction in Figure 6.

[0072] Figure 8E is a schematic diagram of the cross-sectional structure along the AA direction in Figure 6. Detailed Implementation

[0073] In the following description, numerous specific details are set forth in order to provide a thorough understanding of various illustrative embodiments of the invention. However, those skilled in the art will understand that embodiments of the invention can be practiced without some or all of these specific details. It should be understood that the terminology used herein is for descriptive purposes only and is not intended to limit the scope of the invention. In the drawings, the same reference numerals refer to the same or similar functions or features in several figures.

[0074] It should be understood that the terms "comprising," "including," and "having" are intended to be open-ended, meaning that there may be additional elements besides those listed. The use of reference numerals such as first, second, third, and fourth should not be construed as imposing any order of position or time among the multiple definitions. Furthermore, terms such as "top," "bottom," "side," "below," and "vertical" used herein are merely for descriptive convenience and refer to the orientation of the components as shown in the figures. It should be understood that any orientation of the components described herein is within the scope of this invention.

[0075] General Introduction to Separation:

[0076] Existing dual-interface smart cards concentrate the dual-interface module's functional circuitry at the module packaging location. This integration method, where the stripe module and chip are in the same area, exposes the chip to excessive heat, pressure, and deformation during card sealing and use. Furthermore, the chip's mechanical reliability is insufficient, and the cost is too high. To address this issue, this invention proposes a novel dual-interface smart card. The dual-interface smart card includes a substrate layer and a stripe module. The substrate layer includes a carrier layer, a first connection structure, an antenna, and a chip module. The first connection structure, antenna, and chip module are all carried by the carrier layer, and the first connection structure and the antenna are electrically connected to the chip module.

[0077] The first connection structure and the antenna have overlapping orthographic projection areas on the normal plane of the target surface of the carrier layer; the chip module and the strip module mounting area of ​​the dual-interface smart card do not overlap in the orthographic projection areas on the target surface of the carrier layer.

[0078] Wherein, the target surface of the bearing layer is one of the surfaces with the largest area of ​​the bearing layer, and the normal plane of the target surface refers to the plane in which the normal of the target surface is located.

[0079] Referring to Figure 1, which is a top view schematic diagram of one specific embodiment of the novel dual-interface smart card substrate layer of the present invention, the substrate layer 100 of this embodiment includes a carrier layer, a strip module mounting area 110, a chip module 120, an antenna 130, and a first connection structure. The first connection structure is a connection lead between the strip module mounting area 110 and the chip module 120, used to realize the electrical connection between the strip module and the chip. The antenna 130 includes an antenna winding (i.e., the coil in the figure) and an antenna lead (i.e., the connection line between the antenna winding and the chip module 120 in the figure), the antenna lead being the connection lead between the antenna and the chip module 120. The antenna and the first connection structure are collectively referred to as a conductive channel. The carrier layer can be a single-layer or multi-layer film structure, and the material can preferably be a flexible film such as PVC, PC, or PET. The carrier layer is used to support other structures of the substrate layer. The first connection structure and the antenna have overlapping orthographic projection areas on the normal plane of the target surface of the carrier layer. The overlap here specifically refers to the following: excluding the portion where the antenna and the first connection structure are electrically connected to the chip module after the chip module is installed, the orthographic projection areas of the first connection structure and the antenna on the normal plane of the target surface of the carrier layer are a single closed shape (hereinafter referred to as the first connection structure and antenna being on the same layer). It is worth noting that if the orthographic projection areas of the first connection structure and the antenna on the normal plane of the target surface of the carrier layer overlap, but the first connection structure and the antenna are located in different layer structures (e.g., different sub-substrate layers), this is not within the scope of the same layer in this embodiment of the invention. The target surface of the substrate layer 100 is the surface with the largest area of ​​the substrate layer 100, and the normal plane of the target surface refers to the plane where the normal of the target surface is located. The antenna and the first connection structure can be generated by methods including but not limited to wire winding or etching. For the wire winding method, both the first connection structure and the antenna are enameled conductive wires; for the etching method, both the first connection structure and the antenna are conductive metal foils. In this embodiment of the invention, the enameled conductive wire is preferably made of copper, and the conductive metal foil is preferably made of aluminum or copper. However, it is worth noting that other suitable materials can also be used for the enameled conductive wire and conductive metal foil mentioned above, and the embodiments of the present invention do not specifically limit this.

[0080] It should be further explained that, since the diameter of the enameled conductive wire is much larger than the thickness of the conductive metal foil layer, and the diameter of the enameled conductive wire is comparable to the thickness of the substrate layer structure, for the winding method of the enameled conductive wire, as long as the first connecting structure and the antenna are carried by the same substrate layer structure, the orthographic projection areas of the first connecting structure and the antenna on the normal plane of the target surface of the carrying layer can overlap, which is the same layer setting defined in this invention; while for the etching and wiring method of the conductive metal foil, to satisfy the overlap of the orthographic projection areas of the first connecting structure and the antenna on the normal plane of the target surface of the carrying layer, the first connecting structure and the antenna must be located on the same plane.

[0081] The top views of Figures 1, 2-2B, and 4W illustrate the wire-wound wiring method. These are for illustrative purposes only, and it is understood that the etching wiring method is similarly applicable and should not be limited to the wiring method. In the scheme where the first connection structure and antenna are on the same layer, Figures 3-3C and 4Z are only examples of the wire-wound wiring method.

[0082] The strip module of this invention includes contact pads, a support layer, and conductive pads. The contact pads and conductive pads are located on both sides of the support layer. The contact pads include effective contacts conforming to the ISO7816 protocol. Referring to Figure 1A, which is one schematic diagram of the strip module mounting area structure of a novel dual-interface smart card substrate layer according to a specific embodiment of this invention, corresponding to the winding method, Figure 1B is a schematic diagram of the strip module structure of a novel dual-interface smart card according to a specific embodiment of this invention. As an example, only the 8-pin module scheme is shown in the figures; the same applies to the 6-pin module scheme, which will not be detailed here. As shown in Figure 1A, the strip module mounting area includes five closely wound first connection structure terminals (i.e., first connection structure terminals for connecting the conductive pads of the strip module). The projection area corresponding to each closely wound first connection structure terminal matches the projection area corresponding to the effective contact after the strip module is installed. As shown in Figure 1B, the strip module has conductive pads on the surface corresponding to the effective contacts, and the conductive pads are electrically connected to the corresponding effective contacts. The tightly wound first connection structure terminal can be electrically connected to the corresponding conductive pad of the strip module via conductive adhesive, thereby achieving an effective contact connection with the strip module. Preferably, the conductive pad is inclined, which increases the contact area with the tightly wound first connection structure terminal and improves the reliability of the electrical connection. It is worth noting that the conductive pad is actually a three-dimensional structure, and its height can be adjusted according to design requirements. The conductive pad can be made of metal materials such as copper or aluminum.

[0083] Referring to Figure 1C, which is a second schematic diagram of the strip module mounting area structure of the new dual-interface smart card substrate layer according to a specific embodiment of the present invention, corresponding to the etching method. As shown in Figure 1C, the strip module mounting area includes five first connection structure terminals in the form of etched pads (i.e., first connection structure terminals for connecting the conductive pads of the strip module). The projection area corresponding to each first connection structure terminal in the form of etched pads matches the projection area corresponding to the effective contact after the strip module is installed. The strip module still adopts the structure shown in Figure 1B. Each first connection structure terminal in the form of etched pads can be electrically connected to the corresponding conductive pad of the strip module by conductive glue or solder ball soldering, thereby realizing the electrical connection with the effective contact of the strip module.

[0084] Based on the above, the chip module 120 is mounted on the substrate layer using methods including but not limited to COB (chip on board) packaging and WLCSP (Wafer Level Chip Scale Packaging). Figure 1D is one of the structural schematic diagrams of the chip module 120 when using COB packaging, and Figure 1E is one of the structural schematic diagrams of the chip module 120 when using WLCSP packaging.

[0085] Referring to Figure 1D, the COB-packaged chip module 120 includes a substrate and a chip. The target surface of the substrate is used to mount the chip, and this target surface is one of the largest surfaces of the substrate. Preferably, the chip is mounted at the center of the target surface of the substrate, i.e., the line connecting the center point of the chip and the center point of the substrate is perpendicular to the target surface of the substrate. The target surface of the substrate also has multiple chip module contact pad groups to achieve electrical connection between the chip and the antenna and the first connection structure. Based on this, electrical connection between the chip and the strip module and the antenna can be achieved, thereby realizing contact communication and contactless communication of the dual-interface smart card. It is worth noting that, to ensure the basic contact and contactless functions of the smart card, the number of chip module contact pad groups includes at least 7 groups: 2 groups are used to achieve electrical connection between the two free ends of the chip and the antenna, and 5 groups are used to achieve electrical connection between the chip and the effective contact points of the strip module. The number of chip module contact pad groups in Figure 1D can be adjusted according to actual application needs; the number of chip module contact pad groups in Figure 1D is only an example. It is worth noting that each chip module contact pad group includes one chip contact pad and one conductive channel contact pad. The chip contact pad and the conductive channel contact pad can be integrally formed or are two independent contact pads electrically connected by wires or other conductive structures. The chip contact pad and the conductive channel contact pad are made of the same conductive material and can be manufactured using the same process. Refer to Figure 1F, which is one of the cross-sectional structural diagrams along the AA direction in Figure 1D. As shown in Figure 1F, the chip contact pad is connected to the chip pins through chip connection lines. After the connection is completed, the chip, chip connection lines, and chip contact pads are encapsulated with encapsulating adhesive, which can be applied using processes such as epoxy resin coating. The conductive channel contact pad is used to connect to the first connection structure terminal (i.e., the chip-side first connection structure terminal used to connect the chip module) or the antenna terminal (i.e., the terminal of the antenna lead). Based on the aforementioned embodiments, it is known that the other terminal of the first connection structure is electrically connected to the corresponding contact of the strip module. Therefore, the chip module contact pad assembly of this embodiment can achieve electrical connection between the chip, the antenna, and the strip module.

[0086] Preferably, the plurality of chip module contact pads are evenly distributed around the chip. This shortens the length of the chip connection lines and optimizes the first connection structure and antenna arrangement. Of course, depending on the actual application requirements, the plurality of chip module contact pads can also adopt other layouts, such as being arranged side by side on one side of the chip, or having the chip module contact pads connected to the antenna and the chip module contact pads connected to the strip module arranged separately. This embodiment of the invention does not specifically limit these arrangements.

[0087] Optionally, the chip can also be flip-chip mounted on the target surface of the substrate. When flip-chip mounted, the chip pins can be directly electrically connected to the chip contact pads on the substrate via solder balls. Based on this, compared to the method shown in Figure 1F, the embodiments of the present invention can achieve the electrical connection between the chip pins and the chip contact pads without setting chip connection lines.

[0088] It is worth noting that when the chip module 120 is installed, the terminals of the antenna and the first connection structure overlap with the matching conductive channel contact pads on the chip module in the projection direction. Based on this, in this embodiment of the invention, the terminals of the antenna and the first connection structure can be soldered to the matching conductive channel contact pads or bonded with conductive adhesive, thereby achieving electrical connection between the antenna and the first connection structure and the chip and strip module. Specifically, the soldering method can be spot welding or other methods, and this embodiment of the invention does not specifically limit this. The substrate can be a flexible PCB board or epoxy glass cloth, or a composite bearing material, such as a metal base plate supporting PVC or PE materials. Based on this, it can provide higher stress strength than PVC material alone, ensuring the reliability of the chip installation and use process, while reducing costs.

[0089] Referring to Figure 1E, the WLCSP-packaged chip module 120 consists only of a chip and solder balls. The chip pins can be electrically connected to an external module via the solder balls. It is understood that the number and position of the solder balls in Figure 1E can be adjusted as needed in practical applications, and this embodiment of the invention does not impose specific limitations on this. Referring to Figure 1G, it is a schematic cross-sectional view along direction AA in Figure 1E. The WLCSP package size is only about 0%-20% larger than the bare chip size, and its thickness is relatively thin. This method can minimize the chip module's footprint while meeting the manufacturing process requirements of dual-interface smart cards. The solder ball array of the WLCSP-packaged chip is electrically connected to the antenna and the terminals (conductive metal foil etched wiring) of the first connection structure designed in the substrate layer through soldering or other conductive connection methods. Precise soldering processes, such as reflow soldering or ultrasonic soldering, are used to ensure the reliability and conductivity of the connection. The WLCSP package allows the chip module 120 to be embedded in the substrate layer with minimal footprint while maintaining excellent electrical performance and mechanical stability. Through precise positioning and reliable electrical connections, the WLCSP package ensures the overall performance of dual-interface smart cards while extending the chip's lifespan, meeting the dual requirements of high performance and high reliability for modern dual-interface smart cards.

[0090] Preferably, for the wire-wound method, the chip module 120 is packaged using COB packaging; for the etching wiring method, the chip module 120 can be packaged using either COB packaging or WLCSP packaging.

[0091] Based on the aforementioned substrate layer structure, this embodiment of the invention maximizes chip lifespan while ensuring the mechanical and electrical performance of the dual-interface smart card by optimizing the chip module's location. Specifically, this embodiment of the invention generates multiple corresponding constraints to determine the optimal location of the chip module based on a comprehensive consideration of mechanical performance, electrical performance, and chip lifespan.

[0092] Constraint diagram: Positional distribution of the strip module mounting area and the chip module

[0093] 1. First constraint figure

[0094] The first constraint diagram refers to the substrate layer antenna winding size method corresponding to the new dual-interface smart card in the specific implementation of the present invention, which is full winding, 2 / 3 winding, or 3 / 4 winding.

[0095] Referring to Figure 2, which is a schematic diagram of the preferred position of the substrate layer chip module corresponding to the full antenna wrapping of the new dual-interface smart card in a specific embodiment of the present invention; referring to Figure 2A, which is a schematic diagram of the preferred position of the substrate layer chip module corresponding to the 2 / 3 antenna wrapping of the new dual-interface smart card in a specific embodiment of the present invention; and referring to Figure 2B, which is a schematic diagram of the preferred position of the substrate layer chip module corresponding to the 3 / 4 antenna wrapping of the new dual-interface smart card in a specific embodiment of the present invention. In conjunction with Figures 2-2B, to facilitate the description of the planar positional relationship in the process of determining the preferred position of the chip module, this embodiment of the present invention is based on the orthographic projection areas formed on the target surface of the substrate layer 100 by the strip module mounting area 110, the chip module 120, and the antenna 130, i.e., the strip projection area, the chip module projection area, and the antenna projection area. It can be understood that the orthographic projection area is the area obtained by projecting along the normal direction of the target surface of the substrate layer 100. It is worth noting that the antenna projection area refers to the orthographic projection area corresponding to the antenna winding, i.e., excluding the orthographic projection area corresponding to the antenna leads. Based on this, the specific process for determining the preferred location of the projection area of ​​the substrate layer chip module is as follows:

[0096] The determination of the preferred location of the chip module projection area includes strong constraint regions and weak constraint regions generated based on strong and weak constraint conditions. Optionally, the strong constraint regions may include, but are not limited to, magnetic stripe projection regions, embossed projection regions, and antenna projection regions. The magnetic stripe projection region is the orthographic projection region of the carrier layer corresponding to the smart card magnetic stripe mounting area, and the embossed projection region is the orthographic projection region of the carrier layer corresponding to the smart card embossing area. The weak constraint regions may include, but are not limited to, imprinting projection regions, resistance projection regions, and the central axis. The imprinting projection region is the area enclosed by the straight line containing the long side of the stripe projection region and the left and right edges of the target surface of the carrier layer. The resistance projection region is the target half-region where the stripe mounting area is located, among the two half-regions divided by the vertical central axis of the target surface of the carrier layer. Strong constraint regions are areas where the chip module projection area cannot be located or set, while weak constraint regions are areas where the chip module projection area preferably cannot be located or set. If the chip module projection area is set in a weak constraint region, the limitations of the weak constraint conditions need to be overcome by strengthening the chip module. The strong constraints of this invention embodiment are as follows: Considering the risk of chip damage during the installation of the magnetic stripe and the fabrication of the embossed printing during the dual-interface smart card manufacturing process, this invention embodiment generates a first strong constraint: the chip module projection area avoids the magnetic stripe projection area and the embossed printing projection area. Based on this, damage to the chip during the magnetic stripe and embossed printing processes can be avoided. Furthermore, this invention embodiment further considers the impact of chip placement on antenna performance. If the chip module projection area coincides with the antenna, the installation of the chip module 120 will affect antenna performance or even cause antenna damage. Based on this, this invention embodiment generates a second strong constraint: the chip module projection area avoids the antenna projection area. Based on this, the installation of the chip module 120 can be avoided from affecting antenna performance or damaging the antenna.

[0097] The weak constraints of this embodiment are as follows: Since the strip module requires a new dual-interface smart card imprinting test after installation, this test uses a three-wheel imprinting method. The three imprinting rollers move along the imprinting projection area shown in Figures 2-2B. If the chip is located in the imprinting projection area, it will be squeezed by the three imprinting rollers and will also face the risk of damage. Based on this, this embodiment generates a first weak constraint: the chip module projection area avoids the imprinting projection area. Therefore, damage to the chip can be avoided during the imprinting test after the strip module is installed. Furthermore, this embodiment considers that a torsion test will be performed after the dual-interface smart card is manufactured. During the torsion test, the torque is greatest on the central axis of the dual-interface smart card, as shown in Figures 2-2B, including the vertical and horizontal central axes. If the chip is located on the central axis of the dual-interface smart card, it will also face a significant risk of damage. Based on this, this embodiment generates a second weak constraint: the chip module projection area avoids the central axis. Therefore, damage to the chip can be avoided during the torsion test. Building upon the above, this invention further discovers through research that during the use of a dual-interface smart card, the chip is subjected to continuous compression after entering the card slot, increasing the resistance to card insertion and removal. Prolonged compression also affects the chip's lifespan. Positioning the chip module on the right side of the vertical central axis, compared to placing the chip on the left side (i.e., the resistance projection area shown in Figures 2-2B), significantly shortens the compression stroke, reducing insertion resistance and extending chip lifespan. Based on this, this invention further adds a third weak constraint: the chip module projection area avoids the left side of the vertical central axis (i.e., the resistance projection area). This reduces insertion resistance and maximizes chip lifespan while ensuring the electrical performance of the dual-interface smart card.

[0098] Based on the above five constraint conditions (the first strong constraint condition, the second strong constraint condition, the first weak constraint condition, the second weak constraint condition, and the third weak constraint condition), the embodiments of the present invention can determine the preferred position area of the chip module projection area, that is, the area formed by the lower edge of the magnetic stripe projection area, the upper edge of the embossing projection area, and the left and right edges of the carrier layer, which does not overlap with the antenna projection area, the imprinting projection area, and the resistance projection area; and the chip module projection area does not overlap with the central axis of the target surface of the carrier layer (the same applies to subsequent embodiments). To facilitate the characterization of the preferred position area, the embodiments of the present invention establish a plane rectangular coordinate system with the center point of the stripe projection area as the origin (i.e., A0 in FIG. 2), and the preferred position area of the chip module is the area 1 formed by A1(D1, H1), A2(D2, H1), A3(D1, H2), A4(D2, H2) and the area 2 formed by B1(D1, -H1), B2(D2, -H1), B3(D1, -H3), B4(D2, -H3). Among them, D1 is the vertical distance from the center point of the stripe projection area to the vertical central axis, D2 is the vertical distance from the center point of the stripe projection area to the rightmost inner loop antenna projection, H1 is the vertical distance from the center point of the stripe projection area to the upper edge of the stripe projection area, H2 is the vertical distance from the center point of the stripe projection area to the lower edge of the magnetic stripe projection area, and H3 is the vertical distance from the center point of the stripe projection area to the upper edge of the embossing projection area.

[0099] Optionally, the shape of the chip module 120 is preferably a rectangle, composed of four corner points C1(X1, Y1), C2(X2, Y2), C3(X3, Y3), C4(X4, Y4), and is completely located within area 1 or area 2, and it is necessary to ensure that all four corner points satisfy the constraint conditions of this area. Based on this, the logical expression for the preferred position of the chip module 120 is:

[0100] [(D1 < X1 < D2) and (H1 < Y1 < H2)] and [(D1 < X2 < D2) and (H1 < Y2 < H2)] and [(D1 < X3 < D2) and (H1 < Y3 < H2)] and [(D1 < X4 < D2) and (H1 < Y4 < H2)] (indicating that the chip module projection area is located within area 1), or, [(D1 < X1 < D2) and (-H3 < Y1 < -H1)] and [(D1 < X2 < D2) and (-H3 < Y2 < -H1)] and [(D1 < X3 < D2) and (-H3 < Y3 < -H1)] and [(D1 < X4 < D2) and (-H3 < Y4 < -H1)] (indicating that the chip module projection area is located within area 2).

[0101] It is worth noting that the above five constraint schemes are the optimal implementation of this invention. In practical applications, only the first and second strong constraints can be considered, or only some weak constraints can be considered based on the first and second strong constraints. That is, the chip module projection area can also be located in at least one of the resistance projection area and the imprinting projection area, and can overlap with the central axis. However, when the chip module projection area is set in the resistance projection area, the imprinting projection area, and the central axis, a corresponding protective structure needs to be provided for the chip module 120 to avoid damage to the chip due to pressure. The drag projection area is region 3 formed by A3(D1, H2), A5(-D3, H2), B5(-D3, -H3), and B3(D1, -H3) in Figures 2-2B, where D3 is the vertical distance from the center point of the strip projection area to the projection of the innermost left-side antenna. The imprint projection area is region 4 formed by A2(D2, H1), B2(D2, -H1), B6(-D3, -H1), and A6(-D3, H1) in Figures 2-2B. The central axis is line segment 5 formed by A3(D1, H2) and B3(D1, -H3) and line segment 6 formed by B2(D2, -H1) and B6(-D3, -H1) in Figures 2-2B.

[0102] Based on this, considering only the first and second strong constraints, the preferred location area of ​​the chip module projection area also includes the resistance projection area, the embossing projection area, and the central axis. That is, the preferred location area of ​​the chip module projection area is the area formed by the lower edge of the magnetic strip projection area, the upper edge of the embossing projection area, and the left and right edges of the carrier layer, which does not overlap with the antenna projection area and the strip projection area. Specifically, these are the aforementioned areas 1, 2, 3, and 4, and the chip module projection area can overlap with the central axis.

[0103] Considering the first strong constraint, the second strong constraint, and the first weak constraint, the preferred location area of ​​the chip module projection region also includes the portion of the resistance projection region and the central axis that does not overlap with the imprinted projection region. Specifically, the preferred location area of ​​the chip module projection region is the region formed by the lower edge of the magnetic stripe projection region, the upper edge of the embossed projection region, and the left and right edges of the support layer, that does not overlap with the antenna projection region and the imprinted projection region. Specifically, this refers to the portion of regions 1, 2, and 3 that does not overlap with region 4, and the chip module projection region can overlap with the central axis.

[0104] Considering the first strong constraint, the second strong constraint, and the second weak constraint, the preferred location area of ​​the chip module projection region also includes the portions of the resistance projection region and the embossing projection region that do not overlap with the central axis. Specifically, the preferred location area of ​​the chip module projection region is the region formed by the lower edge of the magnetic stripe projection region, the upper edge of the embossing projection region, and the left and right edges of the carrier layer, which does not overlap with the antenna projection region and the stripe projection region. Specifically, this refers to regions 1, 2, 3, and 4 mentioned above, and the chip module projection region does not overlap with the central axis.

[0105] Considering the first strong constraint, the second strong constraint, and the third weak constraint, the preferred location of the chip module projection area also includes the portion of the central axis and the imprinted projection area that does not overlap with the resistance projection area. Specifically, the preferred location of the chip module projection area is the region formed by the lower edge of the magnetic stripe projection area, the upper edge of the embossed projection area, and the left and right edges of the support layer, that does not overlap with the antenna projection area and the resistance projection area. Specifically, this refers to the portion of regions 1, 2, and 4 that does not overlap with region 3, and the chip module projection area can overlap with the central axis.

[0106] Considering the first strong constraint, the second strong constraint, the first weak constraint, and the second weak constraint, the preferred location of the chip module projection area also includes the portion of the resistance projection area that does not overlap with the central axis and the imprinted projection area. Specifically, the preferred location of the chip module projection area is the region formed by the lower edge of the magnetic stripe projection area, the upper edge of the embossed projection area, and the left and right edges of the support layer, that does not overlap with the antenna projection area and the imprinted projection area. Specifically, this refers to the portion of regions 1, 2, and 3 that does not overlap with region 4, and the chip module projection area does not overlap with the central axis.

[0107] Considering the first strong constraint, the second strong constraint, the first weak constraint, and the third weak constraint, the preferred location of the chip module projection area also includes the portion along the central axis that does not overlap with the drag projection area and the embossing projection area. Specifically, the preferred built-in area of ​​the chip module projection area is the region formed by the lower edge of the magnetic stripe projection area, the upper edge of the embossed projection area, and the left and right edges of the support layer, which does not overlap with the antenna projection area, the embossed projection area, and the drag projection area. Specifically, this refers to the aforementioned areas 1 and 2, and the chip module projection area can overlap with the central axis.

[0108] Considering the first strong constraint, the second strong constraint, the second weak constraint, and the third weak constraint, the preferred location of the chip module projection area also includes the portion of the imprint projection area that does not overlap with the resistance projection area and the central axis. Specifically, the preferred location of the chip module projection area is the region formed by the lower edge of the magnetic stripe projection area, the upper edge of the embossed projection area, and the left and right edges of the carrier layer, which does not overlap with the resistance projection area; and the chip module projection area does not overlap with the central axis of the target surface of the carrier layer. Specifically, this refers to the portion of regions 1, 2, and 4 that does not overlap with region 3, and the chip module projection area does not overlap with the central axis.

[0109] 2. Second constraint figure

[0110] The second constraint diagram is the substrate layer antenna winding size method corresponding to the new dual-interface smart card of the present invention, which is half-winding.

[0111] Referring to Figure 3, this is one of the schematic diagrams of the substrate layer structure corresponding to the new dual-interface smart card winding-same-layer-antenna half-wrap in a specific embodiment of the present invention. Due to the large diameter of the winding wire, when the antenna is set in the same layer as the first connection structure, the antenna cannot pass under the strip module mounting area; otherwise, the thickness of the dual-interface smart card will be insufficient or its reliability will be reduced. Based on this, referring to Figure 3A, this is a schematic diagram of the preferred position of the substrate layer chip module corresponding to the new dual-interface smart card winding-same-layer-antenna half-wrap in a specific embodiment of the present invention. Specifically, the process for determining the preferred position of the chip module projection area is as follows:

[0112] Considering that the installation of the magnetic stripe and the embossing process during the manufacturing of dual-interface smart cards still pose a risk of chip damage, the aforementioned first strong constraint condition is retained; considering the impact of chip settings on antenna performance, the aforementioned second strong constraint condition is retained; considering that the squeezing of the three-roll embossing rollers still poses a risk of chip damage, the aforementioned first weak constraint condition is retained; considering that the torsion test process poses a significant risk of chip damage, the aforementioned second weak constraint condition is retained; considering that during the use of dual-interface smart cards, the chip will still be subjected to continuous squeezing after entering the card slot, which will increase the resistance to card insertion and removal, the aforementioned third weak constraint condition is retained.

[0113] Based on the above five constraints, the preferred position area of the chip module projection area can be determined in the embodiments of the present invention. It should be noted that since the space in the upper edge area and the lower edge area of the dual-interface smart card is too small, the installation of the chip module cannot be achieved. Therefore, the preferred position area of the chip module projection area is Area 1 formed by A1(D1, H1), A2(D2, H1), A3(D1, H2), A4(D2, H2) and Area 2 formed by B1(D1, -H1), B2(D3, -H1), B3(D1, -H3), B4(D3, -H3). Among them, D1 is the vertical distance from the center point of the strip projection area to the vertical central axis, D2 is the vertical distance from the center point of the strip projection area to the projection of the innermost right antenna, D3 is the vertical distance from the center point of the strip projection area to the right edge of the card, H1 is the vertical distance from the center point of the strip projection area to the upper edge of the strip projection area, H2 is the vertical distance from the center point of the strip projection area to the lower edge of the magnetic stripe projection area, and H3 is the vertical distance from the center point of the strip projection area to the upper edge of the embossed projection area.

[0114] Similarly to the foregoing embodiments, the shape of the chip module 120 is preferably a rectangle, composed of four corner points C1(X1, Y1), C2(X2, Y2), C3(X3, Y3), C4(X4, Y4), and is completely located within Area 1 or Area 2, and it is necessary to ensure that all four corner points satisfy the constraints of this area. Based on this, the logical expression for the preferred position of the chip module 120 is:

[0115] [(D1 < X1 < D2) and (H1 < Y1 < H2)] and [(D1 < X2 < D2) and (H1 < Y2 < H2)] and [(D1 < X3 < D2) and (H1 < Y3 < H2)] and [(D1 < X4 < D2) and (H1 < Y4 < H2)] (indicating that the chip module projection area is located within Area 1), or, [(D1 < X1 < D3) and (-H3 < Y1 < -H1)] and [(D1 < X2 < D3) and (-H3 < Y2 < -H1)] and [(D1 < X3 < D3) and (-H3 < Y3 < -H1)] and [(D1 < X4 < D3) and (-H3 < Y4 < -H1)] (indicating that the chip module projection area is located within Area 2).

[0116] It is worth noting that the above five constraint schemes are the optimal implementation of this invention. In practical applications, only the first and second strong constraint conditions can be considered, or only some weak constraint conditions can be considered based on the first and second strong constraint conditions. That is, the chip module projection area can also be located in at least one of the resistance projection area and the imprinting projection area, and can overlap with the central axis. However, when the chip module projection area is set in the resistance projection area, the imprinting projection area, and the central axis, a corresponding protective structure needs to be provided for the chip module 120 to avoid damage to the chip module due to pressure. Among them, considering that the antenna projection area partially overlaps with the resistance projection area and the imprinting projection area, the resistance projection area, the imprinting projection area, and the central axis described below are all usable resistance projection area, imprinting projection area, and central axis after removing the influence of the antenna projection area. Specifically, the drag projection area is region 3 formed by A3(D1, H2), A5(D4, H2), A6(D4, -H4), and A7(D1, -H4) in Figure 3A, and region 4 formed by B1(D1, -H1), B3(D1, -H3), B5(-D5, -H3), and B6(-D5, -H1). Here, D4 ​​is the vertical distance from the center point of the strip projection area to the projection of the innermost left-side antenna; D5 is the vertical distance from the center point of the strip projection area to the left edge of the card; and H4 is the vertical distance from the center point of the strip projection area to the projection of the straight line segment of the lower innermost antenna. The imprint projection area is region 5 formed by A6(D4, -H4), A9(D6, -H4), A10(D6, H1), and A8(D4, H1) in Figure 3A. Here, D6 is the lateral distance from the center point of the strip projection area to the right end point of the projection of the straight line segment of the lower innermost antenna. The central axis is line segment 6 formed by A3(D1, H2) and A7(D1, -H4) in Figure 3A, line segment 7 formed by B1(D1, -H1) and B3(D1, -H3), and line segment 8 formed by B2(D3, -H1) and B6(-D5, -H1). It is worth noting that the chip module 120 preferably avoids overlapping with the stripe projection area 110 to prevent excessive compression of the chip during use of the dual-interface smart card. Therefore, the area enclosed by the left antenna and the left edge of the card cannot be used to install the chip module.

[0117] Based on this, considering only the first and second strong constraints, the preferred location area of ​​the chip module also includes the resistance projection area, the imprint projection area, and the central axis. That is, the preferred location area of ​​the chip module is: area 1-5, which can overlap with the central axis.

[0118] Considering the first strong constraint, the second strong constraint, and the first weak constraint, the preferred location area of ​​the chip module projection area also includes the resistance projection area and the part of the central axis that does not overlap with the imprint projection area. That is, the preferred location area of ​​the chip module is: area 1-area 4, and it can overlap with the central axis.

[0119] Considering the first strong constraint, the second strong constraint, and the second weak constraint, the preferred location area of ​​the chip module projection area also includes the parts of the resistance projection area and the imprinting projection area that do not overlap with the central axis. That is, the preferred location area of ​​the chip module is: area 1-area 5, which do not overlap with the central axis.

[0120] Considering the first strong constraint, the second strong constraint, and the third weak constraint, the preferred location area of ​​the chip module projection area also includes the part of the central axis and the imprint projection area that does not overlap with the resistance projection area. That is, the preferred location areas of the chip module are: area 1-2 and area 5, and can overlap with the central axis.

[0121] Considering the first strong constraint, the second strong constraint, the first weak constraint, and the second weak constraint, the preferred location area of ​​the chip module projection area also includes the part of the resistance projection area that does not overlap with the central axis and the imprint projection area. That is, the preferred location area of ​​the chip module is the part of region 1-3 and region 4 that does not overlap with region 5 and does not overlap with the central axis.

[0122] Considering the first strong constraint, the second strong constraint, the first weak constraint, and the third weak constraint, the preferred location area of ​​the chip module projection region also includes the part of the central axis that does not overlap with the resistance projection region and the imprint projection region. That is, the preferred location area of ​​the chip module is: region 1-2, which can overlap with the central axis.

[0123] Considering the first strong constraint, the second strong constraint, the second weak constraint, and the third weak constraint, the preferred location area of ​​the chip module projection area also includes the part of the imprint projection area that does not overlap with the resistance projection area and the central axis, that is, the part of region 1-2 and region 5 that does not overlap with region 3-4 and does not overlap with the central axis.

[0124] Referring to Figure 3B, this is the second schematic diagram of the substrate layer structure corresponding to the new dual-interface smart card winding-same-layer-antenna half-winding in a specific embodiment of the present invention. Referring to Figure 3C, this is the third schematic diagram of the substrate layer structure corresponding to the new dual-interface smart card winding-same-layer-antenna half-winding in a specific embodiment of the present invention. Referring to Figure 3B, when the chip module is located in area A (i.e., the area formed by A1, A2, A3, and A4 in Figure 3A), the first connection structure needs to connect to the chip module by crossing the antenna winding. Preferably, the crossing position is located in the antenna bend area to reduce mechanical stress damage caused by the overlap between the antenna and the first connection structure, thereby improving the reliability of the smart card. Referring to Figure 3C, when the chip module is located in area B (i.e., the area formed by B1, B2, B3, and B4 in Figure 3A), the first connection structure can connect to the chip module without crossing the antenna winding, but some antenna leads will cross the antenna winding to achieve the connection between the antenna terminal and the chip module. When the first connecting structure does not cross the antenna winding and is located outside the antenna winding area, it should also not be placed in the embossed area to avoid damage from subsequent card manufacturing embossing. Of course, in special designs, such as conductive metal foil etching schemes, the damage from embossing can be overcome by widening the first connecting structure, and the first connecting structure can be placed in the embossed area. This solution is a mature technology and will not be described in detail in this invention.

[0125] Positional relationship between the first connection structure, the antenna, and the substrate layer structure

[0126] As can be seen from the foregoing embodiments, for the substrate layer 100 of the dual-interface smart card of this embodiment, the first connection structure and the antenna have overlapping (i.e., they are on the same layer) projection areas on the normal plane of the target surface of the carrier layer. The target surface of the substrate layer 100 is the surface with the largest area of ​​the substrate layer 100, and the normal plane of the target surface refers to the plane where the normal of the target surface is located.

[0127] The antenna and the first connection structure can be generated by methods including but not limited to wire winding or etching. For the wire winding method, both the first connection structure and the antenna are enameled conductive wires; for the etching method, both the first connection structure and the antenna are conductive metal foils.

[0128] Simultaneously, corresponding to the wire-winding method, the strip module mounting area includes five closely wound first connection structure terminals. The projection area corresponding to each closely wound first connection structure terminal matches the projection area corresponding to the effective contact after the strip module is installed. Electrical connection between the strip module and the first connection structure terminals can be achieved using anisotropic conductive adhesive. Corresponding to the etching method, the strip module mounting area includes five etched pad-type first connection structure terminals. The projection area corresponding to each etched pad-type first connection structure terminal matches the projection area corresponding to the effective contact after the strip module is installed. Electrical connection between the strip module and the first connection structure terminals can be achieved using anisotropic conductive adhesive or soldering. The chip module 120 is mounted on the substrate layer using methods including but not limited to COB (chip on board) packaging and WLCSP (Wafer Level Chip Scale Packaging). Preferably, for the wire-winding method, the chip module 120 is packaged using COB packaging.

[0129] Based on this, the structure of the substrate layer 100 of the dual-interface smart card in this embodiment of the invention will be different depending on the generation method of different antennas and the first connection structure.

[0130] Specifically, refer to Figure 4-4L, which is a cross-sectional view of Figure 1 along the AA direction. The first connecting structure is on the same layer as the antenna, and the conductive channel is fabricated using a winding method. The final installed strip module and chip module are mounted on the same side of the substrate layer, i.e., the chip module is mounted upright. Figure 4A shows the cross-section during the chip module installation process, and Figures 4B-4L show the cross-section after the chip module is installed. Refer to Figures 4M-4V, which are one of the distorted top views of Figure 1 (the chip module is represented by a dashed line), a cross-sectional view along the AA direction. The first connecting structure is on the same layer as the antenna, and the conductive channel is fabricated using a winding method. The final installed strip module and chip module are mounted on opposite sides of the substrate layer, i.e., the chip module is mounted upside down. Figure 4M shows the cross-section during the chip module installation process, and Figures 4N-4V show the cross-section after the chip module is installed. It should be understood that the full-winding method used for the antenna in Figure 1 is only an example; the actual use of 3 / 4 winding and 2 / 3 winding methods also applies. As shown in Figure 4-4V, in this embodiment of the invention, the carrier layer of substrate layer 100 can be a single layer, or formed by laminating a first sub-substrate layer (i.e., layer 1 in the figure) and a second sub-substrate layer (i.e., layer 2 in the figure), or alternatively, formed by laminating a first sub-substrate layer, a second sub-substrate layer, and a third sub-substrate layer (i.e., layer 3 in the figure). The largest non-laminated surface of the first sub-substrate layer and the largest non-laminated surface of the second sub-substrate layer constitute the target surface of the carrier layer; the first connection structure and the antenna are simultaneously carried by the first sub-substrate layer or the second sub-substrate layer. The laminated surface is the surface laminated with another sub-substrate layer, and the non-laminated surface is the surface not laminated with another sub-substrate layer. To facilitate characterizing the positional differences between the same side and opposite sides, this embodiment of the invention first describes the substrate layer structure and the corresponding surfaces of the chip module in the strip module mounting area. Specifically, the first surface of the substrate layer structure (carrier layer, first sub-substrate layer, second sub-substrate layer, and third sub-substrate layer) refers to the surface with the largest area in the substrate layer that is closest to the strip module to be finally installed. The second surface of the substrate layer refers to the surface with the largest area in the substrate layer that is furthest from the strip module to be finally installed. The first surface of the chip module refers to the surface with the largest area in the chip module that does not have an electrical connection structure. In the case where the chip module adopts on-board chip COB packaging, it refers to the surface with the largest area in the substrate that does not have a chip installed.

[0131] It is worth noting that, in the embodiments of the present invention, the first surface associated with the carrier layer, substrate layer or sub-substrate layer refers to the surface with the largest area and the closest vertical distance to the finally installed strip module, and the second surface refers to the surface with the largest area and the farthest vertical distance to the finally installed strip module; the first sub-substrate layer refers to the sub-substrate layer with the closest vertical distance to the finally installed strip module, and the second sub-substrate layer refers to the sub-substrate layer with the farthest vertical distance to the finally installed strip module.

[0132] Based on this, the relationship between the chip module and the substrate layer can be divided into: upright chip module and flip-chip chip module. As shown in Figure 4-4L, when the chip module is upright, the vertical distance between the first surface of the chip module and the first surface of the carrier layer (or the first surface of the first sub-substrate layer) is less than the vertical distance between the first surface of the chip module and the second surface of the carrier layer (or the second surface of the second sub-substrate layer). As shown in Figure 4M-4V, when the chip module is flip-chip, the vertical distance between the first surface of the chip module and the second surface of the carrier layer (or the second surface of the second sub-substrate layer) is less than the vertical distance between the first surface of the chip module and the first surface of the carrier layer (or the first surface of the first sub-substrate layer).

[0133] More specifically, referring to Figure 4, for the case where the substrate layer 100 has a single carrier layer, the situation can be further subdivided into two sub-situations based on the positions of the first connecting structure and the antenna: The first sub-situation is where the first connecting structure and the antenna are located near the same surface of the carrier layer. Based on their positional relationship within the carrier layer, this sub-situation can be further divided into two sub-situations: the first connecting structure and the antenna are simultaneously near either the first or second surface of the carrier layer. The second sub-situation is where the first connecting structure and the antenna are located near different surfaces of the carrier layer. Based on their positional relationship within the carrier layer, this sub-situation can also be divided into two sub-situations: the first connecting structure and the antenna are respectively near either the first or second surface of the carrier layer. Figure 4 only shows one of these situations as an example.

[0134] Furthermore, as shown in Figure 4, when the chip module is mounted upright or upside down, the chip module is installed through the mounting holes provided in the carrier layer. The terminals of the first connection structure and the antenna are exposed in the mounting holes, so that the first surface of the chip module can be flush with the first surface or the second surface of the carrier layer. The terminals of the first connection structure and the antenna are electrically connected to the conductive channel contact pads of the chip module.

[0135] Referring to Figures 4A-4K, 4M-4N, and 4P-4V, for the case where the carrier layer of substrate layer 100 is formed by laminating a first sub-substrate layer (i.e., layer 1 in the figure) and a second sub-substrate layer (i.e., layer 2 in the figure), it can be further subdivided into the following two sub-cases based on the positions of the first connecting structure and the antenna: The first sub-case is where the first connecting structure and the antenna are simultaneously carried by the first sub-substrate layer. Based on the positional relationship between the first connecting structure and the antenna within the sub-substrate layer, the first sub-case can be further divided into four sub-cases: the first connecting structure and the antenna are simultaneously adjacent to either the first or second surface of the first sub-substrate layer; and the first connecting structure and the antenna are respectively adjacent to either the first or second surface of the first sub-substrate layer. The second sub-case is where the first connecting structure and the antenna are simultaneously carried by the second sub-substrate layer. Based on the positional relationship between the first connecting structure and the antenna within the sub-substrate layer, the second sub-case can also be divided into four sub-cases: the first connecting structure and the antenna are simultaneously adjacent to either the first or second surface of the second sub-substrate layer; and the first connecting structure and the antenna are respectively adjacent to either the first or second surface of the second sub-substrate layer. It is worth noting that the first connection structure can be embedded or semi-embedded on the first or second surface of the carrier layer and the sub-substrate layer when the conductive channel is made by winding.

[0136] Furthermore, referring to Figures 4A-4K, when the chip module is mounted upright, it is installed through the first mounting hole (mounting hole 1) in sub-substrate layer 1 (i.e., the first sub-substrate layer) and the second mounting hole (mounting hole 2) in sub-substrate layer 2 (i.e., the second sub-substrate layer). Referring to Figures 4M-4N and 4P-4V, when the chip module is mounted flip-chip, it is installed through the second mounting hole (mounting hole 2) in sub-substrate layer 1 (i.e., the first sub-substrate layer) and the first mounting hole (mounting hole 1) in sub-substrate layer 2 (i.e., the second sub-substrate layer).

[0137] Preferably, the size of the first mounting hole is the same as the size of the chip module substrate, and the size of the second mounting hole is larger than the size of the encapsulating adhesive to accommodate the protruding portion of the chip module encapsulation area. The size of the first mounting hole is larger than the size of the second mounting hole.

[0138] In one embodiment of the present invention, the orthographic projection area of ​​the conductive channel contact pad of the chip module on the target surface of the carrier layer overlaps with the orthographic projection area of ​​the second mounting hole on the target surface of the carrier layer. That is, the second mounting hole exposes each conductive channel contact pad disposed on the chip module substrate to the second mounting hole. At the same time, the second mounting hole overlaps with the orthographic projection area of ​​the second surface of the second sub-substrate layer on the normal plane of the target surface of the carrier layer. That is, the second mounting hole penetrates the second sub-substrate layer (as shown in FIG. 4B). Based on this, the stepped surface formed between the sub-substrate layer 1 and the sub-substrate layer 2 can support the conductive channel contact pad of the chip module. After the chip module is installed, the upper surface of the substrate (i.e., the first surface of the chip module) is flush with the upper surface of the sub-substrate layer 1 (i.e., the first surface of the first sub-substrate layer), which can minimize the impact on subsequent card manufacturing processes. Meanwhile, based on the aforementioned embodiments, when the chip module is installed, the first connection structure terminal and the antenna terminal overlap with the matching conductive channel contact pad in the vertical direction. Therefore, the electrical connection process between the first connection structure terminal and the antenna terminal and the matching conductive channel contact pad can be realized through the second mounting hole, such as spot welding.

[0139] Furthermore, the orthographic projection area of ​​the conductive channel contact pad of the chip module on the target surface of the carrier layer does not overlap with the orthographic projection area of ​​the second mounting hole on the target surface of the carrier layer, that is, the conductive channel contact pad is not exposed in the second mounting hole (as shown in Figure 4D), or the conductive channel contact pad is partially exposed in the second mounting hole, but the orthographic projection area of ​​the second mounting hole and the second surface of the second sub-substrate layer on the normal plane of the target surface of the carrier layer does not overlap (the second mounting hole does not penetrate the second surface of the second sub-substrate layer, as shown in Figure 4C). In this embodiment of the invention, holes can be drilled in the corresponding sub-substrate layer in the projection area corresponding to the conductive channel contact pad (i.e., welding holes in Figures 4C-4D) so that the first connection structure terminal and the antenna terminal are exposed simultaneously through the welding holes, and then the welding process, such as spot welding, is realized by the welding holes to the first connection structure terminal and the antenna terminal with the matching conductive channel contact pad. When the first mounting hole is located in the first sub-substrate layer, a plurality of welding holes matching the antenna terminal and the first connection structure terminal are provided in the second sub-substrate layer (as shown in Figures 4C and 4D); when the first mounting hole is located in the second sub-substrate layer, a plurality of welding holes matching the antenna terminal and the first connection structure terminal are provided in the first sub-substrate layer, but this case is not shown; it is worth noting that in subsequent embodiments of the present invention, the welding of the first connection structure terminal and the antenna terminal to the matching conductive channel contact pad can be completed using the second mounting holes or welding holes shown in Figures 4B-4D. For the sake of simplifying the illustration, the embodiments of the present invention have not shown them one by one.

[0140] Based on the foregoing, it can be understood that the first connection structure terminal and the antenna terminal overlap with the matching conductive channel contact pad in the vertical direction. Therefore, the welding of the first connection structure terminal and the antenna terminal to the matching conductive channel contact pad can be achieved through the aforementioned second mounting hole or welding hole. Based on this, the relative positional relationship between the first connection structure terminal and the antenna terminal and the matching conductive channel contact pad in the dual-interface smart card substrate layer has been clearly stated. Therefore, for the sake of simplified illustration, this embodiment of the invention only shows the first connection structure terminal and the antenna terminal electrically connected to the conductive channel contact pad in some cross-sectional views. Meanwhile, in the actual product structure, the orthographic projection area of ​​the first connection structure on the normal plane of the target surface of the carrier layer overlaps with the orthographic projection areas of the strip module and the chip module on the normal plane of the target surface of the carrier layer, respectively. Based on the foregoing, it can also be understood that since there are many first connection structures, showing them all would affect the representation of the relative positional relationship between the first connection structure and the antenna in the cross-sectional views. Therefore, this embodiment of the invention only shows one set of first connection structures in all cross-sectional views. However, it is understood that the dual-interface smart card substrate layer of this embodiment of the invention actually includes multiple sets of first connection structures, which is hereby declared in this embodiment of the invention.

[0141] Based on Figures 4L and 4O, the dual-interface smart card substrate layer of this embodiment of the invention further includes a third sub-substrate layer (i.e., sub-substrate layer 3 in Figures 4L and 4O). After the chip module and the antenna carried by the sub-substrate layer are electrically connected and assembled with the first connection structure, the third sub-substrate layer can be pressed together with the first sub-substrate layer or the second sub-substrate layer to provide better support for the substrate layer. The figures only show the case where the third sub-substrate layer is pressed together with the second sub-substrate layer.

[0142] Based on Figures 3B and 3C in the aforementioned embodiments, it can be seen that when the first connecting structure is on the same layer as the antenna, the conductive channel is fabricated by a winding method, and the antenna winding is half-winding, in the top view of the dual-interface smart card substrate layer, there are two positional relationships between the first connecting structure and the antenna: the first is that the first connecting structure needs to cross the antenna winding through the antenna bend area to connect to the chip module (as shown in Figure 3B); the second is that the first connecting structure can connect to the chip module without crossing the antenna winding, but some antenna leads will cross the antenna winding to achieve the connection between the antenna terminal and the chip module (as shown in Figure 3C). For the above two situations, Figure 4Z is a top view of the new dual-interface smart card of the present invention (corresponding to the situation shown in Figure 3B), and Figure 4Z' is a cross-sectional structural diagram of Figure 4Z along the AA direction. As shown in Figures 4Z and 4Z', the difference between a dual-interface smart card substrate layer with a half-wound antenna and one with a full-wound, 3 / 4-wound, or 2 / 3-wound antenna lies in the location of the antenna or the first connecting structure in the top view. Correspondingly, the horizontal position of the cross-sectional structure corresponding to the antenna winding or the first connecting structure differs in the cross-sectional structural diagram. Based on this, it can be understood that the situation shown in Figure 3C is similar, and will not be shown in the image here. It is worth noting that although Figures 4Z and 4Z' only show the dual-interface smart card substrate layer structure corresponding to the case where the carrier layer is composed of two sub-substrate layers and the antenna and the first connection structure are respectively close to the first surface and the second surface of the first sub-substrate layer, the one-layer, two-layer, or three-layer substrate layer structures involved in the aforementioned embodiments, the chip module mounting methods of upright and flip-chip mounting, the electrical connection method of welding the first connection structure terminals and antenna terminals to the matching conductive channel contact pads or solder balls using mounting holes or solder holes, and the vertical layout of the first connection structure and antenna in the substrate layer are all applicable to dual-interface smart card substrate layers where the antenna winding is semi-wound. For the sake of simplifying the illustration, the present invention has not shown them all.

[0143] Referring to Figure 4W, which illustrates a novel dual-interface smart card according to a specific embodiment of the present invention, Figures 4X and 4Y are cross-sectional structural diagrams along the AA direction of Figure 4W, showing the upright and inverted configurations of the chip module. Based on Figure 4X, it can be seen that, depending on variations in thickness and usage conditions, the dual-interface smart card of this embodiment further includes a supplementary support layer and a strip module. The supplementary support layer is respectively pressed onto the first and second surfaces of the carrier layer, or the first and second sub-substrate layers, or the first and third sub-substrate layers. The supplementary support layer can be made of materials such as PVC, and other materials can be used to form the upper and lower surfaces of the smart card; this embodiment of the present invention does not specifically limit this. It is worth noting that Figures 4X and 4Y only show the dual-interface smart card structure corresponding to the case where the carrier layer consists of two sub-substrate layers and the first connection structure and the antenna are simultaneously adjacent to the first surface of the first sub-substrate layer. Based on the aforementioned embodiments, it can be seen that the same applies to the case where the carrier layer consists of one or three sub-substrate layers, the first connection structure and the antenna are located in other positions, and the chip module is mounted upright or flipped to fit each other. For the sake of simplifying the illustration, the present invention has not shown them one by one.

[0144] After the supplementary support layer is laminated and supported onto the smart card substrate layer, the strip module will be installed. The strip module includes contact pads, a support layer, and multiple conductive pads arranged from top to bottom. By slotting the corresponding strip mounting area in the supplementary support layer and substrate layer, the terminals of the first connection structure are exposed, and the strip module is installed. The conductive pads of the strip module are electrically connected to the matching first connection structure terminals in the substrate layer via anisotropic conductive adhesive or solder balls. The contact surface of the contact pads of the strip module is on the same plane as the first surface of the supplementary support layer. The contact surface of the contact pad refers to the surface of the contact pad that physically contacts an external terminal (e.g., a card reader) for communication. It is understood that the thickness of the support layer and conductive pads in the strip module can be adjusted according to process requirements.

[0145] Specifically, referring to Figures 5 and 5B, which are cross-sectional view diagrams along the AA direction of Figure 1; Figure 5C, a second distorted top view of Figure 1 (with the antenna and first connecting structure becoming solid lines), is a cross-sectional view along the AA direction; and Figure 5E, one of the distorted top views of Figure 1 (with the chip module becoming dashed lines), is a cross-sectional view along the AA direction. Correspondingly, the first connecting structure and the antenna are on the same layer, the conductive channel is fabricated by etching, and the final installed strip module and chip module are installed on the same side of the substrate layer, i.e., the chip module is mounted upright. Figures 5, 5B, 5C, and 5E show the cross-sections of the chip module after installation. The corresponding cross-sections of the chip module installation process are similar to those in Figure 4A, and will not be shown individually in this embodiment of the invention. Referring to Figure 5A, a distorted top view of Figure 1 (the chip module is represented by dashed lines), it shows a cross-sectional structure along the AA direction. Figures 5D and 5F are distorted top views of Figure 1 again (the antenna and the first connecting structure are represented by solid lines), showing cross-sectional structures along the AA direction. The first connecting structure and the antenna are on the same layer, and the conductive channels are fabricated using etching. The final installed strip module and the chip module are located on opposite sides of the substrate layer, i.e., the chip module is flip-chip mounted. Figures 5A, 5D, and 5F show the cross-sections of the chip module after installation. The cross-sections of the chip module installation process are similar to those in Figure 4M, and will not be shown individually in this embodiment. It is understood that the full-card wiring method used for the antenna in Figure 1 is only an example; the actual use of 3 / 4 wiring and 2 / 3 wiring methods also applies. As shown in Figures 5-5H, in this embodiment of the invention, the carrier layer of substrate layer 100 can be a single layer, or formed by laminating a first sub-substrate layer (i.e., layer 1 in the figure) and a second sub-substrate layer (i.e., layer 2 in the figure), or alternatively, formed by laminating a first sub-substrate layer, a second sub-substrate layer, and a third sub-substrate layer. The largest non-laminated surface of the first sub-substrate layer and the largest non-laminated surface of the second sub-substrate layer constitute the target surface of the carrier layer; the first connection structure and the antenna are simultaneously carried by the first sub-substrate layer or the second sub-substrate layer. The laminated surface is the surface laminated with another sub-substrate layer, and the non-laminated surface is the surface not laminated with another sub-substrate layer.To facilitate characterizing the positional differences between the same side and opposite sides, this embodiment of the invention first describes the substrate layer structure and the corresponding surfaces of the chip module in the strip module mounting area. Specifically, the first surface of the substrate layer structure (carrier layer, first sub-substrate layer, second sub-substrate layer, and third sub-substrate layer) refers to the surface with the largest area in the substrate layer that is closest to the strip module to be finally installed. The second surface of the substrate layer refers to the surface with the largest area in the substrate layer that is furthest from the strip module to be finally installed. The first surface of the chip module refers to the surface with the largest area in the chip module that does not have an electrical connection structure. When the chip module adopts on-board chip COB packaging, it refers to the surface with the largest area in the substrate that does not have a chip installed. When the chip module adopts wafer-level chip WLCSP packaging, it refers to the surface with the largest area in the chip that does not have solder balls.

[0146] It is worth noting that, in the embodiments of the present invention, the first surface associated with the carrier layer, substrate layer or sub-substrate layer refers to the surface with the largest area and the closest vertical distance to the finally installed strip module, and the second surface refers to the surface with the largest area and the farthest vertical distance to the finally installed strip module; the first sub-substrate layer refers to the sub-substrate layer with the closest vertical distance to the finally installed strip module, and the second sub-substrate layer refers to the sub-substrate layer with the farthest vertical distance to the finally installed strip module.

[0147] Based on this, the relationship between the chip module and the substrate layer can be divided into: upright chip module and flip-chip chip module. Considering the thickness of the chip module, as shown in Figures 5, 5B, 5C, and 5E, when the chip module is upright, the vertical distance between the first surface of the chip module and the first surface of the carrier layer (or the first surface of the first sub-substrate layer) is less than the vertical distance between the first surface of the chip module and the second surface of the carrier layer (or the second surface of the second sub-substrate layer). As shown in Figures 5A, 5D, and 5F, when the chip module is flip-chip, the vertical distance between the first surface of the chip module and the second surface of the carrier layer (or the second surface of the second sub-substrate layer) is less than the vertical distance between the first surface of the chip module and the first surface of the carrier layer (or the first surface of the first sub-substrate layer).

[0148] More specifically, referring to Figures 5C and 5D, for the case where the substrate layer 100 has a single carrier layer, it can be further subdivided into the following two sub-cases based on the positions of the first connecting structure and the antenna: The first sub-case is where the first connecting structure and the antenna are simultaneously supported on the first surface of the carrier layer; the second sub-case is where the first connecting structure and the antenna are simultaneously supported on the second surface of the carrier layer. Figures 5C and 5D only show one of the above cases as examples.

[0149] Referring to Figures 5-5A and 5E-5H, for the case where the carrier layer of substrate layer 100 is formed by laminating the first sub-substrate layer (i.e., layer 1 in the figure) and the second sub-substrate layer (i.e., layer 2 in the figure), it can be further subdivided into the following three sub-cases based on the positions of the first connecting structure and the antenna: The first sub-case is where the first connecting structure and the antenna are simultaneously carried by the first surface of the first sub-substrate layer; the second sub-case is where the first connecting structure and the antenna are simultaneously carried by the first surface of the second sub-substrate layer; and the third sub-case is where the first connecting structure and the antenna are simultaneously carried by the second surface of the second sub-substrate layer. It is worth noting that when the antenna and the first connecting structure are fabricated by etching, they can be carried by the substrate's layer structure using floating, embedded, or semi-embedded methods. It should be noted that Figure 5G is a cross-sectional view along the AA direction of Figure 1 in a modified top view (the antenna and the first connecting structure are replaced by solid lines). Figure 5H is a cross-sectional view along the AA direction of Figure 1 in a modified top view (the chip module is replaced by dashed lines). For the cross-sectional structural diagrams shown in Figures 5G and 5H, the chip module can be mounted either upright or upside down.

[0150] More specifically, referring to Figure 5-5H, based on the packaging form of the chip module, it can be further subdivided into the following two scenarios: The first seed scenario is that the chip module uses COB packaging. The second seed scenario is that the chip module uses WLCSP packaging.

[0151] When the chip module is COB packaged, the carrier layer is preferably formed by laminating the first sub-substrate layer (i.e., layer 1 in the figure) and the second sub-substrate layer (i.e., layer 2 in the figure), and the antenna and the first connection structure are carried on the first surface of the second sub-substrate layer.

[0152] As shown in Figure 5, when the chip module is mounted upright, it is mounted through the first mounting hole (mounting hole 1) in sub-substrate layer 1 (i.e., the first sub-substrate layer) and the second mounting hole (mounting hole 2) in sub-substrate layer 2 (i.e., the second sub-substrate layer). As shown in Figure 5A, when the chip module is mounted flip-chip, it is mounted through the second mounting hole (mounting hole 2) in sub-substrate layer 1 (i.e., the first sub-substrate layer) and the first mounting hole (mounting hole 1) in sub-substrate layer 2 (i.e., the second sub-substrate layer).

[0153] Preferably, the size of the first mounting hole is the same as the size of the chip module substrate, and the size of the second mounting hole is larger than the size of the encapsulating adhesive to accommodate the protruding portion of the chip module encapsulation area. The size of the first mounting hole is larger than the size of the second mounting hole.

[0154] In one embodiment of the present invention, similar to the wire-winding method, the orthographic projection area of ​​the conductive channel contact pads of the chip module on the target surface of the carrier layer overlaps with the orthographic projection area of ​​the second mounting hole on the target surface of the carrier layer. That is, the second mounting hole exposes each conductive channel contact pad on the chip module substrate to the second mounting hole. At the same time, the second mounting hole overlaps with the orthographic projection area of ​​the second surface of the second sub-substrate layer on the normal plane of the target surface of the carrier layer. That is, the second mounting hole penetrates the second sub-substrate layer (as shown in Figure 4B, this is only for describing the mounting hole and solder hole. It can be understood that this embodiment is for the etching wiring method and the chip module is COB packaged, the same below). Based on this, the stepped surface formed between the sub-substrate layer 1 and the sub-substrate layer 2 can support the conductive channel contact pads of the chip module. After the chip module is installed, the upper surface of the substrate (i.e., the first surface of the chip module) is flush with the upper surface of the sub-substrate layer 1 (i.e., the first surface of the first sub-substrate layer), which can minimize the impact on subsequent card manufacturing processes. Meanwhile, based on the aforementioned embodiments, when the chip module is installed, the first connection structure terminal and the antenna terminal overlap with the matching conductive channel contact pad in the vertical direction. Therefore, the electrical connection process between the first connection structure terminal and the antenna terminal and the matching conductive channel contact pad can be achieved through the second mounting hole, such as welding or conductive adhesive pressing.

[0155] Furthermore, for cases where the conductive channel contact pad is not exposed in the second mounting hole (as shown in Figure 4D), or the conductive channel contact pad is partially exposed in the second mounting hole, but the second mounting hole and the orthographic projection area of ​​the second surface of the second sub-substrate layer on the normal plane of the target surface of the carrier layer do not overlap (the second mounting hole does not penetrate the second surface of the second sub-substrate layer, as shown in Figure 4C), embodiments of the present invention can also drill holes in the corresponding projection area of ​​the conductive channel contact pad in the corresponding sub-substrate layer (i.e., welding holes in Figures 4C-4D), so that the first connection structure terminal and the antenna terminal are simultaneously exposed through the welding holes, and then the welding process of the first connection structure terminal and the antenna terminal with the matching conductive channel contact pad is realized through the welding holes, such as spot welding, wedge welding, reflow soldering, etc. When the first mounting hole is located in the first sub-substrate layer, multiple solder holes matching the antenna terminal and the first connection structure terminal are provided in the second sub-substrate layer (as shown in Figures 4C and 4D); when the first mounting hole is located in the second sub-substrate layer, multiple solder holes matching the antenna terminal and the first connection structure terminal are provided in the first sub-substrate layer, but this case is not shown. It is worth noting that in subsequent embodiments of the present invention, the second mounting holes or solder holes shown in Figures 4B-4D can be used to complete the welding or conductive adhesive bonding of the first connection structure terminal and the antenna terminal to the matching conductive channel contact pad. For the sake of simplifying the illustration, not all of them are shown in the embodiments of the present invention. It should be noted that for the case where the etching process matches the COB chip module, the setting of solder holes is not necessary; the electrical connection between the COB chip module and the first connection structure and the antenna terminal can be achieved by conductive adhesive bonding.

[0156] Based on the foregoing, it can be understood that the first connection structure terminal and the antenna terminal overlap with the matching conductive channel contact pad in the vertical direction. Therefore, the welding of the first connection structure terminal and the antenna terminal to the matching conductive channel contact pad can be achieved through the aforementioned second mounting hole or welding hole. Based on this, the relative positional relationship between the first connection structure terminal and the antenna terminal and the matching conductive channel contact pad in the dual-interface smart card substrate layer has been clearly stated. Therefore, for the sake of simplified illustration, this embodiment of the invention only shows the first connection structure terminal and the antenna terminal electrically connected to the conductive channel contact pad in some cross-sectional views. Meanwhile, in the actual product structure, the orthographic projection area of ​​the first connection structure on the normal plane of the target surface of the carrier layer overlaps with the orthographic projection areas of the strip module and the chip module on the normal plane of the target surface of the carrier layer, respectively. Based on the foregoing, it can also be understood that since there are many first connection structures, showing them all would affect the representation of the relative positional relationship between the first connection structure and the antenna in the cross-sectional views. Therefore, this embodiment of the invention only shows one set of first connection structures in all cross-sectional views. However, it is understood that the dual-interface smart card substrate layer of this embodiment of the invention actually includes multiple sets of first connection structures, which is hereby declared in this embodiment of the invention.

[0157] As shown in Figures 5C-5H, when the chip module is WLCSP packaged, the carrier layer can be a single layer (as shown in Figures 5C-5D), or it can include a first sub-substrate layer (i.e., layer 1 in the figure) and a second sub-substrate layer (i.e., layer 2 in the figure) (as shown in Figures 5E-5H). Regardless of whether the chip module is mounted upright or flip-chip, when the first connection structure and the antenna are located between the layer structures of the two sub-substrates, since the WLCSP packaged chip module is relatively thin, the flexible substrate layer can accommodate its thickness. Therefore, there is no need to set mounting holes in the substrate layer. The chip module is soldered to the terminals of the first connection structure and the antenna terminals by solder balls, or electrically connected to the terminals of the first connection structure and the antenna terminals by anisotropic conductive adhesive.

[0158] As shown in Figure 5B, the dual-interface smart card substrate layer of this embodiment of the invention further includes a third sub-substrate layer (i.e., sub-substrate layer 3 in Figure 5B). After the chip module and the antenna carried by the sub-substrate layer are electrically connected and assembled with the first connection structure, the third sub-substrate layer can be pressed together with the first sub-substrate layer or the second sub-substrate layer to provide better support for the substrate layer. The figure only shows the case where the third sub-substrate layer is pressed together with the second sub-substrate layer.

[0159] It is worth noting that the etching method for the conductive metal foil requires that the orthographic projection areas of the first connecting structure and the antenna on the target surface of the carrier layer overlap, meaning that the first connecting structure and the antenna must be located on the same plane. However, in the semi-wrap wiring method, the first connecting structure and / or the antenna may overlap on the orthographic projection plane (as shown in Figures 3B-3C). In the case of overlap, an insulating layer needs to be placed between the conductive metal foils, rather than on the same plane. Therefore, the semi-wrap wiring method cannot be achieved by setting the first connecting structure and the antenna on the same layer (on the same plane).

[0160] Referring to Figure 4W, which is a top view of the novel dual-interface smart card according to a specific embodiment of the present invention, Figures 5I and 5J are schematic cross-sectional views of Figure 4W along the AA direction. As shown in Figure 5I, depending on variations in thickness and usage conditions, the dual-interface smart card of this embodiment further includes a supplementary support layer and a strip module. The supplementary support layer can be laminated to the first and second surfaces of the carrier layer, or the first and second sub-substrate layers, or the first and third sub-substrate layers, respectively. The supplementary support layer can be made of materials such as PVC to form the upper and lower surfaces of the smart card, or other materials; this embodiment of the present invention does not specifically limit its use. It is worth noting that the figure only shows a dual-interface smart card structure in which the chip module is in a COB or WLCSP package and is mounted upright, and the first connection structure and the antenna are located between two sub-substrate layers. Based on the aforementioned embodiments, it is known that the same applies to reasonable combinations of situations where the carrier layer consists of one or three sub-substrate layers, or where the first connection structure and the antenna are located in other positions, or where the chip module is mounted upright or flipped. For the sake of simplifying the illustration, the present invention has not shown them all.

[0161] After the supplementary support layer is laminated and supported onto the smart card substrate layer, the strip module will be installed. The strip module includes contact pads, a support layer, and multiple conductive pads arranged from top to bottom. By slotting the corresponding strip mounting area in the supplementary support layer and substrate layer, the terminals of the first connection structure are exposed, and the strip module is installed. The conductive pads of the strip module are electrically connected to the matching first connection structure terminals in the substrate layer via anisotropic conductive adhesive or solder balls. The contact surface of the contact pads of the strip module is on the same plane as the first surface of the supplementary support layer. The contact surface of the contact pad refers to the surface of the contact pad that physically contacts an external terminal (e.g., a card reader) for communication. It is understood that the thickness of the support layer and conductive pads in the strip module can be adjusted according to process requirements.

[0162] Test Structure

[0163] Referring to Figure 6, which is a schematic diagram of the substrate layer strip module mounting area corresponding to the new dual-interface smart card of this invention, it can be understood that after the chip module is electrically connected and integrated with the first connection structure and antenna, the electrical connectivity of the first connection structure needs to be tested to ensure that the terminals of the first connection structure in the form of tightly wound or etched pads in the strip module mounting area are electrically connected to the chip module, thereby ensuring the pass rate of the dual-interface smart card. To address this issue, this invention proposes an innovative connectivity testing scheme. As shown in Figure 6, this invention exposes the conductive parts in the terminals of the first connection structure by opening test holes in the strip projection area. Test probes can then be inserted into the test holes and contact the conductive parts in the terminals of the first connection structure to perform connectivity testing. Referring to Figure 6, it can be understood that the test holes can be integrated test holes similar to U-grooves, or conventional discrete test holes (i.e., one test hole for each first connection structure terminal). This invention does not specifically limit this. The opening method of the test holes in this invention also differs depending on the conductive channel generation method and the substrate layer structure.

[0164] For the test structure, when the first connection structure and the antenna are located on the same layer or different layers, the first connection structure and the strip module are electrically connected in the strip module mounting area. The connection position of the first connection structure and the strip module is on the same plane. For the test hole, when the first connection structure and the antenna are located on the same layer or different layers, the situation is the same. This invention will not describe them one by one here.

[0165] For the case where the first connection structure and the antenna are located on the same layer and are in a wire-wound configuration, refer to Figures 7 to 7C, which are schematic cross-sectional views of the substrate layer strip module mounting area along the AA direction corresponding to a specific embodiment of the new dual-interface smart card of the present invention. These figures correspond to the cases where the first connection structure is disposed on the first surface of the first sub-substrate layer, the second surface of the first sub-substrate layer, the first surface of the second sub-substrate layer, and the second surface of the second sub-substrate layer, respectively. It is worth noting that the first connection structure corresponding to the wire-wound configuration is embedded or semi-embedded within the substrate layer surface, while the first connection structure corresponding to the etching configuration can be floating, embedded, or semi-embedded within the substrate layer surface. The layer structure of the substrate supports the first connection structure. It is understood that for the terminals of the tightly wound structure, the cross-section can be elliptical or circular. For simplicity, only a rectangle is used to illustrate the cross-section of the first connection structure terminal in the figures.

[0166] Referring to Figures 7 to 7C, the finished substrate layer preferably consists of two sub-substrate layers; the same applies to a single-layer structure. Based on this, the test holes can be configured in two ways: Method 1: Drilling through the sub-substrate layer structure from above the first connecting structure terminal (i.e., in the direction of the first surface of the substrate layer structure) to generate a first type of test hole corresponding to the terminal tightly wrapped around the first connecting structure; Method 2: Drilling through the sub-substrate layer from below the first connecting structure terminal (i.e., in the direction of the second surface of the substrate layer structure) to generate a second type of test hole corresponding to the terminal tightly wrapped around the first connecting structure. It is understood that either the first type of test hole or the second type of test hole can be selected for drilling testing (both cases are shown simultaneously in the figures). The shapes of the first type of test hole and the second type of test hole can be the same or different; this embodiment of the invention does not specifically limit this.

[0167] Specifically, referring to Figure 7, when the first connecting structure is supported on the first surface of the first sub-substrate layer, the first type of test hole penetrates a portion of the first sub-substrate layer, and the second type of test hole penetrates the second sub-substrate layer and a portion of the first sub-substrate layer. Referring to Figure 7A, when the first connecting structure is supported on the second surface of the first sub-substrate layer, the first type of test hole penetrates a portion of the first sub-substrate layer, and the second type of test hole penetrates the second sub-substrate layer and a portion of the first sub-substrate layer. Referring to Figure 7B, when the first connecting structure is supported on the first surface of the second sub-substrate layer, the first type of test hole penetrates the first sub-substrate layer and a portion of the second sub-substrate layer, and the second type of test hole penetrates a portion of the second sub-substrate layer. Referring to Figure 7C, when the first connecting structure is supported on the second surface of the second sub-substrate layer, the first type of test hole penetrates the first sub-substrate layer and a portion of the second sub-substrate layer, and the second type of test hole penetrates a portion of the second sub-substrate layer. It is worth noting that, regardless of whether it is the first type of test hole or the second type of test hole, the drilling depth into the first connection structure is only required to remove the insulating enamel coating on its surface to expose the internal metal wires. Preferably, the depth of the test hole into the first connection structure does not exceed the radius of the first connection structure.

[0168] When fabricating the card, additional support layers need to be laminated onto the first and second surfaces of the substrate layer, and strip modules need to be installed in the strip module mounting area. To install the strip modules, holes need to be drilled in the strip module mounting area on the card structure surface (strip mounting holes). The size of the strip mounting holes is the same as the size of the strip projection area, and the additional support layer, carrier layer or sub-substrate layer (if any) in the corresponding area needs to be removed to expose the tightly wound terminals in the strip mounting area.

[0169] When the opening direction of the strip mounting hole is the same as the opening direction of the test hole, the test hole will be covered by the strip mounting hole, meaning that both the depth and area of ​​the strip mounting hole are larger than those of the test hole. Therefore, the finished dual-interface smart card will not include a test hole. However, it is worth noting that although the depth of the strip mounting hole is greater than the depth of the test hole, its depth into the first connection structure preferably does not exceed the radius of the first connection structure. This avoids reducing the exposed area of ​​the conductive parts of the terminals of the first connection structure, thereby ensuring the electrical connectivity between the finished smart card strip module and the first connection structure.

[0170] When the opening direction of the strip mounting hole is different from the opening direction of the test hole, the test hole will not be covered by the strip mounting hole. Since the area of ​​the test hole is small, the use of the card will not be affected after the supplementary support layer is covered, so there is no need to backfill with filler. Since the supplementary support layer and the bearing layer can be pressed together by hot pressing, there will be some melted material in the test hole, and it is not a complete through hole. For the sake of simplifying the drawings, this is not shown one by one. Based on this, the dual-interface smart card will include a test hole. Of course, it is also possible to backfill the test hole with filler. It is worth noting that the drilling depth of the strip mounting hole needs to remove the enameled layer of the tightly wound terminal of the first connection structure to expose more metal area. In order to establish electrical connection contact with the strip module, since the test hole on the opposite side of the strip mounting hole has already entered the first test structure to a certain depth, the depth of the strip mounting hole into the first connection structure should not be too deep, preferably not exceeding the radius of the conductor of the first connection structure. On the one hand, this prevents the metal part of the first connection structure from being penetrated and damaged, and on the other hand, it ensures that the exposed area of ​​the conductive metal part is as large as possible to enhance the conductive contact.

[0171] Referring to Figures 7D-7E, which are cross-sectional structural diagrams of the installation area of ​​the new dual-interface smart card strip module along the AA direction in a specific embodiment of the present invention, corresponding to the winding form, and as shown in Figures 7D-7E, if the opening direction of the strip mounting hole is the same as the opening direction of the test hole, the test hole will be covered by the strip mounting hole, that is, the depth of the strip mounting hole is greater than the depth of the test hole. Based on this, the finished dual-interface smart card will not contain a test hole (as shown in Figure 7E). However, if the opening direction of the strip mounting hole is different from the opening direction of the test hole, the test hole will not be covered by the strip mounting hole. Based on this, the finished dual-interface smart card will contain a test hole (as shown in Figure 7D). It is worth noting, however, that although the depth of the strip mounting hole is greater than the depth of the test hole, its depth into the first connecting structure preferably cannot exceed the radius of the first connecting structure. It is understood that in practical applications, embodiments of the present invention can also add a third sub-substrate layer according to the thickness of the card. The test opening can be set after the third sub-substrate layer is installed, or the third sub-substrate layer can be installed after the opening test is completed. The former may result in the presence of test hole structures in the third sub-substrate layer (if the test hole is located on the side where the third sub-substrate layer is installed), while the latter will result in a complete third sub-substrate layer structure. For better support, it is preferable to install the third sub-substrate layer after completing the hole testing.

[0172] For the case where the first connection structure and the antenna are located on the same layer, and the conductive channel is generated by etching, refer to Figures 8 to 8A, which are schematic cross-sectional views of the substrate layer strip module mounting area along the AA direction corresponding to the new dual-interface smart card of the present invention. These figures correspond to the cases where the carrier layer is a single layer and the first connection structure is located on the first surface of the carrier layer, and the carrier layer is two layers and the first connection structure is supported between two sub-substrate layers.

[0173] As shown in Figure 8A, the finished substrate layer preferably consists of two sub-substrate layers. Based on this, the test holes include two configuration methods: Method 1 involves drilling through the sub-substrate layer above the first connection structure terminal to create a first type of test hole corresponding to the etched pad-shaped first connection structure terminal; Method 2 involves drilling through the sub-substrate layer below the first connection structure terminal to create a second type of test hole corresponding to the etched pad-shaped first connection structure terminal. It is understood that either the first type or the second type of test hole can be selected for drilling and testing (both cases are shown simultaneously in the figure). The shapes of the first type and the second type of test holes can be the same or different; this embodiment of the invention does not specifically limit this.

[0174] Specifically, referring to Figure 8, when the first connection structure is supported on the first surface of the first sub-substrate layer, it is not necessary to open a first type of test hole to access the etched pad terminals of the first connection structure for testing. There are no first type of test holes in the substrate layer; only second type of test holes exist that penetrate the first sub-substrate layer. Referring to Figure 8A, when the first connection structure is supported between two sub-substrate layers, either the first type of test hole penetrates the first sub-substrate layer, or the second type of test hole penetrates the second sub-substrate layer. It is worth noting that, regarding the etching method, since the first connection structure in the form of etched pads is relatively thin, both the first and second type of test holes expose only the etched pads in the depth direction, avoiding penetration into the first connection structure as much as possible. This is to prevent the etched pad-type first connection structure from perforating or breaking and failing, thus affecting the electrical connectivity between the finished smart card strip module and the first connection structure.

[0175] When fabricating the card, additional support layers need to be laminated onto the first and second surfaces of the substrate layer, and strip modules need to be installed in the strip module mounting area. To install the strip modules, holes (strip mounting holes) need to be drilled in the strip module mounting area on the card structure surface. The size of the strip mounting holes is the same as the size of the strip projection area, and the additional support layer, carrier layer or sub-substrate layer (if any) in the corresponding area needs to be removed to expose the etched pad terminals of the first connection structure in the strip mounting area.

[0176] If the opening direction of the strip mounting hole is the same as the opening direction of the test hole, the test hole will be covered by the strip mounting hole, meaning the depth of the strip mounting hole is the same as the depth of the test hole. Therefore, the finished dual-interface smart card will not include a test hole.

[0177] However, if the opening direction of the strip mounting hole is different from the opening direction of the test hole, the test hole will not be covered by the strip mounting hole. Since the test hole area is small, the use of the card is not affected after the supplementary support layer is used, therefore backfilling is unnecessary. Because the supplementary support layer and the load-bearing layer can be bonded by hot pressing, some molten material will exist in the test hole, making it not a completely through hole. For the sake of simplicity, this is not shown in detail in the accompanying drawings. Therefore, the finished dual-interface smart card will include a test hole. Of course, backfilling the test hole with material is also possible.

[0178] Referring to Figures 8B-8E, which are schematic cross-sectional views of the mounting area of ​​the new dual-interface smart card strip module along the AA direction in a specific embodiment of the present invention, and corresponding to the etching pattern, as shown in Figures 8B-8E, if the opening direction of the strip mounting hole is the same as the opening direction of the test hole, the test hole will be covered by the strip mounting hole, that is, the depth of the strip mounting hole is the same as the depth of the test hole. Therefore, the finished dual-interface smart card will not contain a test hole (as shown in Figures 8B and 8D). However, if the opening direction of the strip mounting hole is different from the opening direction of the test hole, the test hole will not be covered by the strip mounting hole. Therefore, the finished dual-interface smart card will contain a test hole (as shown in Figures 8C and 8E).

Claims

1. A dual-interface smart card substrate layer, characterized in that, include: The carrier layer, the first connection structure, the antenna, and the chip module; The first connection structure, the antenna, and the chip module are all carried by the carrier layer, and the first connection structure and the antenna are electrically connected to the chip module respectively; The first connection structure and the antenna have overlapping orthographic projection areas on the normal plane of the target surface of the carrier layer; the chip module and the strip module mounting area of ​​the carrier layer do not overlap in the orthographic projection areas of the target surface of the carrier layer. Wherein, the target surface of the bearing layer is one of the surfaces with the largest area of ​​the bearing layer, and the normal plane of the target surface refers to the plane in which the normal of the target surface is located.

2. The dual-interface smart card substrate layer as described in claim 1, characterized in that, The carrier layer has a first surface and a second surface, and the first connection structure is disposed on the same surface of the carrier layer adjacent to the antenna.

3. The dual-interface smart card substrate layer as described in claim 2, characterized in that, The first connection structure overlaps with the orthographic projection of the first surface of the carrier layer onto the normal plane of the target surface of the carrier layer; the antenna overlaps with the orthographic projection of the first surface of the carrier layer onto the normal plane of the target surface of the carrier layer.

4. The dual-interface smart card substrate layer as described in claim 2, characterized in that, The first connection structure overlaps with the orthographic projection of the second surface of the carrier layer onto the normal plane of the target surface of the carrier layer; the antenna overlaps with the orthographic projection of the second surface of the carrier layer onto the normal plane of the target surface of the carrier layer.

5. The dual-interface smart card substrate layer as described in claim 1, characterized in that, The carrier layer has a first surface and a second surface, and the first connection structure and the antenna are respectively disposed near different surfaces of the carrier layer.

6. The dual-interface smart card substrate layer as described in claim 5, characterized in that, The first connection structure overlaps with the orthographic projection of the first surface of the carrier layer onto the normal plane of the target surface of the carrier layer; the antenna overlaps with the orthographic projection of the second surface of the carrier layer onto the normal plane of the target surface of the carrier layer.

7. The dual-interface smart card substrate layer as described in claim 5, characterized in that, The first connection structure overlaps with the orthographic projection of the second surface of the carrier layer onto the normal plane of the target surface of the carrier layer; the antenna overlaps with the orthographic projection of the first surface of the carrier layer onto the normal plane of the target surface of the carrier layer.

8. The dual-interface smart card substrate layer as described in any one of claims 2-7, characterized in that, The vertical distance between the first surface of the chip module and the first surface of the carrier layer is less than the vertical distance between the first surface of the chip module and the second surface of the carrier layer; wherein, the first surface of the chip module refers to the surface with the largest area in the chip module that does not have an electrical connection structure.

9. The dual-interface smart card substrate layer as described in any one of claims 2-7, characterized in that, The vertical distance between the first surface of the chip module and the first surface of the carrier layer is greater than the vertical distance between the first surface of the chip module and the second surface of the carrier layer; the first surface of the chip module refers to the surface with the largest area in the chip module that does not have an electrical connection structure.

10. A dual-interface smart card substrate layer, characterized in that, include: The carrier layer, the first connection structure, the antenna, and the chip module; The first connection structure, the antenna, and the chip module are all carried by the carrier layer, and the first connection structure and the antenna are electrically connected to the chip module respectively; The first connection structure and the antenna have overlapping orthographic projection areas on the normal plane of the target surface of the carrier layer; the chip module and the strip module mounting area of ​​the carrier layer do not overlap in the orthographic projection areas of the target surface of the carrier layer. Wherein, the target surface of the bearing layer is one of the surfaces with the largest area of ​​the bearing layer, the normal plane of the target surface refers to the plane where the normal of the target surface is located, the bearing layer is formed by laminating a first sub-substrate layer and a second sub-substrate layer, and the non-laminated surface with the largest area of ​​the first sub-substrate layer and the non-laminated surface with the largest area of ​​the second sub-substrate layer constitute the target surface of the bearing layer. The first connection structure and the antenna are simultaneously carried by either the first sub-substrate layer or the second sub-substrate layer.

11. The dual-interface smart card substrate layer as described in claim 10, characterized in that, Both the first sub-substrate layer and the second sub-substrate layer have a first surface and a second surface. The first connection structure and the antenna are simultaneously disposed adjacent to the target surface of the first sub-substrate layer or the second sub-substrate layer. The target surface of the first sub-substrate layer or the second sub-substrate layer is the first surface or the second surface.

12. The dual-interface smart card substrate layer as described in claim 11, characterized in that, The first connection structure overlaps with the orthographic projection of the first surface of the first sub-substrate layer onto the normal plane of the target surface of the carrier layer; the antenna overlaps with the orthographic projection of the first surface of the first sub-substrate layer onto the normal plane of the target surface of the carrier layer.

13. The dual-interface smart card substrate layer as described in claim 11, characterized in that, The first connection structure overlaps with the orthographic projection of the second surface of the first sub-substrate layer onto the normal plane of the target surface of the carrier layer; the antenna overlaps with the orthographic projection of the second surface of the first sub-substrate layer onto the normal plane of the target surface of the carrier layer.

14. The dual-interface smart card substrate layer as described in claim 11, characterized in that, The first connection structure overlaps with the orthographic projection of the first surface of the second sub-substrate layer onto the normal plane of the target surface of the carrier layer; the antenna overlaps with the orthographic projection of the first surface of the second sub-substrate layer onto the normal plane of the target surface of the carrier layer.

15. The dual-interface smart card substrate layer as described in claim 11, characterized in that, The first connection structure overlaps with the orthographic projection of the second surface of the second sub-substrate layer onto the normal plane of the target surface of the carrier layer; the antenna overlaps with the orthographic projection of the second surface of the second sub-substrate layer onto the normal plane of the target surface of the carrier layer.

16. The dual-interface smart card substrate layer as described in claim 10, characterized in that, Both the first sub-substrate layer and the second sub-substrate layer have a first surface and a second surface, and the first connection structure and the antenna are respectively disposed near different surfaces of the first sub-substrate layer or the second sub-substrate layer.

17. The dual-interface smart card substrate layer as described in claim 16, characterized in that, The first connection structure overlaps with the orthographic projection of the first surface of the first sub-substrate layer onto the normal plane of the target surface of the carrier layer; the antenna overlaps with the orthographic projection of the second surface of the first sub-substrate layer onto the normal plane of the target surface of the carrier layer.

18. The dual-interface smart card substrate layer as described in claim 16, characterized in that, The first connection structure overlaps with the orthographic projection of the second surface of the first sub-substrate layer onto the normal plane of the target surface of the carrier layer; the antenna overlaps with the orthographic projection of the first surface of the first sub-substrate layer onto the normal plane of the target surface of the carrier layer.

19. The dual-interface smart card substrate layer as described in claim 16, characterized in that, The first connection structure overlaps with the orthographic projection of the first surface of the second sub-substrate layer onto the normal plane of the target surface of the carrier layer; the antenna overlaps with the orthographic projection of the second surface of the second sub-substrate layer onto the normal plane of the target surface of the carrier layer.

20. The dual-interface smart card substrate layer as described in claim 16, characterized in that, The first connection structure overlaps with the orthographic projection of the second surface of the second sub-substrate layer onto the normal plane of the target surface of the carrier layer; the antenna overlaps with the orthographic projection of the first surface of the second sub-substrate layer onto the normal plane of the target surface of the carrier layer.

21. The dual-interface smart card substrate layer as described in claims 1-20, characterized in that, The carrier layer is provided with mounting holes adapted to the chip module.

22. The dual-interface smart card substrate layer as described in claim 21, characterized in that, The chip module includes a substrate and a chip. The chip is mounted on a target surface of the substrate. The target surface of the substrate is also provided with a plurality of chip module contact pads. The plurality of chip module contact pads are used to realize the electrical connection between the chip and the antenna and the first connection structure. The target surface of the substrate is one of the surfaces with the largest area of ​​the substrate.

23. The dual-interface smart card substrate layer as described in claim 22, characterized in that, Each chip module contact pad group includes a chip contact pad and a conductive channel contact pad, and the chip contact pad is electrically connected to the conductive channel contact pad; The chip contact pad is electrically connected to the chip pins, and the conductive channel contact pad is electrically connected to the first connection structure terminal or the antenna terminal.

24. The dual-interface smart card substrate layer as described in claim 23, characterized in that, The target surface of the substrate is also provided with encapsulating adhesive for packaging chips and chip contact pads.

25. The dual-interface smart card substrate layer as described in claim 24, characterized in that, The vertical distance between the first surface of the chip module and the first surface of the first sub-substrate layer is less than the vertical distance between the first surface of the chip module and the second surface of the second sub-substrate layer. The first surface of the chip module refers to the surface with the largest area in the chip module that does not have an electrical connection structure.

26. The dual-interface smart card substrate layer as described in claim 25, characterized in that, The first surface of the chip module and the first surface of the first sub-substrate layer are located on the same plane.

27. The dual-interface smart card substrate layer as described in claim 25 or 26, characterized in that, The mounting holes include a first mounting hole provided in the first sub-substrate layer and a second mounting hole provided in the second sub-substrate layer; The size of the first mounting hole matches the size of the substrate of the chip module, and the size of the first mounting hole is larger than that of the second mounting hole.

28. The dual-interface smart card substrate layer as described in claim 24, characterized in that, The vertical distance between the first surface of the chip module and the second surface of the second sub-substrate layer is less than the vertical distance between the first surface of the chip module and the first surface of the first sub-substrate layer. The first surface of the chip module refers to the surface with the largest area in the chip module that does not have an electrical connection structure.

29. The dual-interface smart card substrate layer as described in claim 28, characterized in that, The first surface of the chip module and the second surface of the second sub-substrate layer are located on the same plane.

30. The dual-interface smart card substrate layer as described in claim 28 or 29, characterized in that, The mounting holes include a second mounting hole provided in the first sub-substrate layer and a first mounting hole provided in the second sub-substrate layer; The size of the first mounting hole matches the size of the substrate of the chip module, and the size of the first mounting hole is larger than that of the second mounting hole.

31. The dual-interface smart card substrate layer as described in claim 27 or 30, characterized in that, The conductive channel contact pad of the chip module overlaps with the orthographic projection area of ​​the second mounting hole on the target surface of the carrier layer, and the second mounting hole penetrates the sub-substrate layer.

32. The dual-interface smart card substrate layer as described in claim 27 or 30, characterized in that, The orthographic projection area of ​​the conductive channel contact pad of the chip module on the target surface of the carrier layer does not overlap with the orthographic projection area of ​​the second mounting hole on the target surface of the carrier layer.

33. The dual-interface smart card substrate layer as described in claim 27 or 30, characterized in that, The conductive channel contact pad of the chip module overlaps with the orthographic projection area of ​​the second mounting hole on the target surface of the carrier layer, and the second mounting hole does not penetrate the sub-substrate layer in which it is located.

34. The dual-interface smart card substrate layer as described in claim 32 or 33, characterized in that, When the first mounting hole is located in the first sub-substrate layer, the second sub-substrate layer is also provided with a plurality of soldering holes that match the antenna terminal and the first connection structure terminal; When the first mounting hole is located in the second sub-substrate layer, the first sub-substrate layer is also provided with a plurality of solder holes that match the antenna terminal and the first connection structure terminal; In the above situation, the orthographic projection area of ​​each welding hole on the target surface of the carrier layer overlaps with the orthographic projection area of ​​the corresponding antenna terminal or the first connection structure terminal on the target surface of the carrier layer.

35. The dual-interface smart card substrate layer as described in claims 1-15, characterized in that, The chip module includes a chip and a plurality of solder balls disposed on the bottom of the chip corresponding to the chip pins. The plurality of solder balls are used to realize the electrical connection between the chip and the antenna and the first connection structure.

36. The dual-interface smart card substrate layer as described in claim 35, characterized in that, The vertical distance between the first surface of the chip module and the first surface of the first sub-substrate layer or the first surface of the carrier layer is less than the vertical distance between the first surface of the chip module and the second surface of the second sub-substrate layer or the second surface of the carrier layer. The first surface of the chip module refers to the surface with the largest area in the chip module that does not have an electrical connection structure.

37. The dual-interface smart card substrate layer as described in claim 35, characterized in that, The vertical distance between the first surface of the chip module and the first surface of the first sub-substrate layer or the first surface of the carrier layer is greater than the vertical distance between the first surface of the chip module and the second surface of the second sub-substrate layer or the second surface of the carrier layer. The first surface of the chip module refers to the surface with the largest area in the chip module that does not have an electrical connection structure.

38. The dual-interface smart card substrate layer as described in claims 21-37, characterized in that, The orthographic projection area of ​​the antenna and the first connection structure on the target surface of the carrier layer overlaps with the orthographic projection area of ​​the conductive channel contact pad or solder ball of the chip module on the target surface of the carrier layer.

39. The dual-interface smart card substrate layer as described in claims 10-38, characterized in that, The dual-interface smart card substrate layer also includes a third sub-substrate layer, which is laminated with the first sub-substrate layer or the second sub-substrate layer.

40. A dual-interface smart card, characterized in that, Includes a strip module, a supplementary support layer, and a dual-interface smart card substrate layer as described in any one of claims 1-9; The strip module includes contact pads, a support layer, and conductive pads; The target surface of the supplementary support layer is pressed together with the first and second surfaces of the bearing layer; The contact surface of the contact pad of the strip module is on the same plane as the first surface of the supplementary support layer; The target surface of the supplementary support layer is one of the surfaces with the largest area of ​​the supplementary support layer.

41. The dual-interface smart card as described in claim 40, characterized in that, The strip module is electrically connected to the first connection structure in the strip module mounting area of ​​the carrier layer via anisotropic conductive adhesive or conductive solder.

42. A dual-interface smart card, characterized in that, Includes a strip module, a supplementary support layer, and a dual-interface smart card substrate layer as described in any one of claims 10-39; The strip module includes contact pads, a support layer, and conductive pads; The target surface of the supplementary support layer is pressed against the first surface of the first sub-substrate layer and the second surface of the second sub-substrate layer or the second surface of the third sub-substrate layer; The contact surface of the contact pad of the strip module is on the same plane as the first surface of the supplementary support layer; The target surface of the supplementary support layer is one of the surfaces with the largest area of ​​the supplementary support layer.

43. The dual-interface smart card as described in claim 42, characterized in that, The strip module is electrically connected to the first connection structure in the strip module mounting area of ​​the carrier layer via anisotropic conductive adhesive or conductive solder.

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