Method of manufacturing a semiconductor device

Abstract

The application provides a preparation method of a semiconductor device, comprising the following steps: providing a substrate, wherein the substrate is provided with a gate structure; forming a side wall oxide layer on the substrate and the gate structure; forming a stress memory layer on the side wall oxide layer and performing a first annealing process; removing the stress memory layer and part of the thickness of the side wall oxide layer; performing a nitrogen doping process on the remaining side wall oxide layer; and etching to remove the remaining side wall oxide layer. The unexpected effect of the application is that: by performing the nitrogen doping process on the remaining side wall oxide layer, nitrogen ions are doped into the remaining side wall oxide layer, so as to increase the etching rate when the remaining side wall oxide layer is etched to be removed, to ensure that the remaining side wall oxide layer can be removed completely, to avoid that the remaining side wall oxide layer on the substrate affects the formation of a subsequent metal contact layer, and to improve the conductive performance of the device.

Description

Semiconductor device fabrication methods Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method for fabricating a semiconductor device. Background Technology

[0002] Currently, a major method to increase the switching frequency of field-effect transistors (FETs) is to increase the drive current, and the main way to increase the drive current is to increase carrier mobility. Stress memory technology (SMT) improves carrier mobility in the channel by creating stable stress in the channel region of the FET. Generally, tensile stress can make the molecular arrangement in the channel region more loose, thereby improving electron mobility, which is suitable for NMOS transistors, while compressive stress makes the molecular arrangement in the channel region more compact, which helps to improve hole mobility, and is suitable for PMOS transistors.

[0003] In traditional stress memory technology, a stress memory layer is typically deposited followed by a high-temperature annealing process. The stress generated during annealing is stored in the polysilicon gate. Afterward, the stress memory layer is removed, but the stress stored in the polysilicon gate can still be conducted to the transistor channel. However, before forming the stress memory layer, a sidewall oxide layer exists on the substrate and the polysilicon gate as an injection barrier layer for source / drain doping. Removing the stress memory layer requires further removal of the sidewall oxide layer. The high temperature of the high-temperature annealing process can cause the silicon-oxygen bonds in the sidewall oxide layer to break, leading to a qualitative change in the sidewall oxide layer. Figure 1 shows the relationship between the high-temperature annealing temperature and the etching rate of the oxide material. As shown in Figure 1, the higher the high-temperature annealing temperature, the lower the etching rate of the oxide material after the qualitative change. The altered sidewall oxide layer is difficult to completely etch away, and a portion of the sidewall oxide layer remains on the substrate after etching. This residual sidewall oxide layer makes it difficult to form a metal contact layer on the substrate, resulting in decreased conductivity and adversely affecting the device. Summary of the Invention

[0004] In view of this, the embodiments of this application aim to provide a method for fabricating a semiconductor device to solve the problem in the prior art that the sidewall oxide layer is difficult to remove after high-temperature degradation.

[0005] This application provides a method for fabricating a semiconductor device, including:

[0006] A substrate is provided, wherein a gate structure is present on the substrate;

[0007] A sidewall oxide layer is formed on the substrate and the gate structure;

[0008] A stress memory layer is formed on the sidewall oxide layer and a first annealing process is performed.

[0009] Remove the stress memory layer and a portion of the sidewall oxide layer;

[0010] The remaining sidewall oxide layer is subjected to a nitrogen-doping process; and,

[0011] Etching is used to remove the remaining sidewall oxide layer.

[0012] In some embodiments, the gate structure includes a gate oxide layer, a gate conductive layer, a gate shielding layer, and a first sidewall structure, wherein the gate oxide layer, the gate conductive layer, and the gate shielding layer are stacked sequentially from bottom to top, the first sidewall structure covers the sides of the gate oxide layer, the gate conductive layer, and the gate shielding layer, and the sidewall oxide layer conformally covers the top surface of the substrate, the sides of the first sidewall structure, and the top surface of the gate shielding layer.

[0013] In some embodiments, the portion of the sidewall oxide layer covering the top surface of the substrate and the top surface of the gate shielding layer is a first portion, and the portion of the sidewall oxide layer covering the side surface of the first sidewall structure is a second portion. After the sidewall oxide layer is formed, a sidewall nitride layer is also formed on the second portion.

[0014] Remove a portion of the thickness of the first part, perform a nitrogen-doping process on the remaining first part, and etch to remove the remaining first part; and,

[0015] After removing the remaining first portion, the second portion and the sidewall nitriding layer constitute the second sidewall structure.

[0016] In some embodiments, after the sidewall oxide layer is formed, the thickness of the sidewall oxide layer is less than or equal to 30 nm; and / or, after removing part of the thickness of the first portion, the remaining thickness of the first portion is less than or equal to 10 nm.

[0017] In some embodiments, after the sidewall oxide layer is formed and before the stress memory layer is formed, ion implantation is performed on the substrates on both sides of the gate structure using the sidewall oxide layer as an implantation barrier layer to form source / drain regions in the substrates on both sides of the gate structure.

[0018] In some embodiments, the stress memory layer includes a stress buffer layer and a stress introduction layer stacked sequentially from bottom to top.

[0019] In some embodiments, prior to forming the sidewall oxide layer, the preparation method further includes:

[0020] An ion blocking layer is formed on the substrate and the gate structure; and,

[0021] After removing the remaining sidewall oxide layer, the ion-blocking layer is also removed.

[0022] In some embodiments, after the nitrogen doping process and before removing the remaining sidewall oxide layer, the remaining sidewall oxide layer is subjected to a second annealing process in an oxygen-containing gas.

[0023] In some embodiments, after removing the remaining sidewall oxide layer, the preparation method further includes:

[0024] Oxidize the top surface of the substrate to form a nitrogen-containing oxide layer on the top surface of the substrate; and,

[0025] Remove the nitrogen-containing oxide layer.

[0026] In some embodiments, after removing the remaining sidewall oxide layer, the preparation method further includes:

[0027] Metal contact layers are formed on the substrates on both sides of the gate structure.

[0028] This application provides a method for fabricating a semiconductor device, including providing a substrate having a gate structure; forming a sidewall oxide layer on the substrate and the gate structure; forming a stress memory layer on the sidewall oxide layer and performing a first annealing process; removing the stress memory layer and a portion of the sidewall oxide layer; performing a nitrogen-doping process on the remaining sidewall oxide layer; and etching to remove the remaining sidewall oxide layer. An unexpected effect of this application is that by performing a nitrogen-doping process on the remaining sidewall oxide layer, nitrogen ions are incorporated into the remaining sidewall oxide layer, thereby increasing the etching rate when etching to remove the remaining sidewall oxide layer. This ensures that the remaining sidewall oxide layer can be completely removed, preventing residual sidewall oxide layer on the substrate from affecting the formation of subsequent metal contact layers and improving the conductivity of the device. Attached Figure Description

[0029] Figure 1 shows the relationship between the high-temperature annealing temperature and the etching rate of the oxide material.

[0030] Figure 2 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application.

[0031] Figure 3 is a schematic diagram of the substrate and gate structure provided in an embodiment of this application.

[0032] Figure 4 is a schematic diagram of a structure in which a sidewall oxide layer and a sidewall nitride layer are formed on a substrate and a gate structure according to an embodiment of this application.

[0033] Figure 5 is a schematic diagram of the structure after etching the sidewall nitriding layer according to an embodiment of this application.

[0034] Figure 6 is a schematic diagram of ion implantation on the substrates on both sides of the gate structure according to an embodiment of this application.

[0035] Figure 7 is a schematic diagram of a structure in which a stress memory layer is formed on the sidewall oxide layer and the sidewall nitride layer according to an embodiment of this application.

[0036] Figure 8 is a schematic diagram of the structure of the first part of the etched sidewall oxide layer provided in an embodiment of this application.

[0037] Figure 9 is a schematic diagram of a nitrogen-doping process for the remaining first part according to an embodiment of this application.

[0038] Figure 10 shows the etching thickness curves of the oxide material without DPN process and the etching thickness curves of the oxide material with DPN process, according to an embodiment of this application.

[0039] Figure 11 is a schematic diagram of the structure provided by removing the remaining first part according to an embodiment of this application.

[0040] Figure 12 shows the nitrogen content curves in the sidewall oxide layer and substrate before and after performing the second annealing process, according to an embodiment of this application.

[0041] Figure 13 is a schematic diagram of the structure of oxidizing the top surface of the substrate according to an embodiment of this application.

[0042] Figure 14 is a schematic diagram of the structure of removing the nitrogen-containing oxide layer on the top surface of the substrate according to an embodiment of this application.

[0043] Figure 15 is a schematic diagram of a structure in which a metal contact layer is formed on the top surface of a substrate according to an embodiment of this application.

[0044] The attached figures are labeled as follows:

[0045] 100 - Substrate; 101 - Trench isolation structure; 102 - Source / drain region; 200 - Gate structure; 201 - Gate oxide layer; 202 - Gate conductive layer; 203 - Gate shielding layer; 214 - First sub-sidewall; 224 - Second sub-sidewall; 234 - Sidewall oxide layer; 244 - Sidewall nitride layer; 301 - Stress buffer layer; 302 - Stress introduction layer; 400 - Nitrogen-containing oxide layer; 500 - Metal contact layer. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0047] One embodiment of this application provides a method for fabricating a semiconductor device. Figure 2 is a flowchart of the method for fabricating a semiconductor device according to an embodiment of this application. As shown in Figure 2, the method for fabricating the semiconductor device includes:

[0048] Step S100: Provide a substrate having a gate structure on it;

[0049] Step S200: Form a sidewall oxide layer on the substrate and gate structure;

[0050] Step S300: Form a stress memory layer on the sidewall oxide layer and perform the first annealing process;

[0051] Step S400: Remove the stress memory layer and a portion of the sidewall oxide layer;

[0052] Step S500: Perform a nitrogen doping process on the remaining sidewall oxide layer; and,

[0053] Step S600: Etch to remove the remaining sidewall oxide layer.

[0054] Figures 3 to 15 are schematic diagrams corresponding to the steps of a semiconductor device fabrication method according to an embodiment of this application. Next, the fabrication method of a semiconductor device according to an embodiment of this application will be described in detail with reference to Figures 3 to 15.

[0055] As shown in Figure 3, in step S100, a substrate 100 is provided. The material of the substrate 100 can be silicon, germanium, silicon-germanium, silicon-on-insulator, germanium-on-insulator, gallium arsenide, silicon carbide, etc. A trench isolation structure 101 is formed in the substrate 100. The trench isolation structure 101 extends from the substrate 100 into the substrate 100 and is used to define active regions within the substrate 100. Two adjacent active regions are isolated by the trench isolation structure 101. The top of the trench isolation structure 101 can be higher than the surface of the substrate 100 or flush with the surface of the substrate 100. The material of the trench isolation structure 101 is silicon oxide, but it should not be limited thereto. In other embodiments, the trench isolation structure 101 can also be other dielectric materials, such as high-k (dielectric constant) dielectrics like metal oxides.

[0056] Please refer to Figure 3. The substrate 100 has several gate structures 200 arranged at intervals (only one gate structure 200 is schematically shown in Figure 3). There is a certain distance between two adjacent gate structures 200, and all gate structures 200 can be fabricated simultaneously.

[0057] Further, the gate structure 200 includes a gate oxide layer 201, a gate conductive layer 202, a gate shielding layer 203, and a first sidewall structure. The gate oxide layer 201, the gate conductive layer 202, and the gate shielding layer 203 are stacked sequentially on the substrate 100 from bottom to top. The first sidewall structure covers the sides of the gate oxide layer 201, the gate conductive layer 202, and the gate shielding layer 203. The gate oxide layer 201, the gate conductive layer 202, and the gate shielding layer 203 are all patterned film layers. The first sidewall structure is a double-layer structure, including a first sub-sidewall 214 and a second sub-sidewall 224. The first sub-sidewall 214 covers the sides of the gate oxide layer 201, the gate conductive layer 202, and the gate shielding layer 203, and the second sub-sidewall 224 covers the sides of the first sub-sidewall 214. In some embodiments, the gate structure 200 may include only the gate oxide layer 201, the gate conductive layer 202, and the gate shielding layer 203 (excluding the first sidewall structure); or the first sidewall structure may be a single-layer structure or a multi-layer structure with more than two layers.

[0058] The steps for forming the gate structure 200 may be as follows: depositing a gate oxide material layer, a gate conductive material layer, and a gate shielding material layer (not shown in Figure 3) all over the substrate 100, then etching the gate shielding material layer, the gate conductive material layer, and the gate oxide material layer until the substrate 100 is exposed, and the remaining gate oxide material layer, the gate conductive material layer, and the gate shielding material layer constitute the gate oxide layer 201, the gate conductive layer 202, and the gate shielding layer 203, respectively; then, depositing a first sub-sidewall material layer all over the substrate 100, and then forming a second sub-sidewall material layer (not shown in Figure 3) on the first sub-sidewall material layer, and then removing the second sub-sidewall material layer and the first sub-sidewall material layer on the top surface of the substrate 100 and the top surface of the gate shielding layer 203, and retaining the second sub-sidewall material layer and the first sub-sidewall material layer on the sidewalls of the gate oxide material layer, the gate conductive material layer, and the gate shielding material layer to form the second sub-sidewall 224 and the first sub-sidewall 214, respectively.

[0059] As shown in Figure 4, in step S200, a sidewall oxide layer 234 is formed on the substrate 100 and the gate structure 200. The sidewall oxide layer 234 conformally covers the top surface of the substrate 100 and the top and side surfaces of the gate structure 200 (specifically, it covers the side surface of the first sidewall structure and the top surface of the gate shielding layer 203). In some embodiments, the sidewall oxide layer 234 can be formed using processes such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition, but it should not be limited thereto.

[0060] In some embodiments, the sidewall oxide layer 234 is thinner; for example, the thickness of the sidewall oxide layer 234 may be less than 30 nm.

[0061] Next, for ease of description, the portion of the sidewall oxide layer 234 covering the top surface of the substrate 100 and the top surface of the gate shielding layer 203 will be referred to as the first portion, and the portion of the sidewall oxide layer 234 covering the side surface of the first sidewall structure will be referred to as the second portion.

[0062] Please continue referring to Figure 4. A sidewall nitride layer 244 is formed on the sidewall oxide layer 234, and the sidewall nitride layer 244 conformally covers the top surface of the sidewall oxide layer 234. In some embodiments, the sidewall nitride layer 244 can be formed using processes such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition, but should not be limited thereto.

[0063] As shown in Figure 5, the sidewall nitride layer 244 is etched to remove the portion of the sidewall nitride layer 244 covering the first part, leaving only the portion of the sidewall nitride layer 244 covering the second part, so that the sidewall nitride layer 244 is only located on the second part.

[0064] In some embodiments, the material of the gate oxide layer 201 may be a dielectric material such as silicon oxynitride or silicon oxide, and the material of the gate conductive layer 202 may typically be a conductive material such as polysilicon or metal; the material of the first sub-sidewall 214 may be the same as the material of the sidewall nitride layer 244, for example, it may be an oxide material such as silicon oxide or silicon carbide, and the material of the second sub-sidewall 224 may be the same as the material of the sidewall nitride layer 244, for example, it may be a nitride material such as silicon nitride.

[0065] As shown in Figure 6, ion implantation is performed on the substrates 100 on both sides of the gate structure 200 to form source / drain regions 102 within the substrates 100 on both sides of the gate structure 200. During ion implantation, the sidewall oxide layer 234 can serve as an implantation barrier layer.

[0066] As shown in Figure 7, step S300 is performed to form a stress memory layer on the sidewall oxide layer 234. Specifically, a stress buffer layer 301 is first formed on the sidewall oxide layer 234, which conformally covers the sidewall oxide layer 234 (specifically, the first part) and the sidewall nitride layer 244. Then, a stress introduction layer 302 is formed on the stress buffer layer 301, conformally covering the stress buffer layer 301. The stress introduction layer 302 and the stress buffer layer 301 together constitute the stress memory layer. The stress buffer layer 301 can serve as an etching stop layer during the subsequent etching of the stress introduction layer 302, and also acts as a stress buffer to prevent unnecessary damage to the gate structure 200 caused by the stress introduction layer 302. The stress introduction layer 302 can be used to induce corresponding stress in the channel region of the substrate 100.

[0067] Furthermore, for NMOS devices, the stress-introducing layer 302 can have tensile stress, which will increase the electron mobility in the channel region of the NMOS device; for PMOS devices, the stress-introducing layer 302 can have compressive stress, which will increase the hole mobility in the channel region of the PMOS device. It should be understood that the stress-introducing layer 302 with the desired stress type can be obtained by adjusting the process parameters.

[0068] In some embodiments, the stress buffer layer 301 may be made of a dielectric material such as TEOS (tetraethyl orthosilicate) or silicon oxide, while the stress introduction layer 302 may typically be made of a dielectric material such as silicon nitride.

[0069] Please refer to Figure 7 for the first annealing process performed on the stress memory layer. This first annealing process may include a spike annealing process and a laser annealing process performed sequentially. The spike annealing process is used to activate the source / drain regions 102 in the substrate 100, while the laser annealing process is used for stress memory. Specifically, the spike annealing process is first performed to activate the doped ions in the source / drain regions 102, ensuring uniform ion distribution and repairing lattice damage to the substrate 100 caused by ion implantation. Then, the laser annealing process is performed to transfer the stress introduced into the layer 302 into the channel region within the substrate 100, thereby improving the stress in the channel region, increasing carrier mobility, and enhancing device performance.

[0070] In some embodiments, the temperature of the peak annealing process can be 900℃~1100℃, the annealing time can be 1 minute~5 minutes, and the annealing can be completed in an inert gas atmosphere; the temperature of the laser annealing process can be 1100℃~1300℃, the annealing time can be less than or equal to 1 second, and the laser annealing can use a laser with a wavelength of 2000nm~20000nm.

[0071] It should be noted that, due to the extremely high temperature of the first annealing process, the silicon-oxygen bonds in the stress buffer layer 301 and the sidewall oxide layer 234 will break after the first annealing process, resulting in a qualitative change in the stress buffer layer 301 and the sidewall oxide layer 234. As can be seen from Figure 1, the etching rate of the qualitatively changed stress buffer layer 301 and the sidewall oxide layer 234 decreases, which will exacerbate the difficulty of removing the stress buffer layer 301 and the sidewall oxide layer 234 in the subsequent process. Furthermore, since the stress buffer layer 301 will also undergo a qualitative change after the first annealing process, even if the first part is removed before the formation of the stress buffer layer 301, the same problem will still be faced when removing the stress buffer layer 301 in the subsequent process, that is, the stress buffer layer 301 on the top surface of the substrate 100 is difficult to completely remove.

[0072] As shown in Figure 8, step S400 is executed to remove the stress memory layer. Specifically, the stress-introducing layer 302 can first be removed using a wet etching process. In this case, the etching solution for wet etching can be a phosphoric acid solution. The phosphoric acid solution can etch the stress-introducing layer 302, but does not erode the stress buffer layer 301, thus effectively removing the stress-introducing layer 302.

[0073] Next, the stress buffer layer 301 can be removed by a wet etching process. In this case, the etching solution for wet etching can be a hydrofluoric acid solution.

[0074] Please refer to Figure 8 to see how a portion of the sidewall oxide layer 234 is removed. Specifically, a wet etching process can be used to etch the sidewall oxide layer 234, thereby removing a portion of its thickness. It is understood that since the second portion of the sidewall oxide layer 234 is covered by a sidewall nitride layer 244, when wet etching the portion of the sidewall oxide layer 234, only the first portion of the sidewall oxide layer 234 will be etched; the second portion will not be etched. After etching, the first portion of the sidewall oxide layer 234 retains a portion of its thickness.

[0075] In some embodiments, after removing a portion of the sidewall oxide layer 234, the remaining first portion has a smaller thickness, for example, less than or equal to 10 nm.

[0076] It should be noted that since the stress buffer layer 301 and the sidewall oxide layer 234 are made of similar materials, a one-step wet etching process can be used for etching. In this case, the stress buffer layer 301 and the sidewall oxide layer 234 can be regarded as the same film to be removed, and a one-step wet etching process can be used for etching. However, since both the stress buffer layer 301 and the sidewall oxide layer 234 undergo a qualitative change during the first annealing process, the etching of the film to be removed is extremely difficult and difficult to remove completely. Therefore, in this step, we do not consider how to completely remove the first part that has undergone qualitative change. Instead, after removing the stress buffer layer 301, we intentionally only remove a portion of the first part of the thickness, leaving a portion of the first part to be removed later.

[0077] As shown in Figure 9, step S500 is performed to dope the remaining sidewall oxide layer 234 with nitrogen. In some embodiments, only the remaining first portion may be doped with nitrogen, thereby incorporating nitrogen ions into the remaining first portion. Since the remaining first portion is relatively thin, the nitrogen doping process preferably employs a DPN (Decoupled Plasma Nitridation) process, which enables the incorporation of nitrogen ions into the remaining first portion and prevents nitrogen ions from entering the substrate 100.

[0078] During the nitrogen doping process, the number of nitrogen ions incorporated can be 5% to 20% of the number of atoms in the sidewall oxide layer 234, thereby ensuring the nitrogen ion content in the entire remaining first part and improving the etching rate of the remaining first part.

[0079] In some embodiments, the nitrogen doping process can also employ an ion implantation process, that is, nitrogen ions are implanted into the remaining sidewall oxide layer 234 (specifically, within the remaining first portion of the sidewall oxide layer 234) using an ion implantation process. Of course, since the implantation depth of the ion implantation process is difficult to control precisely, and the thickness of the remaining first portion is relatively thin, when implanting nitrogen ions into the remaining first portion, nitrogen ions may be implanted into the substrate 100.

[0080] In some embodiments, the remaining entire sidewall oxide layer 234 (the remaining first and second portions) may also be subjected to a nitrogen doping process, thereby incorporating nitrogen ions into the remaining entire sidewall oxide layer 234 (the remaining first and second portions).

[0081] Figure 10 shows the etching thickness curves of the oxide material without the DPN process and with the DPN process, according to an embodiment of this application. As can be seen from Figure 10, after performing the DPN process, the etching thickness of the oxide material can be significantly increased within the same etching time. Therefore, after performing the nitrogen-doping process on the remaining first portion, the etching rate of the remaining first portion can be increased, allowing it to be completely removed.

[0082] As shown in Figure 11, step S600 is performed to etch away the remaining sidewall oxide layer 234. In some embodiments, a wet etching process can be used to etch the remaining sidewall oxide layer 234. Since the second portion is covered by the sidewall nitride layer 244, the wet etching process will only remove the remaining first portion until the remaining first portion is completely removed. At this time, the second portion and the sidewall nitride layer constitute the second sidewall structure of the gate structure.

[0083] It should be noted that when the gate structure 200 has a first sidewall structure and a second sidewall structure can be subsequently regenerated, the sidewall nitride layer 244 may not be formed after the sidewall oxide layer 234 is formed. Thus, when removing a portion of the sidewall oxide layer 234, a portion of the entire sidewall oxide layer 234 (both the first and second portions) is removed; when performing a nitrogen doping process on the remaining sidewall oxide layer 234, the entire remaining sidewall oxide layer 234 (both the first and second portions) is also doped; and when removing the remaining sidewall oxide layer 234, the entire remaining sidewall oxide layer 234 (both the first and second portions) is removed.

[0084] Furthermore, when performing nitrogen doping on the remaining sidewall oxide layer 234, nitrogen may also be introduced into the substrate 100, leading to a decrease in the performance of the substrate 100. Therefore, before removing the remaining sidewall oxide layer 234, a second annealing process can be performed on the remaining sidewall oxide layer 234 in an oxygen-containing gas. In the high-temperature and oxygen-containing atmosphere, nitrogen atoms in the sidewall oxide layer 234 can be trapped within the sidewall oxide layer 234, achieving high-temperature nitrogen fixation and preventing nitrogen escape. Simultaneously, unwanted nitrogen within the substrate 100 (the region near the top surface of the substrate 100) will be drawn into the sidewall oxide layer 234, reducing the nitrogen content within the substrate 100 and preventing adverse effects on the performance of the substrate 100 after nitrogen doping.

[0085] Figure 12 shows the nitrogen content curves in the sidewall oxide layer 234 and the substrate 100 before and after the second annealing process, according to an embodiment of this application. As can be seen from Figure 12, there is a certain amount of nitrogen in the substrate 100 before the second annealing process, while the nitrogen content in the substrate 100 is significantly reduced after the second annealing process, and the nitrogen content in the sidewall oxide layer 234 increases, indicating that the nitrogen in the substrate 100 enters the sidewall oxide layer 234.

[0086] In some embodiments, the temperature of the second annealing process can be, for example, above 1100°C, and the oxygen-containing gas can be oxygen or the like. Furthermore, the heating rate of the second annealing process is 40–60°C / s. This setting allows the annealing temperature to reach the required temperature in a short time, minimizing nitrogen escape and improving the effectiveness of the second annealing process. Of course, in other embodiments, the heating rate of the second annealing process can be selected as needed, and this application does not limit it in this regard.

[0087] Furthermore, after removing the remaining first portion, some nitrogen ions may remain on the surface of substrate 100, contaminating the surface of substrate 100 and affecting subsequent processes. Based on this, after removing the remaining first portion of the sidewall oxide layer 234, as shown in Figure 13, the top surface of substrate 100 is oxidized to form a nitrogen-containing oxide layer 400 on the top surface of substrate 100. In this way, the nitrogen ions remaining on the surface of substrate 100 can be fixed in the nitrogen-containing oxide layer 400.

[0088] In some embodiments, the material containing the oxynitride layer 400 may be, for example, silicon oxynitride, but should not be limited thereto.

[0089] In some embodiments, hydrogen peroxide can be used to oxidize the top surface of the substrate 100, thereby rapidly and efficiently forming a nitrogen-containing oxide layer 400 on the top surface of the substrate 100, and avoiding the introduction of other impurity elements during the oxidation of the top surface of the substrate 100. In other embodiments, other processes can also be used to oxidize the top surface of the substrate 100.

[0090] Next, as shown in Figure 14, the nitrogen-containing oxide layer 400 is removed to remove residual nitrogen on the top surface of the substrate 100, thus preventing residual nitrogen on the top surface of the substrate 100 from affecting subsequent processes. As can be seen from Figure 14, after removing the nitrogen-containing oxide layer 400, the top surface of the substrate 100 has a recess, which is specifically located on the top surface of the source / drain regions 102 and on both sides of the gate structure 200, but the recess will not affect the implementation of this application.

[0091] As shown in Figure 15, a metal contact layer 500 is formed on the top surface of the substrate 100. The metal contact layer 500 is located on the top surface of the source / drain region 102 and fills the recess. Furthermore, the metal contact layer 500 is also located on both sides of the gate structure 200. The process for forming the metal contact layer 500 can be as follows: a metal layer is formed on the top surface of the substrate 100, followed by high-temperature annealing. The metal layer reacts with the substrate 100 to form the metal contact layer 500, which is located on the contact surface between the metal layer and the substrate 100. Afterward, excess metal layer is removed.

[0092] It is understood that in the aforementioned steps, the sidewall oxide layer 234 on the top surface of the substrate 100 has been completely removed, and the metal contact layer 500 can be formed well on the top surface of the substrate 100, thereby improving the conductivity of the device.

[0093] In some embodiments, the material of the metal contact layer 500 may be a metal silicide, such as cobalt silicide, nickel silicide, etc.

[0094] In some embodiments, before forming the sidewall oxide layer 234, an ion barrier layer may be formed on the substrate 100 and the gate structure 200, the ion barrier layer conformally covering the top surface of the substrate 100 and the top and side surfaces of the gate structure 200. During the nitrogen doping process, the ion barrier layer can prevent nitrogen from entering the substrate 100. After removing the remaining sidewall oxide layer 234, the ion barrier layer can be removed. Thus, a second annealing process and an oxide process on the top surface of the substrate 100 are unnecessary, improving fabrication efficiency and reducing fabrication costs.

[0095] Optionally, the material of the ion barrier layer should avoid being an oxidizing material that will undergo qualitative changes at high temperatures. At the same time, the material of the ion barrier layer can also be used as an implantation barrier layer, which will not be listed here.

[0096] In summary, this embodiment provides a method for fabricating a semiconductor device, including providing a substrate 100 having a gate structure 200; forming a sidewall oxide layer 234 on the substrate 100 and the gate structure 200; forming a stress memory layer on the sidewall oxide layer 234 and performing a first annealing process; removing the stress memory layer and a portion of the sidewall oxide layer 234; performing a nitrogen doping process on the remaining sidewall oxide layer 234; and etching to remove the remaining sidewall oxide layer 234. An unexpected effect of this application is that by performing a nitrogen doping process on the remaining sidewall oxide layer 234, nitrogen ions are incorporated into the remaining sidewall oxide layer 234, thereby increasing the etching rate when etching to remove the remaining sidewall oxide layer 234. This ensures that the remaining sidewall oxide layer 234 can be completely removed, preventing the residual sidewall oxide layer 234 on the substrate 100 from affecting the formation of the subsequent metal contact layer 500, and improving the conductivity of the device.

[0097] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0098] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0099] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0100] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate having a gate structure; a sidewall oxide layer is formed on the substrate and the gate structure; A stress memory layer is formed on the sidewall oxide layer and a first annealing process is performed, during which the silicon-oxygen bonds in the sidewall oxide layer break, causing a qualitative change in the sidewall oxide layer; the stress memory layer and a portion of the sidewall oxide layer are then removed. The remaining sidewall oxide layer is subjected to a nitrogen-doping process; and etched to remove the remaining sidewall oxide layer; after the nitrogen-doping process and before removing the remaining sidewall oxide layer, the remaining sidewall oxide layer is subjected to a second annealing process in an oxygen-containing gas.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The gate structure includes a gate oxide layer, a gate conductive layer, a gate shielding layer, and a first sidewall structure. The gate oxide layer, the gate conductive layer, and the gate shielding layer are stacked sequentially from bottom to top. The first sidewall structure covers the sides of the gate oxide layer, the gate conductive layer, and the gate shielding layer. The sidewall oxide layer conformally covers the top surface of the substrate, the sides of the first sidewall structure, and the top surface of the gate shielding layer.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The portion of the sidewall oxide layer covering the top surface of the substrate and the top surface of the gate shielding layer is the first portion, and the portion of the sidewall oxide layer covering the side surface of the first sidewall structure is the second portion. After the sidewall oxide layer is formed, a sidewall nitride layer is also formed on the second portion. Remove a portion of the thickness of the first part, perform a nitrogen-doping process on the remaining first part, and etch to remove the remaining first part; Furthermore, after removing the remaining first portion, the second portion and the sidewall nitriding layer constitute the second sidewall structure.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, After the sidewall oxide layer is formed, the thickness of the sidewall oxide layer is less than or equal to 30 nm; and / or, after removing part of the thickness of the first portion, the remaining thickness of the first portion is less than or equal to 10 nm.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, After the sidewall oxide layer is formed and before the stress memory layer is formed, ion implantation is performed on the substrates on both sides of the gate structure using the sidewall oxide layer as an implantation barrier layer to form source / drain regions in the substrates on both sides of the gate structure.

6. The method for fabricating a semiconductor device according to any one of claims 1 to 5, characterized in that, The stress memory layer includes a stress buffer layer and a stress introduction layer stacked sequentially from bottom to top.

7. The method for fabricating a semiconductor device according to any one of claims 1 to 5, characterized in that, Before forming the sidewall oxide layer, the preparation method further includes: forming an ion blocking layer on the substrate and the gate structure; and removing the ion blocking layer after removing the remaining sidewall oxide layer.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, After removing the remaining sidewall oxide layer, the preparation method further includes: oxidizing the top surface of the substrate to form a nitrogen-containing oxide layer on the top surface of the substrate; and removing the nitrogen-containing oxide layer.

9. The method for fabricating a semiconductor device according to any one of claims 1 to 5, characterized in that, After removing the remaining sidewall oxide layer, the fabrication method further includes forming a metal contact layer on the substrate on both sides of the gate structure.

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