Image sensor and method of manufacturing the same

Abstract

This application discloses an image sensor and a method for manufacturing the same. The method includes: forming a first trench and a second trench that are interconnected in a semiconductor layer, wherein the first trench has a large opening size in the middle; forming an isolation dielectric layer in the first trench and the second trench that are interconnected, wherein an air gap is formed in the isolation dielectric layer at least in the first trench; and removing the upper part of the semiconductor layer, wherein the portion of the isolation dielectric layer retained in the trench forms an isolation structure, and the portion of the isolation dielectric layer exposed forms a grid structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to an image sensor and a method for manufacturing the same. Background Technology

[0002] Image sensors are devices that convert optical images into pixel signals for output. Based on the different photosensitive elements and photosensitive principles, they are divided into charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. Among them, CMOS image sensors are widely used image sensors, including front-side illumination (FSI) image sensors and back-side illumination (BSI) image sensors.

[0003] Existing complementary metal-oxide-semiconductor (CMOS) image sensors require the formation of a metal grid to isolate incident light. However, in current technologies, the process of forming the metal grid is complex, resulting in high production costs and a tendency to cause metal contamination. The metal grid also leads to the loss of incident light, reducing the photosensitivity of the image sensor. Summary of the Invention

[0004] In view of the above problems, this application provides an image sensor and a method for manufacturing the same, wherein the grid structure is formed by an isolation dielectric layer and an air gap is formed in the grid structure to control photon crosstalk without reducing light sensitivity.

[0005] According to one aspect of the present invention, a method for manufacturing an image sensor is provided, comprising: forming a first trench and a second trench that are interconnected in a semiconductor layer, the first trench having a large opening size in the middle; forming an isolation dielectric layer in the interconnected first trench and the second trench, wherein an air gap is formed in at least the isolation dielectric layer in the first trench; and removing the upper portion of the semiconductor layer, wherein a portion of the isolation dielectric layer retained in the trench forms an isolation structure, and a portion of the isolation dielectric layer exposed forms a grid structure.

[0006] Optionally, the method for forming a first trench and a second trench that are interconnected in a semiconductor layer includes: forming a hard mask layer on the semiconductor layer; forming an opening through its thickness in the hard mask layer and forming a pre-trench in the semiconductor layer; continuing to etch the semiconductor layer through the opening in the hard mask layer to form a first trench; continuing to etch the semiconductor layer through the opening in the hard mask layer to form a second trench that is connected to the first trench; wherein the first trench is formed using an anisotropic wet etching process, such that the middle part of the first trench has a large opening size.

[0007] Optionally, the method of forming the isolation dielectric layer includes: forming a first isolation dielectric layer, the first isolation dielectric layer covering the sidewalls of the first trench, the bottom and sidewalls of the second trench, and the surface of the semiconductor layer; forming a second isolation dielectric layer, the second isolation dielectric layer conformally covering the surface of the first isolation dielectric layer; and forming a third isolation dielectric layer, filling the remaining space of the first trench and the second trench, and covering the surface of the second isolation dielectric layer above the semiconductor layer; wherein, the second isolation dielectric layer has a higher dielectric constant relative to the first isolation dielectric layer and the third isolation dielectric layer.

[0008] Optionally, after forming the isolation dielectric layer, the process further includes removing the isolation dielectric layer from the surface of the semiconductor layer.

[0009] Optionally, the top of the grid structure forms a transverse arrangement of a first isolation medium layer, a second isolation medium layer, a third isolation medium layer, a second isolation medium layer, and a first isolation medium layer.

[0010] Optionally, after forming the grid structure, the method further includes: forming a first dielectric layer that covers the surface of the semiconductor layer; forming a second dielectric layer that covers the surface of the first dielectric layer and also covers the top and sidewalls of the grid structure; forming a third dielectric layer that conformally covers the surface of the second dielectric layer; wherein the second dielectric layer is made of the same material as the second isolation dielectric layer, and the second dielectric layer contacts the second isolation dielectric layer exposed at the top of the grid structure.

[0011] According to another aspect of the present invention, an image sensor is provided, comprising: a semiconductor layer; a deep trench extending from a first surface of the semiconductor layer toward its interior; and an isolation dielectric layer including a portion located in the deep trench and a portion extending outside the deep trench; wherein the portion of the isolation dielectric layer located in the deep trench constitutes an isolation structure for isolating adjacent photosensitive areas, and the portion of the isolation dielectric layer extending outside the deep trench forms a grid structure, the grid structure having a larger size in the middle, and an air gap being formed in the isolation dielectric layer in the middle of the grid structure.

[0012] Optionally, the isolation dielectric layer includes a first isolation dielectric layer, a second isolation dielectric layer, and a third isolation dielectric layer stacked together, wherein the second isolation dielectric layer has a higher dielectric constant than the first isolation dielectric layer and the third isolation dielectric layer.

[0013] Optionally, a transverse arrangement of a first isolation medium layer, a second isolation medium layer, a third isolation medium layer, a second isolation medium layer, and a first isolation medium layer is formed on the top of the grid structure.

[0014] Optionally, it further includes: a first dielectric layer covering the surface of the semiconductor layer; a second dielectric layer covering the surface of the first dielectric layer and covering the top and sidewalls of the grid structure; and a third dielectric layer conformally covering the surface of the second dielectric layer; wherein the second dielectric layer is made of the same material as the second isolation dielectric layer, and the second dielectric layer contacts the second isolation dielectric layer exposed at the top of the grid structure.

[0015] The unexpected technical effect of this application is:

[0016] In this embodiment, an air gap is formed in the grid structure, and the air gap and the isolation medium surrounding the air gap form a composite air grid structure, which controls photon crosstalk without reducing light sensitivity and provides next-generation grid technology support for pixel shrinkage of image sensors.

[0017] In this application, the grid structure and the deep trench isolation structure are formed through the same filling step to achieve precise alignment of the grid structure and the deep trench isolation structure.

[0018] In this application, the isolation medium includes a second isolation medium layer with a high dielectric constant to draw out free charges in the deep trench. In a preferred embodiment, the second dielectric layer is formed on the substrate, and the second dielectric layer is in contact with the second isolation medium layer, so that free charges on the substrate surface and the isolation structure can be drawn out through the same external structure.

[0019] In this application, by selecting the crystal orientation of the semiconductor layer, a larger opening size is made in the middle of the first trench, thereby forming an air gap in the isolation dielectric layer during the formation of the isolation dielectric layer in the first trench. Attached Figure Description

[0020] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0021] Figure 1 A schematic diagram of a traditional image sensor is shown;

[0022] Figure 2 A schematic diagram of an image sensor provided according to an embodiment of this application is shown;

[0023] Figure 3 A flowchart illustrating a method for manufacturing an image sensor according to an embodiment of this application is provided.

[0024] Figures 4a to 4i This is a schematic diagram illustrating the steps of an exemplary image sensor manufacturing method provided in this application embodiment, wherein:

[0025] Figure 4a This illustration shows a schematic cross-sectional view of a hard mask layer formed on a semiconductor layer in an embodiment of this application;

[0026] Figure 4b This illustration shows a schematic diagram of an opening through the thickness of a hard mask layer and a pre-trench formed in a semiconductor layer, as described in an embodiment of this application.

[0027] Figure 4c This diagram illustrates the process of etching the semiconductor layer through an opening in the hard mask layer to form the first trench.

[0028] Figure 4d This diagram illustrates a process of etching the semiconductor layer through an opening in the hard mask layer in an embodiment of this application to form a second trench that communicates with the first trench.

[0029] Figure 4e This diagram illustrates the formation of the isolation medium layer in an embodiment of this application.

[0030] Figure 4f This illustration shows a schematic diagram of removing the isolation dielectric layer on the surface of the hard mask layer and removing the hard mask layer in an embodiment of this application.

[0031] Figure 4g This diagram illustrates the removal of the upper part of the semiconductor layer in an embodiment of this application.

[0032] Figure 4h This diagram illustrates a first dielectric layer formed on the surface of a semiconductor layer in an embodiment of this application.

[0033] Figure 4i This diagram illustrates the formation of the second and third dielectric layers in an embodiment of this application.

[0034] Explanation of reference numerals in the attached figures: 101-Substrate; 102-Photosensitive area; 103-Deep trench isolation structure; 104-Dielectric layer; 105-Metal grid; 1051-First grid layer; 1052-Second grid layer; 1053-Third grid layer; 201-Semiconductor layer; 203-Isolation structure; 2041-Second mask layer; 2042-Third mask layer; 2043-Fourth mask layer; 205-Grid structure; AG-Air gap; DT-Deep trench; DT1-First trench; DT2-Second trench; DT3-Pre-trench; IDL-Isolation dielectric layer; IDLa-First isolation dielectric layer; IDLb-Second isolation dielectric layer; IDLc-Third isolation dielectric layer; HM-Hard mask layer; HMa-Opening. Detailed Implementation

[0035] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0036] This application may be presented in various forms, some of which will be described below.

[0037] Figure 1 A schematic diagram of a traditional image sensor is shown. (Example) Figure 1 As shown, the image sensor includes a substrate 101, within which a plurality of deep trench isolation structures 103 extending from the surface of the substrate 101 into its interior are disposed. The deep trench isolation (DTI) structures 103 isolate the substrate to form a plurality of photosensitive areas 102. The substrate 101 is made of, for example, silicon (Si). A dielectric layer 104 is disposed on the surface of the substrate 101, and a metal grid 105 formed by stacking different materials is disposed on the surface of the dielectric layer 104.

[0038] The metal grid 105 includes a first grid layer 1051, a second grid layer 1052, and a third grid layer 1053. The first grid layer 1051 is, for example, a titanium (Ti) layer, the second grid layer 1052 is, for example, a tungsten (W) layer, and the third grid layer 1053 is, for example, an oxide layer. In existing image sensors, to eliminate optical crosstalk between color filters, the absorption characteristics of the metal grid 105 are used to reduce photoelectric crosstalk by utilizing visible light. However, this reduces the photosensitivity of the image sensor and limits the reduction in pixel size.

[0039] In view of this, one embodiment of this application provides an image sensor. Figure 2 A schematic diagram of an image sensor provided according to an embodiment of this application is shown, such as... Figure 2As shown, the image sensor includes a semiconductor layer 201, a deep trench DT, and an isolation dielectric layer IDL. The deep trench DT extends from the first surface of the semiconductor layer 201 into its interior. The isolation dielectric layer IDL includes a portion located within the deep trench DT and a portion extending outside the deep trench DT. The portion of the isolation dielectric layer IDL located within the deep trench DT constitutes an isolation structure 203 that isolates adjacent photosensitive areas, and the portion of the isolation dielectric layer IDL extending outside the deep trench DT forms a grid structure 205.

[0040] The isolation dielectric layer (IDL) includes one or more dielectric layers. In this embodiment, the isolation dielectric layer (IDL) includes, from the outside to the inside, a first isolation dielectric layer (IDLa), a second isolation dielectric layer (IDLb), and a third isolation dielectric layer (IDLc).

[0041] In a deep trench (DT), a first insulating dielectric layer IDLa covers the bottom and sidewalls of the DT, a second insulating dielectric layer IDLb covers the surface of the first insulating dielectric layer IDLa, and a third insulating dielectric layer IDLc fills the remaining space in the DT. Further, the first and second insulating dielectric layers IDLa and IDLb have a thinner thickness than the third insulating dielectric layer IDLc. The first insulating dielectric layer IDLa is, for example, an oxide layer (OX), and its thinness prevents excessive stress on the sidewalls of the DT from being caused by an excessively thick dielectric layer. The dielectric constant of the second insulating dielectric layer IDLb is greater than that of the first insulating dielectric layer IDLa. The second insulating dielectric layer IDLb is, for example, hafnium dioxide (HfO2), zirconium oxide (ZrO2), titanium dioxide (TiO2), etc., which have dielectric constants higher than silicon oxide (SiO2). The third insulating dielectric layer IDLc is, for example, an oxide layer (OX).

[0042] Outside the deep trench DT, the first isolation medium layer IDLa, the second isolation medium layer IDLb, and the third isolation medium layer IDLc are exposed on the top surface of the grid structure 205. A transversely stacked structure of the first isolation medium layer IDLa, the second isolation medium layer IDLb, the third isolation medium layer IDLc, the second isolation medium layer IDLb, and the first isolation medium layer IDLa is formed on the top surface of the grid structure in a horizontally sequential manner. The middle portion of the grid structure 205 has a larger dimension, and an air gap AG is formed in the middle portion of the grid structure 205. In a preferred embodiment, the air gap AG also extends to the lower part of the grid structure 205, and even extends into the interior of the isolation structure 203. In one embodiment, the air gap AG is formed in the third isolation medium layer IDLc.

[0043] Furthermore, the image sensor also includes a first dielectric layer 2041, a second dielectric layer 2042, and a third dielectric layer 2043. The first dielectric layer 2041 covers a first surface of the substrate 201. The second dielectric layer 2042 conformally covers the surface of the first dielectric layer 2041 and the sidewalls and top of the grid structure 205. The third dielectric layer 2043 conformally covers the surface of the second dielectric layer 2042. The second dielectric layer 2042 is in contact with the second isolation dielectric layer IDLb exposed on the top of the grid structure 205, and the material of the second dielectric layer 2042 is the same as that of the second isolation dielectric layer IDLb. In a preferred embodiment, the connected second dielectric layer 2042 and the second isolation dielectric layer IDLb are led out to release free charges on the surface of the substrate 201 and inside the isolation structure 203.

[0044] Although not shown in the figures, it should be understood that the substrate also includes shallow trench isolation structures extending from the second surface of the substrate inwards. The substrate is isolated by both deep trench isolation structures and shallow trench isolation structures to form multiple photosensitive areas. The combination of shallow trench isolation structures and deep trench isolation structures achieves better isolation between adjacent photosensitive areas, thereby reducing crosstalk effects in the image sensor. It should be noted that the embodiments of this application manufacture a back-illuminated image sensor. A back-illuminated image sensor allows light to enter the pixel area through the back side; therefore, one side of the first surface of the substrate corresponds to the back side of the subsequently formed image sensor.

[0045] In this embodiment, an air gap AG is formed in the grid structure 205. The air gap AG and the isolation medium surrounding the air gap AG form a composite air grid structure, which controls photon crosstalk without reducing light sensitivity and provides next-generation grid technology support for pixel shrinkage of image sensors.

[0046] In this application, the grid structure and the deep trench isolation structure are formed through the same filling step to achieve precise alignment of the grid structure and the deep trench isolation structure.

[0047] In this application, the isolation medium includes a second isolation medium layer with a high dielectric constant to draw out free charges in the deep trench. In a preferred embodiment, a second dielectric layer 2042 is formed on the substrate 201, and the second dielectric layer 2042 is in contact with the second isolation medium layer IDLb, so that free charges on the surface of the substrate 201 and the isolation structure 203 can be drawn out through the same external structure.

[0048] Corresponding to the image sensor provided in the above embodiments, another embodiment of this application also provides a method for manufacturing an image sensor. Figure 3 A flowchart illustrating a method for manufacturing an image sensor according to an embodiment of this application is shown, with reference to... Figure 3 The manufacturing method includes:

[0049] Step S10: Form a first trench and a second trench that are interconnected in the semiconductor layer, wherein the first trench has a large opening size in the middle.

[0050] Step S20: An isolation medium layer is formed in the interconnected first trench and second trench, and an air gap is formed in the isolation medium layer of at least the first trench;

[0051] Step S30: Remove the upper part of the semiconductor layer, wherein the portion of the isolation dielectric layer retained in the trench forms an isolation structure, and the portion of the isolation dielectric layer exposed forms a grid structure.

[0052] Figures 4a to 4i This is a schematic diagram illustrating the steps of an exemplary image sensor manufacturing method provided in this application embodiment. The following is in conjunction with... Figure 3 as well as Figures 4a to 4i The manufacturing method of the image sensor provided in the embodiments of this application will be described in detail.

[0053] Step S10: Form an interconnected first trench DT1 and a second trench DT2 in the semiconductor layer. The first trench DT1 has a larger opening size in the middle, such as... Figures 4a to 4d As shown.

[0054] like Figure 4a As shown, a hard mask layer HM is formed on the semiconductor layer 201.

[0055] Semiconductor layer 201 may be selected from any one of semiconductor substrate, epitaxial semiconductor layer or combination thereof. In this embodiment, semiconductor layer 201 includes a single semiconductor substrate (e.g., silicon substrate) or an epitaxial semiconductor layer (e.g., silicon epitaxial layer), and the crystal orientation of the single semiconductor substrate or epitaxial semiconductor layer is

[111] .

[0056] In other embodiments, semiconductor layer 201 includes a stacked first semiconductor layer and a second semiconductor layer. The first semiconductor layer is, for example, a silicon substrate, and the second semiconductor layer is located on the surface of the first semiconductor layer, for example, a silicon epitaxial layer. The crystal orientations of the first semiconductor layer and the second semiconductor layer may be the same or different. When the crystal phases of the first semiconductor layer and the second semiconductor layer are the same, their crystal orientations are both

[111] . When the crystal phases of the first semiconductor layer and the second semiconductor layer are different, at least the crystal orientation of the second semiconductor layer is

[111] . The subsequently formed pre-trench DT3 and the first trench DT1 are formed in the second semiconductor layer to ensure that the first trench DT1 obtains the desired shape.

[0057] The hard mask layer HM can be selected from any of the following: oxide layer, nitride layer, or combination thereof. In this embodiment, the hard mask layer HM is, for example, an oxide layer with a thickness of, for example, 200 Å to 500 Å.

[0058] like Figure 4b As shown, an opening HMa extending through the thickness of the hard mask layer HM is formed, and a pre-trench DT3 is formed in the semiconductor layer 201.

[0059] The formation of the opening HMa and the pre-trench DT3 includes photolithography and etching steps. In the photolithography step, a resist mask layer is formed on the surface of the hard mask layer HM. A mask is placed on the resist mask layer, and the pattern of the mask is transferred to the resist mask layer using photolithography to form a patterned resist mask layer. In the etching step, the hard mask layer HM and the semiconductor layer 201 are etched through the patterned resist mask layer, transferring the pattern of the resist mask layer to the hard mask layer HM and the semiconductor layer 201, thereby forming an opening HMa that extends through the thickness of the hard mask layer HM, and forming a pre-trench DT3 in the semiconductor layer 201.

[0060] In this embodiment, for example, a dry etching process is used to etch the hard mask layer HM and the semiconductor layer 201 to form the opening HMa and the pre-trench DT3. Further, after forming the opening HMa and the pre-trench DT3, the resist mask layer is removed.

[0061] like Figure 4c As shown, the semiconductor layer 201 is etched through the opening HMa of the hard mask layer HM to form the first trench DT1.

[0062] In this step, a wet etching process is used to etch the semiconductor layer 201. The etchant enters the pre-trench DT3 through the opening HMa of the hard mask layer HM, thereby etching the sidewalls and bottom surface of the pre-trench DT3. Since the hard mask layer HM and the semiconductor layer 201 have different etching selectivity ratios, the hard mask layer HM is unaffected when the etchant etches the semiconductor layer 201. The etchant is, for example, a solution including tetramethylammonium hydroxide (TMAH).

[0063] In this embodiment, the desired shape of the first trench DT1 is obtained by selecting the crystal orientation of the semiconductor layer 201. As described above, the crystal orientation of the semiconductor layer 201 is

[111] . Typically, the ratio of the etching rate of the crystal plane with crystal orientation

[111] to the etching rate of other crystal planes is close to 1:100. In other words, the etching rates of the crystal planes with crystal orientation

[110] and crystal planes with crystal orientation

[100] are much greater than the etching rate of the crystal plane with crystal orientation

[111] . Since the crystal plane with crystal orientation

[111] is difficult to etch, a rhomboid first trench DT1 is formed along the crystal plane with crystal orientation

[111] . The center of the rhomboid first trench DT1 has a large opening size.

[0064] like Figure 4dAs shown, the semiconductor layer 201 is etched through the opening HMa of the hard mask layer HM to form a second trench DT2 that communicates with the first trench DT1. The first trench DT1 and the second trench DT2 are interconnected to form a trench extending from the surface of the semiconductor layer 201 into its interior.

[0065] In this step, the semiconductor layer 201 is etched using a dry etching process. Due to the vertical characteristics of dry etching, the etchant etches the bottom of the first trench DT1, and the second trench DT2 formed extends downward from the bottom of the first trench DT1. The opening size of the hard mask layer HM limits the opening size of the second trench DT2.

[0066] Step S20: An isolation medium layer IDL is formed in the trench, wherein at least the isolation medium layer IDL of the first trench DT1 has an air gap AG, such as Figure 4e and Figure 4f As shown.

[0067] like Figure 4e As shown, in this step, for example, a deposition process is used to form an isolation dielectric layer (IDL). The isolation dielectric layer (IDL) comprises one or more dielectric layers. In this embodiment, the isolation dielectric layer (IDL) comprises a first isolation dielectric layer (IDLa), a second isolation dielectric layer (IDLb), and a third isolation dielectric layer (IDLc). The first isolation dielectric layer (IDLa) covers the surface of the hard mask layer (HM) and the bottom and sidewalls of the trench. The second isolation dielectric layer (IDLb) conformally covers the surface of the first isolation dielectric layer (IDLa), and the third isolation dielectric layer (IDLc) covers the surface of the second isolation dielectric layer (IDLb) above the hard mask layer (HM) and fills the remaining space in the trench. Furthermore, because the first trench (DT1) has a large opening size in the middle, an air gap (AG) is formed at least in the middle of the first trench (DT1) when the rest of the trench is completely filled. In other embodiments, due to the rapid sealing of the top of the first trench (DT1), the air gap (AG) may also extend into the interior of the second trench (DT2).

[0068] In one embodiment, the first isolation dielectric layer IDLa is, for example, an oxide layer (OX), and the second isolation dielectric layer IDLb is a dielectric layer with a high dielectric constant. A high dielectric constant dielectric layer typically refers to a dielectric layer with a dielectric constant higher than that of silicon oxide (SiO2), such as hafnium dioxide (HfO2), zirconium oxide (ZrO2), titanium dioxide (TiO2), etc. The third isolation dielectric layer IDLc is, for example, an oxide layer (OX).

[0069] like Figure 4f As shown, the isolation dielectric layer IDL on the surface of the hard mask layer HM is removed, and the hard mask layer HM is also removed.

[0070] In this step, for example, chemical mechanical polishing (CMP) is used, which simultaneously removes the isolation dielectric layer (IDL) and the hard mask layer (HM) to planarize the surface of the exposed semiconductor layer 201. In other embodiments, an etch-back process can also be used to remove the isolation dielectric layer (IDL) and the hard mask layer (HM).

[0071] It is worth noting that the surface of the remaining isolation dielectric layer IDL in the trench is flush with the surface of the semiconductor layer 201, and the isolation dielectric layer IDL does not expose the air gap AG. In other words, the opening at the top of the air gap AG is still blocked by the isolation dielectric layer IDL. Furthermore, a lateral arrangement of the first isolation dielectric layer IDLa, the second isolation dielectric layer IDLb, the third isolation dielectric layer IDLc, the second isolation dielectric layer IDLb, and the first isolation dielectric layer IDLa is formed on the surface of the isolation dielectric layer IDL.

[0072] Step S30: Remove the upper part of the semiconductor layer 201, wherein the portion of the isolation dielectric layer IDL retained in the trench forms an isolation structure 203, and the exposed portion of the isolation dielectric layer IDL forms a grid structure 205, as shown. Figure 4g As shown.

[0073] In this step, the semiconductor layer 201 is etched back, so that the upper part of the semiconductor layer 201 is removed while the lower part of the semiconductor layer 201 is retained. After the upper part of the semiconductor layer 201 is removed, the sidewalls of the isolation dielectric layer IDL surrounding the upper part of the semiconductor layer 201 are exposed.

[0074] Furthermore, this embodiment also includes the steps of forming a first dielectric layer 2041, a second dielectric layer 2042, and a third dielectric layer 2043, as detailed below. Figure 4h and Figure 4i As shown.

[0075] like Figure 4h As shown, a first dielectric layer 2041 is formed on the surface of the semiconductor layer 201.

[0076] In this step, for example, a wet oxidation process is used to form a first dielectric layer 2041 on the surface of the semiconductor layer 201. The first dielectric layer 2041 will not be formed on the sidewalls and surface of the exposed isolation dielectric layer IDL (grid structure 205). The first dielectric layer 2041 can repair the damage to the semiconductor layer 201 caused by etching.

[0077] like Figure 4i As shown, a second dielectric layer 2042 and a third dielectric layer 2043 are formed.

[0078] In this step, for example, a deposition process is used to form a second dielectric layer 2042 and a third dielectric layer 2043. The second dielectric layer 2042 covers the surface of the first dielectric layer 204, as well as the exposed sidewalls and surface of the isolation dielectric layer IDL. The third dielectric layer 2043 conformally covers the surface of the second dielectric layer 2042.

[0079] The second dielectric layer 2042 and the second isolation dielectric layer IDLb are made of the same material, and the second dielectric layer 2042 and the second isolation dielectric layer IDLb are in contact on the top surface of the isolation dielectric layer IDL (grid structure 205). The third dielectric layer 2043 is, for example, an oxide layer.

[0080] The unexpected technical effect of this application is:

[0081] In this embodiment, an air gap is formed in the grid structure, and the air gap and the isolation medium surrounding the air gap form a composite air grid structure, which controls photon crosstalk without reducing light sensitivity and provides next-generation grid technology support for pixel shrinkage of image sensors.

[0082] In this application, the grid structure and the deep trench isolation structure are formed through the same filling step to achieve precise alignment of the grid structure and the deep trench isolation structure.

[0083] In this application, the isolation medium includes a second isolation medium layer with a high dielectric constant to draw out free charges in the deep trench. In a preferred embodiment, the second dielectric layer is formed on the substrate, and the second dielectric layer is in contact with the second isolation medium layer, so that free charges on the substrate surface and the isolation structure can be drawn out through the same external structure.

[0084] In this application, by selecting the crystal orientation of the semiconductor layer, a larger opening size is made in the middle of the first trench, thereby forming an air gap in the isolation dielectric layer during the formation of the isolation dielectric layer in the first trench.

[0085] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit the application to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing an image sensor, characterized in that, include: A first trench and a second trench are formed in a semiconductor layer, which are interconnected. The middle part of the first trench has a larger opening size relative to the bottom and top of the first trench. An isolation medium layer is formed in the interconnected first and second trenches, and an air gap is formed in at least the isolation medium layer in the first trench. The upper part of the semiconductor layer is removed, and the portion of the isolation dielectric layer remaining in the trench forms an isolation structure. The portion of the isolation dielectric layer that is exposed, including the air gap, forms a grid structure. The top of the grid structure becomes a transverse arrangement of the first isolation dielectric layer, the second isolation dielectric layer, the third isolation dielectric layer, the second isolation dielectric layer, and the first isolation dielectric layer. as well as A first dielectric layer is formed, which covers the surface of the semiconductor layer; A second dielectric layer is formed, which covers the surface of the first dielectric layer and also covers the top and sidewalls of the grid structure; A third dielectric layer is formed, conformally covering the surface of the second dielectric layer; The second medium layer is made of the same material as the second isolation medium layer, and at the top of the grid structure, the second medium layer is in contact with the second isolation medium layer exposed at the top of the grid structure.

2. The method for manufacturing an image sensor according to claim 1, wherein, Methods for forming interconnected first and second trenches in a semiconductor layer include: A hard mask layer is formed on the semiconductor layer; and An opening extending through its thickness is formed in the hard mask layer, and a pre-trench is formed in the semiconductor layer; The semiconductor layer is etched through the opening in the hard mask layer to form the first trench; The semiconductor layer is etched through the opening in the hard mask layer to form a second trench that communicates with the first trench. The first trench is formed by an anisotropic wet etching process, which gives the middle part of the first trench a large opening size.

3. The method for manufacturing an image sensor according to claim 1, wherein, The method for forming the isolation dielectric layer includes: A first isolation dielectric layer is formed, which covers the sidewalls of the first trench, the bottom and sidewalls of the second trench, and the surface of the semiconductor layer; A second insulating dielectric layer is formed, the second insulating dielectric layer conformally covering the surface of the first insulating dielectric layer; and A third isolation dielectric layer is formed to fill the remaining space of the first trench and the second trench, and to cover the surface of the second isolation dielectric layer above the semiconductor layer; Among them, the second isolation dielectric layer has a higher dielectric constant than the first isolation dielectric layer and the third isolation dielectric layer.

4. The method for manufacturing an image sensor according to claim 3, wherein, After forming the isolation dielectric layer, the process further includes: removing the isolation dielectric layer from the surface of the semiconductor layer.

5. An image sensor, comprising: Semiconductor layer; Deep trenches extend from the first surface of the semiconductor layer into its interior; An isolation medium layer includes a portion located in the deep trench and a portion extending outside the deep trench. The portion of the isolation medium layer located in the deep trench constitutes an isolation structure that isolates adjacent photosensitive areas. The portion of the isolation medium layer extending outside the deep trench forms a grid structure. The middle part of the grid structure has a wider dimension relative to the bottom and top of the grid structure, and an air gap is formed in the isolation medium layer in the middle part of the grid structure. The top of the grid structure forms a transverse arrangement of a first isolation medium layer, a second isolation medium layer, a third isolation medium layer, a second isolation medium layer, and a first isolation medium layer. as well as A first dielectric layer, the first dielectric layer covering the surface of the semiconductor layer; A second dielectric layer covers the surface of the first dielectric layer and also covers the top and sidewalls of the grid structure; A third dielectric layer conformally covers the surface of the second dielectric layer; The second medium layer is made of the same material as the second isolation medium layer, and at the top of the grid structure, the second medium layer is in contact with the second isolation medium layer exposed at the top of the grid structure.

6. The image sensor according to claim 5, wherein, The isolation dielectric layer includes a first isolation dielectric layer, a second isolation dielectric layer and a third isolation dielectric layer stacked together. The second isolation dielectric layer has a higher dielectric constant than the first isolation dielectric layer and the third isolation dielectric layer.

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