Cascode semiconductor device and manufacturing method thereof

Abstract

The present disclosure relates to a discrete cascode semiconductor device and an associated manufacturing method, the device comprising: a high voltage depletion mode device die having a gate terminal, a source terminal, and a drain terminal arranged on a first main surface thereof; a low voltage enhancement mode device die having a gate terminal and a source terminal formed on a first main surface thereof and a drain terminal formed on a second main surface opposite the first main surface; wherein a drain terminal of the high voltage device die is mounted on the drain connection; a source terminal of the low voltage device die and a gate terminal of the high voltage device are mounted on a common source connection; and the drain terminal of the low voltage device die is mounted on the source terminal of the high voltage device.

Description

[0001] This application is a divisional application of the patent application with application number 202010284962X, application date April 13, 2020, entitled "Common Source Common Gate Semiconductor Device and Manufacturing Method Thereof". Technical Field

[0002] This disclosure relates to a cascode semiconductor device and an associated method of manufacturing the same. Specifically, this disclosure relates to a cascode arrangement of a depletion-mode transistor die and an enhancement-mode transistor die, and an associated method of assembling such an arrangement. Background Technology

[0003] The cascode arrangement of transistors is well-known, especially for controlling normally-on (or depletion-mode) high-voltage semiconductor devices at zero gate-source voltage. A single-package cascode arrangement can be used in switching-mode applications, particularly in power supplies requiring efficient power switching. Typically, such as... Figure 1a and Figure 1b As shown, the cascode arrangement 100 may include a normally off (or enhancement-type) low-voltage device 102, which is connected in series with a high-voltage depletion-type device 104 via a common connection from the gate of a high-voltage device 104 to the source of the low-voltage device 102 and from the drain of the low-voltage device 102 to the source of the high-voltage device 104. Therefore, when the drain-source voltage of the low-voltage enhancement-type device 102 reaches the threshold voltage of the high-voltage device 104, the high-voltage depletion-type device 104 can be turned off. Thus, adding a low-voltage enhancement-type device 102 to form a cascode arrangement with the high-voltage depletion-type device 104 allows a normally open high-voltage device to be used as a normally off or enhancement-type device.

[0004] Typically, the high-voltage depletion-mode device 104 can be a gallium nitride (GaN) or silicon carbide (SiC) based JFET or HEMT, and the low-voltage enhancement-mode device 102 can be a silicon (Si) based MOSFET, and both the high-voltage and low-voltage devices are integrated into a single semiconductor device package 100.

[0005] As in Figure 1aAs shown in more detail, both the high-voltage and low-voltage devices are integrated into a single semiconductor device package 100, with the high-voltage device 104 typically mounted to a die pad 110. The low-voltage device 102 is then mounted or stacked on top of the high-voltage device 104. However, this mounting requires the use of an insulating material 106 between the die pad 110 and the high-voltage device 104 to electrically insulate the high-voltage device 104 from the die pad 110. The insulating material 106 can be a ceramic material. Ceramic-based insulators are preferred over glass or ceramic insulators because they are more robust at high operating temperatures. Additionally, ceramics are compatible with copper deposition processes to form so-called direct-bonded copper plating (DBPC) substrates. Typically, the insulating material 106 can be soldered 108 to the die pad 110, and similarly, the high-voltage device 104 can be soldered to the die pad 110. Drain and source connections 112 can be made to the high-voltage device 104 using suitable wire bonding. Similarly, the carrier 110 can be electrically connected to the high-voltage device 104 or the low-voltage device 102 via an electrical via (not shown) passing through the insulating material 106 to the die pad 110.

[0006] Furthermore, the aforementioned common-source-cascode device connection between the corresponding gate, source, and drain of the high-voltage device 104 and the low-voltage device 102 is currently formed by wire bonding 114 and 116 to achieve... Figure 1b The common-source, common-gate configuration. Due to the inductive effect of the leads during operation, this wire-bonded connection is compromised by DC power and switching losses. Connections using wire bonding result in higher parasitic inductance and capacitance, which can lead to so-called gate bounce. Gate bounce is a mis-turn-on mechanism in which, during high-frequency switching operation, a high-voltage device is switched to the "on" state when it should be in the "off" state. Furthermore, such as R... DSon Such devices may experience increased resistance, and lead connections may be affected by faults, especially during high-voltage operation of high-voltage devices.

[0007] Figure 1b The first cascode arrangement 100 and the second cascode arrangement 100' shown in the circuit diagram can be configured according to... Figure 1c The circuit diagram shows a half-bridge configuration. In the half-bridge configuration, the drain of the second cascode configuration 100' is connected to the source terminal of the low-voltage device 102, together with the gate of the high-voltage device 104.

[0008] In addition, the known arrangement described above is difficult to manufacture and requires a large package size to accommodate multiple wire bonds and die pads. Summary of the Invention

[0009] The various example embodiments address problems such as those mentioned above and / or others that may become clear from the following disclosures concerning improving the electrical and thermal performance of high-voltage and low-voltage transistors with cascode connections.

[0010] In certain example embodiments, aspects of this disclosure relate to the arrangement of high-voltage transistor dies relative to low-voltage transistor dies in a cascode arrangement and the manner of their electrical connection.

[0011] According to an embodiment, a discrete common-source common-gate semiconductor device is provided. The semiconductor device includes: a high-voltage depletion-type device die having a gate, a source, and a drain terminal arranged on a first main surface thereon; and a low-voltage enhancement-type device die having a gate and a source terminal formed on its first main surface and a drain terminal formed on a second main surface opposite to the first main surface; wherein the drain terminal of the high-voltage device die is mounted on a drain connection; the source terminal of the low-voltage device die and the gate terminal of the high-voltage device are mounted on a common-source connection; and the drain terminal of the low-voltage device die is mounted on the source terminal of the high-voltage device.

[0012] The gate terminal of a low-voltage device die can be mounted on a gate connection. The drain connection, common-source connection, and gate connection can be clamp-on wire connections. The clamp-on wire connection may include a bend between the first and second ends, such that the connection is formed as a gull-wing lead. The clamp-on wire connection may include mechanical supports for high-voltage depletion-mode device dies and low-voltage enhancement-mode device dies.

[0013] The carrier can be mounted on the second primary surface of the high-voltage device, wherein the carrier includes an insulating core disposed between two outer metal layers. The top surface of the carrier can be exposed through the top surface of the molding material.

[0014] A semiconductor device is also provided, comprising: a first cascode semiconductor device and a second cascode semiconductor device according to an embodiment, wherein the first cascode semiconductor device and the second cascode semiconductor device are arranged in a half-bridge configuration.

[0015] According to an embodiment, a method for manufacturing a discrete common-source cascode semiconductor device is provided, the method comprising the steps of: providing a high-voltage depletion-type device die having a gate, a source, and a drain terminal disposed on a first main surface thereon; providing a low-voltage enhancement-type device die having a gate and a source terminal formed on the first main surface thereon and a drain terminal formed on a second main surface opposite to the first main surface; mounting the drain terminal of the high-voltage device die on a drain connection; mounting the source terminal of the low-voltage device die and the gate terminal of the high-voltage device on a common-source connection; and mounting the drain terminal of the low-voltage device die on a gate connection.

[0016] The method may further include mounting the drain terminal of the low-voltage device die onto the gate connection. The drain connection, common-source connection, and gate connection may be clip-on bonding wire connections.

[0017] The method may further include providing a bent portion between a first end and a second end of a clamp-on bonding wire connection, such that the connection is formed as a gull-wing lead. The clamp-on bonding wire connection may include mechanical supports for high-voltage depletion-mode device dies and low-voltage enhancement-mode device dies.

[0018] The method may further include mounting a carrier onto a second primary surface of a high-voltage device, wherein the carrier includes an insulating core disposed between two outer metal layers. The top surface of the carrier may be exposed through the top surface of the molding material. Attached Figure Description

[0019] The features of this disclosure will be described in more detail with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments and should not be considered as limiting the scope thereof. These drawings are for ease of understanding of this disclosure and are not necessarily drawn to scale. Those skilled in the art will readily recognize the advantages of the claimed subject matter when reading this specification in conjunction with the accompanying drawings, in which the same reference numerals are used to denote the same elements, wherein:

[0020] Figure 1a A side view of a known semiconductor device cascode package arrangement is shown;

[0021] Figure 1b A circuit diagram showing a known cascode connection between a high-voltage transistor and a low-voltage transistor is shown.

[0022] Figure 1c It shows Figure 1b The circuit diagram of a known half-bridge arrangement with two common source and common gate arrangements of the type shown.

[0023] Figure 2a A bottom view of a discrete cascode semiconductor device according to an embodiment is shown;

[0024] Figure 2b A first side view of a discrete cascode semiconductor device according to an embodiment is shown;

[0025] Figure 2c A top view of a discrete cascode semiconductor device according to an embodiment is shown;

[0026] Figure 2d A second side bottom view of a discrete cascode semiconductor device according to an embodiment is shown;

[0027] Figure 3a A top-side perspective view of a discrete cascode semiconductor device according to an embodiment is shown;

[0028] Figure 3b A bottom perspective view of a discrete cascode semiconductor device according to an embodiment is shown;

[0029] Figure 4a A bottom view of a half-bridge arrangement of a common-source, common-gate semiconductor device is shown;

[0030] Figure 4b A first side view showing a half-bridge arrangement of a common-source, common-gate semiconductor device;

[0031] Figure 4c A top view of a half-bridge arrangement of a common-source, common-gate semiconductor device is shown;

[0032] Figure 4d A second side view of a half-bridge arrangement of a cascode semiconductor device is shown; and

[0033] Figures 5a to 5g The steps in an example processing flow for assembling a common-source, common-gate semiconductor device according to an embodiment are shown. Detailed Implementation

[0034] Figures 2a to 2d Various views of a discrete cascode semiconductor device 200 according to an embodiment are shown. (Refer to...) Figure 2d The discrete cascode semiconductor device 200 includes a high-voltage depletion-mode device 204 (hereinafter, the high-voltage device) and a low-voltage enhancement-mode device 202 (hereinafter, the low-voltage device). The high-voltage device 204 and the low-voltage device 202 are discrete device dies. The low-voltage device 202 and the high-voltage device 204 are configured and integrated in a single package to form the semiconductor device 200 according to an embodiment.

[0035] like Figure 2a As shown, the high-voltage device 204 includes a gate terminal 222, a source terminal 228, and a drain terminal 220 on its first main surface, and is therefore considered a lateral device. This contrasts with a vertical device in which at least one of the terminals (typically the drain terminal) is formed on a second main surface opposite the first surface. The low-voltage device 202 includes a gate terminal 224 and a source terminal 226 formed on its first main surface and a drain terminal 218 formed on its second main surface, and is therefore considered a vertical device. The terminals of each of the low-voltage device 202 and the high-voltage device 204 listed above are configured and arranged to form electrical and mechanical connections with the semiconductor device 200 via external leads, or to form low-voltage to high-voltage die connections, as will be discussed in more detail below.

[0036] Regarding the high-voltage device 204, one or more gate terminals 222, drain terminals 220, and source terminals 228 are arranged on its first main surface. Each of the gate terminals 222, source terminals 228, and drain terminals 220 is arranged coplanarly on the first main surface, that is, the gate terminals 218, source terminals 222, and drain terminals 220 are in the same plane on the first main surface.

[0037] For the high-voltage device 204, drain connection 212 is electrically connected to and fixedly attached to drain terminal 220. Drain connection 212 forms an external drain connection for the cascode semiconductor device 200. Similarly, for the low-voltage device 202, source connection 214 is electrically connected to and fixedly attached to source terminal 226. Source connection 214 forms an external source connection or source lead for the cascode semiconductor device 200. Furthermore, source connection 214 is electrically connected to and fixedly attached to one or more gate terminals 222 of the high-voltage device 204. Referring to the above... Figure 1b The common-source cascode circuit diagram discussed shows that the electrical connection between the one or more gate terminals 222 of the high-voltage device 204 and the source terminal 226 of the low-voltage device 202 forms a common connection between the gate of the high-voltage device and the source of the low-voltage device.

[0038] The source terminal 228 of the high-voltage device 204 is electrically connected to and fixedly attached to the drain terminal 218 of the low-voltage device 202. In other words, the drain terminal 218 of the low-voltage device 202 is mounted on the source terminal 228 of the high-voltage device 204, thereby mounting and attaching the low-voltage device 202 to the source terminal 228 of the high-voltage device 204. To facilitate this attachment, the area of ​​the source terminal 228 of the high-voltage device 204 can be substantially equal to or larger than the area of ​​the drain terminal 218 of the low-voltage device 202, so as to facilitate stacking the low-voltage device 202 on the source terminal 228 of the high-voltage device 204. Referring to the above... Figure 1b The common source cascode circuit diagram discussed shows that the electrical connection between the source terminal 228 and the drain terminal 218 of the high-voltage device 204 forms the connection between the source of a common high-voltage device and the drain of a low-voltage device.

[0039] Based on the above discussion, those skilled in the art will thus see that the drain of the cascode semiconductor device 200 is the drain of the high-voltage device 204, the gate of the cascode semiconductor device 200 is the gate of the low-voltage device 202, and the source of the cascode semiconductor device 200 is typically the source of the high-voltage device leading to the low-voltage drain. This aligns with the above reference. Figure 1b The common source cascode circuit diagram is discussed.

[0040] Figure 2a and Figure 2dThe corresponding external gate connection, external source connection, and external drain connection of the cascode device 200 are shown. The external drain of the cascode device 200 includes the electrical and mechanical attachment of external drain connection 212 to the drain terminal 220 of the high-voltage device 204. The external gate of the cascode device 200 includes the electrical and mechanical attachment of external gate connection 216 to the gate terminal 224 of the low-voltage device 202. The external source of the cascode device 200 includes the electrical and mechanical attachment of external source connection 214 to both one or more gate terminals 222 of the high-voltage device 204 and the source terminal 228 of the low-voltage device 202. Thus, according to the above reference... Figure 1b The common-source cascode circuit diagram discussed here provides an external source connection 214 that provides a common connection between one or more gate terminals 222 of the high-voltage device 204 and the source terminal 228 of the low-voltage device 202.

[0041] The external drain connection 212, external gate connection 216, and external source connection 214 of the cascode device 200 are each arranged as corresponding external leads. The external gate connection 216 (gate lead), external source connection 214 (source lead), and external drain connection 212 (drain lead) form the external leads of the cascode semiconductor device 200. In this respect, the corresponding gate lead, source lead, and drain lead are each substantially elongated components, each having a first distal end and a second distal end. The corresponding first end of the lead is configured and arranged to connect to contacts arranged on an external carrier (not shown), such as a PCB. The lead may optionally include a bend 230 between the first and second distal ends, thereby forming a so-called "gull-wing" lead.

[0042] The corresponding second distal end of the lead is configured and arranged to allow the corresponding terminals of the high-voltage device 204 and the low-voltage device 202, as described above, to be electrically and mechanically attached thereto. The mechanical attachment of the external drain connection 212 to the drain terminal 220 of the high-voltage device 204 provides a mechanical support point for the high-voltage device. Similarly, the mechanical connection of the external source connection 214 to one or more gate terminals 222 of the high-voltage device provides one or more additional mechanical support points for the high-voltage device. The mechanical support provided by both the external drain connection 212 and the external source connection 214 is achieved by the upright portions 232, 234 arranged on their respective second distal ends.

[0043] Regarding the external drain connection 212, the dimensions of the upright portion 232 are configured to approximately match the dimensions of the drain terminal 220 of the high-voltage device 204. Regarding the external source connection 214, the dimensions of one or more upright portions 234 are configured to approximately match the dimensions of one or more corresponding gate terminals of the high-voltage device. Furthermore, the external source connection 214 also includes a downstand portion 236 to allow electrical and mechanical connection between the source terminal 226 of the low-voltage device 202 and the external source connection 214, thus forming a common gate-source connection between the high-voltage device and the low-voltage device. Additionally, the arrangement of the downstand portion also provides mechanical support for the low-voltage device 202, which is mounted to the high-voltage device 204 via the common drain-source connection as described above. Figure 2b and Figure 2d As shown in the side view, the height difference between the contact surfaces (i.e., the corresponding upright and inverted surfaces in contact with the corresponding device) is substantially equal to the thickness of the low-voltage device 202.

[0044] The external gate connection 216 may also include a portion whose dimensions are set to approximately match the dimensions of the gate terminal 224 of the low-voltage device 204.

[0045] Both external drain connection 212 and external source connection 214 can be branched or split to provide multiple pin-outs. The current-carrying capacity of external drain connection 212 and external source connection 214 can be substantially equal.

[0046] The above arrangement of external mechanical connections to the corresponding terminals of the high-voltage and low-voltage semiconductor devices allows for a cascode arrangement of the high-voltage device 204 and the low-voltage device 202, which does not require dedicated die pads or leadframes, nor does it require electrical connection of the high-voltage and low-voltage devices to such leadframes. In other words, external connections are used to support the high-voltage and low-voltage devices in the cascode arrangement, thus the cascode semiconductor device 200 according to the embodiment can be considered to have no or no die pads. Thus, the current arrangement does not have dedicated die pads, and support for the high-voltage device 204 and / or low-voltage device 202 is achieved using two or more leads mechanically connected to them. In this embodiment, support for the high-voltage device 204 is provided via source connection 214 and drain connection 212, and support for the low-voltage device 202 is provided at least via source connection 214. Optionally, additional support for the high-voltage device 204 and low-voltage device 202 can be provided via gate connection 216.

[0047] like Figure 2dAs shown, the second main surface of the high-voltage device 204 can be securely attached to the first main surface of the optional carrier 206 via an adhesive layer 208. This adhesive layer 208 can be an insulating type adhesive because the high-voltage device 204 is not electrically connected to the carrier 206. The carrier 206 can be a direct-bonded copper plated (DBPC) type carrier, comprising a three-layer structure: an insulating ceramic core, such as AlN or alumina, sandwiched between two outer copper layers. The copper layers may optionally be coated with a NiPd or Ag metallization layer to protect the copper from oxidation.

[0048] The carrier 206 serves as an insulating layer between the high-voltage device and the external connection, and also improves thermal performance. The top copper layer allows for electrical connection thereto. The bottom copper layer adjacent to the high-voltage device 204 is used to reduce the mismatch in the coefficient of thermal expansion between the high-voltage device 204 and the core of the DBPC when the high-voltage device is operating.

[0049] like Figure 3a As shown, the second main surface of the carrier 206 is arranged to be exposed through the top surface of the molding material 238. Figure 3a and Figure 3b As shown, the molding material 238 is arranged to encapsulate the high-voltage semiconductor device 204 and the low-voltage semiconductor device 202, and external gate connections, external source connections, and external drain connections are partially encapsulated outside the molding material by having their corresponding first ends encapsulated. This allows the gate connections, source connections, and drain connections to be connected to an external carrier such as a PCB.

[0050] Similarly, the low-voltage device 202 is securely attached to the high-voltage device 204 via an additional adhesive layer 209, forming the common drain-source connection discussed above. The additional adhesive layer may be a conductive layer, such as solder or conductive Ag sintered material.

[0051] Figures 4a to 4d The above reference is shown. Figures 2a to 2d The first cascode device 200 and the second cascode device 200' of the aforementioned type are arranged in a half-bridge configuration. This is to achieve... Figure 1c The circuit uses a consistent half-bridge arrangement, extending the drain connection of the first cascode device 100 to connect with the source connection of the second cascode device 100'. This connection can be achieved using a standard half-bridge connection 240. The half-bridge connection 240 provides... Figures 2a to 2d The arrangement is consistent with the drain terminal of the high-voltage device of the first cascode device 200 and the source terminal of the high-voltage device of the second cascode device 200'. Similarly, as Figures 2a to 2dIn this arrangement, the carrier 206 serves as an insulating layer between the high-voltage device and the external connection, and also improves thermal performance. The top copper layer allows for electrical connection with it. The bottom copper layer adjacent to the high-voltage device 204 is used to reduce the thermal expansion coefficient mismatch between the high-voltage device 204 and the core of the DBPC.

[0052] according to Figures 2a to 2d The arrangement of the second main surface of the support member 206 is such that... Figure 4c The top surface of the molded material 238 shown is exposed.

[0053] Reference Figures 5a to 5g An example method for assembling a common-source, common-gate semiconductor device according to an embodiment is described. For example... Figure 5a As shown, the process begins by arranging multiple insulating carriers 206 on a temporary carrier frame 502. The temporary carrier frame 502 can be arranged to include multiple locations arranged in a matrix to accommodate optional insulating carriers 206. (Refer to...) Figure 5b An adhesive layer 208 is formed on the carrier 206.

[0054] like Figure 5c As shown, a high-voltage semiconductor device 204 is then mounted on an insulating carrier 206. A low-voltage semiconductor device 202 is then mounted or stacked on top of the corresponding high-voltage semiconductor device 204, consistent with the above discussion regarding the electrical connection between the source terminal of the high-voltage semiconductor device 204 and the drain terminal of the low-voltage semiconductor device 202. The low-voltage semiconductor device 202 is fixedly and electrically attached to the high-voltage device 204 using any suitable material such as solder or conductive adhesive. After the stacking of the high-voltage and low-voltage semiconductor devices, suitable solder or conductive adhesive is applied to the terminals of the high-voltage and low-voltage semiconductor devices to fixably and electrically attach drain connection 212, source connection 214, and gate connection 216, as referred to above. Figures 2a to 2d Described.

[0055] In the absence of an insulating carrier, the high-voltage semiconductor device 204 can be directly placed on the temporary carrier frame 502.

[0056] like Figure 5c As shown, the drain connection 212, source connection 214, and gate connection 216 configured as a matrix are fixedly and electrically attached to the corresponding terminals of the high-voltage semiconductor device and the low-voltage semiconductor device. In this way, the corresponding drain connection 212, source connection 214, and gate connection 216 of multiple discrete cascode semiconductor devices 200 are attached in a single operation.

[0057] After attaching drain, source, and gate connections, each of the discrete cascode semiconductor devices 200 in the matrix is ​​encapsulated with a molding material, such as... Figure 5e As shown. Then, the drain connection, source connection, and gate connection are separated from the matrix and formed into their final geometry, as shown. Figure 5f As shown. Each of the discrete cascode semiconductor devices 200 is then isolated from the matrix to form the final discrete cascode semiconductor device 200.

[0058] Although reference Figures 2a to 2d The embodiments described above illustrate the processing flow; however, those skilled in the art should understand that the example assembly methods described above can also be applied to the above-mentioned references. Figures 4a to 4d The description of the half-bridge layout.

[0059] In the above embodiments, the high-voltage device die may be selected from one or more GaN-based transistors, one or more GaN-based HEMTs, or one or more SiC-based transistors, and the low-voltage device die may be one or more field-effect transistors, such as one or more silicon-based transistors.

[0060] Specific and preferred aspects of the invention are set forth in the appended independent claims. Combinations of features from the dependent and / or independent claims may be combined as needed, and not limited to those described in the claims.

[0061] The scope of this disclosure includes any novel feature or combination of features, or any generalization thereof, disclosed herein, whether expressly or impliedly, whether related to the claimed invention or whether it alleviates any or all the problems posed by this invention. The applicant hereby expressly states that new claims may be made for these features during the proceedings of this application or any such further application derived therefrom. Specifically, with reference to the appended claims, features of dependent claims may be combined with features of independent claims, and features of individual independent claims may be combined in any suitable manner, not merely in the specific combinations listed in the claims.

[0062] Features described in the context of a single embodiment may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, the various features described in the context of a single embodiment may also be provided individually or in any suitable sub-combination.

[0063] The term "comprising" does not exclude other elements or steps, and the term "a" does not exclude multiple elements or steps. Reference numerals in the claims should not be construed as limiting the scope of the claims.

Claims

1. A discrete cascode semiconductor device, comprising: A high-voltage depletion-type device die having a gate terminal, a source terminal, and a drain terminal disposed on its first main surface; A low-voltage enhancement-mode device die has a gate terminal and a source terminal formed on its first main surface and a drain terminal formed on a second main surface opposite to the first main surface; The drain terminal of the high-voltage device die is mounted on the drain connection; The source terminal of the low-voltage device die and the gate terminal of the high-voltage device are mounted on a common-source connection; and The drain terminal of the low-voltage device die is mounted on the source terminal of the high-voltage device.

2. The discrete cascode semiconductor device according to claim 1, wherein, The gate terminal of the low-voltage device die is mounted on the gate connection.

3. The discrete cascode semiconductor device according to claims 1 and 2, wherein, Drain connection, common source connection, and gate connection are clamp-on bonding wire connections.

4. The discrete cascode semiconductor device according to claim 4, wherein, The clamp-on bonding wire connection includes a bent portion between the first end and the second end, such that the connection is formed as a gull-wing wire.

5. The discrete cascode semiconductor device according to claims 3 to 4, wherein, The clip-on bonding wire connection includes mechanical supports for the high-voltage depletion-type device die and the low-voltage enhancement-type device die.

6. The discrete cascode semiconductor device according to claim 1 or 2, further comprising a carrier mounted on the second main surface of the high-voltage device, wherein, The carrier includes an insulating core disposed between two outer metal layers.

7. The discrete cascode semiconductor device according to claim 6, wherein, The top surface of the carrier is exposed through the top surface of the molding material.

8. A semiconductor device comprising a first cascode semiconductor device and a second cascode semiconductor device according to claims 1 to 7, wherein, The first cascode semiconductor device and the second cascode semiconductor device are arranged in a half-bridge configuration.

9. A method for manufacturing a discrete cascode semiconductor device, the method comprising the following steps: A high-voltage depletion-type device die having a gate terminal, a source terminal, and a drain terminal disposed on its first main surface is provided; A low-voltage enhancement-mode device die is provided having a gate terminal and a source terminal formed on its first main surface and a drain terminal formed on a second main surface opposite to the first main surface; The drain terminal of the high-voltage device die is mounted on the drain connection; The source terminal of the low-voltage device die and the gate terminal of the high-voltage device are mounted on a common-source connection; as well as The drain terminal of the low-voltage device die is mounted on the gate connection.

10. The method of claim 9, further comprising: The drain terminal of the low-voltage device die is mounted on the gate connection.

11. The method according to claim 9 or 10, wherein, Drain connection, common source connection, and gate connection are clamp-on bonding wire connections.

12. The method of claim 11, further comprising: A bend is provided between the first and second ends of the clamp-on bonding wire connection, such that the connection is formed as a gull-wing wire.

13. The method according to claims 9 to 12, wherein, The clip-on bonding wire connection includes mechanical supports for the high-voltage depletion-type device die and the low-voltage enhancement-type device die.

14. The method according to claim 9 or 10, further comprising: The carrier is mounted on the second main surface of the high-voltage device, wherein the carrier includes an insulating core disposed between two outer metal layers.

15. The method of claim 14, further comprising exposing the top surface of the carrier through the top surface of the molding material.

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