Semiconductor device

Abstract

A semiconductor device (1) is provided with: a substrate (10); n (N is an integer of 2 or more) first electrodes (22) provided on the substrate (10); a first dielectric film (23) provided on the N first electrodes (22); m second electrodes (24) (where M is an integer of 3 or more satisfying M > N) provided on the N first electrodes (22) via a first dielectric film (23); a first protective layer (26) covering the N first electrodes (22) and the M second electrodes (24); three or more external electrodes (27) penetrating the first protective layer (26); and a second protective layer (29) that covers the external electrodes (27) other than two external electrodes (27) among the three or more external electrodes (27), at least one second electrode (24) is disposed on each first electrode (22), M capacitor elements (CAP1), (CAP2), and (CAP3) are configured from N first electrodes (22), a first dielectric film (23), and M second electrodes (24), the M capacitor elements (CAP1), (CAP2), and (CAP3) are electrically connected in series, and the M capacitor elements (CAP1), (CAP2), and (CAP3) are electrically connected in series. Among the M capacitor elements (CAP1), (CAP2) and (CAP3), two capacitor elements (CAP1) and (CAP2) having two second electrodes (24A) and (24B) disposed on the same first electrode (22A) are electrically connected in series through the first electrode (22A). The two external electrodes (27), which are not covered by the second protective layer (29), constitute two terminal electrodes (27A) and (27B) that are electrically connected to two capacitor elements (CAP1) and (CAP3) among the M capacitor elements (CAP1), (CAP2) and (CAP3), respectively. Among the M capacitor elements (CAP1), (CAP2) and (CAP3), two capacitor elements (CAP2) and (CAP3) having two second electrodes (24B) and (24C) disposed on different first electrodes (22A) and (22B) are electrically connected in series by an external electrode (27C) that does not constitute two terminal electrodes (27A) and (27B), and the external electrode (27C) that does not constitute the two terminal electrodes (27A) and (27B) is covered by a second protective layer (29).

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] As a representative capacitor element used in semiconductor integrated circuits, MIM (Metal Insulator Metal) capacitors are known for example. MIM capacitors are capacitors with a parallel plate-type structure in which an insulator is sandwiched between a lower electrode and an upper electrode.

[0003] Patent Document 1 discloses a demultiplexer comprising a common port, a first signal port, a second signal port, a low-pass filter disposed between the common port and the first signal port that selectively allows signals with frequencies below a first cutoff frequency within a first pass band to pass, and a high-pass filter disposed between the common port and the second signal port that selectively allows signals with frequencies above a second cutoff frequency higher than the first cutoff frequency to pass. The low-pass filter includes a first LC resonant circuit and a first elastic wave resonator disposed on a branch line connecting the path from the first LC resonant circuit to the first signal port to ground. The resonant frequency of the first elastic wave resonator is higher than the first cutoff frequency.

[0004] Patent Document 2 discloses a capacitor manufacturing method, which includes the steps of forming a dielectric film on a wafer, forming a monitoring electrode with a predetermined area on a monitoring region included in a region where the dielectric film is formed on the wafer, measuring the capacitance value of a capacitor formed by the monitoring electrode and the dielectric film in the monitoring region, calculating the area of ​​an upper electrode formed in the region other than the monitoring region, i.e., the capacitor forming region, based on the measured capacitance value, and forming the upper electrode in the capacitor forming region based on the calculated area.

[0005] Patent Document 1: Japanese Patent Application Publication No. 2017-112525

[0006] Patent Document 2: Japanese Patent No. 6372677

[0007] In the high-frequency circuits of RF modules used for communication, frequencies above 700MHz are used. To improve communication speed, frequencies above 3GHz will be used in the future.

[0008] Figure 19 This is a circuit diagram representing a filter circuit using a comparison method.

[0009] For example, as in patent document 1 Figure 1 , Figure 19 This achieves a filter circuit that prevents the desired frequency from being transmitted to the later stages of the circuit. Connecting L and C in series allows the signal at the resonant frequency f0 = 1 / 2π√(LC) to be directed to ground.

[0010] The higher the frequency, the greater the impact of the deviation of the constants L and C on the resonant frequency. Therefore, high-frequency circuits select components with the smallest specification deviations.

[0011] As an example, in Figure 19 In an LC filter circuit, with L = 1nH and C = 1pF, f0 = 5.03GHz. However, assuming a capacitance deviation of ±0.05pF for C, and a variation of C = 0.95–1.05pF, f0 varies to 4.91–5.16GHz. For a filter characteristic of a high-frequency circuit, this variation in the resonant frequency f0 becomes a fatal problem.

[0012] To address the aforementioned issues, a component with smaller deviations in C and L is considered. However, conventional electronic components have a minimum limit for deviation, which may not be adequate to handle certain situations. Summary of the Invention

[0013] The present invention was made to solve the above-mentioned problems, and its purpose is to provide a semiconductor device with small capacitance deviation.

[0014] The semiconductor device of the present invention comprises: a substrate; N (where N is an integer of 2 or more) first electrodes disposed on the substrate; a first dielectric film disposed on the N first electrodes; M (where M is an integer of 3 or more satisfying M > N) second electrodes disposed on the N first electrodes via the first dielectric film; a first protective layer covering the N first electrodes and the M second electrodes; three or more external electrodes penetrating the first protective layer; and a second protective layer covering the external electrodes other than two of the three or more external electrodes, wherein at least one second electrode is disposed on each of the first electrodes, and the device comprises the N first electrodes and the first dielectric film. The above-mentioned M second electrodes constitute M capacitor elements. The above-mentioned M capacitor elements are electrically connected in series. Two capacitor elements having two second electrodes disposed on the same first electrode are electrically connected in series through the first electrode. The above-mentioned two external electrodes not covered by the above-mentioned second protective layer constitute two terminal electrodes that are electrically connected to two capacitor elements of the above-mentioned M capacitor elements respectively. Two capacitor elements having two second electrodes disposed on different first electrodes are electrically connected in series through external electrodes that do not constitute the above-mentioned two terminal electrodes. The above-mentioned external electrodes that do not constitute the above-mentioned two terminal electrodes are covered by the above-mentioned second protective layer.

[0015] According to the present invention, a semiconductor device with small capacitance deviation can be provided. Attached Figure Description

[0016] Figure 1 This is a cross-sectional view schematically illustrating an example of a capacitor according to the first embodiment of the present invention.

[0017] Figure 2 This is a top view schematically illustrating an example of a capacitor according to the first embodiment of the present invention.

[0018] Figure 3 Show Figure 1 as well as Figure 2 The equivalent circuit of the capacitor is shown.

[0019] Figure 4 This is a cross-sectional view schematically illustrating an example of a capacitor according to a second embodiment of the present invention.

[0020] Figure 5 This is a top view schematically illustrating an example of a capacitor according to a second embodiment of the present invention.

[0021] Figure 6 Show Figure 4 as well as Figure 5 The equivalent circuit of the capacitor is shown.

[0022] Figure 7 This is a cross-sectional view schematically illustrating an example of a capacitor according to a third embodiment of the present invention.

[0023] Figure 8 This is a top view schematically illustrating an example of a capacitor according to a third embodiment of the present invention.

[0024] Figure 9 Show Figure 7 as well as Figure 8 The equivalent circuit of the capacitor is shown.

[0025] Figure 10 This is a cross-sectional view schematically illustrating an example of a capacitor according to a fourth embodiment of the present invention.

[0026] Figure 11 This is a top view schematically illustrating an example of a capacitor according to the fourth embodiment of the present invention.

[0027] Figure 12 Show Figure 10 as well as Figure 11 The equivalent circuit of the capacitor is shown.

[0028] Figure 13 This is a cross-sectional view schematically illustrating an example of a capacitor according to the fifth embodiment of the present invention.

[0029] Figure 14 This is a top view schematically illustrating an example of a capacitor according to the fifth embodiment of the present invention.

[0030] Figure 15 Show Figure 13 as well as Figure 14 The equivalent circuit of the capacitor is shown.

[0031] Figure 16 This is a cross-sectional view schematically illustrating an example of a capacitor according to the sixth embodiment of the present invention.

[0032] Figure 17 This is a top view schematically illustrating an example of a capacitor according to the sixth embodiment of the present invention.

[0033] Figure 18 Show Figure 16 as well as Figure 17 The equivalent circuit of the capacitor is shown.

[0034] Figure 19 This is a circuit diagram representing a filter circuit using a comparison method. Detailed Implementation

[0035] The semiconductor device of the present invention will now be described.

[0036] However, the present invention is not limited to the following structures, and can be appropriately modified and applied without changing the spirit of the invention. Furthermore, structures combining two or more of the preferred structures of the present invention described below are also considered part of the present invention.

[0037] The embodiments shown below are examples, and of course, parts of the structure shown in different embodiments can be replaced or combined. In the second embodiment and thereafter, descriptions of matters identical to those in the first embodiment are omitted, and only the differences are explained. In particular, the same effects of the same structure are not mentioned sequentially in each embodiment.

[0038] In the following description, unless otherwise specified, each embodiment will be referred to simply as "the semiconductor device of the present invention." The shape and arrangement of the semiconductor device and its constituent elements are not limited to the examples shown in the figures.

[0039] Furthermore, as one embodiment of the semiconductor device of the present invention, a capacitor will be used as an example for description below. The semiconductor device of the present invention can be either the capacitor itself or a device including a capacitor.

[0040] The semiconductor device of the present invention is characterized by comprising: a substrate; N (where N is an integer of 2 or more) first electrodes disposed on the substrate; a first dielectric film disposed on the N first electrodes; M (where M is an integer of 3 or more satisfying M > N) second electrodes disposed on the N first electrodes via the first dielectric film; a first protective layer covering the N first electrodes and the M second electrodes; three or more external electrodes penetrating the first protective layer; and a second protective layer covering the external electrodes other than two of the three or more external electrodes, wherein at least one second electrode is disposed on each of the first electrodes, and the N first electrodes and the first dielectric film are disposed on the substrate. The dielectric film and the aforementioned M second electrodes constitute M capacitor elements. The M capacitor elements are electrically connected in series. Two capacitor elements having two second electrodes disposed on the same first electrode are electrically connected in series through the first electrode. The two external electrodes not covered by the aforementioned second protective layer constitute two terminal electrodes that are electrically connected to two capacitor elements of the M capacitor elements respectively. Two capacitor elements having two second electrodes disposed on different first electrodes are electrically connected in series through external electrodes that do not constitute the aforementioned two terminal electrodes. The aforementioned external electrodes that do not constitute the aforementioned two terminal electrodes are covered by the aforementioned second protective layer.

[0041] Furthermore, in this specification, "first, second, third, fourth, ... electrodes" refers to the electrodes that, counting from the substrate side, exist in the first layer (first), second layer (second), third layer (third), fourth layer (fourth), ... electrodes forming a capacitor element.

[0042] In addition, in this specification, "capacitor element" refers to an element (small capacitor) consisting of a dielectric film and a pair of electrodes facing each other through the dielectric film, and "capacitor" represents the concept of including multiple capacitor elements.

[0043] [First Implementation]

[0044] The capacitor of the first embodiment of the present invention has two (i.e., N=2) first electrodes, three (i.e., M=3) second electrodes, and three external electrodes.

[0045] Figure 1 This is a cross-sectional view schematically illustrating an example of a capacitor according to the first embodiment of the present invention. Figure 2 This is a top view schematically illustrating an example of a capacitor according to the first embodiment of the present invention. Figure 1 It is along Figure 2 The capacitor shown is a cross-sectional view along line I-I. Figure 3 Show Figure 1 as well as Figure 2 The equivalent circuit of the capacitor is shown.

[0046] In this instruction manual, such as Figure 1 as well as Figure 2 As shown, the length, width, and thickness directions of the capacitor (semiconductor device) are defined by arrows L, W, and T, respectively. Here, the length direction L, width direction W, and thickness direction T are orthogonal to each other.

[0047] Figure 1 as well as Figure 2 The capacitor 1 shown is characterized by having a substrate 10, an insulating film 21 disposed on the substrate 10, two first electrodes 22 disposed on the insulating film 21, a first dielectric film 23 disposed on the two first electrodes, three second electrodes 24 disposed on the two first electrodes 22 via the first dielectric film 23, a moisture-resistant film 25 disposed on the first dielectric film 23 and the second electrodes 24, a first protective layer 26 covering the two first electrodes 22, the three second electrodes 24 and the moisture-resistant film 25, three external electrodes 27 penetrating the first protective layer 26, and a second protective layer 29 covering one of the three external electrodes 27 except for the two external electrodes 27.

[0048] If one of the two first electrodes 22 is designated as first electrode 22A and the other as first electrode 22B, then the second electrode 24 includes second electrodes 24A and 24B disposed on the first electrode 22A, and second electrode 24C disposed on the first electrode 22B.

[0049] Furthermore, at least one second electrode 24 is disposed on each of the first electrodes 22. The two first electrodes 22, the first dielectric film 23, and the three second electrodes 24 constitute three capacitor elements CAP1, CAP2, and CAP3, which are connected in series (see reference). Figure 3 Two capacitor elements CAP1 and CAP2, which have two second electrodes 24A and 24B disposed on the same first electrode 22A, are electrically connected in series through the first electrode 22A. Two external electrodes 27 not covered by the second protective layer 29 constitute two terminal electrodes 27A and 27B that are electrically connected to two capacitor elements CAP1 and CAP3, respectively. Two capacitor elements CAP2 and CAP3, which have two second electrodes 24B and 24C disposed on different first electrodes 22A and 22B, are electrically connected in series through external electrodes 27C that do not constitute two terminal electrodes 27A and 27B. The external electrodes 27C that do not constitute two terminal electrodes 27A and 27B are covered by the second protective layer 29.

[0050] Therefore, it is possible to manufacture capacitors with smaller capacitance deviations (capacitance variations). The reasons for this are explained below.

[0051] Assuming the capacitance due to the thickness variation of the dielectric film within the wafer plane is C0 ± ΔC0, and if the capacitances of capacitor elements CAP1, CAP2, and CAP3 are respectively set as C1, C2, and C3, then the capacitance achievable using the above three-series capacitor structure can be calculated according to 1 / C = 1 / C1 + 1 / C2 + 1 / C3, becoming C0 / 3 + ΔC0 / 3. In other words, by connecting three capacitors in series, the capacitance variation can be reduced to 1 / 3.

[0052] Whether capacitors C1, C2, and C3 have the same value or different combinations of values, the target capacitance value C0 / 3 can be achieved. However, the capacitance deviation, which reflects the thickness deviation of the dielectric film, varies depending on the capacitor. When using different capacitors C1, C2, and C3, the total capacitance deviation ΔC0 / 3 becomes larger. Therefore, it is preferable that capacitors C1, C2, and C3 have the same value.

[0053] Furthermore, in this specification, "the same quantity" means that the quantities are substantially the same.

[0054] Another advantage is that by connecting multiple capacitor elements in series, low-capacitance capacitors can be easily formed. For example, with a dielectric film thickness of 1 μm, the capacitance is 1 pF when one capacitor is formed on a single chip. On the other hand, with the above structure, the electrode area is 1 / 4, and there are three capacitors connected in series, so low-capacitance capacitors with a capacitance of less than 0.1 pF can be formed.

[0055] Furthermore, the two capacitor elements CAP2 and CAP3, formed by different first electrodes 22A and 22B, are not electrically connected in series through a shared second electrode, but are electrically connected in series through an external electrode 27C that penetrates the first protective layer 26. Therefore, interference between capacitor elements CAP2 and CAP3 can be suppressed. This interference is particularly effective when the substrate 10 is a semiconductor substrate.

[0056] The following is a detailed description of each structure.

[0057] The substrate 10 is not particularly limited, but is preferably a semiconductor substrate such as a silicon substrate or a gallium arsenide substrate, or an insulating substrate such as glass or alumina.

[0058] The insulating film 21 is configured to cover the entire main surface of one side of the substrate 10. While the insulating film 21 may also cover only a portion of the main surface of the substrate 10, it must be located in an area larger than the first electrode 22 and overlapping the entire area of ​​the first electrode 22. Furthermore, if the substrate 10 is an insulating substrate such as glass or alumina, the insulating film 21 may not be provided.

[0059] That is, by providing an insulating film 21, capacitor elements CAP1, CAP2, and CAP3 are electrically insulated from the semiconductor substrate. This reduces the parasitic capacitance of each capacitor element CAP1, CAP2, and CAP3.

[0060] The material constituting the insulating film 21 is not particularly limited, but preferred examples include SiO2, SiN, Al2O3, HfO2, Ta2O5, ZrO2, etc.

[0061] The first electrode 22 is disposed at a position away from the end of the substrate 10. That is, the end of the first electrode 22 is located inside the substrate 10.

[0062] The material constituting the first electrode 22 is not particularly limited, but preferably includes Cu, Ag, Au, Al, Ni, Cr or Ti, or alloys containing at least one of these metals.

[0063] The first dielectric film 23 is configured to cover the first electrode 22 except for the opening. Figure 1 In this process, the end of the first dielectric film 23 is also disposed on the surface of the insulating film 21 extending from the end of the first electrode 22 to the end of the substrate 10. Alternatively, the end of the first dielectric film 23 may not be disposed at the end of the substrate 10.

[0064] The material constituting the first dielectric film 23 is not particularly limited, but oxides or nitrides such as SiO2, SiN, Al2O3, HfO2, and Ta2O5 are preferred.

[0065] The second electrode 24 is configured to sandwich the first dielectric film 23 and be opposite to the first electrode 22. More specifically, the second electrodes 24A and 24B are opposite to the first electrode 22A, and the second electrode 24C is opposite to the first electrode 22B.

[0066] In this embodiment, such as Figure 2 As shown, the three second electrodes 24 have the same area and the same planar shape. Specifically, the three second electrodes 24 are rectangular in shape with the same dimensions in the length direction L and the width direction W.

[0067] Furthermore, in this specification, when referred to simply as "area," it means the area viewed from above in the thickness direction T, and "planar shape" means the shape viewed from above in the thickness direction T.

[0068] The material constituting the second electrode 24 is not particularly limited, but preferably includes Cu, Ag, Au, Al, Ni, Cr or Ti, or alloys containing at least one of these metals.

[0069] The moisture-resistant film 25 is configured to cover the first dielectric film 23 and the second electrode 24, except for the opening. By providing the moisture-resistant film 25, the moisture resistance of the capacitor element, especially the first dielectric film 23, is improved. Alternatively, the moisture-resistant film 25 may not be provided.

[0070] The material constituting the moisture-resistant membrane 25 is not particularly limited, but moisture-resistant materials such as SiO2 and SiN are preferred.

[0071] In the first protective layer 26, openings are provided at positions overlapping with the openings of the first dielectric film 23 and the moisture-resistant film 25 (the openings overlapping with the first electrode 22B), and at positions overlapping with the openings of the moisture-resistant film 25 (the openings overlapping with the second electrode 24). By providing the first protective layer 26, the capacitor element, especially the first dielectric film 23, can be protected from moisture.

[0072] The material constituting the first protective layer 26 is not particularly limited, but resin materials such as polyimide resin and resin in solder resist are preferred.

[0073] The thickness of the first protective layer 26 is not particularly limited, but it is preferably 0.5 μm or more and 10 μm or less, more preferably 1 μm or more and 5 μm or less. By electrically connecting the two capacitor elements CAP2 and CAP3 using the external electrode 27C formed on the first protective layer 26 having such a thickness, the electric field coupling between the first electrode 22 and the external electrode 27C is mitigated. With this structure, the parasitic capacitance of each capacitor element CAP1, CAP2, and CAP3 can be reduced. By adopting this structure and the aforementioned insulating film 21, the parasitic capacitance of each capacitor element CAP1, CAP2, and CAP3 can be minimized.

[0074] The external electrodes 27 constituting terminal electrodes 27A and 27B are electrically connected to the capacitor elements (CAP1 and CAP3) connected in series at both ends of the three capacitor elements CAP1, CAP2 and CAP3, respectively. More specifically, the external electrodes 27 constituting terminal electrodes 27A and 27B are connected to the second electrode 24A and the first electrode 22B, respectively.

[0075] On the other hand, the external electrode 27C, which does not constitute terminal electrodes 27A and 27B, is a connection wiring and is electrically connected to the capacitor element (here, capacitor element CAP2) and the other capacitor element (here, capacitor element CAP3) among the three capacitor elements CAP1, CAP2, and CAP3, excluding the capacitor element connected in series at both ends. More specifically, the external electrode 27C is connected to the second electrodes 24B and 24C.

[0076] The material constituting the external electrode 27 is not particularly limited, but Cu, Ni, Ag, Au, or Al are preferred. The external electrode 27 can be a single-layer structure or a multi-layer structure. Preferably, the outermost surface of the external electrode 27 is composed of Au or Sn.

[0077] When the external electrode 27 has a multilayer structure, such as Figure 1 As shown, the external electrode 27 may also have a seed layer 28a, a first plating layer 28b, and a second plating layer 28c sequentially from the substrate 10 side.

[0078] As the seed layer 28a of the external electrode 27, for example, a laminate of a conductive layer made of titanium (Ti) and a conductive layer made of copper (Cu) (Ti / Cu) can be used.

[0079] Materials that form the first plating layer 28b of the external electrode 27 include, for example, nickel (Ni).

[0080] Materials constituting the second plating layer 28c of the external electrode 27 include, for example, gold (Au) and tin (Sn).

[0081] The materials constituting the three external electrodes 27 can be the same or different from each other.

[0082] An opening is provided in the second protective layer 29 to expose the terminal electrodes 27A and 27B. The second protective layer 29 insulates the external electrode 27 (external electrode 27C), excluding the terminal electrodes 27A and 27B, from the outside. Furthermore, by providing the second protective layer 29, the capacitor elements, especially the first dielectric film 23, can be more effectively protected from moisture.

[0083] The material constituting the second protective layer 29 is not particularly limited, but resin materials such as polyimide resin and resin in solder resist are preferred.

[0084] The distance between adjacent capacitor elements is not particularly limited, but it is preferably 5 μm or more and 100 μm or less, more preferably 10 μm or more and 50 μm or less. By keeping it below 100 μm, the difference in the thickness of the first dielectric film 23 between each capacitor element is reduced, and capacitor elements with the same capacitance can be formed.

[0085] For example, it can be manufactured using the same methods as conventional MIM capacitors. Figure 1 as well as Figure 2 The capacitor shown is 1.

[0086] [Second Implementation]

[0087] The second embodiment of the present invention differs from the first embodiment in that at least two of the three second electrodes of the capacitor have different areas.

[0088] Figure 4 This is a cross-sectional view schematically illustrating an example of a capacitor according to a second embodiment of the present invention. Figure 5 This is a top view schematically illustrating an example of a capacitor according to a second embodiment of the present invention. Figure 4 It is along Figure 5 The capacitor shown is a cross-sectional view along line I-I. Figure 6 Show Figure 4 as well as Figure 5 The equivalent circuit of the capacitor is shown.

[0089] exist Figure 1 as well as Figure 2 In the capacitor 1 shown, although the capacitance deviation can be reduced, there is a possibility that the capacitance center may shift from the desired value.

[0090] In contrast, Figure 4 as well as Figure 5 In the capacitor 2 shown, at least two of the three second electrodes 24 have different areas. This allows for adjustment of the capacitor center. This is because the area of ​​each second electrode 24 can be set to counteract the thickness distribution of the first dielectric film 23 within the wafer plane.

[0091] More specifically, each second electrode 24 is composed of a first region 30a with a rectangular planar shape and a second region 30b with a rectangular planar shape protruding from the first region 30a. Moreover, the first regions 30a of the three second electrodes 24 have the same area, while the areas of at least two of the second regions 30b of the three second electrodes 24 are different from each other.

[0092] Alternatively, the areas of all the second electrodes 24 may be different from each other, or the areas of the second regions 30b of all the second electrodes 24 may be different from each other.

[0093] For example, it can be manufactured using the method described in Patent Document 2. Figure 4 as well as Figure 5 The capacitor shown is 2.

[0094] In this embodiment, the capacitor center can be adjusted to a desired value. Furthermore, since the area of ​​the second electrode 24 can be corrected to offset the thickness distribution of the first dielectric film 23 within the wafer surface, the capacitance distribution can be reduced. That is, a capacitor that allows for adjustment of the capacitor center and suppresses capacitance deviation can be realized.

[0095] [Third Implementation]

[0096] The capacitor of the third embodiment of the present invention differs from that of the second embodiment in that it further comprises a second dielectric film on three (i.e., M=3) second electrodes and three (i.e., M=3) third electrodes, at least two of which have different areas.

[0097] Figure 7 This is a cross-sectional view schematically illustrating an example of a capacitor according to a third embodiment of the present invention. Figure 8 This is a top view schematically illustrating an example of a capacitor according to a third embodiment of the present invention. Figure 7 It is along Figure 8 The capacitor shown is a cross-sectional view along line I-I. Figure 9 Show Figure 7 as well as Figure 8 The equivalent circuit of the capacitor is shown.

[0098] Figure 7 as well as Figure 8The capacitor 3 shown also includes a second dielectric film 31 disposed on the three second electrodes 24, and three third electrodes 32 disposed on the three second electrodes 24 respectively via the second dielectric film 31.

[0099] That is, three capacitor elements CAP4, CAP5, and CAP6 are formed by three second electrodes 24, a second dielectric film 31, and three third electrodes 32, and the six capacitor elements CAP1 to CAP6 are connected in series (see reference). Figure 9 ).

[0100] Thus, in this embodiment, the number of series connections can be increased, further suppressing capacitance deviation. Furthermore, since the capacitor elements are formed in the thickness direction, chip miniaturization is possible.

[0101] In addition, Figure 7 as well as Figure 8 In the capacitor 3 shown, at least two of the three third electrodes 32 have different areas. This allows for adjustment of the capacitor center. This is because the area of ​​each third electrode 32 can be set to offset the thickness distribution of the second dielectric film 31 within the wafer plane.

[0102] More specifically, each third electrode 32 is composed of a first region 33a with a rectangular planar shape and a second region 33b with a rectangular planar shape protruding from the first region 33a. Moreover, the first regions 33a of the three third electrodes 32 have the same area, while the areas of at least two of the second regions 33b of the three third electrodes 32 are different from each other.

[0103] Alternatively, the areas of all the third electrodes 32 may be different from each other, or the areas of the second regions 33b of all the third electrodes 32 may be different from each other.

[0104] also, Figure 8 The diagram shows the state where each third electrode 32 completely overlaps with the opposing second electrode 24 when viewed from above in the thickness direction T. However, it is also possible that each third electrode 32 partially overlaps with the opposing second electrode 24 when viewed from above in the thickness direction T. Alternatively, each third electrode 32 may be formed within the frame of each second electrode 24.

[0105] For example, it can be manufactured using the method described in Patent Document 2. Figure 7 as well as Figure 8 The capacitor shown is 3.

[0106] The following is a detailed description of the various structures unique to this embodiment.

[0107] The second dielectric film 31 is configured to cover the second electrode 24 except for the opening. Figure 7In this configuration, the end of the second dielectric film 31 is also disposed on the surface of the first dielectric film 23 between the end of the first electrode 22 and the first dielectric film 23. Alternatively, the end of the second dielectric film 31 may not be disposed at the end of the substrate 10.

[0108] The material constituting the second dielectric film 31 is not particularly limited, but oxides or nitrides such as SiO2, SiN, Al2O3, HfO2, and Ta2O5 are preferred.

[0109] The third electrode 32 is configured to sandwich the second dielectric film 31 and face the second electrode 24. More specifically, the third electrode 32 includes a third electrode 32A facing the second electrode 24A, a third electrode 32B facing the second electrode 24B, and a third electrode 32C facing the second electrode 24C.

[0110] The material constituting the third electrode 32 is not particularly limited, but preferably includes Cu, Ag, Au, Al, Ni, Cr or Ti, or alloys containing at least one of these metals.

[0111] The external electrodes 27 constituting terminal electrodes 27A and 27B are electrically connected to the capacitor elements (capacitor elements CAP4 and CAP3) connected in series at both ends of the six capacitor elements CAP1 to CAP6. More specifically, the external electrodes 27 constituting terminal electrodes 27A and 27B are connected to the third electrode 32A and the first electrode 22B, respectively.

[0112] On the other hand, the external electrode 27C, which does not constitute terminal electrodes 27A and 27B, is electrically connected to two of the six capacitor elements CAP1 to CAP6, excluding the capacitor element connected in series at both ends (here, capacitor elements CAP5 and CAP6). More specifically, the external electrode 27C is connected to the third electrodes 32B and 32C.

[0113] In this embodiment, a capacitor with a large number of series connections can be achieved, the capacitor center can be adjusted, and capacitor deviation can be further suppressed. In addition, chip miniaturization can be achieved.

[0114] [Fourth Implementation]

[0115] The capacitor of the fourth embodiment of the present invention differs from that of the third embodiment in that it further comprises a third dielectric film on three (i.e., M=3) third electrodes and three (i.e., M=3) fourth electrodes, and at least two of the three fourth electrodes have different areas.

[0116] Figure 10 This is a cross-sectional view schematically illustrating an example of a capacitor according to a fourth embodiment of the present invention. Figure 11This is a top view schematically illustrating an example of a capacitor according to the fourth embodiment of the present invention. Figure 10 It is along Figure 11 The capacitor shown is a cross-sectional view along line I-I. Figure 12 Show Figure 10 as well as Figure 11 The equivalent circuit of the capacitor is shown.

[0117] Figure 10 as well as Figure 11 The capacitor 4 shown also includes a third dielectric film 34 disposed on the three third electrodes 32, and three fourth electrodes 35 disposed on the three third electrodes 32 respectively via the third dielectric film 34.

[0118] That is, three capacitor elements CAP7, CAP8, and CAP9 are formed by three third electrodes 32, a third dielectric film 34, and three fourth electrodes 35, and the nine capacitor elements CAP1 to CAP9 are connected in series (see reference). Figure 12 ).

[0119] Thus, in this embodiment, the increased number of series connections further suppresses capacitance deviation. Furthermore, since the capacitor elements are formed in the thickness direction, chip miniaturization is possible.

[0120] In addition, Figure 10 as well as Figure 11 In the capacitor 4 shown, at least two of the three fourth electrodes 35 have different areas. This allows for adjustment of the capacitor center. This is because the area of ​​each fourth electrode 35 can be set to offset the thickness distribution of the third dielectric film 34 within the wafer plane.

[0121] More specifically, each fourth electrode 35 is composed of a first region 36a with a rectangular planar shape and a second region 36b with a rectangular planar shape protruding from the first region 36a. Moreover, the first regions 36a of the three fourth electrodes 35 have the same area, while the areas of at least two of the second regions 36b of the three fourth electrodes 35 are different from each other.

[0122] Alternatively, the areas of all the fourth electrodes 35 may be different from each other, or the areas of the second regions 36b of all the fourth electrodes 35 may be different from each other.

[0123] also, Figure 11 The diagram shows the state where each fourth electrode 35 completely overlaps with the opposing third electrode 32 when viewed from above in the thickness direction T. However, it is also possible that each fourth electrode 35 partially overlaps with the opposing third electrode 32 when viewed from above in the thickness direction T. Furthermore, Figure 11The diagram shows the state where each third electrode 32 completely overlaps with the opposing second electrode 24 when viewed from above in the thickness direction T. However, it is also possible that each third electrode 32 partially overlaps with the opposing second electrode 24 when viewed from above in the thickness direction T. Alternatively, each fourth electrode 35 may be formed within the frame of each third electrode 32, and each third electrode 32 may be formed within the frame of each second electrode 24.

[0124] For example, it can be manufactured using the method described in Patent Document 2. Figure 10 as well as Figure 11 The capacitor shown is 4.

[0125] The following is a detailed description of the various structures unique to this embodiment.

[0126] The third dielectric film 34 is configured to cover the third electrode 32 in the portion except for the opening. Figure 10 In this process, the end of the third dielectric film 34 is also disposed on the surface of the second dielectric film 31 between the end of the first electrode 22 and the second dielectric film 31. The end of the third dielectric film 34 may also not be disposed at the end of the substrate 10.

[0127] The material constituting the third dielectric film 34 is not particularly limited, but oxides or nitrides such as SiO2, SiN, Al2O3, HfO2, and Ta2O5 are preferred.

[0128] The fourth electrode 35 is configured to sandwich the third dielectric film 34 and face the third electrode 32. More specifically, the fourth electrode 35 includes a fourth electrode 35A facing the third electrode 32A, a fourth electrode 35B facing the third electrode 32B, and a fourth electrode 35C facing the third electrode 32C.

[0129] The material constituting the fourth electrode 35 is not particularly limited, but preferably includes Cu, Ag, Au, Al, Ni, Cr or Ti, or alloys containing at least one of these metals.

[0130] The external electrodes 27 constituting terminal electrodes 27A and 27B are electrically connected to the capacitor elements (capacitor elements CAP7 and CAP3) connected in series at both ends of the nine capacitor elements CAP1 to CAP9. More specifically, the external electrodes 27 constituting terminal electrodes 27A and 27B are connected to the fourth electrode 35A and the first electrode 22B, respectively.

[0131] On the other hand, the external electrode 27C, which does not constitute terminal electrodes 27A and 27B, is electrically connected to two capacitor elements (capacitor elements CAP8 and CAP9) out of the nine capacitor elements CAP1 to CAP9, excluding the capacitor element connected in series at both ends. More specifically, the external electrode 27C is connected to the fourth electrodes 35B and 35C.

[0132] In this embodiment, a capacitor with a large number of series connections can be achieved, the capacitor center can be adjusted, and capacitor deviation can be further suppressed. In addition, chip miniaturization can be achieved.

[0133] [Fifth Implementation]

[0134] The fifth embodiment of the present invention differs from the second embodiment in that the capacitor is located within a semiconductor substrate and element isolation is provided between the three capacitor elements.

[0135] Figure 13 This is a cross-sectional view schematically illustrating an example of a capacitor according to the fifth embodiment of the present invention. Figure 14 This is a top view schematically illustrating an example of a capacitor according to the fifth embodiment of the present invention. Figure 13 It is along Figure 14 The capacitor shown is a cross-sectional view along line I-I. Figure 15 Show Figure 13 as well as Figure 14 The equivalent circuit of the capacitor is shown.

[0136] Figure 13 as well as Figure 14 The substrate 10 of the capacitor 5 shown is a semiconductor substrate, and element isolation 37 is provided between the three capacitor elements CAP1, CAP2 and CAP3 in the semiconductor substrate.

[0137] This reduces the current flowing through the semiconductor substrate between adjacent capacitor elements, thus reducing mutual interference between them. Consequently, the accuracy of the capacitance center value and capacitance deviation of capacitor 5 can be improved.

[0138] Specifically, the element isolation 37 is a structure in which a cavity is formed in a semiconductor substrate and a SiO2 film is buried (STI: Shallow Trench Isolation).

[0139] like Figure 14 As shown, the preferred element isolation 37 is preferably disposed at least between adjacent capacitor elements (here, between capacitor elements CAP1 and CAP2, and between capacitor elements CAP2 and CAP3), and is configured to surround each capacitor element CAP1, CAP2, and CAP3. Furthermore, the preferred element isolation 37 is configured to overlap with and surround the periphery of the first electrode 22.

[0140] [Sixth Implementation Method]

[0141] The capacitor of the sixth embodiment of the present invention differs from that of the fifth embodiment in that the material for element isolation is different.

[0142] Figure 16 This is a cross-sectional view schematically illustrating an example of a capacitor according to the sixth embodiment of the present invention. Figure 17 This is a top view schematically illustrating an example of a capacitor according to the sixth embodiment of the present invention. Figure 16 It is along Figure 17 The capacitor shown is a cross-sectional view along line I-I. Figure 18 Show Figure 16 as well as Figure 17 The equivalent circuit of the capacitor is shown.

[0143] exist Figure 16 as well as Figure 17 In the capacitor 6 shown, the substrate 10 is an n-type semiconductor substrate, and the element isolation 37 is a structure in which a p+ active layer is formed on the n-type semiconductor substrate. For example, such element isolation 37 can be formed by implanting p-type impurities at a high concentration on the n-type semiconductor substrate using ion implantation.

[0144] This embodiment also reduces the current flowing through the semiconductor substrate between adjacent capacitor elements, thus reducing mutual interference between adjacent capacitor elements. As a result, the accuracy of the capacitance center value and capacitance deviation of capacitor 6 can be improved.

[0145] [Other implementation methods]

[0146] The semiconductor device of the present invention is not limited to the above-described embodiments. Various applications and modifications can be applied to the structure, manufacturing conditions, etc. of semiconductor devices such as capacitors within the scope of the present invention.

[0147] For example, in the above embodiments, the case of M=3 was described, but M is not particularly limited as long as it is an integer greater than or equal to 3 that satisfies M>N; for example, M=4 is also possible. For example, in the first embodiment, a fourth second electrode may be provided on the first electrode 22B via the first dielectric film 23, and a terminal electrode 27B may be connected to this second electrode. Furthermore, in the third embodiment, a fourth second electrode may be provided on the first electrode 22B via the first dielectric film 23, and a fourth third electrode may be provided on this second electrode via the second dielectric film 31, and a terminal electrode 27B may be connected to this third electrode. Moreover, in the fourth embodiment, a fourth second electrode may be provided on the first electrode 22B via the first dielectric film 23, a fourth third electrode may be provided on the second electrode via the second dielectric film 31, a fourth fourth electrode may be provided on the third electrode via the third dielectric film 34, and a terminal electrode 27B may be connected to this fourth electrode.

[0148] Furthermore, while the above embodiment describes the case where N=2, N is not particularly limited to any integer greater than 2; for example, N=3 is also possible. For instance, in the first embodiment, a third first electrode may be provided between the two first electrodes 22A and 22B, and a fourth and fifth second electrode may be provided on the first electrode via the first dielectric film 23, thereby forming a fourth and fifth capacitor element (a total of five capacitor elements connected in series). The fourth capacitor element is electrically connected in series with capacitor element CAP2 via external electrodes that do not constitute terminal electrodes 27A and 27B, and the fifth capacitor element is electrically connected in series with capacitor element CAP3 via external electrodes that do not constitute terminal electrodes 27A and 27B.

[0149] The following information is disclosed in this specification.

[0150] <1> A semiconductor device comprising:

[0151] substrate;

[0152] N (where N is an integer greater than 2) first electrodes are disposed on the above-mentioned substrate;

[0153] A first dielectric film is disposed on the aforementioned N first electrodes;

[0154] M second electrodes (where M is an integer greater than 3 satisfying M > N) are disposed on the N first electrodes via the first dielectric film;

[0155] The first protective layer covers the aforementioned N first electrodes and the aforementioned M second electrodes;

[0156] Three or more external electrodes, penetrating the aforementioned first protective layer; and

[0157] The second protective layer covers all but two of the three or more external electrodes mentioned above.

[0158] At least one second electrode is disposed on each of the aforementioned first electrodes.

[0159] The above-mentioned N first electrodes, the above-mentioned first dielectric film, and the above-mentioned M second electrodes constitute M capacitor elements.

[0160] The above M capacitor elements are connected in series.

[0161] Among the aforementioned M capacitor elements, two capacitor elements having two second electrodes disposed on the same first electrode are connected in series via the first electrode.

[0162] The two external electrodes not covered by the second protective layer constitute two terminal electrodes that are electrically connected to two of the M capacitor elements, respectively.

[0163] Two capacitor elements having two second electrodes disposed on different first electrodes are electrically connected in series via external electrodes that do not constitute the two terminal electrodes.

[0164] The external electrode, which does not constitute the two terminal electrodes, is covered by the second protective layer.

[0165] <2> According to the semiconductor device described in <1>,

[0166] At least two of the M second electrodes mentioned above have different areas.

[0167] <3> The semiconductor device according to <1> or <2> further comprises:

[0168] A second dielectric film is disposed on the aforementioned M second electrodes; and

[0169] M third electrodes are respectively disposed on the M second electrodes via the aforementioned second dielectric film.

[0170] <4> Based on the semiconductor device described in <3>,

[0171] At least two of the M third electrodes mentioned above have different areas.

[0172] <5> The semiconductor device described in <3> or <4> further comprises:

[0173] A third dielectric film is disposed on the aforementioned M third electrodes; and

[0174] M fourth electrodes are respectively disposed on the M third electrodes via the aforementioned third dielectric film.

[0175] <6> Based on the semiconductor device described in <5>,

[0176] At least two of the aforementioned M fourth electrodes have different areas.

[0177] <7> The semiconductor device described in any one of <1> to <6>

[0178] The aforementioned substrate is a semiconductor substrate.

[0179] Component isolation is provided between the above M capacitor elements in the above semiconductor substrate.

[0180] Explanation of reference numerals in the attached figures

[0181] 1, 2, 3, 4, 5, 6… Capacitor (semiconductor device), 10… Substrate, 21… Insulating film, 22, 22A, 22B… First electrode, 23… First dielectric film, 24, 24A, 24B, 24C… Second electrode, 25… Moisture-resistant film, 26… First protective layer, 27… External electrode, 27A, 27B… External electrode (terminal electrode), 27C… External electrode (connection wiring), 28a… Seed layer, 28b… First plating layer, 28c… Second plating layer, 29… Second… Protective layer, 30a…first region of the second electrode, 30b…second region of the second electrode, 31…second dielectric film, 32, 32A, 32B, 32C…third electrode, 33a…first region of the third electrode, 33b…second region of the third electrode, 34…third dielectric film, 35, 35A, 35B, 35C…fourth electrode, 36a…first region of the fourth electrode, 36b…second region of the fourth electrode, 37…element isolation, CAP1~CAP9…capacitor elements.

Claims

1. A semiconductor device, wherein, have: substrate; N first electrodes are disposed on the above-mentioned substrate, wherein N is an integer greater than or equal to 2; A first dielectric film is disposed on the aforementioned N first electrodes; M second electrodes are disposed on the N first electrodes via the first dielectric film, wherein M is an integer greater than or equal to 3 that satisfies M > N; The first protective layer covers the aforementioned N first electrodes and the aforementioned M second electrodes; Three or more external electrodes, penetrating the aforementioned first protective layer; and The second protective layer covers all but two of the three or more external electrodes mentioned above. At least one second electrode is disposed on each of the aforementioned first electrodes. The above-mentioned N first electrodes, the above-mentioned first dielectric film, and the above-mentioned M second electrodes constitute M capacitor elements. The above M capacitor elements are connected in series. Among the aforementioned M capacitor elements, two capacitor elements having two second electrodes disposed on the same first electrode are connected in series via the first electrode. The two external electrodes not covered by the second protective layer constitute two terminal electrodes that are electrically connected to two of the M capacitor elements, respectively. Two capacitor elements having two second electrodes disposed on different first electrodes are electrically connected in series via external electrodes that do not constitute the two terminal electrodes. The external electrode, which does not constitute the two terminal electrodes, is covered by the second protective layer.

2. The semiconductor device according to claim 1, wherein, At least two of the M second electrodes mentioned above have different areas.

3. The semiconductor device according to claim 1 or 2, wherein, It also has: A second dielectric film is disposed on the aforementioned M second electrodes; and M third electrodes are respectively disposed on the M second electrodes via the aforementioned second dielectric film.

4. The semiconductor device according to claim 3, wherein, At least two of the aforementioned M third electrodes have different areas.

5. The semiconductor device according to claim 3 or 4, wherein, It also has: A third dielectric film is disposed on the aforementioned M third electrodes; and M fourth electrodes are respectively disposed on the M third electrodes via the aforementioned third dielectric film.

6. The semiconductor device according to claim 5, wherein, At least two of the aforementioned M fourth electrodes have different areas.

7. The semiconductor device according to any one of claims 1 to 6, wherein, The aforementioned substrate is a semiconductor substrate. Component isolation is provided between the above M capacitor elements in the above semiconductor substrate.

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