MEMS-CMOS device vertical interconnection integrated packaging preparation method

Abstract

The invention relates to an MEMS-CMOS device vertical interconnection integrated packaging preparation method, which comprises the following steps of: processing a TSV (Through Silicon Via) on a first silicon wafer (3), and filling crystalline silicon (2a); respectively processing a CMOS circuit layer and an RDL layer on the first silicon wafer, and processing a germanium bonding point (8) on the other surface of the first silicon wafer; a second SOI silicon wafer (10) and a third SOI silicon wafer (11) are fused and bonded to form a cavity (9), an aluminum / titanium / aluminum bonding point (12) is prepared on the third silicon wafer, an MEMS movable microstructure (13) is prepared on the third silicon wafer, the metal aluminum / titanium / aluminum bonding point and the MEMS movable microstructure are electrically connected, and the aluminum-germanium bonding point of the first silicon wafer and the aluminum-germanium bonding point of the third silicon wafer are subjected to eutectic bonding. According to the invention, the size of an integrated packaging chip of the MEMS device and the CMOS processing circuit is greatly reduced, and meanwhile, the RDL structure can realize wafer-level bonding packaging without considering the types, layout and size of the MEMS device and the CMOS circuit.

Description

Technical Field

[0001] This invention belongs to the field of microelectromechanical systems (MEMS) and wafer-level bonding and packaging, specifically relating to a method for fabricating vertical interconnect integrated packaging of MEMS-CMOS devices. Background Technology

[0002] In the fields of microelectromechanical systems (MEMS), microelectronics, and optoelectronics, wafer-level bonding technology is being widely applied. MEMS devices, due to their internal movable microstructures, are highly susceptible to damage or failure caused by external environmental factors such as dust, particles, moisture, and mechanical forces. Therefore, MEMS devices require hermetic packaging to prevent damage to these movable microstructures, while maintaining a stable gas damping coefficient to improve device performance. Aluminum-germanium eutectic bonding is a wafer-level packaging technology that has been widely used in recent years for MEMS accelerometers, MEMS gyroscopes, and pressure gauges, and has become a key technology for the development and practical application of MEMS devices. Aluminum-germanium eutectic bonding uses a metal layer as the intermediate bonding medium. Taking advantage of the lower melting temperature of the eutectic alloy compared to the single metal, heating causes a eutectic reaction between the two metals at a lower temperature, resulting in a tight bond and achieving wafer-level bonding. Compared to other bonding methods commonly used in MEMS devices (anodic bonding, silicon-silicon fused bonding, and intermediate layer bonding), eutectic bonding offers better hermeticity and lower outgassing due to the use of a metal dielectric. Furthermore, the bonding metal required for eutectic bonding is easier to pattern, resulting in a narrower sealing ring and allowing for smaller bonded package sizes in MEMS devices. Most importantly, Al-Ge bonding materials offer compatibility with CMOS processes, enabling MEMS devices to be integrated with CMOS circuit fabrication technologies. In addition to forming the bonded package, Al-Ge eutectic bonding also provides electrical pathways for the chip structure, facilitating the introduction of vertical interconnect metal layers and enabling vertical silicon wafer stacking packaging technology, thereby further reducing chip size and packaging costs.

[0003] The function of MEMS sensors is achieved by integrating MEMS devices and CMOS processing circuits according to specific requirements. Currently, the following three schemes are commonly used for the integration and packaging of MEMS devices and CMOS circuits: (1) fixing MEMS devices and CMOS processing circuits on a planar structure and using wire bonding to achieve electrical interconnection; (2) performing 3D bonding packaging of MEMS devices and CMOS processing circuits and then using wire bonding to achieve electrical interconnection; (3) using special processing technology to integrate MEMS devices and CMOS processing circuits on the same chip. However, the above solutions have the following problems: (1) Solution 1 has a simple process, but the chip area is large after the MEMS device and the CMOS processing circuit are electrically interconnected, and the chip area cannot be reduced after integration; (2) Although Solution 2 can realize the three-dimensional bonding and packaging of MEMS device and CMOS processing circuit, it cannot realize the vertical electrical interconnection between different MEMS devices and the matching CMOS circuit, so wire bonding is still required to realize their electrical interconnection, and the chip area is still large after integration; (3) Although Solution 3 can realize the integration of MEMS circuit and CMOS processing circuit on the same chip, which can greatly reduce the chip area after integration, the process is more complicated and the processing difficulty is high. Summary of the Invention

[0004] The purpose of this invention is to provide a method for achieving vertical electrical interconnection between MEMS devices and CMOS processing circuits without wire bonding. Furthermore, by using aluminum-germanium bonding material, no special processing is required, making it compatible with both MEMS and CMOS fabrication processes. This enables the integrated packaging of MEMS chips and CMOS processing circuits. The use of RDL redistribution allows for compatibility with different MEMS devices and their associated CMOS circuits, increasing design flexibility and applicability. The process is simple, low-cost, and significantly reduces the size of the integrated MEMS sensor.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A method for fabricating vertical interconnect integrated packaging of MEMS-CMOS devices, characterized by the following steps:

[0007] (1) Fabricating TSV through-hole structures on the first silicon wafer:

[0008] First, the first silicon wafer is thermally oxidized, with an oxide layer thickness of 18000Å~20000Å. The surface of the first silicon wafer is patterned using photolithography to form TSV patterns, and TSV vias are formed by etching 400μm~450μm along the TSV patterns. The first silicon wafer is then thinned by CMP until the thinned surface completely exposes the TSV via structure.

[0009] Next, the first silicon wafer is thermally oxidized again, and an insulating silicon oxide layer is formed on the surface of the TSV via. The TSV via is then filled with polysilicon so that the polysilicon fills the entire TSV via.

[0010] Finally, mechanical polishing is performed on both sides of the first silicon wafer to remove excess polysilicon and insulating silicon oxide layer from the surface of the silicon wafer, exposing the surface of the first silicon wafer.

[0011] (2) Fabricating the CMOS circuit layer on the first silicon wafer:

[0012] Plasma-enhanced chemical vapor deposition is performed on the surface of the first silicon wafer to generate a SiO2 layer. Then, the required CMOS circuit structure layer is processed on the surface of the SiO2 layer, and electrical interconnections between CMOS circuits are formed through aluminum metal leads.

[0013] (3) Fabrication of the RDL layer on the first silicon wafer:

[0014] On the surface of the CMOS layer, a PE SiO2 layer is formed. The PE SiO2 layer is then subjected to photolithography and etching processes to expose the circuit aluminum PAD and TSV via structures of the CMOS layer below the PE SiO2 layer. Finally, an aluminum layer is sputtered on the surface of the PE SiO2 layer and photolithography is performed on the aluminum layer to enable the CMOS circuit aluminum PAD and TSV structures to be electrically interconnected through RDL aluminum leads.

[0015] (4) Processing germanium bonding points on the other side of the first silicon wafer:

[0016] PE SiO2 is formed on the other side of the first silicon wafer, and then photolithography is performed on the PE SiO2 to expose the TSV structure under the PE SiO2 dielectric; a metal germanium layer is sputtered or evaporated on the PE SiO2 surface, and metal germanium bonding points that are electrically interconnected with the TSV via are formed by photolithography.

[0017] (5) Melt bonding of the second SOI silicon wafer and the third SOI silicon wafer:

[0018] First, the second SOI silicon wafer is thermally oxidized. Then, the second silicon wafer is processed by photolithography, etching and other processes to form a cavity structure. The second SOI silicon wafer and the third SOI silicon wafer are fused together to form a sealed cavity. Finally, the substrate silicon and the intermediate insulating layer SiO2 of the third SOI silicon wafer are removed by mechanical thinning process and HF etching process.

[0019] (6) Fabrication of aluminum / titanium / aluminum bonding points on the third silicon wafer:

[0020] PE SiO2 is applied to the surface of the third silicon wafer, and then photolithography is performed on the PE SiO2 to expose the silicon under the PE SiO2 dielectric. A metallic aluminum / titanium / aluminum composite film is sputtered or evaporated on the PE SiO2 surface, and photolithography and etching processes are performed on the metallic aluminum / titanium / aluminum composite film to form metallic aluminum / titanium / aluminum bonding points.

[0021] (7) Fabrication of MEMS movable microstructures on a third silicon wafer:

[0022] Photolithography and etching processes are performed on the surface of the third silicon wafer to form a MEMS movable microstructure, enabling electrical interconnection between the metal aluminum / titanium / aluminum bonding points and the MEMS movable microstructure.

[0023] (8) Aluminum-germanium eutectic bonding between the first and third silicon wafers:

[0024] Before aluminum-germanium bonding, the silicon wafers are subjected to pre-bonding treatment. Ar plasma is used to bombard the surfaces of the first and third silicon wafers to remove the oxide layer and organic matter on the metal surface of the bonding point.

[0025] The first and third silicon wafers are aligned on a bonding alignment machine and then placed in the bonding machine. Temperature is applied to the first and third silicon wafers simultaneously, and the temperature is controlled at 425℃~450℃. A certain pressure is applied to the bonding wafer, with a bonding pressure of 5000N~50000N, and the time is maintained for 10min~50min. Finally, the temperature of the bonding chamber is slowly reduced to room temperature.

[0026] The further technical solution is as follows:

[0027] The aforementioned MEMS movable microstructures include, but are not limited to, MEMS gyroscopes, MEMS accelerometers, MEMS optical sensors, MEMS pressure sensors, MEMS radio frequency devices, and MEMS microphone devices.

[0028] This invention proposes a method and structure for fabricating vertical interconnect integrated packaging of MEMS-CMOS devices. The silicon wafer 1 serves both as a carrier for the CMOS processing circuit and as a bonding protective layer for the movable MEMS structure. The RDL structure enables the redistribution of PAD points in the CMOS circuit, allowing electrical interconnection between the PAD points and the TSV structure to accommodate MEMS devices and CMOS circuits of different structures. The TSV structure achieves electrical interconnection between the movable MEMS microstructure and the CMOS processing circuit through the RDL structure. This invention enables wafer-level vertical interconnect bonding and packaging of MEMS structures and CMOS, significantly reducing the chip size of the integrated packaging of MEMS devices and CMOS processing circuits. Furthermore, the RDL structure can achieve wafer-level bonding and packaging regardless of the type, layout, or size of the MEMS devices and CMOS circuits. Attached Figure Description

[0029] Figure 1 Schematic diagram of cross-section of silicon wafer 1 after processing the TSV structure;

[0030] Figure 2 A cross-sectional view of silicon wafer 1 after CMOS circuitry has been fabricated.

[0031] Figure 3 Schematic diagram of cross-section of silicon wafer 1 after RDL layer processing;

[0032] Figure 4 Schematic diagram of a cross section of silicon wafer 1 after processing a metal germanium bonding layer;

[0033] Figure 5 Schematic diagram of cross-section after SOI silicon wafer 2 and SOI silicon wafer 3 are fused and bonded to form a bonding cavity;

[0034] Figure 6 Schematic diagram of cross-section after silicon wafer 2 has been processed with aluminum 1 / titanium / aluminum 2 bonding layer;

[0035] Figure 7 A schematic cross-sectional view of a silicon wafer 2 after processing a movable MEMS microstructure.

[0036] Figure 8 A schematic cross-sectional view of silicon wafer 1 and silicon wafer 2 after aluminum-germanium eutectic bonding.

[0037] In the figure: 1: Insulating layer SiO2; 2: TSV through-hole structure; 3: First double-polished silicon wafer; 4: PE SiO2 layer; 5: CMOS circuit layer; 6: PE SiO2 layer; 7: RDL layer; 8: Metal germanium bonding point; 9: Bonding cavity; 10: Second SOI silicon wafer; 11: Top silicon layer of third SOI silicon wafer 3; 12: Metal aluminum / titanium / aluminum bonding point; 13: MEMS movable microstructure. Detailed Implementation

[0038] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0039] The SOI silicon wafers and double-polished silicon wafers to be bonded were surface-cleaned. The cleaning solution used was a mixed solution of H2SO4 and H2O2, with a mass concentration of 98% for H2SO4 and 30% for H2O2, and a volume ratio of H2SO4:H2O2 = 4:1. The temperature of the cleaning solution was 120~130℃, and the cleaning time was 15~20 min. Then, the samples were rinsed with deionized water for 10 min, and finally dried in a spin dryer.

[0040] A method for fabricating vertical interconnect integrated packaging of MEMS-CMOS devices includes the following steps:

[0041] 1. For example Figure 1As shown in the figure, this embodiment of the invention provides a cross-sectional view of a first silicon wafer 3 after processing a TSV through-hole structure:

[0042] First, the cleaned first silicon wafer 3 undergoes thermal oxidation, resulting in an oxide layer thickness of 18000 Å to 20000 Å. A photolithography process is then used to pattern the surface of the first silicon wafer 3, forming a TSV pattern with TSV apertures of 10 μm to 15 μm in size. The first silicon wafer 3 with the photolithographically patterned TSVs is then placed in a dielectric etching machine to etch away the 18000 Å to 20000 Å thermal oxide layer on the surface of the TSV apertures, while maintaining a certain amount of over-etching. Finally, the first silicon wafer 3 is placed in a silicon etching machine. TSV vias 2 with a depth of 400μm~450μm are etched. The etched silicon wafer is then placed in a mixed solution of standard H2SO4 and H2O2 for cleaning to remove the photoresist on the surface of the first silicon wafer 3. The first silicon wafer 3 is then placed in a BOE solution (HF:H2O=3:1) to remove the thermal oxide layer on the surface of the first silicon wafer 3. The first silicon wafer 3 is then thinned by CMP to a wafer thickness of 350μm~450μm, so that the thinned surface is completely exposed to expose the TSV via 2 structure.

[0043] Next, the CMP surface is chemically and mechanically polished to control the surface roughness below 10 Å. Then, the first silicon wafer 3 is cleaned with a mixed solution of H2SO4 and H2O2. After cleaning, the first silicon wafer 3 is thermally oxidized to control the thickness of the silicon oxide layer on the surface of the first silicon wafer 3 to be 18000 Å~20000 Å, and an insulating silicon oxide layer 1 is formed on the surface of the TSV via 2. The TSV via 2 is filled with polysilicon so that the polysilicon 2a fills the entire TSV via 2. Finally, the front and back sides of the filled first silicon wafer 3 are mechanically polished to remove excess polysilicon and silicon oxide layers from the surface of the silicon wafer, exposing the surface of the first silicon wafer 3.

[0044] 2. For example Figure 2 As shown in the figure, this embodiment of the invention provides a cross-sectional view of a first silicon wafer 3 after CMOS circuit processing. After completing the TSV structure processing, a PE (plasma-enhanced chemical vapor deposition) SiO2 layer 4 with a thickness of 5000 Å to 6000 Å is formed on the surface of the first silicon wafer 3. Then, the required CMOS circuit structure layer 5 is processed on the surface of the PE SiO2 layer 4, and electrical interconnections between CMOS circuits are formed through aluminum leads.

[0045] 3. For example Figure 3As shown in the figure, the embodiment of the present invention provides a cross-sectional view of the first silicon wafer 3 after processing the RDL layer. After the CMOS layer 5 is processed, a PE SiO2 layer 6 with a thickness of 5000Å~6000Å is applied to the surface of the CMOS layer 5. Then, photolithography, SiO2 dielectric etching and organic resist removal processes are performed on the PE SiO2 layer 6 to expose the circuit aluminum PAD and TSV via structures of the CMOS layer 5 below the PE SiO2 layer 6. Finally, an aluminum layer 7 is sputtered on the surface of the PE SiO2 layer 6, and photolithography, aluminum etching and organic resist removal processes are performed on the aluminum layer 7 to achieve electrical interconnection of the CMOS circuit aluminum PAD and TSV structures through the RDL aluminum 7a leads.

[0046] 4. For example Figure 4 As shown in the figure, this embodiment of the invention provides a cross-sectional view of the other side of the first silicon wafer 3 after the metal germanium bonding layer is processed. After the CMOS circuit and TSV structure are completed and electrically interconnected on the silicon wafer 3, PE SiO2 with a thickness of 5000Å~6000Å is processed on the other side of the silicon wafer 3. Then, photolithography, SiO2 dielectric etching and organic resist removal processes are performed on the PE SiO2 to expose the TSV structure under the PE SiO2 dielectric. A metal germanium layer with a thickness of 6000Å~8000Å is sputtered or evaporated on the PE SiO2 surface, and metal germanium bonding points 8 that are electrically interconnected with the TSV vias are formed through photolithography, germanium etching and organic resist removal processes.

[0047] 5. For example Figure 5 As shown in the figure, this embodiment of the invention provides a cross-sectional view of the second SOI silicon wafer 10 and the third SOI silicon wafer 11 after fusion bonding to form a bonding cavity. First, the cleaned second SOI silicon wafer 10 is thermally oxidized, with an oxide layer thickness of 5000 Å to 6000 Å. Next, the second silicon wafer 10 undergoes photolithography, dielectric etching, silicon etching, and resist removal processes to form a cavity 9 structure. The depth of the cavity structure is determined based on the displacement amount of the MEMS movable structure design, and its depth is controlled between 0.5 μm and 10 μm. The second SOI silicon wafer 10 and the third SOI silicon wafer 11 are fused together using silicon-silicon fusion bonding. A high-temperature annealing process is used to achieve electrical interconnection of the silicon on the insulating layer of the second SOI silicon wafer 10 and the third SOI silicon wafer 11. Finally, CMP and HF etching processes are used to remove the substrate silicon and the insulating layer SiO2 of the third SOI silicon wafer 11.

[0048] 6. For example Figure 6As shown in the figure, the embodiment of the present invention provides a cross-sectional view of the aluminum 1 / titanium / aluminum 2 bonding layer on the third silicon wafer 11. PE SiO2 with a thickness of 5000Å~6000Å is applied to the surface of the third silicon wafer 11. Then, photolithography, SiO2 dielectric etching, and organic resist removal processes are performed on the PE SiO2 to expose the silicon under the PE SiO2 dielectric. Finally, an aluminum / titanium / aluminum composite film is sputtered or evaporated on the PE SiO2 surface. The first aluminum layer has a thickness of 800Å~1200Å, the titanium layer has a thickness of 400Å~800Å, and the second aluminum 2 layer has a thickness of 9000Å~15000Å. Photolithography, etching, and organic resist removal processes are then performed on the aluminum / titanium / aluminum composite film to form aluminum / titanium / aluminum bonding points 12.

[0049] 7. For example Figure 7 As shown in the figure, the embodiment of the present invention provides a cross-sectional view of the third silicon wafer 11 after processing the MEMS movable microstructure. Photolithography, dielectric etching, silicon etching and dry resist removal processes are performed on the surface of the third silicon wafer 11 to form the MEMS movable microstructure 13, and to form the metal aluminum / titanium / aluminum bonding points 12 and realize the electrical interconnection of the MEMS movable microstructure.

[0050] 8. For example Figure 8 As shown in the figure, this embodiment of the invention provides a cross-sectional view of the first silicon wafer 3 and the third silicon wafer 11 after aluminum-germanium eutectic bonding. Before aluminum-germanium bonding, silicon wafers 3 and 11 are subjected to pre-bonding treatment. Ar plasma is used to bombard the metal surfaces of the bonding points of the first silicon wafer 3 and the third silicon wafer 11 to remove the oxide layer and organic matter on the metal surfaces of the bonding points. The treated first silicon wafer 3 and third silicon wafer 11 are aligned on a bonding alignment machine and then placed in the bonding machine. When the bonding wafer is sent into the bonding chamber, the vacuum system evacuates the bonding device to a vacuum environment or fills it with a chemically inert gas such as N2 or a reducing gas H2. Then, the temperature of the first silicon wafer 3 and the third silicon wafer 11 is simultaneously applied to control the temperature at 425°C to 450°C. A certain pressure is applied to the bonding wafer, with a bonding pressure of 5000N to 50000N, and the time is maintained for 10min to 50min. Finally, the temperature of the bonding chamber is slowly reduced to room temperature.

[0051] The double-polished silicon wafer used in this invention has a thickness of 300μm to 875μm and its resistivity is unlimited.

[0052] The MEMS movable microstructure in this invention can be various types of devices such as MEMS gyroscope, MEMS accelerometer, MEMS optical sensor, MEMS pressure sensor, MEMS radio frequency and MEMS microphone.

Claims

1. A method for fabricating vertical interconnect integrated packaging of MEMS-CMOS devices, characterized in that... Includes the following steps: S1. Process TSV through-hole structures on the first silicon wafer (3): First, the first silicon wafer (3) is thermally oxidized, with an oxide layer thickness of 18000Å~20000Å. The surface of the first silicon wafer (3) is patterned using photolithography to form a TSV pattern. TSV vias (2) are formed by etching 400μm~450μm along the TSV pattern. The first silicon wafer (3) is then thinned by CMP until the thinned surface completely exposes the TSV via (2) structure. Next, the first silicon wafer (3) is thermally oxidized again, and an insulating silicon oxide layer (1) is formed on the surface of the TSV via (2). Polysilicon is then used to fill the TSV via (2) so that the polysilicon (2a) fills the entire TSV via (2). Finally, the front and back sides of the first silicon wafer (3) are mechanically polished to remove excess polysilicon and insulating silicon oxide layer (1) from the surface of the silicon wafer, exposing the surface of the first silicon wafer (3); S2. Fabricate a CMOS circuit layer on the first silicon wafer (3): Plasma-enhanced chemical vapor deposition is performed on the surface of the first silicon wafer (3) to generate a SiO2 layer (4), and then the required CMOS circuit structure layer (5) is processed on the surface of the SiO2 layer (4), and electrical interconnection between CMOS circuits is formed through aluminum metal leads; S3. Prepare an RDL layer on the first silicon wafer (3): On the surface of the CMOS layer (5), a PE SiO2 layer (6) is applied. The PE SiO2 layer (6) is then subjected to photolithography and etching processes to expose the circuit aluminum PAD and TSV via structure of the CMOS layer (5) below the PE SiO2 layer (6). Finally, an aluminum layer (7) is sputtered on the surface of the PE SiO2 layer (6). The aluminum layer (7) is then subjected to photolithography and etching processes to enable the CMOS circuit aluminum PAD and TSV structure to be electrically interconnected through the RDL aluminum (7a) leads. S4. Process the germanium bonding points on the other side of the first silicon wafer (3): A PE SiO2 layer is formed on the other side of the first silicon wafer (3), and then photolithography and etching processes are performed on the PE SiO2 to expose the TSV structure under the PE SiO2 dielectric layer; a metal germanium layer is sputtered or evaporated on the PE SiO2 surface, and metal germanium bonding points (8) that are electrically interconnected with the TSV via are formed by photolithography. S5, the second SOI silicon wafer (10) and the third SOI silicon wafer (11) are fused together: First, the second SOI silicon wafer (10) is thermally oxidized. Then, the second SOI silicon wafer (10) is processed by photolithography, etching and other processes to form a cavity (9) structure. The second SOI silicon wafer (10) and the third SOI silicon wafer (11) are fused together to form a sealed cavity structure. Then, the substrate silicon and the intermediate insulating layer SiO2 of the third SOI silicon wafer (11) are removed by mechanical thinning process and HF etching process. S6. Prepare aluminum / titanium / aluminum bonding points on the third silicon wafer (11): PE SiO2 is applied to the surface of the third silicon wafer (11), and then photolithography is performed on the PE SiO2 to expose the silicon under the PE SiO2 medium; a metal aluminum / titanium / aluminum composite film is sputtered or evaporated on the PE SiO2 surface, and photolithography and etching processes are performed on the metal aluminum / titanium / aluminum composite film to form metal aluminum / titanium / aluminum bonding points (12). S7. Fabricate MEMS movable microstructures on the third silicon wafer (11): Photolithography and etching processes are performed on the surface of the third silicon wafer (11) to form a MEMS movable microstructure (13), so that the aluminum / titanium / aluminum bonding point (12) and the MEMS movable microstructure (13) are electrically interconnected. S8, Aluminum-germanium eutectic bonding of the first silicon wafer (3) and the third silicon wafer (11): The first silicon wafer (3) and the third silicon wafer (11) are aligned on the bonding alignment machine and then placed in the bonding machine. Temperature is applied to the first silicon wafer (3) and the third silicon wafer (11) simultaneously, and the temperature is controlled at 425℃~450℃. A certain pressure is applied to the bonding wafer, with a bonding pressure of 5000N~50000N, and the time is maintained for 10min~50min. Finally, the temperature of the bonding chamber is slowly reduced to room temperature.

2. The method for fabricating a vertical interconnect integrated package of MEMS-CMOS devices according to claim 1, characterized in that: In step 8, before aluminum-germanium bonding, silicon wafers (3) and (11) are subjected to bonding pretreatment. Ar plasma is used to bombard the surfaces of the first silicon wafer (3) and the third silicon wafer (11) to remove the oxide layer and organic matter on the surface of the bonding anchor metal.

3. A method for fabricating vertical interconnect integrated packaging of MEMS-CMOS devices according to claim 1 or 2, characterized in that: The aforementioned MEMS movable microstructures include, but are not limited to, MEMS gyroscopes, MEMS accelerometers, MEMS optical sensors, MEMS pressure sensors, MEMS radio frequency devices, and MEMS microphone devices.

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