Socket plate and automatic test device

Abstract

The invention provides an interface device for increasing signal density. The socket PCB (214) is provided with a socket guide (212) on a first surface thereof. On the second surface of the socket PCB (214), a plurality of pads (P2) are formed by dividing into two rectangular regions (RGN1, RGN2) having long sides in the y direction. Each of the socket guides (212) is disposed in a third region (RGN3) sandwiched between the first region (RGN1) and the second region (RGN2). Each socket guide (212) is electrically connected to a portion of the plurality of pads included in the first region (RGN1) and a portion of the plurality of pads included in the second region (RGN2).

Description

Technical Field

[0001] This disclosure relates to socket boards. Background Technology

[0002] Automatic test equipment (ATE) is used in the inspection of various semiconductor devices such as memory and CPU (Central Processing Unit). ATE supplies test signals to the semiconductor device under test (hereinafter referred to as the device under test (DUT)), measures the DUT's response to the test signals, determines whether the DUT is good or bad, or identifies the defective part.

[0003] In recent years, DRAM (Dynamic Random Access Memory) has continued to advance in terms of speed. In GDDR (Graphics Double Data Rate) memory integrated into graphics tablets, under the GDDR6X standard, a transfer speed of 21Gbps is achieved through NRZ (NonReturn to Zero) mode.

[0004] In the next generation of GDDR7, PAM4 (Pulse Amplitude Modulation 4) is adopted, increasing the transmission speed to 40Gbps. NRZ technology is also progressing towards higher speeds year by year, with the next generation reaching around 28Gbps.

[0005] Patent Document 1 discloses an interface device and an automated testing device capable of testing high-speed devices with high precision. In this interface device, the socket board and the pin electronic circuitry are connected via an interlayer and wiring.

[0006] Prior technology literature

[0007] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2024-014522 Summary of the Invention

[0009] [Summary of the Invention]

[0010] [The problem the invention aims to solve]

[0011] The multi-pin architecture of DUTs, especially memory, continues to advance. As the electrical distance between the pin-based integrated circuit (IC) and the DUT increases, parasitic impedance increases, the bandwidth of the transmission path narrows, and high-speed transmission becomes difficult.

[0012] This disclosure is made in view of such circumstances, and one of the exemplary purposes of one of the solutions is to provide a socket board capable of accurately measuring high-speed signals.

[0013] [Solutions for solving the problem]

[0014] One embodiment of this disclosure includes a socket printed circuit board (PCB) comprising a socket substrate and N (N being a natural number) socket guides disposed on a first surface of the PCB. A plurality of pads serving as electrical contacts to an interposer layer are formed on a second surface of the PCB. The plurality of pads are divided into a first region and a second region, the first and second regions being separated from each other along a first direction with their long sides aligned in a first direction. The N socket guides are respectively disposed in a third region sandwiched between the first and second regions, and each socket guide is electrically connected to a portion of the plurality of pads contained in the first region and a portion of the plurality of pads contained in the second region.

[0015] It should be noted that any combination of the above-mentioned constituent elements, or any substitution of the constituent elements or descriptions among methods, apparatuses, systems, etc., are also valid forms of this invention or disclosure. Furthermore, the description of this matter (the solution to the problem) does not represent all the essential features of this invention; therefore, sub-combinations of these described features may also constitute this invention. Attached Figure Description

[0016] Figure 1 This is a diagram representing the ATE implementation method.

[0017] Figure 2 This is a cross-sectional view of an interface device according to an embodiment.

[0018] Figure 3 This is a diagram illustrating a front-end module of one embodiment.

[0019] Figure 4 It means Figure 3 A three-dimensional diagram of the composition of a FEU.

[0020] Figure 5 It means Figure 3 A cross-sectional view of the components of a FEU.

[0021] Figure 6 This is a cross-sectional view showing an example of the connection between a pin-based electronic IC and a docking station (DUT).

[0022] Figure 7 This is a cross-sectional view of the socket plate in the embodiment.

[0023] Figure 8 This is a diagram showing the layout of multiple second pads on the second side of the connector PCB.

[0024] Figure 9 This is a diagram showing a variation of the layout of multiple second pads on the second side of a connector PCB.

[0025] Figure 10 This is a perspective view showing the layout of the socket plate in the implementation method.

[0026] Figure 11 This is a top view showing the layout of the socket plate in the embodiment.

[0027] Figure 12 This is a top view showing the layout of the interface board for the comparative technology.

[0028] Figure 13 This is a top view showing the layout of the socket plate in the modified example.

[0029] [Symbol Explanation]

[0030] 1DUT

[0031] 100ATE

[0032] 120 Tester

[0033] 130 test head

[0034] 200 Interface Device

[0035] 210 socket board

[0036] 212 socket

[0037] 214 socket PCB

[0038] P1 First pad

[0039] P2 Second Pad

[0040] SIG signal pin

[0041] GND ground pin

[0042] 216 Socket board side connector

[0043] 218 Intermediary Layer

[0044] 219 Cable Clips

[0045] 220 wiring

[0046] 222 FPC cable

[0047] 230 motherboard

[0048] 300 Front-end Modules

[0049] 310-pin electronic PCB

[0050] 312 FPC connector

[0051] 314 Intermediary Layer

[0052] 316 Cable Clip

[0053] 320 condenser plate

[0054] 400-pin electronic IC Detailed Implementation

[0055] (Summary of the implementation method)

[0056] This description provides a summary of several exemplary embodiments of the present disclosure. This summary serves as a prelude to the detailed description that follows, and aims to provide a basic understanding of the embodiments, simplifying the explanation of several concepts of one or more embodiments without limiting the breadth of the invention or disclosure. This summary is not an inclusive overview of all embodiments to be considered, nor does it define the scope of some or all of the embodiments by identifying essential elements of all embodiments. For simplicity, "an embodiment" is sometimes used to indicate one or more embodiments (examples, variations) disclosed in this specification.

[0057] One embodiment of the connector board includes a connector printed circuit board and N (N being a natural number) connector guides disposed on a first surface of the connector printed circuit board. On a second surface of the connector printed circuit board, a plurality of pads are formed in a first region and a second region, the first region and the second region being separated from each other in a second direction with a first direction as their long side. The N connector guides are respectively disposed in a third region sandwiched between the first region and the second region, and each connector guide is electrically connected to a portion of the plurality of pads included in the first region and a portion of the plurality of pads included in the second region.

[0058] According to this structure, the pads connected to a DUT are arranged in two columns in a way that sandwiches the DUT. This shortens the wiring length compared to arranging them in one column. In addition, it makes the wiring length of multiple pins more uniform.

[0059] In one embodiment, at least one of the N socket guides can be included in the area disposed in the first region and the second region in a first direction. This allows for a reduction in wiring length.

[0060] In one embodiment, N=2, and the two connector guides can be included in the range of the first region and the second region in the first direction.

[0061] In one embodiment, N=4, and the two connector guides can be included in the range of the first region and the second region in the first direction.

[0062] One embodiment of the automatic testing apparatus may include the aforementioned socket plate.

[0063] (Implementation Method)

[0064] Hereinafter, preferred embodiments will be described with reference to the accompanying drawings. Identical or equivalent constituent elements, components, and processes shown in the drawings will be labeled with the same symbols, and repetitive descriptions will be omitted where appropriate. Furthermore, these embodiments are not intended to limit the disclosure and invention but are illustrative; all features and combinations thereof described in the embodiments may not necessarily represent the essential features and combinations thereof of the disclosure and invention.

[0065] In addition, the dimensions (thickness, length, width, etc.) of the components shown in the attached drawings are sometimes appropriately enlarged or reduced for ease of understanding. Moreover, the dimensions of multiple components do not necessarily indicate their size relationship. In the attached drawings, even if a component A is depicted as thicker than another component B, component A may actually be thinner than component B.

[0066] In this specification, "the state of connection between component A and component B" includes not only the case where component A and component B are physically directly connected, but also the case where component A and component B are indirectly connected via other components that do not substantially affect their electrical connection state or impair the function or effect performed by their combination.

[0067] Similarly, "the state in which component C is connected (set between) component A and component B" includes not only the case where component A and component C, or component B and component C are directly connected, but also the case where they are indirectly connected via other components that do not substantially affect their electrical connection state or impair the function or effect performed by their combination.

[0068] Figure 1 This is a diagram illustrating an implementation of ATE100. ATE100 includes a tester 120, a test head 130, a processor 150, and an interface device 200.

[0069] The tester 120 centrally controls the ATE100. Specifically, the tester 120 executes the test program, controls the test head 130 and the processor 150, and collects the measurement results.

[0070] The processor 150 supplies (loads) the DUT1 to the interface device 200 and unloads the tested DUT1 from the interface device 200. In addition, the processor 150 distinguishes the DUT1 into qualified and unqualified products.

[0071] The test head 130 includes hardware that generates a test signal to be supplied to the DUT1 and detects signals from the DUT (referred to as device signals). Additionally, it may include power supply circuitry that generates the power supply voltage to be supplied to the DUT1 and the interface device 200.

[0072] The interface device 200 includes a socket board 210, wiring 220, and a front-end module 300.

[0073] In this embodiment, multiple pin-based electronic ICs (PE-ICs) 400 are disposed in the interface device 200 rather than within the test head 130. The pin-based electronic ICs 400 are application-specific integrated circuits (ASICs) that integrate a driver for generating test signals and a comparator for receiving device signals. The test signals and device signals are NRZ signals or PAM4 signals.

[0074] More specifically, the multi-pin electronic IC 400 is modularized. This module is referred to as the front-end module 300.

[0075] The interface board 210 has multiple interfaces 212. DUT1 is mounted in the interface 212. The front-end module 300 is connected to the interface 212 via wiring 220.

[0076] The above is the structure of ATE100.

[0077] According to the ATE100, a front-end module 300, which is modularly composed of multiple pin-based electronic ICs 400, is built into the interface device 200, thereby enabling the pin-based electronic ICs 400 to be positioned near the DUT1. This significantly shortens the transmission distance of test signals and device signals compared to previous methods.

[0078] For example, in conventional ATEs, the pin-controlled electronic IC and the interface board are connected by a coaxial cable with a length of approximately 500mm to 600mm. However, in this embodiment, the length of the wiring 220 can be shortened to approximately 100mm to 150mm. This significantly reduces the loss of high-frequency components, enabling the transmission of high-speed test signals and device signals. The ATE100 equipped with this interface device 200 can perform high-speed memory tests exceeding 20Gbps.

[0079] Figure 2 This is a cross-sectional view of an interface device 200A according to an embodiment. Figure 2Only the structure associated with one DUT is shown. In this embodiment, the interface device 200A includes a motherboard 230 and a socket board 210 that is detachable from the motherboard 230. The socket board 210 includes a socket (also called a socket guide) 212 as a mechanical component, a socket printed circuit board (socket PCB) 214, and a socket board side connector 216. It should be noted that sometimes the socket PCB itself is referred to as a socket board, and the socket PCB with the socket guide mounted is referred to as a DSA (Device Specific Adapter) or device board.

[0080] The front-end module 300A includes multiple printed circuit boards (PCBs) 310 on which multiple pin electronic ICs 400 are mounted. The multiple pin electronic PCBs 310 are arranged with their orientation perpendicular to the surfaces (front and back) of the DUT, in other words, to the surface S1 of the socket board 210. In this embodiment, the socket board 210 is parallel to the ground, therefore the multiple pin electronic PCBs 310 are arranged parallel to the direction of gravity.

[0081] The front-end module 300A also features a plate-shaped cooling device (hereinafter referred to as a condenser plate) 320. The condenser plate 320 has a flow path for refrigerant circulation.

[0082] Multiple pin electronic PCBs 310a and 310b and a condenser plate 320 are stacked in a manner where the pin electronic IC 400 and the condenser plate 320 are thermally coupled.

[0083] The motherboard 230 includes a socket board-side connector 232, a spacer frame 234, and a relay connector 236. The front-end module 300A is fixed to the spacer frame 234. The relay connector 236 is electrically and mechanically coupled to the test head-side connector 132.

[0084] As detailed below, wiring 220 can replace conventional coaxial cables with cables made of flexible printed circuits (FPCs) (also known as FPC cables).

[0085] On the other hand, the wiring 224 between the pin electronics PCB 310 and the relay connector 236 only transmits control signals for the pin electronics IC 400, and does not transmit test signals or device signals. Therefore, wiring 224 can also utilize a coaxial cable.

[0086] Figure 3 This is a diagram illustrating a front-end module 300B according to one embodiment.

[0087] Assign 2×M (M≥1) pin-controlled electronic ICs 400 to one DUT1. Assign A to D suffixes to multiple DUTs and pin-controlled electronic ICs 400 to distinguish them as needed. In this example, with DUT1 having 192 I / Os and each pin-controlled electronic IC 400 having 24 I / Os, each DUT is assigned 192 / 24 = 8 (i.e., M = 4) pin-controlled electronic ICs 400.

[0088] The front-end module 300B is configured to be divided into multiple units based on N (N≥2) DUT1s, and the unit of division is called a front-end unit (FEU). In this example, the blocks corresponding to four DUTs constitute one FEU, and one FEU has 2×M×N = 2×4×4 = 32 pins of electronic IC400.

[0089] Figure 3 Although two FEUs are shown, the front-end module 300B can actually have more than two FEUs. For example, in 64 ATEs that can be measured simultaneously, 64 / 4 = 16 FEUs can be set up, and the entire front-end module 300B will have 64 × 192 I / O = 12288 I / Os.

[0090] Figure 4 It means Figure 3 A perspective view of the configuration example of the FEU. The sockets 212A to 212D corresponding to the four DUTs are arranged in a two-row, two-column matrix. Focusing on a single DUT 1A, the eight-pin electronic IC 400A assigned to it is mounted in pairs on four pin electronic PCBs 310a to 310d arranged along the X-direction. The socket PCB 214 with the sockets 212 can be divided according to each DUT, and the socket PCBs 214 corresponding to the four DUTs can be integrally formed into a single substrate.

[0091] Two pin-controlled electronic ICs 400A are mounted on a pin-controlled electronic PCB 310 and arranged along the Y direction. The two pin-controlled electronic ICs 400A are positioned at equal distances from DUT1A.

[0092] Figure 5 It means Figure 3 A cross-sectional view of an example of the components of a FEU. For example... Figure 2 As shown, a condenser plate 320 is provided between the two pin electronics PCBs 310a and 310b. Similarly, a condenser plate 320 is also provided between the two pin electronics PCBs 310c and 310d. As described above, the pin electronics IC 400 is mounted on the pin electronics PCB 310 near the socket board 210. To improve cooling efficiency, the pin electronics IC 400 can be a bare chip, and the pin electronics IC 400 and the condenser plate 320 are thermally coupled via a thermal interface material (TIM) 322.

[0093] In addition, when viewing the FEU from above along the Y-axis, the center of the DUT, i.e., the socket 212A, is located at the center of the four (M) pin electronic PCBs 310a to 310d stacked along the X-direction.

[0094] The above is the structure of FEU.

[0095] The advantages of this FEU are explained. Focusing on the DUT1A with the suffix A, multiple (eight in this example) pin-type electronic ICs 400A corresponding to one DUT1A are mounted in pairs on four pin-type electronic PCBs 310a-310d. This allows for the uniformization of the distance from each of the eight pin-type electronic ICs 400A to the socket 212A. Consequently, the transmission line loss from each pin-type electronic IC 400A to the socket 212A (DUT1A) is uniformized, enabling accurate testing.

[0096] Next, the electrical connection between the pin electronics IC400 and the socket 212 will be explained.

[0097] Figure 6 This is a cross-sectional view showing an example of the connection between the pin electronics IC and the socket (DUT1). The wiring 220 between the pin electronics PCB310 and the socket board 210, which transmits test signals and device signals, uses FPC cable 222.

[0098] When a coaxial cable is used as the wiring 220 between the pin electronics PCB 310 and the socket board 210, the minimum distance between the pin electronics PCB 310 and the socket board 210 is limited due to the rigidity of the coaxial cable. In contrast, by using an FPC cable 222, the distance h between the pin electronics PCB 310 and the socket board 210 can be shortened due to its flexibility compared to using a coaxial cable, thus reducing the transmission distance of test signals and device signals.

[0099] In conventional test setups, Low Insulation Force (LIF) connectors are typically used to allow for the installation and removal of the connector board 210. These LIF connectors exhibit a non-negligible loss of approximately -3dB in frequency bands higher than 14GHz, contributing to waveform distortion at high-speed transmissions of 28Gbps or 40Gbps. By using FPC cable 222 via wiring 220 without requiring LIF connectors, waveform distortion caused by losses (attenuation in the high-frequency band) can be suppressed, enabling accurate testing.

[0100] More specifically, the socket board 210 includes a socket 212 and a socket PCB 214. The socket PCB 214 is a multilayer substrate including a wiring layer and an insulating layer. Wiring is formed in the wiring layer to allow signal paths to move horizontally, and vias VH are formed in the insulating layer to allow signal paths to move vertically. The paths for transmitting test signals and device signals are preferably pulled out to the back of the socket board 210 as horizontally as possible (in the X and Y directions) without moving. Conversely, power signals and low-frequency control signals can be pulled back horizontally inside the socket PCB 214.

[0101] FPC cable 222 is connected to socket board 210 by socket board-side connector 216. Socket board-side connector 216 includes an interposer layer 218 and a cable clip 219.

[0102] Intermediate layer 218 and socket PCB 214 are detachable. Electrodes exposed on the surface of intermediate layer 218 are electrically connected to electrodes exposed on the back side of socket PCB 214. FPC cable 222 is clamped in by cable clip 219 in contact with the back electrode of intermediate layer 218.

[0103] Figure 7 This is a cross-sectional view of the socket board 210 according to the embodiment. The socket board 210 has a socket 212 on the first side of the socket PCB 214 for connection with the DUT. The second side of the socket board 210 is connected to the interposer layer 218 so that it can be installed and removed.

[0104] Additionally, a surface mount device (SMD) 213 is mounted on the second side of the socket board 210. Examples of SMDs 213 include chip capacitors, chip resistors, and chip inductors. Multiple first pads P1 for mounting the SMDs 213 are formed on the second side of the socket PCB 214.

[0105] Additionally, a plurality of second pads P2 are formed on the second side of the socket PCB214 to serve as electrical contacts with the interposer layer 218. The second pads P2 are electrically connected to the corresponding contacts (pins) P3 of the interposer layer 218.

[0106] The first pad P1 has a thickness t1, and the second pad P2 has a thickness t2. The thicknesses t1 and t2 of the two pads P1 and P2 are different (t1 ≠ t2). Specifically, the relationship t2 > t1 holds true.

[0107] Preferably, the thickness t2 of the second pad P2 is more than twice the thickness t1 of the first pad P1. More preferably, the thickness t2 of the second pad P2 is more than five times the thickness t1 of the first pad P1. Even more preferably, the thickness t2 of the second pad P2 is more than eight times the thickness t1 of the first pad P1.

[0108] For example, the thickness t1 of the first pad P1 is 0.03 micrometers with a dimensional tolerance of ±30%. In contrast, the thickness t2 of the second pad P2 is 0.5 micrometers with a dimensional tolerance of ±30%. In this case, the thickness t2 of the second pad P2 is 16 times the thickness t1 of the first pad P1.

[0109] According to the socket plate 210, the first pad P1 for component mounting and the second pad P2, which becomes an electrical contact with the interposer layer 218, have different thicknesses. This improves the peel strength for the SMD 213 and the wear resistance for the electrical contact with the interposer layer 218, thereby improving long-term reliability.

[0110] Figure 8 This diagram shows the layout of multiple second pads P2 on the second side of the connector PCB 214. Multiple pins arranged in a matrix are provided on the surface of the interposer layer 218. Figure 7 P3), and multiple second pads P2 are arranged in a matrix on the second side of the socket PCB214, corresponding to multiple pins P3.

[0111] Multiple second pads P2 are alternately assigned signal pins SIG and ground pins GND in the row direction (vertical orientation) and column direction (horizontal orientation), respectively. In other words, each signal pin SIG is adjacent to the ground pin GND in both the row and column directions, and adjacent to each other in the diagonal direction. Alternatively, it can be understood as a structure where the two rows and two columns of second pads SIG are the smallest unit PU, and this smallest unit PU is arranged along the row and column directions. The smallest unit PU contains two diagonally arranged signal pins SIG and two diagonally arranged ground pins GND.

[0112] The above is the layout of the second pad P2 in the PCB214 of the connector. Compared with the layout in which the signal pins are completely surrounded by the ground pins in the row, column and diagonal directions, this layout can increase the density of signal pins and reduce the area of ​​the connector printed circuit board.

[0113] Figure 9 This is a modified example of the layout of multiple second pads P2 on the second side of the socket PCB214. In this modified example, the ground pins GND in the multiple second pads P2 are formed continuously from one another.

[0114] According to this variation, the impedance of the ground pin GND can be reduced.

[0115] Next, the layout of the DUT and signals in the socket board will be explained.

[0116] Figure 10 This is a perspective view showing the layout of the socket plate 210 in the embodiment. Figure 11This is a top view showing the layout of the socket plate 210 in the embodiment.

[0117] The socket board 210 has a socket PCB 214 and N socket guides (referred to as sockets) 212_1 to 212_N. In this example, N = 2.

[0118] N sockets 212_1 to 212_N are located on the first side (top surface in the figure) of the socket PCB214.

[0119] On the second side (lower surface in the figure) of the connector PCB214, multiple pads P2 are formed by dividing the first region RGN1 and the second region RGN2. The multiple pads P2 become electrical contacts with the interposer layer 218.

[0120] The first region RNG1 and the second region RGN2 are rectangles with the same shape and size, with the first direction (y) as the longer side, and are separated from each other in the second direction (x).

[0121] N sockets 212_1 to 212_N are arranged adjacently along the y-direction in the third region RNG3, which is sandwiched between the first region RGN1 and the second region RNG2 in the x-direction.

[0122] Each socket 212_1 to 212_N is electrically connected to a portion of the plurality of pads P2 contained in the first region RGN1 and a portion of the plurality of pads P2 contained in the second region RNG2. Each pin of socket 212 is connected to its corresponding pad P2 via through-holes and wiring provided on the socket PCB 214.

[0123] One socket 212_1 is positioned between y0 and y1 in the y direction, and the other socket 212_2 is positioned between y1 and y2 in the y direction. y0 is the coordinate of one end of the rectangular regions RGN1 and RGN2, y2 is the coordinate of the other end of the regions RGN1 and RGN2, and y1 is the coordinate of the center.

[0124] exist Figure 11 In the layout, Pa represents the farthest pad among the pads connected to socket 212_1, and Pb represents the nearest pad among the pads connected to socket 212_1.

[0125] The above describes the layout of the socket plate 210. The advantages of this socket plate 210 become clear through comparison with comparative technologies.

[0126] Figure 12 This is a top view showing the layout of the interface board 210R of the comparative technology.

[0127] In this comparative technique, one of the connectors 212_1 is connected to the pad P2 contained in the first region RNG1, and the other connector 212_2 is connected to the pad P2 contained in the second region RNG2.

[0128] exist Figure 12 In the layout, Pc represents the farthest pad among the pads connected to socket 212_1, and Pd represents the nearest pad among the pads connected to socket 212_1.

[0129] Will Figure 11 (Implementation Method) and Figure 12 When comparing (comparative techniques), it can be seen that... Figure 11 (Implementation Method) The length of the wiring connecting the connector to the furthest pad can be shortened. As a result, transmission loss can be reduced, thus widening the bandwidth and enabling testing of higher speed signals.

[0130] Will Figure 11 (Implementation Method) and Figure 12 When making comparisons using (comparative techniques) Figure 11 In the (implementation method), the difference between the distance Pa to the farthest pad and the distance Pb to the nearest pad is less than [the required value]. Figure 12 The difference between the distance Pc to the farthest pad and the distance Pd to the nearest pad in the (comparative technique). That is, according to the implementation, compared with the comparative technique, the wiring length to multiple pins P2 can be made more uniform.

[0131] Figure 13 This is a top view showing the layout of the socket plate 210 in a modified example. In this modified example, the number N of sockets 212 is 4. In this layout, the two central sockets 212_2 and 212_3 are incorporated in the y-direction within the rectangular regions RGN1 and RGN2, ranging from y0 to y2. Therefore, it is possible to enjoy the same... Figure 10 The layout has the same advantages.

[0132] The interface device 200 comes in a variety of forms, but this disclosure is applicable to any form.

[0133] • SBC (Socket Board Change) type

[0134] The SBC type is an interface device that replaces the type of socket board 210 according to the type of DUT.

[0135] • CLS (Cable Less) type

[0136] The CLS type is an interface device 200 that can be separated into an upper DSA (Device Specific Adapter) and a lower motherboard, and the type of DSA can be replaced depending on the type of DUT. When applying the interface device 200 of this embodiment to the CLS type, two methods are considered.

[0137] One approach is to configure the front-end module 300 on the motherboard side. In this case, the front-end module 300 can be shared in tests of different DUTs, which is advantageous from a cost point of view.

[0138] Another approach is to configure the front-end module 300 on the DSA side. In this case, the front-end module 300 is configured according to each DSA, thus increasing the cost of the device. On the other hand, it allows the front-end module 300 to be located close to the DUT, which is advantageous from the viewpoint of high-speed testing.

[0139] • CCN (Cable Connection) type

[0140] The CCN type is an interface device in which the entire interface device 200 is replaced according to the type of DUT. If the interface device 200 of this embodiment is applied to the CCN type, the front-end module 300 can be brought closer to the limit of the DUT, which is advantageous from the viewpoint of high-speed testing.

[0141] • Wafer motherboard

[0142] The interface device 200 can be a wafer motherboard used in wafer-level testing. In this case, the interface device 200 can replace the interface board and have a probe card.

[0143] The above embodiments are examples, and those skilled in the art will understand that the combination of these constituent elements and processing techniques can include various modifications. Such modifications will be described below.

[0144] (Variation Example 1)

[0145] In one embodiment, the pin electronics IC 400 electrically connects the FPC to the printed circuit board using an interposer, but this disclosure is not limited thereto. As wiring 220, the printed circuit board and other wiring may be used instead of the FPC cable 222.

[0146] (Variation Example 2)

[0147] In this embodiment, the interface device 200 with the socket plate 210 parallel to the ground is described, but this disclosure is not limited to this. For example, the socket plate 210 may also be perpendicular to the ground. In this case, Figure 4 , Figure 5 In equations, the Y-direction becomes the direction of gravity.

[0148] While specific terminology has been used to describe the embodiments of this disclosure, such description is merely illustrative to aid understanding and does not limit the scope of this disclosure or technical solution. The scope of this invention is defined by the technical solution; therefore, embodiments, examples, and modifications not described herein are also included within the scope of this invention.

Claims

1. A socket board, characterized in that, The socket plate has: Interface printed circuit board; and N connector guides are disposed on the first surface of the connector printed circuit board, where N is a natural number. On the second surface of the connector printed circuit board, a portion of a plurality of pads is formed by dividing the board into a first region and a second region. The first region and the second region are separated from each other by a first direction as their long side and a second direction. N connector guides are respectively disposed in a third region sandwiched between the first region and the second region, and each connector guide is electrically connected to a portion of a plurality of pads contained in the first region and a portion of a plurality of pads contained in the second region.

2. The socket plate according to claim 1, characterized in that, At least one of the N socket guides is included in the range of the first region and the second region in the first direction.

3. The socket plate according to claim 1, characterized in that, N=2, and the two connector guides are included in the range of the first region and the second region in the first direction.

4. The socket plate according to claim 1, characterized in that, N=4, and two connector guides are included in the range of the first region and the second region in the first direction.

5. An automatic testing device, characterized in that, The automatic testing device includes the socket plate according to any one of claims 1 to 4.

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