Wafer parameter calibration method and system and storage medium

Abstract

The invention relates to the field of wafers, in particular to a wafer parameter calibration method and system and a storage medium, and the method comprises the steps: obtaining historical performance test MAP maps of a plurality of target wafers of the same type; superposing the plurality of historical performance test MAPs, and performing classification iteration to obtain a performance parameter distribution diagram of the target wafer, the performance parameter distribution diagram comprising a plurality of areas; screening a plurality of target chips in each area, and performing parameter calibration on the screened target chips to generate calibration codes; and summarizing the calibration codes of the areas to form a batch calibration code set covering the wafer, and performing parameter calibration on all chips in the wafer according to the batch calibration code set. The test time can be shortened, and the test cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of wafers, in particular to a wafer parameter calibration method and system and a storage medium. BACKGROUND

[0002] Compared with the chip probe test of ordinary semiconductor products, the probe test of Flash products has significant particularity: the core requirement is to determine the performance margin of the chip, that is, to determine the appropriate read-write window, which directly determines the stability and reliability of the read-write operation of the Flash chip and is a key indicator for judging whether the performance of the chip meets the standard.

[0003] In actual production process, due to the influence of manufacturing processes such as photolithography and etching, there is often a significant performance margin difference between the chips (dies) in the center and edge regions (Center / Edge, referred to as C / E) of the wafer; if the difference exceeds the design tolerance range, it will directly lead to the chips in the edge or center region being judged as failed due to the unqualified performance margin, ultimately causing the product yield to decrease, and even causing serious yield loss.

[0004] At present, the mainstream improvement scheme for the above-mentioned wafer center-edge in-plane uniformity difference problem is as follows: Per die trim: by adjusting the temperature coefficient, Bias bias voltage, PUMP pump pressure and other key parameters of the chip, configuration data for accurately calibrating the performance of the chip is generated. The core logic of this scheme is to offset the process fluctuations generated in the manufacturing process of each chip through one-to-one parameter compensation, so as to ensure that the performance of each chip meets the design specifications, and finally effectively improve the difference between the center and edge regions of the wafer and improve the consistency of the chip performance. However, since the calibration and calibration code generation process needs to be performed on each chip on the wafer, the probe test time will be greatly increased. For example: in the production scene of 110nm process node, 12-inch wafer, and chip size of 2x2mm 2 , the probe test time is increased by at least 30%, which not only directly increases the test cost, but also reduces the overall production efficiency, making it difficult to adapt to large-scale production demand. SUMMARY

[0005] The purpose of the present application is to provide a wafer parameter calibration method, system and storage medium, which can reduce the test time and reduce the test cost.

[0006] In order to achieve the above purpose, the technical scheme adopted by the present application is as follows: In a first aspect, the present application provides a wafer parameter calibration method, which comprises: obtaining a historical performance test MAP graph of a plurality of target wafers of the same type; Superimpose a plurality of historical performance test MAP charts, perform classification iteration, and obtain a performance parameter distribution chart of the target wafer, the performance parameter distribution chart including a plurality of regions; Screen a plurality of target chips in each region, calibrate parameters of the screened target chips, and generate calibration codes; Collect the calibration codes of the regions to form a batch calibration code set covering the wafer, and calibrate parameters of all chips in the wafer according to the batch calibration code set.

[0007] Further, the generating of the calibration codes includes: Randomly select a plurality of chips on the wafer in the target region, test performance parameters of the selected chips, and screen a plurality of target chips with medium performance; Connect the screened target chips with a test machine, contact configuration pins of the screened target chips through a probe, write calibration parameters, adjust parameters of the target chips, and obtain initial calibration codes until a calibration target is reached. Verify whether the initial calibration codes are suitable for other chips in the region, if yes, use the obtained initial calibration codes as the calibration codes of the region, and if no, reselect chips and adjust parameters to generate new initial calibration codes.

[0008] Further, verifying whether the initial calibration codes are suitable for other chips in the region includes: writing the initial calibration codes into a plurality of randomly selected chips other than the target chips, retesting performance parameters of the chips; when the performance parameters are within a preset range, it is determined that the target is reached, otherwise it is determined that the target is not reached. Calculate a pass rate of the plurality of randomly selected chips other than the target chips, and in response to the pass rate being greater than a first preset value, it is determined that the initial calibration codes pass the verification, otherwise it is determined that the verification fails.

[0009] Further, after the initial calibration codes pass the verification, the method further includes: Set process fluctuation parameters and corresponding fluctuation ranges in the test machine; Re-test performance parameters of the screened target chips in a process fluctuation environment, if the performance parameters are within a preset range, use the obtained initial calibration codes as batch calibration codes of the region, and if the performance parameters are not within the preset range, adjust parameters of the screened target chips to obtain optimized initial calibration codes.

[0010] Further, when the number of target chips is one, calibrate parameters of the screened target chip to generate calibration codes; When the number of target chips is two or more, adjust parameters of the screened target chips to generate two or more groups of basic calibration codes; The area coverage test is performed, the generated basic calibration code is written into a plurality of chips selected randomly except the target chip, and the performance parameters of the chips are retested; when the performance parameters are within the preset range, it is determined that the standard is met, otherwise it is determined that the standard is not met; the pass rate corresponding to each group of basic calibration codes is calculated; If the fluctuation value of the pass rate corresponding to two or more groups of basic calibration codes is greater than the second preset value, the basic calibration code corresponding to the highest pass rate is taken as the calibration code; If the fluctuation value of the pass rate corresponding to two or more groups of basic calibration codes is not greater than the second preset value, an environmental stability test is performed, and one group of basic calibration codes is selected as the calibration code according to the environmental stability test result.

[0011] Further, an environmental stability test is performed, and one group of basic calibration codes is selected as the calibration code according to the environmental stability test result, including: The performance parameters of the target chip are retested under process fluctuation environment; If the performance parameters of the target chip are within the preset range, the group of basic calibration codes is retained; if the performance parameters of the target chip are not within the preset range, the group of basic calibration codes is removed; The fluctuation range of the performance parameters of the target chip corresponding to the retained several groups of basic calibration codes is identified, and one group of basic calibration codes with the smallest fluctuation range is selected as the calibration code.

[0012] Further, when the number of target chips is two or more, the selected target chips are adjusted in parameters respectively, two or more groups of basic calibration codes are generated, and the mean value of the two or more groups of basic calibration codes is taken as the calibration code.

[0013] Further, after the parameter calibration of all chips in the wafer is performed according to the batch calibration code set, the performance test of the target wafer is re-performed, and the performance test MAP is taken as a new sample and is put into the historical sample library.

[0014] In a second aspect, the present application discloses a wafer parameter calibration system, which comprises: An acquisition module is configured to acquire historical performance test MAPs of a plurality of target wafers of the same type; A classification module is configured to superimpose the historical performance test MAPs and perform classification iteration to obtain a performance parameter distribution map of the target wafer, wherein the performance parameter distribution map comprises a plurality of regions; A generation module is configured to select a plurality of target chips in each region, perform parameter calibration on the selected target chips, and generate calibration codes; A calibration module is configured to collect the calibration codes of the regions to form a batch calibration code set covering the wafer, and perform parameter calibration on all chips in the wafer according to the batch calibration code set.

[0015] In a third aspect, the present application discloses a computer readable storage medium, wherein the computer readable storage medium stores computer instructions, and the computer instructions are used to make a processor execute the steps of the wafer parameter calibration method.

[0016] The unexpected beneficial effects of the present application are as follows: The wafer parameter calibration method classifies and iterates a plurality of historical performance test MAP charts to obtain a performance parameter distribution graph of a target wafer, the performance parameter distribution graph includes a plurality of regions; then only a small number of target chips in each region after division need to be selected to perform calibration, which greatly reduces the total amount of calibration operation; the generated batch calibration code set can directly cover all chips of the wafer, without repeatedly generating calibration codes for single chips, which significantly shortens the overall calibration period. At the same time, the reduction of calibration operation also reduces the occupation pressure and wear risk of the test equipment, reduces the resource consumption of data storage and processing, and reduces the production cost from multiple dimensions such as equipment use and manual operation. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A flowchart of the wafer parameter calibration method according to the embodiment of the present application is shown.

[0018] Figure 2 A performance parameter distribution graph of a target wafer according to the embodiment of the present application is shown.

[0019] Figure 3 A flowchart of generating a calibration code according to the embodiment of the present application is shown.

[0020] Figure 4 A structure diagram of the wafer parameter calibration system according to the embodiment of the present application is shown. DETAILED DESCRIPTION

[0021] The embodiments of the present application will be described below with reference to the drawings and preferred embodiments, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in the present specification. The present application can also be implemented or applied by different specific embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the present application. It should be understood that the preferred embodiments are only for illustrating the present application, but not for limiting the protection scope of the present application.

[0022] It should be noted that the diagrams provided in the following embodiments only schematically illustrate the basic concept of the present application, and therefore only the components related to the present application are shown in the diagrams, but not the number, shape and size of the components when actually implemented. The actual implementation of each component may be a random change in type, number and proportion, and the layout pattern of the components may also be more complex.

[0023] In an embodiment, the present application discloses a wafer parameter calibration method, as shown in Figure 1 The method comprises the following steps: Obtaining historical performance test MAP graphs of a plurality of target wafers of the same type; Superimposing the historical performance test MAP graphs, performing classification iteration, and obtaining a performance parameter distribution graph of the target wafer, wherein the performance parameter distribution graph comprises a plurality of regions; Selecting a plurality of target chips in each region, performing parameter calibration on the selected target chips, and generating calibration codes; Collecting the calibration codes of each region to form a batch calibration code set covering the wafer, and performing parameter calibration on all chips in the wafer according to the batch calibration code set.

[0024] The wafer parameter calibration method disclosed by the present application first performs classification iteration on a plurality of historical performance test MAP graphs to obtain a performance parameter distribution graph of the target wafer, wherein the performance parameter distribution graph comprises a plurality of regions; then only a small number of target chips in each region after division need to be selected for calibration, which greatly reduces the total amount of calibration operations; the generated batch calibration code set can directly cover all chips in the wafer, without the need to repeatedly generate calibration codes for single chips, thereby significantly shortening the overall calibration period. At the same time, the reduction of calibration operation amount also reduces the occupation pressure and wear risk of the test equipment, reduces the resource consumption of data storage and processing, and reduces the production cost from multiple dimensions such as equipment use and manual operation and maintenance.

[0025] The traditional scheme does not consider the performance difference of different regions of the wafer, such as the parameter deviation of the center and edge chips, which is prone to over-calibration or under-calibration, resulting in substandard performance of some chips. Based on the superposition and classification iteration of a plurality of historical performance test MAP graphs, the present application can objectively present the performance common characteristics of different regions of the same type of wafer, ensure that the region division matches the performance law of the actual mass production process, and customize the calibration code of each region according to the performance deviation of the region, so as to accurately compensate for the process fluctuation of the chips in the region, make the performance parameters of all chips in the region stable and fall within the qualified range, effectively improve the in-plane performance uniformity of the wafer, avoid chip failure caused by mismatched local region calibration, and thus reduce yield loss.

[0026] The application takes historical data of the same type of target wafer as the core input, is not bound to a specific wafer size, process node or chip type, and has wide adaptability. For the same type of wafer, such as the same Flash IP and the same application scenario chip, even if there are slight differences in production batches and customer requirements, only the performance data under the new scenario need to be added to the historical data superposition process, and the region division and calibration code can be quickly updated, without the need to redevelop the entire calibration logic; whether it is a wafer of different sizes or a product of different process nodes, the core processes of historical data modeling, regional calibration and batch application can be reused, greatly reducing the adaptation cost of multi-scene production and shortening the production introduction cycle of new types of products.

[0027] Exemplarily, referring to Figure 2 The performance parameter distribution diagram of the target wafer is obtained by superimposing a plurality of historical performance test MAP diagrams and iterating classification, and the performance parameter distribution diagram includes three regions, which are respectively denoted as region I, region II and region III, wherein region I is a central high stability region, and region III is an edge fluctuation region. A plurality of target chips are screened in each region, and the screened target chips are calibrated to generate three groups of calibration codes corresponding to the three regions, denoted as D1, D2 and D3. And three sets of test programs CP_program1, CP_program2 and CP_program3 are matched for the three groups of calibration codes, which fundamentally solves the pain point of incomplete coverage of a single CP flow (wafer probe test flow).

[0028] The traditional single CP flow can only adapt to the performance parameters of a certain region (such as the central region) of the wafer, and in the face of the performance parameter differences of the edge region (region III) caused by process fluctuations, it is easy to appear that the calibration is not up to standard and the test is misjudged; and the chips in region III in the example can compensate for the edge performance deviation through the exclusive D3 calibration code, and then test according to the qualified threshold of the edge region using CP_program3, to ensure that the calibration-test whole process fits the regional characteristics.

[0029] And the three groups of calibration codes and the three sets of CP programs form a closed loop of region-calibration-test, covering all performance intervals of the wafer from the center to the edge, and completely weakening the adverse effects of wafer in-plane uniformity difference on yield.

[0030] In the calibration link, it is not necessary to generate calibration codes for all chips on the wafer, and only a small number of target chips in three regions are screened to generate D1, D2 and D3 calibration codes, which can cover the whole wafer, and the calibration operation amount is reduced from ten thousand to individual, and the calibration time is greatly reduced. In the test link, CP_program1~3 correspond to the performance parameter range of regions I~III, and the test standard does not need to be adjusted for each chip, and only the corresponding program needs to be called according to the region to quickly complete the judgment, avoiding the redundant operation of repeatedly adjusting the threshold value and multiple retesting of the general CP program, further shortening the test period, and finally realizing the cost reduction of the whole process of calibration and test.

[0031] Meanwhile, the method is suitable for various complex circuit designs of different customers, reduces the difficulty of Flash test, unifies the standard of Flash test, and makes the process more standardized and modularized.

[0032] As a preferred embodiment of the present application, referring to Figure 3 The generating calibration code comprises: Randomly selecting a plurality of chips on the wafer in the target region, testing the performance parameters of the selected chips, and screening a plurality of target chips with medium performance; Connecting the selected target chips with the test machine, contacting the configuration pins of the selected target chips through the probe, writing the calibration parameters, adjusting the parameters of the target chips, until the calibration target is reached, and obtaining the initial calibration code; Verifying whether the initial calibration code is suitable for other chips in the region, if yes, taking the obtained initial calibration code as the calibration code of the region; if not, reselecting the chips and adjusting the parameters to generate the initial calibration code again.

[0033] The preferred embodiment discards the one-sidedness of the traditional single chip representing the region by randomly selecting a plurality of chips and screening target chips with medium performance. Random selection can cover chips with different performance fluctuations in the region, avoiding the situation that the calibration code is only suitable for individual chips due to the selection of extreme performance chips (such as the best or worst chip); and the target chip with medium performance can accurately reflect the common performance characteristics of most chips in the region, such as the average parameter deviation and process fluctuation level. The calibration code generated based on this can naturally meet the performance requirements of most chips in the region, and there is no need to fine-tune for a single chip, which guarantees the accuracy of regional batch calibration from the source and avoids the risk of failure caused by the mismatch between the calibration code and the chip performance.

[0034] As a preferred embodiment of the present application, the step of verifying whether the initial calibration code is suitable for the other chips in the region specifically comprises: writing the initial calibration code into a plurality of randomly selected chips other than the target chip, and re-measuring the performance parameters of the chips; when the performance parameters are within the preset range, it is determined that the standard is met, otherwise it is determined that the standard is not met; the pass rate of the plurality of randomly selected chips other than the target chip is calculated, and in response to the pass rate being greater than a first preset value, it is determined that the initial calibration code passes the verification, otherwise it is determined that the initial calibration code fails the verification.

[0035] The preferred embodiment converts the judgment standard of whether the initial calibration code is suitable into a quantitative index of the pass rate, rather than relying on subjective evaluation by humans. By determining whether the performance parameters are within the preset range, and then determining whether the pass rate exceeds the first preset value as the final basis for judgment, the verification result has the characteristics of being measurable and reproducible. This quantitative logic avoids judgment bias caused by experience differences of different operators, ensures that the calibration code verification standard in the same region is uniform, and improves the objectivity and standardization of the verification process.

[0036] Randomly selecting a plurality of chips other than the target chip during the verification process can cover chips in different positions and with different performance characteristics in the region, rather than only verifying a small number of samples with similar performance to the target chip. This sampling method ensures that the verification object is representative of the region, and can effectively detect whether the calibration code can adapt to the performance fluctuations of various chips in the region, thereby ensuring the adaptability of the calibration code to the batch of chips in the region from the source.

[0037] The mechanism of determining that the initial calibration code passes the verification only in response to the pass rate being greater than the first preset value sets a clear access threshold for the calibration code. If the calibration code can only adapt to a small number of chips (the pass rate is lower than the threshold), it is directly determined that the initial calibration code fails the verification, thereby avoiding the situation that the calibration code flows into the subsequent batch calibration link. This early interception can effectively avoid the risk of large-scale performance failure caused by applying unqualified calibration codes to all chips in the region, and reduce the yield loss and rework cost caused by calibration failure. At the same time, the preset threshold can be flexibly adjusted according to the performance requirements of the product, so that the verification standard can adapt to the quality requirements of different scenarios.

[0038] When the pass rate does not reach the preset value, the mechanism of determining that the initial calibration code fails the verification and re-generating the calibration code provides a clear improvement direction for the optimization of the calibration code. By analyzing the performance characteristics of the chips that do not meet the standard, such as which parameters exceed the range and are concentrated in which positions in the region, the defects of the initial calibration code can be accurately located, so that the re-generated calibration code can compensate for the shortcomings. This closed loop of verification, feedback, and optimization promotes the continuous evolution of the calibration code towards higher adaptability, and long-term improves the effect of regional batch calibration.

[0039] As a preferred embodiment of the present application, after the initial calibration code passes the verification, the method further comprises: Set the process fluctuation parameters and corresponding fluctuation range in the tester; Under the process fluctuation environment, retest the performance parameters of the target chips screened out, if the performance parameters are within the preset range, then take the obtained initial calibration code as the batch calibration code of the region; if the performance parameters are not within the preset range, then re-adjust the parameters of the target chips screened out to obtain the optimized initial calibration code.

[0040] As a preferred embodiment of the present application, when the number of target chips is one, directly perform parameter calibration on the screened target chip to generate a calibration code; When the number of target chips is two or more, adjust the parameters of the target chips screened out respectively to generate two or more groups of basic calibration codes; Perform regional coverage testing, write the generated basic calibration codes into other randomly selected multiple chips except the target chips, and retest the performance parameters of the chips; when the performance parameters are within the preset range, it is determined to be up to standard, otherwise it is determined to be not up to standard; the up-to-standard rate corresponding to each group of basic calibration codes is calculated; If the fluctuation value of the up-to-standard rate corresponding to the two or more groups of basic calibration codes is greater than a second preset value, take the basic calibration code corresponding to the highest up-to-standard rate as the calibration code; If the fluctuation value of the up-to-standard rate corresponding to the two or more groups of basic calibration codes is not greater than the second preset value, perform environmental stability testing, and select one group of basic calibration codes as the calibration code according to the environmental stability testing result.

[0041] This preferred embodiment clearly distinguishes the processing logic when the number of target chips is one or two or more: when it is one, directly generate a calibration code to simplify the operation process, which is suitable for the scene where the regional performance is highly uniform and a single chip can represent the whole; when it is two or more, start the comparison and optimization of multiple groups of calibration codes, which is suitable for the scene where the regional performance has slight differences and needs to be covered by multiple samples. This scene-adaptive design avoids the rigid problem of applying a single logic to all situations, neither overcomplicating the single-target-chip scene nor lacking optimization standards for the multi-target-chip scene, which greatly improves the universality of the scheme in different mass production scenarios.

[0042] When the number of target chips is two or more, this embodiment first calculates the up-to-standard rate of each group of basic calibration codes through regional coverage testing, and judges the optimization logic according to the fluctuation value of the up-to-standard rate: if the fluctuation value is greater than a second preset value, directly select the calibration code with the highest up-to-standard rate. This operation takes the actual adaptation effect of the chips in the region as the core standard, ensures that the finally selected calibration code can cover more chips in the region (the higher the up-to-standard rate, the more chips are adapted), and avoids the coverage problem caused by subjective selection (such as randomly selecting a group of calibration codes), which fundamentally guarantees the effectiveness of regional batch calibration.

[0043] When the pass rate of multiple sets of basic calibration codes fluctuates slightly, it indicates that the coverage difference is not large. This embodiment further introduces an environmental stability test selection. This design accurately captures the core demand that stability determines long-term use effect when coverage is similar: for example, the pass rates of two sets of calibration codes are both 95%, the coverage is similar, but one set is stable in performance under temperature fluctuation, and the other set is easy to deviate. The former is selected by the stability test to avoid the short board of only looking at coverage and ignoring long-term reliability. This layered selection logic of first looking at coverage and then looking at stability realizes the balance between short-term production adaptation and long-term use reliability.

[0044] As a preferred embodiment of the present application, the environmental stability test is performed, and one set of basic calibration codes is selected as the calibration code according to the environmental stability test result, which comprises: retesting the performance parameters of the target chip in a process fluctuation environment; if the performance parameters of the target chip are within the preset range, the set of basic calibration codes is retained; if the performance parameters of the target chip are not within the preset range, the set of basic calibration codes is removed; identifying the performance parameter fluctuation range of the target chip corresponding to the retained sets of basic calibration codes, and selecting the set of basic calibration codes with the smallest fluctuation range as the calibration code.

[0045] The first step of this embodiment retests the performance of the target chip in a process fluctuation environment and eliminates unqualified calibration codes. The essence is to set a double access threshold for the calibration codes. The previous regional coverage test ensures that the calibration codes can adapt to most chips in the region, and this link ensures that the calibration codes can adapt to process fluctuations in mass production. In actual mass production, equipment parameter drift, workshop temperature and humidity changes, and raw material batch differences are difficult to completely avoid. If the calibration code can only be qualified in an ideal environment, such as stable voltage, the performance is qualified, and the voltage fluctuates, the performance is unqualified, which will directly lead to the failure of batch chips. This link retests in a fluctuation environment, which can identify such environmentally sensitive calibration codes in advance and directly eliminate them, thereby preventing the risk of yield reduction caused by fluctuations from the source and ensuring the stability of mass production.

[0046] After retaining the calibration codes that pass in the fluctuation environment, this embodiment further selects the calibration code with the smallest performance parameter fluctuation range. The smaller the performance parameter fluctuation range, the more stable the performance of the calibration code in different fluctuation scenarios. Not only can it adapt to short-term fluctuations in the mass production link, but also can support long-term reliable work of the chip in terminal application. For example: two sets of calibration codes can both pass when the voltage fluctuates ±5%, but the performance parameter fluctuation range of A group is 0.1V, and that of B group is 0.3V. After selecting the A group calibration code, even if the maximum amplitude voltage fluctuation occurs in mass production, the performance of the chip can be maintained within a narrower qualified interval, reducing the performance degradation caused by long-term fluctuations and prolonging the reliability of the chip throughout its life cycle.

[0047] For regional batch calibration, the performance consistency of all chips in the same region under fluctuating environment is the key. If the calibration code fluctuation range is large, even if the initial calibration of chips in the region meets the standard, under the influence of production fluctuation, performance deviation of part of the chips may occur, resulting in the expansion of performance difference in the region. The calibration code with the smallest fluctuation range is selected in the embodiment, which can ensure that the performance deviation amplitude of all chips in the region under fluctuating environment is similar, rather than part of the chips with small fluctuation and part of the chips with large fluctuation, thereby further reducing the performance difference on the wafer surface, improving the overall uniformity, avoiding the local yield loss caused by performance differentiation under fluctuation, and finally realizing the positive cycle of batch calibration, fluctuation stability and uniformity optimization.

[0048] As a preferred embodiment of the present application, when the number of target chips is two or more, the selected target chips are respectively adjusted in parameters to generate two or more groups of basic calibration codes, and the mean value of the two or more groups of basic calibration codes is taken as the calibration code.

[0049] Although the two or more target chips are both performance centering chips, due to the slight fluctuation of chip manufacturing process, the basic calibration codes generated by each of them will still have parameter differences, such as the Bias voltage of A group calibration code is 0.8V and that of B group is 0.82V. If a certain group of calibration codes is directly selected, it may be biased towards the performance characteristics of the target chips in this group, resulting in insufficient adaptation of the chips in the region with similar performance to the target chips in another group, such as selecting A group may make the parameters of the chips with similar performance to B group slightly low after calibration. The operation of taking the mean value can integrate the parameter characteristics of multiple groups of calibration codes, which neither deviates towards the parameters of a target chip nor covers the performance interval represented by multiple target chips, so that the final calibration code can adapt to the wider chip performance fluctuation in the region, avoid the local adaptation failure caused by the bias of a single calibration code, and essentially improve the overall calibration adaptability of the region.

[0050] As a preferred embodiment of the present application, after parameter calibration of all chips in the wafer according to the batch calibration code set, the target wafer is retested for performance, and the performance test MAP is taken as a new sample and included in the historical sample library.

[0051] The preferred embodiment incorporates the performance test MAP of the calibrated target wafer into the historical sample library, and the essence is to supplement the calibration effect data in the real production scene for subsequent regional division and calibration code generation. As the amount of data in the sample library continues to accumulate, the performance parameter distribution graph formed by superimposing multiple performance test MAPs will be more in line with the actual characteristics of the current production process. For example, it can more accurately identify the performance fluctuation rules of different regions of the wafer, such as the parameter shift caused by the subtle aging of a device, and avoid regional division deviations caused by insufficient historical sample size or data lag. The calibration code generated based on a more complete sample library can also more accurately match the actual performance needs of the chips in the region, further reducing the risk of calibration failure, forming a positive cycle from data accumulation to precision improvement.

[0052] Moreover, as the MAPs of different working conditions and different batches in the sample library continue to accumulate, hidden performance rules can be gradually mined, such as the specific correlation between the regional performance differences of wafers produced by different devices in different seasons, and then the calibration process can be optimized accordingly. For example, adjusting the selection criteria for target chips in a certain region, optimizing the adjustment range of calibration parameters, and refining the granularity of regional division. This continuous iteration capability enables the calibration scheme to adapt to changes in production needs for a long time, continuously improving calibration efficiency and yield, and ultimately forming a virtuous cycle at the technical level, providing more mature experience support for the calibration of subsequent similar wafer products.

[0053] In summary, the wafer parameter calibration method disclosed by the application classifies and iterates multiple historical performance test MAPs to obtain a performance parameter distribution graph of a target wafer, and the performance parameter distribution graph includes a plurality of regions. Then, only a small number of target chips in each region after division need to be selected to perform calibration, greatly reducing the total amount of calibration operations. The generated batch calibration code set can directly cover all chips on the wafer, without the need to repeatedly generate calibration codes for single chips, significantly shortening the overall calibration period. At the same time, the reduction in the amount of calibration operations also reduces the occupancy pressure and wear risk of the test equipment, reduces the resource consumption of data storage and processing, and reduces production costs from multiple dimensions such as equipment use and manual operation.

[0054] In one embodiment, the application discloses a wafer parameter calibration system, as shown in Figure 4 The parameter calibration system 10 includes: The acquisition module 11 is configured to acquire historical performance test MAPs of a plurality of target wafers of the same type; The classification module 12 is configured to superimpose the historical performance test MAPs to perform classification and iteration, and obtain a performance parameter distribution graph of a target wafer, wherein the performance parameter distribution graph includes a plurality of regions; The generation module 13 is configured to select a plurality of target chips in each region, perform parameter calibration on the selected target chips, and generate calibration codes. The calibration module 14 is configured to collect the calibration codes of the regions to form a batch calibration code set covering the wafer, and calibrate parameters of all chips in the wafer according to the batch calibration code set.

[0055] In one embodiment, the present application discloses a computer readable storage medium, wherein computer instructions are stored in the computer readable storage medium, and the computer instructions are configured to enable a processor to perform the steps of the wafer parameter calibration method.

[0056] The above embodiments are only preferred embodiments for fully illustrating the present application, and the protection scope of the present application is not limited thereto. Any equivalent replacement or transformation of the present application made by those skilled in the art based on the present application is within the protection scope of the present application.

Claims

1. A method for calibrating wafer parameters, characterized in that, include: Obtain historical performance test MAPs for multiple target wafers of the same type; Multiple historical performance test MAP maps are overlaid, classified, and iterated to obtain a performance parameter distribution map of the target wafer, which includes several regions. In each region, select several target chips, calibrate the parameters of the selected target chips, and generate calibration codes; The calibration codes of each region are aggregated to form a batch calibration code set covering the wafer. The parameters of all chips in the wafer are calibrated based on the batch calibration code set.

2. The wafer parameter calibration method according to claim 1, characterized in that, The generation of the calibration code includes: Multiple chips are randomly selected on the wafer in the target area, and the performance parameters of the selected chips are tested to screen out several target chips with moderate performance. The selected target chips are connected to a tester. The configuration pins of the selected target chips are contacted by probes, calibration parameters are written, and the parameters of the target chips are adjusted until the calibration target is reached, thus obtaining the initial calibration code. Verify whether the initial calibration code is compatible with other chips in this area. If so, use the obtained initial calibration code as the calibration code for this area; otherwise, select a new chip, adjust the parameters, and regenerate the initial calibration code.

3. The wafer parameter calibration method according to claim 2, characterized in that, Verifying whether the initial calibration code is compatible with other chips in the region specifically includes: writing the initial calibration code into multiple randomly selected chips other than the target chip, and retesting the chip's performance parameters; if the performance parameters are within the preset range, the chip is deemed to have met the standard; otherwise, it is deemed to have failed the standard. The pass rate of multiple randomly selected chips other than the target chip is calculated. If the pass rate is greater than the first preset value, the initial calibration code verification is deemed to have passed; otherwise, the verification is deemed to have failed.

4. The wafer parameter calibration method according to claim 2, characterized in that: After the initial calibration code verification is successful, the following is also included: Set the process fluctuation parameters and corresponding fluctuation range in the testing machine; Under process fluctuations, the performance parameters of the selected target chips are retested. If the performance parameters are within the preset range, the obtained initial calibration code is used as the batch calibration code for that region. If the performance parameters are not within the preset range, the parameters of the selected target chips are readjusted to obtain an optimized initial calibration code.

5. The wafer parameter calibration method according to claim 2, characterized in that: When the target chip is one, the parameters of the selected target chip are directly calibrated to generate a calibration code. When there are two or more target chips, the parameters of the selected target chips are adjusted to generate two or more sets of basic calibration codes. Regional coverage testing was conducted by writing the generated basic calibration codes into multiple randomly selected chips (excluding the target chip) and retesting the chip performance parameters. If the performance parameters were within the preset range, the chip was deemed to have met the standard; otherwise, it was deemed to have failed the standard. The pass rate corresponding to each set of basic calibration codes was calculated. If the pass rate fluctuation value corresponding to two or more sets of basic calibration codes is greater than the second preset value, the basic calibration code with the highest pass rate will be used as the calibration code. If the compliance rate fluctuation value corresponding to two or more sets of basic calibration codes is not greater than the second preset value, an environmental stability test is conducted, and one set of basic calibration codes is selected as the calibration code based on the environmental stability test results.

6. The wafer parameter calibration method according to claim 1, characterized in that, Environmental stability testing was conducted, and based on the test results, one set of basic calibration codes was selected as the calibration code, including: Retest the performance parameters of the target chip under process fluctuations; If the performance parameters of the target chip are within the preset range, the basic calibration code is retained; if the performance parameters of the target chip are not within the preset range, the basic calibration code is removed. Identify the performance parameter fluctuation range of the target chip corresponding to several sets of retained basic calibration codes, and select the set of basic calibration codes with the smallest fluctuation range as the calibration code.

7. The wafer parameter calibration method according to claim 2, characterized in that, When there are two or more target chips, the parameters of the selected target chips are adjusted to generate two or more sets of basic calibration codes, and the average value of the two or more sets of basic calibration codes is used as the calibration code.

8. The wafer parameter calibration method according to claim 1, characterized in that: After calibrating the parameters of all chips in the wafer according to the batch calibration code set, the target wafer is retested, and the performance test MAP is added to the historical sample library as a new sample.

9. A wafer parameter calibration system, characterized in that, include: The acquisition module is used to acquire historical performance test MAPs of multiple target wafers of the same type; The classification module is used to overlay multiple historical performance test MAP maps, perform classification iterations, and obtain a performance parameter distribution map of the target wafer, which includes several regions. The generation module is used to select several target chips in each region, perform parameter calibration on the selected target chips, and generate calibration codes. The calibration module is used to aggregate the calibration codes of each region to form a batch calibration code set covering the wafer, and to perform parameter calibration on all chips in the wafer based on the batch calibration code set.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the steps of the wafer parameter calibration method as described in any one of claims 1 to 8.

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