Floating-point number multiplier, calculation chip and floating-point number multiplication operation method

Abstract

The invention relates to a floating-point number multiplier, a computing chip and a floating-point number multiplication operation method, and belongs to the technical field of computers. According to the floating-point number multiplier, floating-point multiplication of a target floating-point number type is performed on input data by utilizing multiplication mode indication, the floating-point number type is specified as the floating-point number type of floating-point numbers in the input data, the floating-point numbers in the input data are divided into data groups by preprocessing the input data, and the floating-point numbers in the input data are divided into the data groups based on a target multiplication mode. According to the invention, the floating point data in the same data set is subjected to floating point number type floating point number multiplication operation, so that the floating point number multiplier can perform floating point number multiplication operation of various floating point number types by specifying different multiplication modes for input data of different floating point number types; therefore, the operation requirements of floating-point number multiplication of various floating-point number types can be met.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, and particularly relates to a floating-point number multiplier, a computing chip and a floating-point number multiplication method. BACKGROUND

[0002] With the rapid development of Artificial Intelligence (AI) technology, AI computing can be performed by using an AI chip, and the AI computing process involves floating-point number multiplication, integer multiplication and other multiplication operations.

[0003] The floating-point number multiplication can be implemented by a floating-point number multiplier in the AI chip. However, the floating-point number multiplier in the AI chip currently only supports floating-point number multiplication of one floating-point number type, while in some scenarios, the AI computing process needs floating-point number multiplication of multiple floating-point number types, which causes the floating-point number multiplier to be unable to meet the operation requirements of floating-point number multiplication of multiple floating-point number types in the AI computing process. SUMMARY

[0004] The present disclosure provides a floating-point number multiplier, a computing chip and a floating-point number multiplication method to at least solve the problem that the floating-point number multiplier in the related art cannot meet the operation requirements of floating-point number multiplication of multiple floating-point number types. The technical solutions of the present disclosure are as follows.

[0005] According to a first aspect of an embodiment of the present disclosure, a floating-point number multiplier is provided, which comprises a preprocessing circuit and a floating-point number multiplication circuit, and the preprocessing circuit is connected to the floating-point number multiplication circuit.

[0006] The preprocessing circuit is configured to obtain first input data, second input data and a mode identifier of a target multiplication mode, wherein the first input data comprises at least one first floating-point number, the second input data comprises at least one second floating-point number, the floating-point number types of the first floating-point number and the second floating-point number are both a target floating-point number type, and the target multiplication mode indicates that floating-point number multiplication of the target floating-point number type is performed on the first input data and the second input data.

[0007] The preprocessing circuit is further configured to perform preprocessing on the first input data and the second input data based on the target multiplication mode, to obtain at least one data group, and the data group comprises one first floating-point number and one second floating-point number.

[0008] The floating-point number multiplication circuit is configured to, for any data group, perform floating-point number multiplication on the first floating-point number and the second floating-point number in the data group based on the target multiplication mode, to obtain a product result between the first floating-point number and the second floating-point number in the data group.

[0009] Optionally, the pre-processing circuit is further configured to, for any data group, extract key information of a first floating-point number and a second floating-point number in the data group to obtain key information of the first floating-point number and key information of the second floating-point number in the data group, the key information including a sign, an exponent, and a mantissa;

[0010] The floating-point multiplication circuit is configured to, for any data group, perform floating-point multiplication on the first floating-point number and the second floating-point number in the data group based on the target multiplication mode, the key information of the first floating-point number, and the key information of the second floating-point number in the data group to obtain a multiplication result between the first floating-point number and the second floating-point number in the data group.

[0011] Optionally, the floating-point multiplication circuit includes:

[0012] The sign operator circuit is configured to, for any data group, obtain a sign of the multiplication result based on a sign of the first floating-point number and a sign of the second floating-point number in the data group.

[0013] The exponent operator circuit is configured to, for any data group, obtain an exponent of the multiplication result based on the target multiplication mode, an exponent of the first floating-point number, and an exponent of the second floating-point number in the data group.

[0014] The mantissa operator circuit is configured to, for any data group, obtain a mantissa of the multiplication result based on the target multiplication mode, a mantissa of the first floating-point number, and a mantissa of the second floating-point number in the data group.

[0015] The sign, the exponent, and the mantissa of the multiplication result are used to represent the multiplication result.

[0016] Optionally, the sign operator circuit is configured to, for any data group, perform an exclusive-OR operation on the sign of the first floating-point number and the sign of the second floating-point number in the data group to obtain the sign of the multiplication result.

[0017] The exponent operator circuit is configured to, for any data group, perform a summation operation on a target offset, the exponent of the first floating-point number, and the exponent of the second floating-point number in the data group to obtain the exponent of the multiplication result, the target offset being an offset used when storing a floating-point number of a target floating-point number type indicated by the target multiplication mode.

[0018] The mantissa operator circuit is configured to, for any data group, perform a multiplication operation on the mantissa of the first floating-point number and the mantissa of the second floating-point number in the data group based on the target multiplication mode to obtain the mantissa of the multiplication result.

[0019] Optionally, the mantissa operation sub-circuit includes an input interface and a multiplier array, wherein the input interface is connected to the multiplier array;

[0020] The input interface is used to receive a first binary sequence and a second binary sequence, wherein the first binary sequence includes a binary sequence of the mantissa of the at least one first symbol, and the second binary sequence includes a binary sequence of the mantissa of the at least one second symbol;

[0021] The multiplier array is used to perform multiplication operations on the binary sequence of the mantissa of the first symbol and the binary sequence of the mantissa of the second symbol in the same data group based on the target multiplication pattern, so as to obtain the mantissa of the product result between the first floating-point number and the second floating-point number in the same data group.

[0022] Optionally, the floating-point multiplication circuit further includes a leading zero detection sub-circuit, an exponent adjustment sub-circuit, and a mantissa adjustment sub-circuit, wherein the leading zero detection sub-circuit is connected to the mantissa operation sub-circuit, the exponent adjustment sub-circuit, and the mantissa adjustment sub-circuit.

[0023] The leading zero detection sub-circuit is used to detect leading zeros in the binary sequence of the mantissa of the product result to obtain the number of leading zeros in the mantissa of the product result.

[0024] The mantissa adjustment sub-circuit is used to adjust the mantissa of the product result based on the number of leading zeros, so as to obtain the adjusted mantissa of the product result.

[0025] The exponent adjustment sub-circuit is used to adjust the exponent of the multiplication result based on the number of leading zeros, so as to obtain the adjusted exponent of the product result;

[0026] The sign of the product result, the adjusted exponent of the product result, and the mantissa are used to represent the product result.

[0027] Optionally, the mantissa adjustment unit is used to shift the binary sequence of the mantissa of the product result to the left by the number of leading zeros to obtain the adjusted mantissa of the product result;

[0028] The exponent adjustment sub-circuit is used to subtract the exponent of the multiplication result from the number of leading zeros to obtain the adjusted exponent of the product result.

[0029] Optionally, the floating-point multiplier further includes an anomaly detection sub-circuit, which is connected to the preprocessing circuit;

[0030] The anomaly detection sub-circuit is used to detect whether the product result is an anomaly for any data group, based on the target multiplication mode, the mantissa and exponent of the first floating-point number in the data group, and the mantissa and exponent of the second floating-point number.

[0031] Optionally, the floating-point multiplier further includes a storage circuit, which is connected to the floating-point multiplication circuit;

[0032] The storage circuit is used to store the product result with the bit width of the highest precision floating-point number, wherein the bit width of the target floating-point number type is smaller than the bit width of the highest precision floating-point number.

[0033] Optionally, the target floating-point number type is at least one of 16-bit floating-point, 16-bit 8-bit floating-point, or 4-bit floating-point.

[0034] According to a second aspect of the present disclosure, a computing chip is provided, the computing chip including a processor and a floating-point multiplier, the processor being connected to the floating-point multiplier; the floating-point multiplier including a preprocessing circuit and a floating-point multiplication circuit, the preprocessing circuit being connected to the floating-point multiplication circuit;

[0035] The processor is configured to send floating-point multiplication instructions to the point-multiplier, wherein the floating-point multiplication instructions include first input data, second input data, and a mode identifier of a target multiplication mode. The first input data includes at least one first floating-point number, the second input data includes at least one second floating-point number, the floating-point type of the first floating-point number and the second floating-point number are both of the target floating-point type, and the target multiplication mode indicates that floating-point multiplication of the target floating-point type is performed on the first input data and the second input data.

[0036] The preprocessing circuit is used to receive floating-point multiplication operation instructions, and preprocess the first input data and the second input data based on the target multiplication mode to obtain at least one data group, wherein the data group includes a first floating-point number and a second floating-point number;

[0037] The floating-point multiplication circuit is used to perform floating-point operations on the first and second floating-point numbers in any data group based on the target multiplication mode, to obtain the product result between the first and second floating-point numbers in the data group, and return the product result to the processor.

[0038] Optionally, the preprocessing circuit is further configured to extract key information from the first floating-point number and the second floating-point number in any data group, to obtain key information of the first floating-point number and the second floating-point number in the data group, wherein the key information includes the sign, exponent and mantissa.

[0039] The floating-point multiplication circuit is used to perform floating-point operations on the first and second floating-point numbers in the data group for any data group, based on the target multiplication mode, key information of the first floating-point number in the data group, and key information of the second floating-point number, to obtain the product result between the first and second floating-point numbers in the data group.

[0040] Optionally, the floating-point multiplication circuit includes:

[0041] The sign operation subcircuit is used to obtain the sign of the product result for any data group based on the sign of the first floating-point number and the sign of the second floating-point number in the data group.

[0042] An exponentiation subcircuit is used to obtain the exponent of the product result based on the target multiplication mode, the exponent of the first floating-point number in the data group, and the exponent of the second floating-point number.

[0043] The mantissa operation sub-circuit is used to obtain the mantissa of the product result based on the target multiplication mode, the mantissa of the first floating-point number in the data group, and the mantissa of the second floating-point number.

[0044] The sign, exponent, and mantissa of the product result are used to represent the product result.

[0045] Optionally, the sign operation sub-circuit is used to perform an XOR operation on the sign of the first floating-point number and the sign of the second floating-point number in any data group to obtain the sign of the product result.

[0046] The exponent operation sub-circuit is used to perform a summation operation on the target offset, the exponent of the first floating-point number in the data group, and the exponent of the second floating-point number for any data group to obtain the exponent of the multiplication result. The target offset is the offset used when storing the floating-point number of the target floating-point number type indicated by the target multiplication mode.

[0047] The mantissa operation sub-circuit is used to perform a multiplication operation on the mantissa of the first floating-point number and the mantissa of the second floating-point number in any data group, based on the target multiplication mode, to obtain the mantissa of the product result.

[0048] Optionally, the mantissa operation sub-circuit includes an input interface, a multiplier array, a shift unit, and an adder unit, wherein the input interface, the multiplier array, the shift unit, and the adder unit are connected in sequence, and the multiplier array includes multiple multiplier sub-arrays;

[0049] The input interface is used to receive a first binary sequence and a second binary sequence, wherein the first binary sequence includes a binary sequence of the mantissa of the at least one first symbol, and the second binary sequence includes a binary sequence of the mantissa of the at least one second symbol;

[0050] Each of the multiplier subarrays is used to perform multiplication operations on the binary sequence of the mantissa of the first symbol and the binary sequence of the mantissa of the second symbol in the same data group based on the target multiplication pattern, so as to obtain an intermediate product result corresponding to the same data group.

[0051] The shifting unit is used to shift multiple intermediate product results corresponding to the same data group based on the target multiplication pattern, so as to obtain multiple intermediate product results after the data group is shifted.

[0052] The addition unit is used to perform addition operations on multiple intermediate product results after shifting the same data group to obtain the mantissa of the product result between the first floating-point number and the second floating-point number in the data group.

[0053] Optionally, the floating-point multiplication circuit further includes a leading zero detection sub-circuit, an exponent adjustment sub-circuit, and a mantissa adjustment sub-circuit, wherein the leading zero detection sub-circuit is connected to the mantissa operation sub-circuit, the exponent adjustment sub-circuit, and the mantissa adjustment sub-circuit.

[0054] The leading zero detection sub-circuit is used to detect leading zeros in the binary sequence of the mantissa of the product result to obtain the number of leading zeros in the mantissa of the product result.

[0055] The mantissa adjustment sub-circuit is used to adjust the mantissa of the product result based on the number of leading zeros, so as to obtain the adjusted mantissa of the product result.

[0056] The exponent adjustment sub-circuit is used to adjust the exponent of the multiplication result based on the number of leading zeros, so as to obtain the adjusted exponent of the product result;

[0057] The sign of the product result, the adjusted exponent of the product result, and the mantissa are used to represent the product result.

[0058] Optionally, the mantissa adjustment unit is used to shift the binary sequence of the mantissa of the product result to the left by the number of leading zeros to obtain the adjusted mantissa of the product result;

[0059] The exponent adjustment sub-circuit is used to subtract the exponent of the multiplication result from the number of leading zeros to obtain the adjusted exponent of the product result.

[0060] Optionally, the floating-point multiplier further includes an anomaly detection sub-circuit, which is connected to the preprocessing circuit;

[0061] The anomaly detection sub-circuit is used to detect whether the product result is an anomaly for any data group, based on the target multiplication mode, the mantissa and exponent of the first floating-point number in the data group, and the mantissa and exponent of the second floating-point number.

[0062] Optionally, the floating-point multiplier further includes a storage circuit, which is connected to the floating-point multiplication circuit;

[0063] The storage circuit is used to store the product result with the bit width of the highest precision floating-point number, wherein the bit width of the target floating-point number type is smaller than the bit width of the highest precision floating-point number.

[0064] Optionally, the target floating-point number type is at least one of 16-bit floating-point, 16-bit 8-bit floating-point, or 4-bit floating-point.

[0065] According to a third aspect of the present disclosure, a floating-point multiplication method is provided, the method being applied to a floating-point multiplication circuit, the method comprising:

[0066] Obtain first input data, second input data, and a mode identifier of a target multiplication mode, wherein the first input data includes at least one first floating-point number, the second input data includes at least one second floating-point number, the floating-point number types of the first floating-point number and the second floating-point number are both of the target floating-point number type, and the target multiplication mode indicates that the first input data and the second input data are subjected to floating-point number multiplication operations of the target floating-point number type;

[0067] Based on the target multiplication pattern, the first input data and the second input data are preprocessed to obtain at least one data group, the data group including a first floating-point number and a second floating-point number;

[0068] For any data set, based on the target multiplication mode, floating-point multiplication is performed on the first and second floating-point numbers in the data set to obtain the product between the first and second floating-point numbers in the data set.

[0069] Optionally, the method further includes:

[0070] For any data set, key information is extracted from the first and second floating-point numbers in the data set to obtain key information of the first and second floating-point numbers in the data set. The key information includes the sign, exponent, and mantissa.

[0071] For any data set, based on the target multiplication mode, floating-point multiplication is performed on the first and second floating-point numbers in the data set to obtain the product between the first and second floating-point numbers in the data set, including:

[0072] For any data set, based on the target multiplication mode, the key information of the first floating-point number and the key information of the second floating-point number in the data set, floating-point multiplication is performed on the first floating-point number and the second floating-point number in the data set to obtain the product result between the first floating-point number and the second floating-point number in the data set.

[0073] Optionally, for any data set, based on the target multiplication pattern, key information of the first floating-point number and key information of the second floating-point number in the data set, performing floating-point multiplication on the first and second floating-point numbers in the data set to obtain the product result between the first and second floating-point numbers in the data set includes:

[0074] For any data set, the sign of the product result is obtained based on the sign of the first floating-point number and the sign of the second floating-point number in the data set;

[0075] For any data set, the exponent of the product result is obtained based on the target multiplication mode, the exponent of the first floating-point number in the data set, and the exponent of the second floating-point number.

[0076] For any data set, based on the target multiplication mode, the mantissa of the first floating-point number in the data set, and the mantissa of the second floating-point number, the mantissa of the product result is obtained.

[0077] The sign, exponent, and mantissa of the product result are used to represent the product result.

[0078] Optionally, for any data set, obtaining the sign of the product result based on the sign of the first floating-point number and the sign of the second floating-point number in the data set includes:

[0079] For any data set, perform an XOR operation on the sign of the first floating-point number and the sign of the second floating-point number in the data set to obtain the sign of the product result;

[0080] For any data set, obtaining the exponent of the product result based on the target multiplication pattern, the exponent of the first floating-point number in the data set, and the exponent of the second floating-point number includes:

[0081] For any data set, the target offset, the exponent of the first floating-point number in the data set, and the exponent of the second floating-point number are summed to obtain the exponent of the multiplication result. The target offset is the offset used when storing the floating-point number of the target floating-point number type indicated by the target multiplication mode.

[0082] For any data set, obtaining the mantissa of the product result based on the target multiplication mode, the mantissa of the first floating-point number in the data set, and the mantissa of the second floating-point number includes:

[0083] For any data set, based on the target multiplication mode, the mantissas of the first floating-point number and the mantissas of the second floating-point number in the data set are multiplied to obtain the mantissa of the product result.

[0084] Optionally, for any data set, based on the target multiplication pattern, the mantissas of the first floating-point number and the mantissas of the second floating-point number in the data set are multiplied to obtain the mantissas of the product result, which include:

[0085] Receive a first binary sequence and a second binary sequence, wherein the first binary sequence includes a binary sequence of the mantissa of the at least one first symbol, and the second binary sequence includes a binary sequence of the mantissa of the at least one second symbol;

[0086] Based on the target multiplication pattern, the binary sequence of the mantissa of the first symbol and the binary sequence of the mantissa of the second symbol in the same data group are multiplied to obtain the mantissa of the product result between the first floating-point number and the second floating-point number in the same data group.

[0087] Optionally, the method includes:

[0088] The number of leading zeros in the binary sequence of the mantissa of the product result is obtained by detecting the leading zeros in the mantissa of the product result.

[0089] Based on the number of leading zeros, the mantissa of the product result is adjusted to obtain the adjusted mantissa of the product result;

[0090] Based on the number of leading zeros, the exponent of the multiplication result is adjusted to obtain the adjusted exponent of the product result;

[0091] The sign of the product result, the adjusted exponent of the product result, and the mantissa are used to represent the product result.

[0092] Optionally, adjusting the mantissa of the product result based on the number of leading zeros to obtain the adjusted mantissa of the product result includes:

[0093] Shift the binary sequence of the mantissa of the product result to the left by the number of leading zeros to obtain the adjusted mantissa of the product result;

[0094] The adjustment of the exponent of the multiplication result based on the number of leading zeros, to obtain the adjusted exponent of the product result, includes:

[0095] The exponent of the multiplication result is subtracted from the number of leading zeros to obtain the adjusted exponent of the product result.

[0096] Optionally, the method further includes:

[0097] For any data set, based on the target multiplication pattern, the mantissa and exponent of the first floating-point number in the data set, and the mantissa and exponent of the second floating-point number, it is detected whether the product result is an outlier.

[0098] Optionally, the method further includes:

[0099] The product result is stored with the bit width of the highest precision floating-point number, wherein the bit width of the target floating-point number type is smaller than the bit width of the highest precision floating-point number.

[0100] Optionally, the target floating-point number type is at least one of 16-bit floating-point, 16-bit 8-bit floating-point, or 4-bit floating-point.

[0101] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided such that, when at least one instruction in the computer-readable storage medium is executed by a processor, the device in which the processor resides is capable of performing the method described in the third aspect or any possible implementation thereof.

[0102] According to a fifth aspect of the present disclosure, a computer program product is provided, including one or more instructions that can be executed by a processor, such that a device in which the processor resides can perform the methods described in the third aspect or any possible implementation thereof.

[0103] The technical solutions provided by the embodiments of this disclosure have at least the following beneficial effects:

[0104] The aforementioned floating-point multiplier uses a multiplication mode instruction to perform floating-point multiplication operations on the input data of the target floating-point type. The floating-point type is specified as the floating-point type of the floating-point numbers in the input data. By preprocessing the input data, the floating-point numbers in the input data are divided into data groups. Based on the target multiplication mode, floating-point multiplication operations of the floating-point type are performed on the floating-point data in the same data group. Thus, by specifying different multiplication modes for input data of different floating-point types, the floating-point multiplier can perform floating-point multiplication operations of multiple floating-point types to meet the computational needs of floating-point multiplication operations of multiple floating-point types.

[0105] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0106] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0107] Figure 1 This is a schematic diagram illustrating a structure of multiple floating-point number types according to an exemplary embodiment;

[0108] Figure 2 This is a schematic diagram illustrating a data group partitioning under multiple multiplication modes according to an exemplary embodiment;

[0109] Figure 3 This is a schematic diagram of the structure of a computing chip according to an exemplary embodiment;

[0110] Figure 4 This is a schematic diagram of the structure of a floating-point multiplier according to an exemplary embodiment;

[0111] Figure 5 This is a schematic diagram of the structure of another floating-point multiplier according to an exemplary embodiment;

[0112] Figure 6 This is a schematic diagram of the structure of a mantissa operation sub-circuit according to an exemplary embodiment;

[0113] Figure 7 This is a schematic diagram illustrating the working principle of a multiplier array in multiplication mode 3 according to an exemplary embodiment;

[0114] Figure 8 This is a schematic diagram illustrating the working principle of a multiplier array in multiplication mode 2 according to an exemplary embodiment;

[0115] Figure 9This is a schematic diagram illustrating the working principle of a multiplier array under multiplication mode 0 according to an exemplary embodiment;

[0116] Figure 10 This is a schematic diagram illustrating the working principle of a mantissa operation sub-circuit under multiplication mode 0 according to an exemplary embodiment;

[0117] Figure 11 This is a schematic diagram illustrating the working principle of a leading zero detection sub-circuit according to an exemplary embodiment;

[0118] Figure 12 This is a flowchart illustrating a floating-point multiplication operation method according to an exemplary embodiment. Detailed Implementation

[0119] To facilitate understanding of the technical solutions provided in the embodiments of this application, the composition and types of floating-point numbers will be introduced below:

[0120] A floating-point number can be represented by the following formula (1).

[0121] (-1) s ×1.M×(2) E-offset (1)

[0122] Where S is the sign of the floating-point number, S=0 indicates a positive floating-point number, and S=1 indicates a negative floating-point number; M is the mantissa (man), where M is the fractional part of the mantissa; E is the exponent (esp) of the stored floating-point number; E-offset is the actual exponent of the floating-point number, and offset is the offset used by the computer to store the floating-point number.

[0123] A floating-point number is represented by its sign, mantissa, and exponent. Computers store floating-point numbers by storing these three elements; that is, the stored floating-point number includes the sign, mantissa, and exponent. When storing the mantissa, the integer part (i.e., the 1 in 1.M) is usually hidden, and only the fractional part (i.e., the M in 1.M) is stored. The bits occupied by the sign, mantissa, and exponent in a floating-point number are respectively called the sign bit, mantissa bit, and exponent bit.

[0124] Based on the bit width of the sign bit, mantissa bit, and exponent bit of a floating-point number, stored floating-point numbers have the following various floating-point types:

[0125] 1. 16-bit floating point (FP16)

[0126] like Figure 1As shown, the FP16 has a bit width of 16 bits, where the sign bit, exponent bit, and mantissa bit have bit widths of 1 bit, 5 bits, and 10 bits, respectively.

[0127] 2. 16-bit brain floating point (BP16)

[0128] like Figure 1 As shown, BP16 has a bit width of 16 bits. The bit widths of the sign bit, exponent bit, and mantissa bit of BP16 are 1 bit, 8 bits, and 7 bits, respectively.

[0129] 3. 8-bit floating point (FP8)

[0130] like Figure 1 As shown, the bit width of FP8 is 8 bits. The bit widths of the sign bit, exponent bit, and mantissa bit of FP8 are 1 bit, 4 bits, and 3 bits, respectively.

[0131] 4. 4-bit floating point (FP4)

[0132] like Figure 1 As shown, the bit width of FP4 is 4 bits. The bit widths of the sign bit, exponent bit, and mantissa bit of FP4 are 1 bit, 2 bits, and 1 bit, respectively.

[0133] 5. 32-bit floating point (FP32)

[0134] The FP32 has a bit width of 32 bits. The bit widths of the sign bit, exponent bit, and mantissa bit are 1 bit, 8 bits, and 23 bits, respectively.

[0135] 6. 34-bit floating point (FP64)

[0136] FP64 has a 64-bit width; the sign bit, exponent bit, and mantissa bit widths are 1 bit, 11 bits, and 52 bits, respectively. 6. 13-bit floating-point numbers (FP13)

[0137] 7. The bit width of FP13 is 13 bits. The bit widths of the sign bit, exponent bit, and mantissa bit of FP13 are 1 bit, 5 bits, and 7 bits, respectively.

[0138] 8. 7-bit floating point (FP7)

[0139] The FP7 has a bit width of 7 bits. The bit widths of the sign bit, exponent bit, and mantissa bit are 1 bit, 3 bits, and 1 bit, respectively.

[0140] Multiplying two floating-point numbers of the same type is called floating-point multiplication. Taking floating-point number A and floating-point number B as an example, the operation logic of this floating-point multiplication includes the following steps:

[0141] Step 1: Extract the sign, exponent, and mantissa of floating-point number A and floating-point number B respectively.

[0142] In computers, floating-point numbers are represented using binary sequences. A binary sequence of a floating-point number includes the binary sequences of the sign, mantissa, and exponent. The binary sequence of the floating-point number, sign, mantissa, and exponent is also the binary representation of the floating-point number, sign, mantissa, and exponent.

[0143] Extracting the sign, exponent, and mantissa of a floating-point number refers to extracting the binary sequences of the sign, mantissa, and exponent from the binary sequence of the floating-point number, respectively.

[0144] Step 2: Calculate the sign of the product between the floating-point number A and the floating-point number B.

[0145] For example, performing an XOR operation on the signs of floating-point numbers A and B yields the sign of the product.

[0146] Step 3: Calculate the preliminary exponent of the product result.

[0147] The preliminary exponent refers to the exponent of the product result calculated initially, which is the actual exponent of the product result. The preliminary exponent = the exponent of floating-point number A + floating-point number B - offset, where offset is the offset when storing the floating-point number of this type.

[0148] Step 4: Calculate the initial decimal part of the product result.

[0149] The preliminary mantissa refers to the mantissa of the initially calculated product result, which is the actual mantissa of the product result. Since normalized floating-point numbers hide the integer bits, when both floating-point numbers A and B are normalized, the preliminary mantissa = (1 + mantissa of floating-point number A) * (1 + mantissa of floating-point number B). Since denormalized floating-point numbers do not hide the integer bits, when both floating-point numbers A and B are denormalized, the preliminary mantissa = mantissa of floating-point number A * mantissa of floating-point number B.

[0150] Step 5: Normalize the initial mantissa of the product result to obtain the mantissa of the product result.

[0151] The mantissa of the product result is the normalized mantissa, where 1 ≤ mantissa of the product result < 2.

[0152] If the initial mantissa is greater than or equal to 2, then the binary sequence of the initial mantissa is shifted right by 1 bit to obtain the mantissa of the product result (i.e., the normalized mantissa). Correspondingly, the initial exponent is incremented by 1 to obtain the exponent of the product result.

[0153] If the initial mantissa is less than 1, the binary sequence of the initial mantissa is shifted to the left until 1 ≤ left-shifted mantissa < 2. The left-shifted mantissa is the mantissa of the product result (i.e., the normalized mantissa). Correspondingly, the initial exponent is subtracted from the number of left-shifted bits of the initial mantissa to obtain the exponent of the product result.

[0154] If 1 ≤ preliminary last digit < 2, then the preliminary last digit will be used as the last digit of the product result.

[0155] Step 6: Round off the last digit of the product result.

[0156] Rounding involves discarding unnecessary bits. The bit width of the mantissa of floating-point numbers A and B determines whether the mantissa of the product result is rounded. For example, if the bit width of the mantissa of the product result is greater than the bit width of the mantissa of the floating-point number type, some bits of the mantissa of the product result are discarded, making the bit width of the mantissa of the product result equal to the bit width of the mantissa of the floating-point number type. If the bit width of the mantissa of the product result is less than the bit width of the mantissa of the floating-point number type, at least one 0 is padded to the most significant bit of the mantissa of the product result, making the bit width of the padded mantissa equal to the bit width of the mantissa of the floating-point number type. If the bit width of the mantissa of the product result is equal to the bit width of the mantissa of the floating-point number type, then the mantissa of the product result is not rounded.

[0157] This application provides a floating-point multiplier that supports floating-point multiplication operations for multiple floating-point numbers, including at least two of FP16, BP16, FP8, and FP4. This allows the floating-point multiplier to meet the computational requirements of floating-point multiplication operations for different floating-point numbers.

[0158] Floating-point multiplication of the same floating-point number type refers to the multiplication operation between two floating-point numbers of the same type. For example, FP16*FP16=FP32, BF16*BF16=FP32, FP8*FP8=FP13, FP4*FP4=FP7.

[0159] Floating-point multiplication operations of different floating-point numbers can be indicated by different multiplication modes. That is, a floating-point multiplier supports multiple multiplication modes, each indicating that a floating-point multiplication operation of the same floating-point type is performed on two input data. For example, there are the following four multiplication modes:

[0160] Multiplication mode 0: Indicates that an FP16*FP16 floating-point multiplication operation is performed on two input data;

[0161] Multiplication Mode 1: Indicates that a floating-point multiplication operation of BF16*BF16 is performed on two input data;

[0162] Multiplication Mode 2: Indicates that an FP8*FP8 floating-point multiplication operation is performed on two input data;

[0163] Multiplication Mode 3: Indicates that an FP4*FP4 floating-point multiplication operation is performed on two input data.

[0164] To accommodate different multiplication modes, the input data bit width in each mode is the target bit width, which is the maximum bit width of the various floating-point numbers supported by the floating-point multiplier. For example, for various floating-point numbers including FP16, BP16, FP8, and FP4, the target bit width is 16.

[0165] Based on this, each input data in multiplication mode 0 includes one FP16, and each input data in multiplication mode 1 includes one BP16. Each input data in multiplication mode 1 includes two FP8s, with the two FP8s in the same input data arranged sequentially. Each input data in multiplication mode 2 includes four FP4s, with the four FP4s in the same input data arranged sequentially.

[0166] In any multiplication mode, the floating-point multiplier can perform floating-point multiplication operations on two input data of the corresponding floating-point type.

[0167] For example, in multiplication mode 0, a set of FP16*FP16 floating-point multiplication operations is performed on two input data. The two FP16 values ​​involved in this set of FP16*FP16 floating-point multiplication operations are located on different input data. Figure 2 As shown in Figure (a), assuming the two input data are input data 11 and 12 respectively, input data 11 includes floating-point number 1 and input data 12 includes floating-point number 2. Both floating-point numbers 1 and 2 are FP16. In multiplication mode 0, the floating-point multiplier performs multiplication operations on floating-point numbers 1 and 2.

[0168] For example, in multiplication mode 1, a set of BF16*BF16 floating-point multiplication operations is performed on two input data. The two BF16 values ​​involved in this set of BF16*BF16 floating-point multiplication operations are located in different input data. Figure 2 As shown in Figure (b), assuming the two input data are input data 13 and 14 respectively, input data 13 includes floating-point number 3 and input data 14 includes floating-point number 4. Both floating-point numbers 3 and 4 are BF16. In multiplication mode 1, the floating-point multiplier performs multiplication operations on floating-point numbers 3 and 4.

[0169] For example, in multiplication mode 2, two sets of FP8*FP8 floating-point multiplication operations are performed on two input data, with each set of FP8*FP8 floating-point multiplication operations involving two FP8 values ​​located on different input data. Figure 2 As shown in Figure (c), assuming the two input data are input data 15 and 16 respectively, input data 15 includes floating-point numbers 5 and 6, and input data 16 includes floating-point numbers 7 and 8. Floating-point numbers 5 to 8 are all FP8. In multiplication mode 2, the floating-point multiplier performs multiplication operations on floating-point numbers 5 and 7, and multiplication operations on floating-point numbers 6 and 8.

[0170] For example, in multiplication mode 4, four sets of FP4*FP4 floating-point multiplication operations are performed on two input data, with each set of FP4*FP4 floating-point multiplication operations involving two FP4s located on different input data. Figure 2 As shown in Figure (d), assuming the two input data are input data 17 and 18 respectively, input data 17 includes floating-point numbers 9 to 12, and input data 18 includes floating-point numbers 13 to 16. Floating-point numbers 9 to 16 are all FP4. In multiplication mode 3, the floating-point multiplier performs multiplication operations on floating-point numbers 9 and 13, on floating-point numbers 10 and 14, on floating-point numbers 11 and 15, and on floating-point numbers 12 and 16.

[0171] Optionally, in some embodiments, the multiplication mode can also indicate the number of floating-point multiplication operations to be performed. For example, multiplication mode 0 indicates performing one set of FP16*FP16 floating-point multiplication operations on two input data, multiplication mode 1 indicates performing one set of BF16*BF16 floating-point multiplication operations on two input data, multiplication mode 2 indicates performing two sets of FP8*FP8 floating-point multiplication operations on two input data, and multiplication mode 3 indicates performing four sets of FP4*FP4 floating-point multiplication operations on two input data.

[0172] Because the floating-point multiplier can perform floating-point multiplication operations in multiplication modes 0 through 3, and can perform one, two, and four groups of floating-point multiplication operations respectively in these modes, it can support floating-point multiplication operations with a computing power ratio of 1:1:2:4. In 1:1:2:4, 1, 2, and 4 correspond to floating-point multiplication operations of FP16*FP16, BF16*BF16, FP8*FP8, and FP4*FP4, respectively.

[0173] The floating-point multiplier provided in this application can be applied in computing chips. Next, in conjunction with the attached... Figure 3 This section introduces this type of computing chip.

[0174] Figure 3This is a schematic diagram of the structure of a computing chip provided in an embodiment of this application. Figure 3 The computing chip 200 shown can be any type of computing chip with computing capabilities, such as a Central Processing Unit (CPU) chip, a Microprocessor (MPU), a Graphics Processing Unit (GPU), or a Digital Signal Processor (DSP), but the type of computing chip is not limited to these. A computing chip can be an AI chip, or it may not be an AI chip.

[0175] The computing chip 200 includes a processor 10 and a floating-point multiplier 20, with the processor 10 connected to the floating-point multiplier 20.

[0176] Processor 10 is a computing module with computing capabilities in computing chip 200. Processor 10 can be implemented using at least one of the following hardware forms: DSP, field programmable gate array (FPGA), programmable logic array (PLA), and application specific integrated circuit (ASIC). Processor 10 can be a CPU, but its type is not limited to these.

[0177] The floating-point multiplier 20 is a module in the computing chip 200 used to implement floating-point multiplication operations for various floating-point number types. The floating-point multiplier 20 is the floating-point multiplier provided in the embodiments of this disclosure. In some embodiments, the floating-point multiplier 20 is also referred to as a floating-point multiplication module or a floating-point multiplication device.

[0178] When floating-point multiplication is required, processor 10 can invoke floating-point multiplier 20 to perform the operation. For example, processor 10 sends a floating-point multiplication instruction to floating-point multiplier 20, instructing it to perform floating-point multiplication on the input data in a target multiplication mode. The target multiplication mode is any of the multiple multiplication modes supported by floating-point multiplier 20, specified by the processor based on the floating-point type of the input data. For instance, if the input data contains a floating-point number FP16, the target multiplication mode is multiplication mode 0; if it contains a floating-point number BF16, the target multiplication mode is multiplication mode 1; if it contains a floating-point number FP8, the target multiplication mode is multiplication mode 2; and if it contains a floating-point number FP4, the target multiplication mode is multiplication mode 0.

[0179] The floating-point multiplier 20 receives floating-point multiplication instructions, performs floating-point multiplication operations on the input data in target multiplication mode based on the instructions, and returns the result to the processor 10. The processor 10 receives the result.

[0180] In other embodiments, the floating-point multiplier 20 is not encapsulated in the computing chip 200, that is, the floating-point multiplier 20 is independent of the computing chip 200. The computing chip 200 can communicate with the floating-point multiplier 20, and the processor 10 in the computing chip 200 can call the floating-point multiplier 20 to perform floating-point multiplication operations.

[0181] Most existing AI chips only support floating-point multiplication operations of FP16 or BF16, lacking support for floating-point multiplication operations of low-precision floating-point types such as FP8 and FP4. In AI inference (especially large models), the main bottleneck is often not computing power itself, but storage bandwidth and energy consumption. The core significance of introducing floating-point multiplication operations of low-precision floating-point types such as FP8 and FP4 lies in its ability to significantly reduce storage and bandwidth requirements, improve the parallelism of matrix arrays, and significantly improve energy efficiency, thereby enabling large model inference to achieve higher throughput and lower power consumption with limited hardware resources. Among them, FP8 has become the industry mainstream, balancing accuracy and performance, while FP4 represents the direction of further compression and extreme energy efficiency. Therefore, AI chips require floating-point multiplication operations of various floating-point numbers. The floating-point multiplier 20 provided in this disclosure can support floating-point multiplication operations of various floating-point numbers. When the computing chip 200 is an AI chip, the floating-point multiplier 20 enables the AI ​​chip to support floating-point multiplication operations of various floating-point numbers. In particular, when supporting floating-point multiplication operations of low-precision floating-point numbers such as FP8 and FP4, it can improve the parallelism of the matrix array of the AI ​​chip and significantly improve the energy efficiency ratio.

[0182] Next, combined Figure 4 The internal structure of the floating-point multiplier 20 is described.

[0183] Figure 4 This is a schematic diagram illustrating the structure of a floating-point multiplier 20 according to an exemplary embodiment, such as... Figure 4 As shown, the floating-point multiplier 20 includes a preprocessing circuit 21 and a floating-point multiplication circuit 22, with the preprocessing circuit 21 connected to the floating-point multiplication circuit 22.

[0184] The preprocessing circuit 21 is used to acquire the first input data, the second input data, and the pattern identifier of the target multiplication mode.

[0185] The first input data and the second input data are the two input data involved in this floating-point multiplication operation. Both the first and second input data include at least one floating-point number. The floating-point number in the first input data is called the first floating-point number, and the floating-point number in the second input data is called the second floating-point number. That is, the first input data includes at least one first floating-point number, and the second input data includes at least one second floating-point number. The number of first floating-point numbers in the first input data is the same as the number of second floating-point numbers in the second input data. The first and second floating-point numbers are the multiplicand and multiplier in the floating-point multiplication operation, respectively. Both the first and second floating-point numbers are of the target floating-point number type.

[0186] Depending on the type of the target floating-point number, the number of floating-point numbers in the first and second input data will differ, such as... Figure 5 As shown, din_a and din_b are the first input data and the second input data, respectively. The bit width of din_a and din_b is 16 bits. If the target floating-point number type is FB16, din_a and din_b are both FB16. If the target floating-point number type is BF16, din_a and din_b are both BF16. If the target floating-point number type is FB8, din_a and din_b each include two FB8s. If the target floating-point number type is FB4, din_a and din_b each include four FB4s.

[0187] The target multiplication mode indicates that floating-point multiplication operations of the target floating-point type will be performed on the first input data and the second input data. The target multiplication mode is the multiplication mode corresponding to the target floating-point type among the multiple multiplication modes supported by the floating-point multiplier 20, as specifically described above. The mode identifier for any multiplication mode indicates that the multiplication mode is different for different multiplication modes, such as... Figure 5 As shown, din_mod is the mode identifier of the target multiplication mode. din_mod occupies 2 bits. When din_mod = 00, it represents multiplication mode 0. When din_mod = 01, it represents multiplication mode 1. When din_mod = 10, it represents multiplication mode 2. When din_mod = 11, it represents multiplication mode 3.

[0188] The preprocessing circuit 21 can acquire the first input data, the second input data, and the mode identifier of the target multiplication mode by receiving a floating-point multiplication operation instruction sent by the processor 10, and acquiring the first input data, the second input data, and the mode identifier of the target multiplication mode from the floating-point multiplication operation instruction. The floating-point multiplication operation instruction includes the first input data, the second input data, and the mode identifier of the target multiplication mode, so as to provide input data and specify the multiplication mode for the floating-point multiplier 20.

[0189] The preprocessing circuit 21 is also used to preprocess the first input data and the second input data based on the target multiplication mode to obtain at least one data group. Each data group includes a first floating-point number and a second floating-point number. Each data group is a set of floating-point numbers to be multiplied, so as to realize the grouping of floating-point numbers in the first input data and the second input data, and each data group is a set of floating-point numbers to be multiplied.

[0190] The grouping method can be as follows: if the target multiplication mode is multiplication mode 0 or 1, the floating-point numbers in the first input data and the second input data are divided into one data group; if the target multiplication mode is multiplication mode 2, the floating-point numbers in the first input data and the second input data are divided into two data groups; if the target multiplication mode is multiplication mode 3, the floating-point numbers in the first input data and the second input data are divided into four data groups.

[0191] Taking multiplication mode 0 as an example, Figure 2 As shown in Figure (a), the first input data and the second input data are input data 11 and 12, respectively, and the floating-point numbers 1 and 2 are divided into data group S1.

[0192] Taking the target multiplication mode as multiplication mode 1 as an example, such as Figure 2 As shown in Figure (b), the first input data and the second input data are input data 13 and 14, respectively, and the floating-point numbers 3 and 4 are assigned to data group S2.

[0193] Taking the target multiplication mode as multiplication mode 2 as an example, such as Figure 2 As shown in Figure (c), the first input data and the second input data are input data 15 and 16, respectively. The floating-point numbers 5 and 7 are assigned to data group S3, and the floating-point numbers 6 and 8 are assigned to data group S4, thus obtaining 2 data groups.

[0194] Taking the target multiplication mode as multiplication mode 3 as an example, such as Figure 2 As shown in Figure (b), the first input data and the second input data are input data 17 and 18, respectively. Floating-point numbers 9 and 13 are assigned to data group S5, floating-point numbers 10 and 14 are assigned to data group S6, floating-point numbers 11 and 15 are assigned to data group S7, and floating-point numbers 12 and 16 are assigned to data group S8, thus obtaining 4 data groups.

[0195] In some embodiments, the preprocessing circuit 21 does not group the first input data and the second input data. Instead, it determines the data group to which each floating-point number in the first input data belongs based on the target multiplication mode, thereby achieving logical grouping. For example, if the target multiplication mode is multiplication mode 0 or 1, it determines that the first input data and the second input data belong to the same data group. Or, if the target multiplication mode is multiplication mode 2 or 3, it determines the position of each first floating-point number in the first input data and the position of each second floating-point number in the second input data based on multiplication mode 2, thereby identifying each first floating-point number in the first input data and each second floating-point number in the second input data, and determining that the i-th first floating-point number in the first input data and the i-th second floating-point number in the second input data belong to data group i, where data group i is the i-th data group among at least one obtained data group. When the target multiplication mode is multiplication mode 2, 1 ≤ i ≤ 2; when the target multiplication mode is multiplication mode 3, 1 ≤ i ≤ 4. Figure 2 For example, assuming the target multiplication mode is multiplication mode 2, it is determined that the floating-point number 5 in input data 15 and the floating-point number 7 in input data 16 belong to data group S1.

[0196] The floating-point multiplication circuit 22 is used to perform floating-point multiplication on the first floating-point number and the second floating-point number in any data group based on the target multiplication mode, so as to obtain the product result between the first floating-point number and the second floating-point number in the data group.

[0197] The product of the first and second floating-point numbers in any data set can also be called the product result corresponding to that data set. Figure 2 For example, in multiplication mode 0, the floating-point multiplication circuit 22 performs floating-point multiplication on the floating-point numbers in data group S1, resulting in a product result of 1 for data group S1. In multiplication mode 1, the floating-point multiplication circuit 22 performs floating-point multiplication on the floating-point numbers in data group S2, resulting in a product result of 2 for data group S2. In multiplication mode 2, the floating-point multiplication circuit 22 performs floating-point multiplication on the floating-point numbers in data group S3, resulting in a product result of 3 for data group S3, and performs floating-point multiplication on the floating-point numbers in data group S4, resulting in a product result of 4 for data group S4. In multiplication mode 3, the floating-point multiplication circuit 22 performs floating-point multiplication on the floating-point numbers in data group S5 to obtain the product result 5 corresponding to data group S5, performs floating-point multiplication on the floating-point numbers in data group S6 to obtain the product result 6 corresponding to data group S6, performs floating-point multiplication on the floating-point numbers in data group S7 to obtain the product result 7 corresponding to data group S7, and performs floating-point multiplication on the floating-point numbers in data group S8 to obtain the product result S8 corresponding to data group S8.

[0198] In target multiplication mode, the product of all data groups is the result of the floating-point multiplication operation. After obtaining the product of all data groups, the floating-point multiplier 20 returns the product of each data group to the processor 10 to indicate that the floating-point multiplication instruction has been executed. The processor 10 receives the product of each data group.

[0199] The floating-point multiplier 20 can receive the multiplication mode corresponding to the input data to be calculated, and use the multiplication mode indication to perform floating-point multiplication operations of a specified floating-point type (such as the target floating-point type) on the input data. The specified floating-point type is the floating-point type of the floating-point numbers in the input data. By preprocessing the input data, the floating-point numbers in the input data are divided into data groups. Based on the target multiplication mode, floating-point multiplication operations of the floating-point type are performed on the floating-point data in the same data group. Thus, by specifying different multiplication modes for input data of different floating-point types, the floating-point multiplier 20 can perform floating-point multiplication operations of multiple floating-point types to meet the computational needs of floating-point multiplication operations of multiple floating-point types. Since the floating-point multiplication circuit 22 can perform floating-point multiplication operations of multiple floating-point types, the floating-point multiplication operations of multiple floating-point types can reuse the floating-point multiplication circuit 22. There is no need to set up a separate floating-point multiplication circuit 22 for each type of floating-point multiplication operation in the floating-point multiplier 20. Therefore, the area of ​​the floating-point multiplier 20 can be reduced, and the chip area occupied by the floating-point multiplier 20 in the computing chip can be reduced, thus meeting the design requirement of small area of ​​the floating-point multiplier 20.

[0200] In some embodiments, the preprocessing circuit 21 is further configured to extract key information from the first floating-point number and the second floating-point number in any data group, and obtain key information of the first floating-point number and the second floating-point number in the data group, wherein the key information includes the sign, exponent and mantissa.

[0201] Taking the extraction of key information from the first floating-point number as an example, the first input data is a binary sequence, which includes at least one binary sequence of the first floating-point number. For any first floating-point number, based on the sign bit, mantissa bit, and exponent bit defined by the floating-point number type corresponding to the target multiplication mode (i.e., the target floating-point number type), the sign, mantissa, and exponent of each first floating-point number are extracted from the binary sequence of the first floating-point number. The extraction method for the key information of the second floating-point number is similar to that of the first floating-point number, and will not be described in detail here.

[0202] The preprocessing circuit 21 is also used to send the key information of the first floating-point number in any data group to the floating-point multiplication circuit 22.

[0203] The floating-point multiplication circuit 22 is used to perform floating-point multiplication on the first and second floating-point numbers in any data group based on the target multiplication mode, the key information of the first floating-point number and the key information of the second floating-point number in the data group, to obtain the product result between the first and second floating-point numbers in the data group (i.e. the product result corresponding to the data group).

[0204] by Figure 5 Taking the floating-point multiplier 20 shown as an example, assuming the first input data is 16-bit din_a and the second input data is 16-bit din_b, din_a, din_mod, and din_mod (i.e., the mode identifier of the target multiplication mode) are input to the preprocessing circuit 21 in the floating-point multiplier 20. Based on din_mod, the preprocessing circuit 21 determines the position of each first floating-point number in din_a, and extracts the sign, exponent, and mantissa of each first floating-point number from din_a; based on din_mod, it determines the position of each second floating-point number in din_b, and extracts the sign, exponent, and mantissa of each first floating-point number from din_a. Extract the sign, exponent, and mantissa of each second floating-point number from each of the first floating-point numbers in `in_b`. Form a first sign sequence from the signs of all first floating-point numbers, a second sign sequence from the signs of all second floating-point numbers, a first mantissa sequence from the mantissas of all first floating-point numbers, a second mantissa sequence from the mantissas of all second floating-point numbers, a first exponent sequence from the exponents of all first floating-point numbers, and a second exponent sequence from the exponents of all second floating-point numbers. Send these sequences (first sign sequence, second sign sequence, first mantissa sequence, second mantissa sequence, first exponent sequence, and second exponent sequence) to the floating-point multiplication circuit 22. The floating-point multiplication circuit 22 receives these sequences and performs floating-point multiplication operations based on the target multiplication mode and these sequences.

[0205] Next, combined Figure 5 The internal structure of the floating-point multiplication circuit 22 and the principle of floating-point multiplication based on the target multiplication mode are introduced.

[0206] like Figure 5 As shown, the floating-point multiplication circuit 22 includes a sign operation sub-circuit 31, an exponent operation sub-circuit 32, and a mantissa operation sub-circuit 33.

[0207] The sign operation subcircuit 31 is used to obtain the sign of the product result for any data set based on the sign of the first floating-point number and the sign of the second floating-point number in the data set. For example, the sign operation subcircuit 31 is used to perform an XOR operation on the sign of the first floating-point number and the sign of the second floating-point number in any data set to obtain the sign of the product result between the first floating-point number and the second floating-point number in the data set.

[0208] byFigure 5 For example, the preprocessing circuit 21 sends a first symbol sequence and a second symbol sequence to the symbol operation sub-circuit 31 to send symbols to the symbol operation sub-circuit 31. The symbol operation sub-circuit 31 receives the first symbol sequence, the second symbol sequence, and din_mod. Based on the target multiplication mode indicated by din_mod, it identifies the symbols of the first floating-point number and the second floating-point number belonging to the same data group from the first symbol sequence and the second symbol sequence. For example, if the target multiplication mode is multiplication mode 0 or 1, the first symbol sequence and the second symbol sequence each include only the symbol of a floating-point number. The first symbol sequence and the second symbol sequence are then used as the symbols of the first floating-point number and the second floating-point number in the same data group, respectively. If the target multiplication mode is multiplication mode 2 or 3, the symbol of the i-th floating-point number in the first symbol sequence is used as the symbol of the first floating-point number in data group i, and the symbol of the i-th floating-point number in the second symbol sequence is used as the symbol of the second floating-point number in data group i, thereby obtaining the symbols of the first floating-point number and the second floating-point number in data group i. For any data set, the sign operation sub-circuit 31 performs an XOR operation on the sign of the first floating-point number and the sign of the second floating-point number in the data set to obtain the sign of the product result corresponding to the data set. For example, if the data set S1 includes floating-point numbers 1 and 2, an XOR operation is performed on the sign of floating-point number 1 and floating-point number 2 to obtain the sign of the product result between floating-point numbers 1 and 2.

[0209] The exponentiation subcircuit 32 is used to obtain the exponent of the product between the first floating-point number and the second floating-point number in the data group for any data group, based on the target multiplication mode, the exponent of the first floating-point number in the data group, and the exponent of the second floating-point number in the data group.

[0210] Optionally, the exponent of the product result calculated by the exponentiation subcircuit 32 is the preliminary exponent of the product result. The exponentiation subcircuit 32 is used, for any data set, to perform a summation operation on the target offset, the exponent of the first floating-point number in the data set, and the exponent of the second floating-point number in the data set, based on the target multiplication mode, the exponent of the first floating-point number in the data set, and the exponent of the second floating-point number in the data set, to obtain the exponent of the product result of the first floating-point number and the second floating-point number in the data set (i.e., the preliminary exponent). That is, the preliminary exponent = the exponent of the first floating-point number in the data set + the exponent of the second floating-point number in the data set + the target offset.

[0211] The target offset is the negative of the offset used when storing the floating-point number of the target floating-point type indicated by the target multiplication mode. Each multiplication mode corresponds to an offset, which is the negative of the offset used when storing the floating-point number of the floating-point type corresponding to that multiplication mode. Different multiplication modes correspond to different target offsets. For example, the offset for multiplication mode 0 is 97, the offset for multiplication mode 1 is -127, the offset for multiplication mode 2 is 1, and the offset for multiplication mode 3 is 1. The target offset is also the offset corresponding to the target multiplication mode.

[0212] by Figure 5 For example, the preprocessing circuit 21 sends a first exponent sequence and a second exponent sequence to the exponent operation sub-circuit 32 to send the exponent. The exponent operation sub-circuit 32 receives the first exponent sequence, the second exponent sequence, and din_mod. Based on the target multiplication pattern indicated by din_mod, it identifies the exponents of the first floating-point number and the second floating-point number belonging to the same data group from the first exponent sequence and the second exponent sequence. The identification method can refer to the method of identifying the sign of the first floating-point number and the sign of the second floating-point number belonging to the same data group from the first sign sequence and the second sign sequence based on the multiplication pattern indicated by din_mod, which will not be elaborated here. The exponent operation sub-circuit 32 obtains the offset (i.e., the target offset) corresponding to the target multiplication pattern indicated by din_mod. For any data group, it performs a summation operation on the offset, the exponent of the first floating-point number in the data group, and the exponent of the second floating-point number in the data group to obtain the preliminary exponent of the product result corresponding to the data group. For example, suppose the target multiplication mode indicated by din_mod is multiplication mode 0, the corresponding offset is 97, the data group includes floating-point numbers 1 and 2, and the initial exponent of the product result corresponding to this data group is the exponent of floating-point number 1 + the exponent of floating-point number 2 + 97.

[0213] The mantissa operation subcircuit 33 is used to obtain the mantissa of the product between the first floating-point number and the second floating-point number in any data set, based on the target multiplication mode, the mantissa of the first floating-point number in the data set, and the mantissa of the second floating-point number in the data set. The sign, exponent, and mantissa of the same product result calculated by the sign operation subcircuit 31, the exponent operation subcircuit 32, and the mantissa operation subcircuit 33 are used to represent the product result.

[0214] Optionally, the mantissa of the product result calculated by the mantissa operation subcircuit 33 is the preliminary mantissa of the product result. The mantissa operation subcircuit 33 is used to perform a multiplication operation on the mantissa of the first floating-point number and the mantissa of the second floating-point number in any data group, based on the target multiplication mode, to obtain the mantissa of the product result between the first floating-point number and the second floating-point number in the data group (i.e., the preliminary mantissa of the product result). That is, the preliminary mantissa = the mantissa of the first floating-point number in the data group * the mantissa of the second floating-point number in the data group.

[0215] For example, Figure 6 This is a schematic diagram of the structure of a mantissa operation sub-circuit 33 provided in an embodiment of the present disclosure, as shown below. Figure 6 As shown, the mantissa operation sub-circuit 33 includes an input interface 41, a multiplier array 42, a shift unit 43, and an adder unit 44, wherein the input interface 41, the multiplier array 42, the shift unit 43, and the adder unit 44 are connected in sequence. That is, the input interface 41 is connected to the multiplier array 42, and the shift unit 43 is connected to both the multiplier array 42 and the adder unit 44.

[0216] Input interface 41 is used to receive a first binary sequence and a second binary sequence, the first binary sequence including a binary sequence of the mantissa of at least one first symbol, and the second binary sequence including a binary sequence of the mantissa of at least one second symbol. Figure 5 For example, the preprocessing circuit 21 sends data to the input interface 41 (not in...). Figure 5 (As shown in the diagram) A first mantissa sequence and a second mantissa sequence are sent to transmit the mantissa. The first mantissa sequence is a first binary sequence, and the second mantissa sequence is a second binary sequence. Input interface 41 receives the first binary sequence and the second binary sequence, and sends the first binary sequence and the second binary sequence to the multiplication array.

[0217] Multiplier array 42 is used to perform multiplication operations on the binary sequence of the mantissa of the first symbol and the binary sequence of the mantissa of the second symbol in the same data group based on the target multiplication pattern, so as to obtain the mantissa of the product result between the first floating-point number and the second floating-point number in the same data group.

[0218] The multiplier array 42 includes multiple multiplier subarrays. For example... Figures 7 to 9 As shown, the multiplier array 42 includes four multiplier subarrays, Mul_sub0 to Mul_sub3. Each multiplier subarray includes multiple multipliers, and the number of multipliers in different multiplier subarrays is the same. For example, each multiplier subarray includes 6*6 multipliers, and each multiplier is used to perform 1-bit*1-bit multiplication operations. Each multiplier subarray is connected to the input interface 41 and the shift unit 23.

[0219] Taking din_mod = 11 and the target multiplication mode as multiplication mode 3 as an example, assume the first input data and the second input data are respectively Figure 2 The input data 17 and 18 are shown. In input data 17, the binary sequences of the mantissas of floating-point numbers 9 to 12 are M_9, M_10, M_11, and M_12, ​​respectively. In input data 18, the binary sequences of the mantissas of floating-point numbers 13 to 16 are M_13, M_14, M_15, and M_16, respectively. Each of M_9 to M16 has a bit width of 2 bits, where the highest bit is the hidden integer bit used to store the mantissa, and the remaining bit is the extracted mantissa. Figure 7 As shown, Man_a and Man_b are the first and second binary sequences, respectively. Man_a1 includes M_9, M_10, M_11, and M_12, ​​while Man_b includes M_13, M_14, M_15, and M_16. Mul_sub0 to Mul_sub3 in the multiplier array 42 all receive din_mod. In multiplication mode 3 indicated by din_mod, Mul_sub0 obtains M_11 from Man_a and M_15 from Man_b, performs multiplication on M_11 and M_15, and obtains the mantissa of the multiplication result corresponding to data group S7. For example, using the 2*2 multipliers in Mul_sub0, a 2-bit*2-bit multiplication operation is performed on M_11 and M_15, with each multiplier multiplying 1 bit from M_11 and 1 bit from M_15. In multiplication mode 3 as indicated by din_mod, Mul_sub1 retrieves M_9 from Man_a1 and M_13 from Man_b, performs multiplication on M_9 and M_13, and obtains the mantissa of the multiplication result corresponding to data set S5. This process is the same as the way Mul_sub0 performs multiplication on M_11 and M_15. In multiplication mode 3 as indicated by din_mod, Mul_sub2 retrieves M_10 from Man_a1 and M_14 from Man_b, performs multiplication on M_10 and M_14, and obtains the mantissa of the multiplication result corresponding to data set S6. This process is the same as the way Mul_sub0 performs multiplication on M_11 and M_15. In multiplication mode 3 indicated by din_mod, Mul_sub3 obtains M_12 from Man_a1 and M_16 from Man_b, performs multiplication on M_12 and M_16, and obtains the mantissa of the multiplication result corresponding to data group S8. This process is the same as the way Mul_sub0 performs multiplication on M_11 and M_15. Thus, multiplier array 42 calculates the mantissa of the product result corresponding to each data group from S5 to S8 in multiplication mode 3, and outputs the mantissa (i.e., the preliminary mantissa) of the product result corresponding to each data group.

[0220] Taking din_mod = 10 and the target multiplication mode as multiplication mode 2 as an example, let's assume the first input data and the second input data are respectively... Figure 2 The input data shown are 15 and 16. In input data 15, the binary sequences of the mantissas of floating-point numbers 5 and 6 are M_5 and M_6, respectively; in input data 16, the binary sequences of the mantissas of floating-point numbers 7 and 8 are M_7 and M_8, respectively. The bit width of M_5 to M_8 is 4 bits, where the highest bit is the hidden integer bit used to store the mantissa, and the remaining 3 bits are the extracted mantissa. Figure 8 As shown, Man_a and Man_b are the first and second binary sequences, respectively. Man_a1 includes M_5 and M_6, and Man_b includes M_7 and M_8. Mul_sub0 to Mul_sub3 in the multiplier array 42 all receive din_mod. In multiplication mode 2 indicated by din_mod, Mul_sub2 and Mul_sub3 are not working, while Mul_sub0 to Mul_sub1 are working. In multiplication mode 2 indicated by din_mod, Mul_sub0 obtains M_6 from Man_a and M_8 from Man_b, performs multiplication on M_6 and M_8, and obtains the mantissa of the multiplication result corresponding to data group S4. For example, using the 4*4 multiplier in Mul_sub0, a 4-bit*4-bit multiplication operation is performed on M_11 and M_15, with each multiplier used to multiply 1 bit from M_6 and 1 bit from M_8. In multiplication mode 2 indicated by din_mod, Mul_sub1 retrieves M_5 from Man_a1 and M_7 from Man_b, performs multiplication on M_5 and M_7, and obtains the mantissa of the multiplication result corresponding to data group S3. This process is the same as the way Mul_sub0 performs multiplication on M_6 and M_8. Thus, multiplier array 42 calculates the mantissa of the product result corresponding to each data group in data groups S3 and S4 in multiplication mode 2, and outputs the mantissa (i.e., the preliminary mantissa) of the product result corresponding to each data group.

[0221] Multiplication of large-bit-width binary sequences can be broken down into multiplication of multiple small-bit-width binary sequences and addition of the results of multiplication of multiple small-bit-width binary sequences. Taking the 12-bit mantissa Man_a * 12-bit mantissa Man_b = mantissa Man_c as an example, the mantissa Man_a consists of two parts, a1 and a0, where a1 and a0 are the high 6 bits and low 6 bits of mantissa Man_a, respectively. The mantissa Man_b consists of two parts, b1 and b0, where b1 and b0 are the high 6 bits and low 6 bits of mantissa Man_b, respectively.

[0222] Let Man_a=a1*26 +a0, Man_b=b1*2 6 If +b0, then c can be expressed by the following formula (2).

[0223] Man_c = Man_a * Man_b = (a1 * 2) 6 +a0)*(b1*2 6 +b0)

[0224] =a1*b1*2 12 +a1*b0*2 6 +a0*b1*2 6 +a0*b0 (2)

[0225] Based on this, when the target multiplication mode is multiplication mode 0 or 1, the first binary sequence is the mantissa of a first floating-point number. The first binary sequence has a bit width of 12 bits. When the target multiplication mode is multiplication mode 0, the high 2 bits of the first binary sequence are 0, and the low 8 bits are the actual mantissa of the first floating-point number. When the target multiplication mode is multiplication mode 1, the high 1 bit of the first binary sequence is 0, and the low 11 bits are the actual mantissa of the first floating-point number. The second binary sequence is the mantissa of a second floating-point number. The second binary sequence has a bit width of 12 bits. When the target multiplication mode is multiplication mode 0, the high 2 bits of the second binary sequence are 0, and the low 8 bits are the actual mantissa of the second floating-point number. When the target multiplication mode is multiplication mode 1, the high 1 bit of the second binary sequence is 0, and the low 11 bits are the actual mantissa of the second floating-point number.

[0226] The first binary sequence consists of two parts, each with a bit width of 6 bits. The second binary sequence also consists of two parts, each with a bit width of 6 bits.

[0227] Optionally, the multiplier array 42 is further configured to perform multiplication operations on each part of the first binary sequence and each part of the second binary sequence respectively when the target multiplication mode is multiplication mode 0 or 1, to obtain multiple intermediate multiplication results, and send the multiple intermediate multiplication results to the shift unit 43. Each intermediate multiplication result is the product of a part of the first binary sequence and a part of the second binary sequence.

[0228] The shift unit 43 is used to perform a shift operation on at least one of the multiple intermediate multiplication results to obtain at least one shifted intermediate multiplication result, and send the unshifted intermediate multiplication result and the shifted intermediate multiplication results to the addition unit 44.

[0229] The addition unit 44 is used to perform addition operations on the unshifted intermediate multiplication results and the shifted intermediate multiplication results to obtain the mantissa of the multiplication result between the first floating-point number and the second floating-point number.

[0230] Taking din_mod = 00 and the target multiplication mode as multiplication mode 0 as an example, assume the first input data and the second input data are respectively Figure 2 The input data shown are 11 and 12. In input data 11, the binary sequence of the mantissa of the floating-point number 1 is Man_a, and in input data 12, the binary sequences of the mantissa of the floating-point number 2 are Man_b. The bit width of each of Man_a to Man_b is 12 bits, where the highest bit is 0, the second highest bit is the integer part hidden when storing the mantissa, and the remaining 10 bits are the extracted mantissa. Figure 9As shown, Man_a and Man_b are the first and second binary sequences, respectively, where Man_a includes a1 and a0, and Man_b includes b1 and b0. Mul_sub0 to Mul_sub3 in multiplier array 42 all receive din_mod. In multiplication mode 0 indicated by din_mod, Mul_sub0 obtains a0 from Man_a and b0 from Man_b, performs multiplication on a0 and b0, and obtains the intermediate product result pp0, i.e., pp0 = a0 * b0. For example, using the 6*6 multipliers in Mul_sub0, a 6-bit * 6-bit multiplication operation is performed on a0 and b0, with each multiplier multiplying 1 bit from a0 and 1 bit from b0. In multiplication mode 0 as indicated by din_mod, Mul_sub1 retrieves a1 from Man_a1 and b0 from Man_b, performs multiplication on a1 and b0, and obtains the intermediate product result pp1, i.e., pp1 = a1 * b0. This process is the same as the way Mul_sub0 performs multiplication on a0 and b0. Similarly, in multiplication mode 0 as indicated by din_mod, Mul_sub2 retrieves a1 from Man_a1 and b1 from Man_b, performs multiplication on a1 and b1, and obtains the intermediate product result pp3, i.e., pp3 = a1 * b1. This process is the same as the way Mul_sub0 performs multiplication on a0 and b0. In multiplication mode 0 indicated by din_mod, Mul_sub3 obtains a0 from Man_a1 and b1 from Man_b, performs multiplication on a0 and b1, and obtains the intermediate product result pp2, i.e., pp2 = a0 * b1. This process is the same as the way Mul_sub0 performs multiplication on a0 and b0. Thus, multiplier array 42 calculates four intermediate product results in multiplication mode 0, namely pp0 to pp3. Each sub-multiplier array in Mul_sub0 to Mul_sub3 sends its calculated intermediate product result to shift unit 43, so shift unit 43 can receive the intermediate product results pp0 to pp3.

[0231] From the above formula (2), we can see that a1*b1*2 12 The exponent of 2 (i.e., 12) is used to obtain a1*b1*2. 12 The number of bits that pp3 needs to be shifted left by is a1*b0*2. 6 The exponent of 2 (i.e., 6) is used to obtain a1*b0*2. 6 The number of bits that pp1 needs to be shifted left by. a0*b1*2 6 The exponent of 2 (i.e., 6) is used to obtain a0*b1*2. 6 The number of bits that pp2 needs to be shifted left. a0*b0*20 The exponent of 2 (i.e. 0) is to obtain a0*b1, the number of bits that pp0 needs to be shifted left, that is, pp0 does not need to be shifted left.

[0232] Based on this, such as Figure 10 As shown, shift unit 43 shifts pp1 and pp2 left by 6 bits respectively to obtain the shifted pp1 and pp2, and shifts pp3 left by 12 bits to obtain the shifted pp3. It then sends the unshifted pp0 and the shifted pp1 to pp3 to the addition unit 44. The addition unit 44 performs addition on the unshifted pp0 and the shifted pp1 to pp3 to obtain the mantissa of the multiplication result between the first floating-point number 1 and the second floating-point number 2, and outputs the mantissa of this multiplication result (i.e., the preliminary mantissa).

[0233] When the target multiplication mode is multiplication mode 1, the working principle of the mantissa operation sub-circuit 33 is similar to that of the mantissa operation sub-circuit 33 in multiplication mode 1. The difference is that in multiplication mode 0, the bit width of the first binary sequence and the second binary sequence is 8 bits, the highest bit is the integer bit hidden when storing the mantissa, and the remaining 7 bits are the extracted mantissa. The bit width of the mantissa of the multiplication result calculated by the addition unit 44 can be 22 bits. In multiplication mode 1, the bit width of the mantissa of the multiplication result calculated by the addition unit 44 can be 16 bits, which will not be elaborated here.

[0234] In some embodiments, the addition unit 44 includes a carry-save adder (CSA) and a carry-lookahead adder (CLA). The CSA can be integrated into the multiplier array 42 or located outside the multiplier array 42. Figure 5 This is illustrated using the example of CSA integrated in multiplier array 42. Figure 10 As shown, the CSA is a 4-input, 2-output CSA. The CSA performs carry-preserving addition on the inputs pp0 to pp3, obtaining the sum sequence and carry sequence corresponding to data group S1. The sum sequence includes the sum of each bit except for the carry when performing addition on the intermediate product results pp0 to pp3, and the carry sequence includes the carry of each bit when performing addition on the intermediate product results pp0 to pp3. For example... Figure 5As shown, the floating-point multiplication circuit 22 also includes a storage sub-circuit 34, which provides data storage functionality. The storage sub-circuit 34 can be a register or other type of device with data storage capabilities. The storage sub-circuit 34 is connected to the mantissa operation sub-circuit 33. For example, the storage sub-circuit 34 is connected to the adder unit 44 (such as CSA and CLA) in the mantissa operation sub-circuit 33, where CSA is integrated into the multiplier array and not in the multiplier array. Figure 5 As shown, the CSA stores the sum and carry sequences in the storage sub-circuit 34. The storage sub-circuit 34 sends the sum and carry sequences to the CLA according to the system clock cycle. The CLA receives the sum and carry sequences and performs a carry-lookahead addition operation on them to obtain the preliminary mantissa of the multiplication result corresponding to data group S1. Through the calculation of the preliminary mantissa of the multiplication result by the CSA and CLA, the CSA can concurrently sum multiple bits, thereby improving the calculation efficiency of the preliminary mantissa.

[0235] In some embodiments, the addition unit 44 may also be a regular adder. Here, the type of the addition unit 44 is not limited in the embodiments of this disclosure.

[0236] As can be seen from the above introduction, the multiplier array 42 can provide mantissa multiplication operations for various multiplication modes. That is, the multiplier array 42 can be reused for various multiplication modes, eliminating the need for a separate multiplier array for each multiplication mode, thereby reducing the area of ​​the floating-point multiplier 20. It should be understood that when the floating-point multiplier 20 supports multiplication mode 0 and / or multiplication mode 1, the mantissa operation subcircuit 33 includes a shift unit 43 and an adder unit 44. When the floating-point multiplier 20 does not support multiplication mode 0 and multiplication mode 1, the mantissa operation subcircuit 33 may not include the shift unit 43 and the adder unit 44.

[0237] In some embodiments, such as when the exponentiation subcircuit 32 calculates the preliminary exponent and the mantissa subcircuit 33 calculates the preliminary exponent, ... Figure 5 As shown, the floating-point multiplication circuit 22 also includes a leading zero detection sub-circuit 35, an exponent adjustment sub-circuit 36, and a mantissa adjustment sub-circuit 37. The leading zero detection sub-circuit 35 is connected to the mantissa operation sub-circuit 33, the exponent adjustment sub-circuit 36, and the mantissa adjustment sub-circuit 37, as shown. Figure 5 As shown, the leading zero detection sub-circuit 35 is connected to the CAL in the mantissa operation sub-circuit 33.

[0238] The leading zero detection subcircuit 35 is used to detect leading zeros in the binary sequence of the mantissa of any product result, and obtain the number of leading zeros in the mantissa of the product result. A leading zero refers to all zeros starting from the most significant bit of the binary sequence of the mantissa and preceding the first 1 in the binary sequence. For example, if the binary sequence of a mantissa is 000011111, the first four 0s in this binary sequence are leading zeros, and the number of leading zeros in this binary sequence is 4. Optionally, the leading zero detection subcircuit 35 is used to detect leading zeros in the binary sequence of the mantissa of the same product result based on a target multiplication pattern.

[0239] by Figure 11 For example, the leading zero detection subcircuit 35 includes detection units corresponding to each multiplication mode. Multiplication modes 0 and 1 correspond to detection unit 501, multiplication mode 2 corresponds to detection units 502 and 503, and multiplication mode 3 corresponds to detection units 504 to 507. The leading zero detection subcircuit 35 also includes a control unit 500, which is connected to the detection units corresponding to each multiplication mode. After obtaining the mantissa (i.e., the preliminary mantissa) of the multiplication result corresponding to each data group, the mantissa subcircuit forms a preliminary mantissa sequence and sends it to the leading zero detection subcircuit 35. The preliminary mantissa of the multiplication result is represented by a binary sequence; therefore, the preliminary mantissa sequence is a binary sequence, which includes four subsequences: Izd_in0 to Izd_in3. When the target multiplication mode is multiplication mode 0 or 1, the initial mantissa sequence represents the mantissa of the product result corresponding to the data group S1 or 2 to be calculated; when the target multiplication mode is multiplication mode 2, the binary sequence composed of subsequences Izd_in0 and Izd_in1 represents the mantissa of the product result corresponding to the data group S3, and the binary sequence composed of subsequences Izd_in2 and Izd_in3 represents the mantissa of the product result corresponding to the data group S4; when the target multiplication mode is multiplication mode 3, the subsequences Izd_in0, Izd_in1, Izd_in2, and Izd_in3 represent the mantissas of the product results corresponding to the data groups S5, S6, S7, and S8, respectively.

[0240] The control unit 500 is used to receive the mode identifier of the target multiplication mode and the preliminary mantissa sequence, enable the leading zero detection function of each detection unit corresponding to the target multiplication mode, and store the received preliminary mantissa sequence.

[0241] Each detection unit is used to perform leading zero detection on the binary sequence of the mantissa representing the same product result in the preliminary mantissa sequence when the leading zero detection function is enabled, to obtain the number of leading zeros of the mantissa of the product result, and to send the number of leading zeros to the exponent adjustment circuit and the mantissa adjustment circuit.

[0242] Taking the target multiplication mode as multiplication mode 0 or 1 as an example, the control unit 500 enables the leading zero detection function of the detection unit 501 corresponding to multiplication mode 0 or 1. After the leading zero detection function is enabled, the detection unit 501 performs leading zero detection on the preliminary mantissa sequence to obtain the number of leading zeros zer0_num_6 of the mantissa of the product result corresponding to data group S1 or 2, and sends zer0_num_6 to the exponent adjustment sub-circuit 36 ​​and the mantissa adjustment sub-circuit 37.

[0243] Taking multiplication mode 2 as an example, the control unit 500 activates the leading zero detection function of the detection units 502 and 503 corresponding to multiplication mode 2. After the leading zero detection function is activated, the detection unit 502 performs leading zero detection on the binary sequence composed of Izd_in2 and Izd_in3 in the preliminary mantissa sequence, and obtains the number of leading zeros zer0_num_5 in the mantissa of the product result corresponding to data group S2. zer0_num_5 is then sent to the exponent adjustment sub-circuit 36 ​​and the mantissa adjustment sub-circuit 37. The detection unit 502 also performs leading zero detection on the binary sequence composed of Izd_in0 and Izd_in1 in the preliminary mantissa sequence, and obtains the number of leading zeros zer0_num_4 in the mantissa of the product result corresponding to data group S3. zer0_num_4 is then sent to the exponent adjustment sub-circuit 36 ​​and the mantissa adjustment sub-circuit 37.

[0244] Taking multiplication mode 3 as an example, the control unit 500 activates the leading zero detection function of the detection units 804 to 807 corresponding to multiplication mode 3. After the leading zero detection function is activated, the detection unit 504 performs leading zero detection on Izd_in3 in the preliminary mantissa sequence to obtain the number of leading zeros zer0_num_3 in the mantissa of the product result corresponding to data group S5, and sends zer0_num_3 to the exponent adjustment sub-circuit 36 ​​and the mantissa adjustment sub-circuit 37. The detection unit 505 performs leading zero detection on Izd_in2 in the preliminary mantissa sequence to obtain the number of leading zeros zer0_num_2 in the mantissa of the product result corresponding to data group S6, and sends zer0_num_2 to the exponent adjustment sub-circuit 36 ​​and the mantissa adjustment sub-circuit 37. Detection unit 506 performs leading zero detection on Izd_in1 in the preliminary mantissa sequence, obtaining the number of leading zeros zer0_num_1 in the mantissa of the product result corresponding to data group S7, and sends zer0_num_1 to the exponent adjustment sub-circuit 36 ​​and the mantissa adjustment sub-circuit 37. Detection unit 507 performs leading zero detection on Izd_in0 in the preliminary mantissa sequence, obtaining the number of leading zeros zer0_num_0 in the mantissa of the product result corresponding to data group S8, and sends zer0_num_0 to the exponent adjustment sub-circuit 36 ​​and the mantissa adjustment sub-circuit 37.

[0245] likeFigure 5 As shown, the mantissa operation subcircuit 33 and the storage subcircuit 34 are connected. The mantissa operation subcircuit 33 is used to store the preliminary mantissa of the product result corresponding to each data group into the storage subcircuit 34. The storage subcircuit 34 is also used to send the preliminary mantissa of the product result corresponding to each data group to the exponent adjustment subcircuit 36. For example, the mantissa operation subcircuit 33 forms a preliminary mantissa sequence from the preliminary mantissas of the product result corresponding to each data group, stores the preliminary mantissa sequence into the storage subcircuit 34, and the storage subcircuit 34 sends the preliminary mantissa sequence to the exponent adjustment subcircuit 36. Optionally, the storage subcircuit 34 sends the preliminary mantissa of the product result corresponding to each data group to the exponent adjustment subcircuit 36 ​​according to the system clock cycle.

[0246] The mantissa adjustment sub-circuit 37 is used to receive the mantissa (i.e., the preliminary exponent exp_tmp) of the product result corresponding to each data group and the number of leading zeros of the mantissa (i.e., the preliminary mantissa) of the product result corresponding to each data group.

[0247] The mantissa adjustment subcircuit 37 is further configured to, for any product result, adjust the mantissa of the product result based on the number of leading zeros in the mantissa, to obtain the adjusted mantissa, which is the normalized mantissa of the product result. Optionally, the mantissa adjustment subcircuit 37 is configured to shift the binary sequence of the mantissa of the product result to the left by leading zeros to obtain the adjusted mantissa, so that the adjusted mantissa is greater than or equal to 1 or less than 2, making the adjusted mantissa a normalized mantissa.

[0248] by Figure 5For example, the mantissa operation subcircuit 33 forms a preliminary mantissa sequence from the preliminary mantissas of the product results corresponding to each data group, and stores the preliminary mantissa sequence in the storage subcircuit 34. The storage subcircuit 34 sends the preliminary mantissa sequence to the mantissa adjustment subcircuit 37. The mantissa adjustment subcircuit 37 receives the mode identifier (din_mod) of the target multiplication mode and the preliminary mantissa sequence, and identifies the preliminary mantissas of each product result in the preliminary mantissa sequence based on the target multiplication mode. For example, if the target multiplication mode is multiplication mode 0 or 1, the data represented by the preliminary mantissa sequence is used as the preliminary mantissa of the product result corresponding to data group S1 or S2, and the preliminary mantissa sequence is shifted to the left by zer0_num_6 bits to obtain the adjusted mantissa of the product result corresponding to data group S1 or S2. If the target multiplication mode is multiplication mode 2, the initial mantissa sequence is divided into two subsequences. These two subsequences are used as the initial mantissas of the product results corresponding to data sets S3 and S4, respectively. These two subsequences are then shifted left by zer0_num_5 and zer0_num_4 positions, respectively, to obtain the adjusted mantissas of the product results corresponding to data sets S3 and S4. If the target multiplication mode is multiplication mode 3, the initial exponent sequence is divided into four subsequences. These four subsequences are used as the initial mantissas of the product results corresponding to data sets S5, S6, S7, and S8, respectively. These four subsequences are then shifted left by zer0_num_3, zer0_num_2, zer0_num_1, and zer0_num_0 positions, respectively, to obtain the adjusted mantissas of the product results corresponding to data sets S5-S8.

[0249] like Figure 5 As shown, the exponentiation sub-circuit 32 is connected to the storage sub-circuit 34. The exponentiation sub-circuit 32 is used to store the preliminary exponent exp_tmp of the product result corresponding to each data group into the storage sub-circuit 34. The storage sub-circuit 34 sends the preliminary exponent exp_tmp of the product result corresponding to each data group to the mantissa adjustment sub-circuit 37 according to the system clock cycle.

[0250] The exponent adjustment sub-circuit 36 ​​is used to receive the exponent (i.e., the preliminary exponent exp_tmp) of the product result corresponding to each data group and the number of leading zeros of the mantissa (i.e., the preliminary mantissa) of the product result corresponding to each data group.

[0251] The exponent adjustment sub-circuit 36 ​​is also used to adjust the exponent (i.e., the preliminary exponent) of any product result based on the number of leading zeros in the mantissa (i.e., the preliminary mantissa) of the product result, to obtain the adjusted exponent of the product result. The sign of the product result, the adjusted exponent of the product result, and the mantissa are used to represent the product result.

[0252] Optionally, the exponent adjustment sub-circuit 36 ​​is used to subtract the exponent of the multiplication result from the number of leading zeros to obtain the adjusted exponent of the product result. That is, the adjusted exponent of the product result = the exponent of the multiplication result - the number of leading zeros.

[0253] by Figure 5 For example, the exponentiation subcircuit 32 assembles the preliminary exponents of the product results corresponding to each data group into a preliminary exponent sequence, stores the preliminary exponent sequence in the storage subcircuit 34, and sends the preliminary exponent sequence to the exponentiation subcircuit 32. The exponentiation subcircuit 32 receives the mode identifier (din_mod) of the target multiplication mode and the preliminary exponent sequence. Based on the target multiplication mode, the exponentiation subcircuit 32 identifies the preliminary exponents of each product result in the preliminary exponent sequence. For example, if the target multiplication mode is multiplication mode 0 or 1, the data represented by the preliminary exponent sequence is used as the preliminary exponent of the product result corresponding to data group S1 or S2. The number of leading zeros zer0_num_6 is subtracted from the preliminary exponent to obtain the adjusted exponent of the product result corresponding to data group S1 or S2. If the target multiplication mode is multiplication mode 2, the initial exponent sequence is divided into two subsequences. These two subsequences are used as the initial exponents of the product results corresponding to data sets S3 and S4, respectively. The number of leading zeros zer0_num_5 is subtracted from the initial exponent of the product result corresponding to data set S3 to obtain the adjusted exponent. The number of leading zeros zer0_num_4 is subtracted from the initial exponent of the product result corresponding to data set S4 to obtain the adjusted exponent. If the target multiplication mode is multiplication mode 3, the initial exponent sequence is divided into 4 subsequences. These 4 subsequences are used as the initial exponents of the product results corresponding to data groups S5, S6, S7, and S8, respectively. The number of leading zeros zer0_num_3 is subtracted from the initial exponent of the product result corresponding to data group S5 to obtain the adjusted exponent. The number of leading zeros zer0_num_2 is subtracted from the initial exponent of the product result corresponding to data group S6 to obtain the adjusted exponent. The number of leading zeros zer0_num_1 is subtracted from the initial exponent of the product result corresponding to data group S7 to obtain the adjusted exponent. The number of leading zeros zer0_num_0 is subtracted from the initial exponent of the product result corresponding to data group S8 to obtain the adjusted exponent.

[0254] In summary, when the target multiplication mode is multiplication mode 0, the floating-point multiplier 20 processes the first and second input data to obtain the sign, exponent, and mantissa of the product result corresponding to the data group S1, thereby completing a floating-point multiplication operation on a group of FP16*FP16.

[0255] When the target multiplication mode is multiplication mode 1, the floating-point multiplier 20 processes the first input data and the second input data to obtain the sign, exponent and mantissa of the product result corresponding to the data group S2, thereby completing the floating-point multiplication operation of a group of BF16*BF16.

[0256] When the target multiplication mode is multiplication mode 2, the floating-point multiplier 20 processes the first input data and the second input data to obtain the sign, exponent and mantissa of the product result corresponding to the data groups S3 and S4, thereby completing the floating-point multiplication operation on the two groups BF8*BF8.

[0257] When the target multiplication mode is multiplication mode 4, the floating-point multiplier 20 processes the first input data and the second input data to obtain the sign, exponent and mantissa of the product results corresponding to the data groups S5 to S8, thereby completing the floating-point multiplication operation on the four groups BF4*BF4.

[0258] like Figure 5 As shown, the floating-point multiplier 20 also includes an output circuit 23. The output circuit 23 is connected to the storage sub-circuit 34, the exponent adjustment sub-circuit 36, and the mantissa adjustment sub-circuit 37. The sign operation sub-circuit 31 is connected to the storage sub-circuit 34. The sign operation sub-circuit 31 is also used to store the sign of the product result corresponding to each data group in the storage sub-circuit 34. The storage sub-circuit 34 sends the product result corresponding to each data group to the output circuit 23, for example, based on the system clock cycle, sending the sign of the product result corresponding to each data group to the output circuit 23.

[0259] The output circuit 23 is used to receive the sign of the product result corresponding to each data group from the storage sub-circuit 34, the adjusted exponent of the product result corresponding to each data group from the exponent adjustment sub-circuit 36, and the adjusted mantissa of the product result corresponding to each data group from the mantissa adjustment sub-circuit 37. The output circuit 23 stores the sign, the adjusted exponent and the adjusted mantissa of the product result corresponding to each data group to realize the storage of the product result corresponding to each data group.

[0260] by Figure 5For example, the sign operation subcircuit 31 forms a third sign sequence (e.g., dout_sign) from the signs of the product results corresponding to each data group, stores the third sign sequence in the storage subcircuit 34, and sends the third sign sequence to the output circuit 23. The exponent adjustment subcircuit 36 ​​forms a third exponent sequence from the adjusted exponents of the product results corresponding to each data group and sends the third exponent sequence to the output circuit 23. The mantissa adjustment subcircuit 37 forms a third mantissa sequence from the adjusted mantissas of the product results corresponding to each data group and sends the third mantissa sequence to the output circuit 23. The output circuit 23 receives the third sign sequence, the third exponent sequence, the third mantissa sequence, and din_mod. Based on the target multiplication mode indicated by din_mod, it identifies the sign of the product results corresponding to each data group from the third sign sequence, the exponent of the product results corresponding to each data group from the third exponent sequence, and the mantissa of the product results corresponding to each data group from the third mantissa sequence. The identification method can be referred to as identifying the preliminary mantissa of the product results corresponding to each data group from the preliminary mantissa sequence, which will not be elaborated here. Output circuit 23 stores the sign, exponent, and mantissa of the product result corresponding to each data group, thereby storing the product result corresponding to each data group. For example, for any data group, output circuit 23 combines the sign, mantissa, and exponent of the product result corresponding to the data group into a binary sequence, which is used to represent the product result. Output circuit 23 stores this binary sequence to store the product result.

[0261] In some embodiments, the floating-point multiplier 20 further includes a storage circuit for storing data storage services. This storage circuit can be a register or other storage device besides a register. Optionally, the storage circuit can be located in the output circuit 23, which stores the product results corresponding to each data group. Optionally, the storage circuit stores the product results with the bit width of the highest precision floating-point number. The bit width of the target floating-point number type is smaller than the bit width of the highest precision floating-point number, for example, the highest precision floating-point number is FP32 or FP64. The target floating-point number type is FP16, BP16, FP8, or FP4. For example, if the bit width of the product result is smaller than the bit width of the highest precision floating-point number, the output circuit 23 can pad the highest value of the product result with at least one zero, making the bit width of the zero-padded product result equal to the bit width of the highest precision floating-point number, and then store the zero-padded product result in the storage circuit.

[0262] The bit width of the mantissa of the product result may be greater than the bit width of the mantissa of the target floating-point number. If the product result is stored according to the bit width of the target floating-point number, the mantissa of the product result needs to be rounded. In this embodiment of the present disclosure, when the bit width of the mantissa of the product result is greater than the bit width of the mantissa of the target floating-point number, the product result is stored with the bit width of the highest precision floating-point number. This also allows the product result to be stored completely, thereby avoiding the rounding of the mantissa of the product result and avoiding the latency introduced by the related rounding logic. While increasing the system frequency, it also reduces the area of ​​the floating-point multiplier 20.

[0263] Optionally, the storage circuit is located outside the output circuit 23. The storage circuit is connected to the floating-point multiplication circuit and the output circuit 23. The storage circuit is used to receive the third sign sequence, the third exponent sequence, the third mantissa sequence, and the pattern identifier of the target multiplication mode. Based on the target multiplication mode, it identifies the sign of the product result corresponding to each data group from the third sign sequence, identifies the exponent of the product result corresponding to each data group from the third exponent sequence, and identifies the mantissa of the product result corresponding to each data group from the third mantissa sequence. It stores the sign, exponent, and mantissa of the product result corresponding to each data group, for example, storing the product result with the bit width of the highest precision floating-point number.

[0264] The output circuit 23 is also used to output the sign, exponent, and mantissa of the product result corresponding to each data group stored in the storage circuit, so as to output the product result corresponding to each data group. For example, the output circuit 23 outputs the product result corresponding to each data group to the processor 10. Figure 5 As shown, assuming the storage circuit stores the product result with the bit width of the highest precision floating-point number, and the bit width of the highest precision floating-point number is 32, then the product result dou of the output circuit 23 is FP32.

[0265] In some embodiments, such as Figure 5 As shown, the floating-point multiplier 20 also includes an anomaly detection sub-circuit 38, which is connected to the preprocessing circuit 21.

[0266] The anomaly detection sub-circuit 38 is used to detect, for any data set, whether the product of the first floating-point number and the second floating-point number in the data set is an anomaly, based on the target multiplication mode, the mantissa and exponent of the first floating-point number and the mantissa and exponent of the second floating-point number in the data set.

[0267] by Figure 5For example, the anomaly detection sub-circuit 38 receives the first mantissa sequence, the second mantissa sequence, the first exponent sequence, the second exponent sequence, and the mode identifier (din_mod) of the target multiplication mode sent by the preprocessing mode. Based on the target multiplication mode, it identifies the exponent of the first symbol and the exponent of the second symbol in each data group from the first exponent sequence and the second exponent sequence, and identifies the mantissa of the first symbol and the mantissa of the second symbol in each data group from the first mantissa sequence and the second mantissa sequence. For any data group, based on the target multiplication mode, the mantissa and exponent of the first floating-point number and the mantissa and exponent of the second floating-point number in the data group, it detects whether the product result between the first floating-point number and the second floating-point number in the data group is an anomaly.

[0268] Outliers can be infinity (inf) or not a number (nan). The outlier detection sub-circuit 38 can detect outliers in the following ways: When the target multiplication mode is multiplication mode 0 or 1, for any data set, if the exponents of the first and second floating-point numbers in the data set are both 1 or the mantissas of the first and second floating-point numbers in the data set are both 0, then the product of the first and second floating-point numbers in the data set is determined to be an outlier (inf). If the exponents of the first and second floating-point numbers in the data set are not both 1 and the mantissas of the first and second floating-point numbers in the data set are not both 0, then the product of the first and second floating-point numbers in the data set is determined to be an outlier (inf). The product of the first floating-point number and the second floating-point number is not an outlier, inf. If the exponents of the first and second floating-point numbers in the data set are both 1, or the mantissas of the first and second floating-point numbers in the data set are not both 0, then the product of the first and second floating-point numbers in the data set is determined to be an outlier, nan. If the exponents of the first and second floating-point numbers in the data set are not both 1, and the mantissas of the first and second floating-point numbers in the data set are both 0, then the product of the first and second floating-point numbers in the data set is determined to be an outlier, nan. When the target multiplication mode is multiplication mode 2, the product of the first and second floating-point numbers in the same data set may be an outlier, nan. That is, when the target multiplication mode is multiplication mode 2, if the exponents of both the first and second floating-point numbers in the data set are 1, or if the mantissas of both the first and second floating-point numbers are not both 0, then the product of the first and second floating-point numbers in the data set is determined to be an outlier, nan; otherwise, the product is determined not to be an outlier, nan. When the target multiplication mode is multiplication mode 3, the product of the first and second floating-point numbers in the same data set is a normal value and cannot be an outlier.

[0269] For any data set, the anomaly detection subcircuit 38 is further configured to send a first anomaly identifier `dout_inf` and a second anomaly identifier `dout_nan` to the storage subcircuit 34. `dout_inf` indicates whether the product of the first and second floating-point numbers in the data set is `inf`. For example, when `dout_inf = 1`, it indicates that the product of the first and second floating-point numbers in the data set is `inf`; when `dout_inf = 0`, it indicates that the product of the first and second floating-point numbers in the data set is not `inf`. `dout_nan` indicates whether the product of the first and second floating-point numbers in the data set is `nan`. For example, when `dout_nan = 1`, it indicates that the product of the first and second floating-point numbers in the data set is `nan`; when `dout_nan = 0`, it indicates that the product of the first and second floating-point numbers in the data set is not `nan`. Therefore, for any data set, when the product of the first floating-point number and the second floating-point number in the data set is inf, the anomaly detection subcircuit 38 sends a dou_inf with a value of 1 to the storage subcircuit 34; when the product of the first floating-point number and the second floating-point number in the data set is not inf, the anomaly detection subcircuit 38 sends a dou_inf with a value of 0 to the storage subcircuit 34; when the product of the first floating-point number and the second floating-point number in the data set is nan, the anomaly detection subcircuit 38 sends a dou_nan with a value of 1 to the storage subcircuit 34; when the product of the first floating-point number and the second floating-point number in the data set is not nan, the anomaly detection subcircuit 38 sends a dou_nan with a value of 0 to the storage subcircuit 34. The storage sub-circuit 34 receives and stores `dout_inf` and `dout_inf` sent for any data group, and sends them to the exponent adjustment sub-circuit 36. If `dout_inf` = 1, the exponent adjustment sub-circuit 36 ​​sends the product of the first and second floating-point numbers in the data group (where `inf` is the product) to the output interface, and the output interface returns the product to the processor 10. If `dout_nan` = 1, the exponent adjustment sub-circuit 36 ​​sends the product of the first and second floating-point numbers in the data group (where `nan` is the product) to the output interface, and the output interface returns the product to the processor 10. This eliminates the need to wait for the calculation results of the sign operation sub-circuit 31, the exponent adjustment sub-circuit 36, and the mantissa adjustment sub-circuit for the data group, thus improving computational efficiency. If `dout_inf` = 0 and `dout_nan` = 0, the exponent adjustment sub-circuit 36 ​​ignores `dout_inf` and `dout_nan`.

[0270] In some embodiments, the storage sub-circuit 34 may also send the dou_inf and dou_nan sent by the anomaly detection sub-circuit 38 for any data group to the output circuit 23. The output circuit 23 returns to the processor the dot product result (inf or nan) between the first floating-point number and the second floating-point number in the data group based on the values ​​of dou_inf and dou_nan, or ignores dou_inf and dou_nan.

[0271] Figure 12 This disclosure also provides a flowchart illustrating a floating-point multiplication method, which is applied to the aforementioned floating-point multiplier 20, as shown below. Figure 12 As shown, the method includes the following steps.

[0272] In step 1201, the floating-point multiplication circuit 20 acquires first input data, second input data, and a mode identifier of the target multiplication mode. The first input data includes at least one first floating-point number, the second input data includes at least one second floating-point number, and the floating-point type of both the first and second floating-point numbers is the target floating-point type. The target multiplication mode indicates that the first input data and the second input data are subjected to floating-point multiplication operations of the target floating-point type.

[0273] In step 1202, the floating-point multiplication circuit 20 preprocesses the first input data and the second input data based on the target multiplication mode to obtain at least one data group, the data group including a first floating-point number and a second floating-point number.

[0274] In step 1203, for any data group, the floating-point multiplication circuit 20 performs floating-point multiplication on the first floating-point number and the second floating-point number in the data group based on the target multiplication mode, to obtain the product result between the first floating-point number and the second floating-point number in the data group.

[0275] Optionally, the method further includes: for any data group, the floating-point multiplication circuit 20 extracts key information from the first floating-point number and the second floating-point number in the data group to obtain key information of the first floating-point number and key information of the second floating-point number in the data group, wherein the key information includes the sign, exponent and mantissa.

[0276] Step 1203 includes: for any data group, the floating-point multiplication circuit 20 performs floating-point multiplication on the first floating-point number and the second floating-point number in the data group based on the target multiplication mode, the key information of the first floating-point number in the data group and the key information of the second floating-point number, to obtain the product result between the first floating-point number and the second floating-point number in the data group.

[0277] Optionally, for any data set, based on the target multiplication pattern, key information of the first floating-point number and key information of the second floating-point number in the data set, performing floating-point multiplication on the first and second floating-point numbers in the data set to obtain the product result between the first and second floating-point numbers in the data set includes:

[0278] For any data set, the sign of the product result is obtained based on the sign of the first floating-point number and the sign of the second floating-point number in the data set;

[0279] For any data set, the exponent of the product result is obtained based on the target multiplication mode, the exponent of the first floating-point number in the data set, and the exponent of the second floating-point number.

[0280] For any data set, based on the target multiplication mode, the mantissa of the first floating-point number in the data set, and the mantissa of the second floating-point number, the mantissa of the product result is obtained.

[0281] The sign, exponent, and mantissa of the product result are used to represent the product result.

[0282] Optionally, for any data set, obtaining the sign of the product result based on the sign of the first floating-point number and the sign of the second floating-point number in the data set includes:

[0283] For any data set, perform an XOR operation on the sign of the first floating-point number and the sign of the second floating-point number in the data set to obtain the sign of the product result;

[0284] For any data set, obtaining the exponent of the product result based on the target multiplication pattern, the exponent of the first floating-point number in the data set, and the exponent of the second floating-point number includes:

[0285] For any data set, the target offset, the exponent of the first floating-point number in the data set, and the exponent of the second floating-point number are summed to obtain the exponent of the multiplication result. The target offset is the offset used when storing the floating-point number of the target floating-point number type indicated by the target multiplication mode.

[0286] For any data set, obtaining the mantissa of the product result based on the target multiplication mode, the mantissa of the first floating-point number in the data set, and the mantissa of the second floating-point number includes:

[0287] For any data set, based on the target multiplication mode, the mantissas of the first floating-point number and the mantissas of the second floating-point number in the data set are multiplied to obtain the mantissa of the product result.

[0288] Optionally, for any data set, based on the target multiplication pattern, the mantissas of the first floating-point number and the mantissas of the second floating-point number in the data set are multiplied to obtain the mantissas of the product result, which include:

[0289] Receive a first binary sequence and a second binary sequence, wherein the first binary sequence includes a binary sequence of the mantissa of the at least one first symbol, and the second binary sequence includes a binary sequence of the mantissa of the at least one second symbol;

[0290] Based on the target multiplication pattern, the binary sequence of the mantissa of the first symbol and the binary sequence of the mantissa of the second symbol in the same data group are multiplied to obtain the mantissa of the product result between the first floating-point number and the second floating-point number in the same data group.

[0291] Optionally, the method includes:

[0292] The number of leading zeros in the binary sequence of the mantissa of the product result is obtained by detecting the leading zeros in the mantissa of the product result.

[0293] Based on the number of leading zeros, the mantissa of the product result is adjusted to obtain the adjusted mantissa of the product result;

[0294] Based on the number of leading zeros, the exponent of the multiplication result is adjusted to obtain the adjusted exponent of the product result;

[0295] The sign of the product result, the adjusted exponent of the product result, and the mantissa are used to represent the product result.

[0296] Optionally, adjusting the mantissa of the product result based on the number of leading zeros to obtain the adjusted mantissa of the product result includes:

[0297] Shift the binary sequence of the mantissa of the product result to the left by the number of leading zeros to obtain the adjusted mantissa of the product result;

[0298] The adjustment of the exponent of the multiplication result based on the number of leading zeros, to obtain the adjusted exponent of the product result, includes:

[0299] The exponent of the multiplication result is subtracted from the number of leading zeros to obtain the adjusted exponent of the product result.

[0300] Optionally, the method further includes:

[0301] For any data set, based on the target multiplication pattern, the mantissa and exponent of the first floating-point number in the data set, and the mantissa and exponent of the second floating-point number, it is detected whether the product result is an outlier.

[0302] Optionally, the method further includes:

[0303] The product result is stored with the bit width of the highest precision floating-point number, wherein the bit width of the target floating-point number type is smaller than the bit width of the highest precision floating-point number.

[0304] Optionally, the target floating-point number type is at least one of 16-bit floating-point, 16-bit 8-bit floating-point, or 4-bit floating-point.

[0305] The method provided in this disclosure uses a multiplication mode instruction to perform floating-point multiplication operations of a specified floating-point type (such as a target floating-point type) on the input data. The specified floating-point type is the floating-point type of the floating-point numbers in the input data. The floating-point multiplier 20 preprocesses the input data, dividing the floating-point numbers in the input data into data groups. Based on the target multiplication mode, it performs floating-point multiplication operations of the floating-point type on the floating-point data in the same data group. Thus, by specifying different multiplication modes for input data of different floating-point types, the floating-point multiplier 20 can perform floating-point multiplication operations of multiple floating-point types to meet the operational requirements of floating-point multiplication operations of multiple floating-point types.

[0306] It should be understood that the above introduction to the floating-point multiplier 20 can be applied to floating-point multiplication operations, and will not be repeated here.

[0307] In an exemplary embodiment, a computer-readable storage medium is provided, wherein when at least one instruction in the computer-readable storage medium is executed by a processor, the device in which the processor resides (such as a computing chip or a computer device) is capable of performing the above-described floating-point multiplication operation method.

[0308] In an exemplary embodiment, a computer program product is also provided, including one or more instructions that can be executed by a processor, enabling the device in which the processor resides (such as a computing chip or computer device) to perform the above-described floating-point multiplication method.

[0309] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0310] In some embodiments, the meaning of A and / or B includes three cases: A and B, and A and B.

[0311] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this disclosure are all authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the input data involved in this disclosure were all obtained with full authorization.

[0312] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0313] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A floating-point multiplier, characterized in that, The floating-point multiplier includes a preprocessing circuit and a floating-point multiplication circuit, wherein the preprocessing circuit is connected to the floating-point multiplication circuit; The preprocessing circuit is used to acquire first input data, second input data, and a mode identifier of a target multiplication mode. The first input data includes at least one first floating-point number, the second input data includes at least one second floating-point number, the floating-point number types of the first floating-point number and the second floating-point number are both target floating-point number types, and the target multiplication mode indicates that the first input data and the second input data are subjected to floating-point number multiplication operations of the target floating-point number type. The preprocessing circuit is further configured to preprocess the first input data and the second input data based on the target multiplication mode to obtain at least one data group, the data group including a first floating-point number and a second floating-point number; The floating-point multiplication circuit is used to perform floating-point multiplication on the first floating-point number and the second floating-point number in any data group based on the target multiplication mode, so as to obtain the product result between the first floating-point number and the second floating-point number in the data group.

2. The floating-point multiplier according to claim 1, characterized in that, The preprocessing circuit is also used to extract key information from the first floating-point number and the second floating-point number in any data group, and to obtain key information of the first floating-point number and the second floating-point number in the data group. The key information includes the sign, exponent and mantissa. The floating-point multiplication circuit is used to perform floating-point multiplication on the first and second floating-point numbers in any data group based on the target multiplication mode, key information of the first floating-point number and key information of the second floating-point number in the data group, to obtain the product result between the first and second floating-point numbers in the data group.

3. The floating-point multiplier according to claim 2, characterized in that, The floating-point multiplication circuit includes: The sign operation subcircuit is used to obtain the sign of the product result for any data group based on the sign of the first floating-point number and the sign of the second floating-point number in the data group. An exponentiation subcircuit is used to obtain the exponent of the product result for any data set based on the target multiplication mode, the exponent of the first floating-point number in the data set, and the exponent of the second floating-point number. The mantissa operation sub-circuit is used to obtain the mantissa of the product result for any data group based on the target multiplication mode, the mantissa of the first floating-point number in the data group, and the mantissa of the second floating-point number. The sign, exponent, and mantissa of the product result are used to represent the product result.

4. The floating-point multiplier according to claim 3, characterized in that, The sign operation sub-circuit is used to perform an XOR operation on the sign of the first floating-point number and the sign of the second floating-point number in any data group to obtain the sign of the product result. The exponent operation sub-circuit is used to perform a summation operation on the target offset, the exponent of the first floating-point number in the data group, and the exponent of the second floating-point number for any data group to obtain the exponent of the multiplication result. The target offset is the offset used when storing the floating-point number of the target floating-point number type indicated by the target multiplication mode. The mantissa operation sub-circuit is used to perform a multiplication operation on the mantissa of the first floating-point number and the mantissa of the second floating-point number in any data group, based on the target multiplication mode, to obtain the mantissa of the product result.

5. The floating-point multiplier according to claim 4, characterized in that, The mantissa operation sub-circuit includes an input interface and a multiplier array, wherein the input interface is connected to the multiplier array; The input interface is used to receive a first binary sequence and a second binary sequence, wherein the first binary sequence includes a binary sequence of the mantissa of the at least one first symbol, and the second binary sequence includes a binary sequence of the mantissa of the at least one second symbol; The multiplier array is used to perform multiplication operations on the binary sequence of the mantissa of the first symbol and the binary sequence of the mantissa of the second symbol in the same data group based on the target multiplication pattern, so as to obtain the mantissa of the product result between the first floating-point number and the second floating-point number in the same data group.

6. The floating-point multiplier according to claim 3, characterized in that, The floating-point multiplication circuit further includes a leading zero detection sub-circuit, an exponent adjustment sub-circuit, and a mantissa adjustment sub-circuit, wherein the leading zero detection sub-circuit is connected to the mantissa operation sub-circuit, the exponent adjustment sub-circuit, and the mantissa adjustment sub-circuit. The leading zero detection sub-circuit is used to detect leading zeros in the binary sequence of the mantissa of the product result to obtain the number of leading zeros in the mantissa of the product result. The mantissa adjustment sub-circuit is used to adjust the mantissa of the product result based on the number of leading zeros, so as to obtain the adjusted mantissa of the product result. The exponent adjustment sub-circuit is used to adjust the exponent of the multiplication result based on the number of leading zeros, so as to obtain the adjusted exponent of the product result; The sign of the product result, the adjusted exponent of the product result, and the mantissa are used to represent the product result.

7. The floating-point multiplier according to claim 6, characterized in that, The mantissa adjustment unit is used to shift the binary sequence of the mantissa of the product result to the left by the number of leading zeros to obtain the adjusted mantissa of the product result. The exponent adjustment sub-circuit is used to subtract the exponent of the multiplication result from the number of leading zeros to obtain the adjusted exponent of the product result.

8. The floating-point multiplier according to any one of claims 3-7, characterized in that, The floating-point multiplier also includes an anomaly detection sub-circuit, which is connected to the preprocessing circuit. The anomaly detection sub-circuit is used to detect whether the product result is an anomaly for any data group, based on the target multiplication mode, the mantissa and exponent of the first floating-point number in the data group, and the mantissa and exponent of the second floating-point number.

9. The floating-point multiplier according to any one of claims 1-7, characterized in that, The floating-point multiplier also includes a storage circuit, which is connected to the floating-point multiplication circuit; The storage circuit is used to store the product result with the bit width of the highest precision floating-point number, wherein the bit width of the target floating-point number type is smaller than the bit width of the highest precision floating-point number.

10. The floating-point multiplier according to claim 9, characterized in that, The target floating-point number type is at least one of 16-bit floating-point, 16-bit 8-bit floating-point, or 4-bit floating-point.

11. A computing chip, characterized in that, The computing chip includes a processor and a floating-point multiplier, the processor being connected to the floating-point multiplier; the floating-point multiplier includes a preprocessing circuit and a floating-point multiplication circuit, the preprocessing circuit being connected to the floating-point multiplication circuit; The processor is configured to send floating-point multiplication instructions to the point-multiplier, wherein the floating-point multiplication instructions include first input data, second input data, and a mode identifier of a target multiplication mode. The first input data includes at least one first floating-point number, the second input data includes at least one second floating-point number, the floating-point type of the first floating-point number and the second floating-point number are both of the target floating-point type, and the target multiplication mode indicates that floating-point multiplication of the target floating-point type is performed on the first input data and the second input data. The preprocessing circuit is used to receive floating-point multiplication operation instructions, and preprocess the first input data and the second input data based on the target multiplication mode to obtain at least one data group, wherein the data group includes a first floating-point number and a second floating-point number; The floating-point multiplication circuit is used to perform floating-point multiplication on the first floating-point number and the second floating-point number in any data group based on the target multiplication mode, so as to obtain the product result between the first floating-point number and the second floating-point number in the data group.

12. The computing chip according to claim 11, characterized in that, The preprocessing circuit is also used to extract key information from the first floating-point number and the second floating-point number in any data group, and to obtain key information of the first floating-point number and the second floating-point number in the data group. The key information includes the sign, exponent and mantissa. The floating-point multiplication circuit is used to perform floating-point multiplication on the first and second floating-point numbers in any data group based on the target multiplication mode, key information of the first floating-point number and key information of the second floating-point number in the data group, to obtain the product result between the first and second floating-point numbers in the data group.

13. The computing chip according to claim 12, characterized in that, The floating-point multiplication circuit includes: The sign operation subcircuit is used to obtain the sign of the product result for any data group based on the sign of the first floating-point number and the sign of the second floating-point number in the data group. An exponentiation subcircuit is used to obtain the exponent of the product result for any data set based on the target multiplication mode, the exponent of the first floating-point number in the data set, and the exponent of the second floating-point number. The mantissa operation sub-circuit is used to obtain the mantissa of the product result for any data group based on the target multiplication mode, the mantissa of the first floating-point number in the data group, and the mantissa of the second floating-point number. The sign, exponent, and mantissa of the product result are used to represent the product result.

14. The computing chip according to claim 13, characterized in that, The sign operation sub-circuit is used to perform an XOR operation on the sign of the first floating-point number and the sign of the second floating-point number in any data group to obtain the sign of the product result. The exponent operation sub-circuit is used to perform a summation operation on the target offset, the exponent of the first floating-point number in the data group, and the exponent of the second floating-point number for any data group to obtain the exponent of the multiplication result. The target offset is the offset used when storing the floating-point number of the target floating-point number type indicated by the target multiplication mode. The mantissa operation sub-circuit is used to perform a multiplication operation on the mantissa of the first floating-point number and the mantissa of the second floating-point number in any data group, based on the target multiplication mode, to obtain the mantissa of the product result.

15. The computing chip according to claim 14, characterized in that, The mantissa operation sub-circuit includes an input interface and a multiplier array, wherein the input interface is connected to the multiplier array; The input interface is used to receive a first binary sequence and a second binary sequence, wherein the first binary sequence includes a binary sequence of the mantissa of the at least one first symbol, and the second binary sequence includes a binary sequence of the mantissa of the at least one second symbol; The multiplier array is used to perform multiplication operations on the binary sequence of the mantissa of the first symbol and the binary sequence of the mantissa of the second symbol in the same data group based on the target multiplication pattern, so as to obtain the mantissa of the product result between the first floating-point number and the second floating-point number in the same data group.

16. The computing chip according to claim 13, characterized in that, The floating-point multiplication circuit further includes a leading zero detection sub-circuit, an exponent adjustment sub-circuit, and a mantissa adjustment sub-circuit, wherein the leading zero detection sub-circuit is connected to the mantissa operation sub-circuit, the exponent adjustment sub-circuit, and the mantissa adjustment sub-circuit. The leading zero detection sub-circuit is used to detect leading zeros in the binary sequence of the mantissa of the product result to obtain the number of leading zeros in the mantissa of the product result. The mantissa adjustment sub-circuit is used to adjust the mantissa of the product result based on the number of leading zeros, so as to obtain the adjusted mantissa of the product result. The exponent adjustment sub-circuit is used to adjust the exponent of the multiplication result based on the number of leading zeros, so as to obtain the adjusted exponent of the product result; The sign of the product result, the adjusted exponent of the product result, and the mantissa are used to represent the product result.

17. The computing chip according to claim 16, characterized in that, The mantissa adjustment unit is used to shift the binary sequence of the mantissa of the product result to the left by the number of leading zeros to obtain the adjusted mantissa of the product result. The exponent adjustment sub-circuit is used to subtract the exponent of the multiplication result from the number of leading zeros to obtain the adjusted exponent of the product result.

18. The computing chip according to any one of claims 13-17, characterized in that, The floating-point multiplier also includes an anomaly detection sub-circuit, which is connected to the preprocessing circuit. The anomaly detection sub-circuit is used to detect whether the product result is an anomaly for any data group, based on the target multiplication mode, the mantissa and exponent of the first floating-point number in the data group, and the mantissa and exponent of the second floating-point number.

19. The computing chip according to any one of claims 11-17, characterized in that, The floating-point multiplier also includes a storage circuit, which is connected to the floating-point multiplication circuit; The storage circuit is used to store the product result with the bit width of the highest precision floating-point number, wherein the bit width of the target floating-point number type is smaller than the bit width of the highest precision floating-point number.

20. The computing chip according to claim 19, characterized in that, The target floating-point number type is at least one of 16-bit floating-point, 16-bit 8-bit floating-point, or 4-bit floating-point.

21. A floating-point multiplication method, characterized in that, The method is applied to a floating-point multiplier, and the method includes: Obtain first input data, second input data, and a mode identifier of a target multiplication mode, wherein the first input data includes at least one first floating-point number, the second input data includes at least one second floating-point number, the floating-point number types of the first floating-point number and the second floating-point number are both of the target floating-point number type, and the target multiplication mode indicates that the first input data and the second input data are subjected to floating-point number multiplication operations of the target floating-point number type; Based on the target multiplication pattern, the first input data and the second input data are preprocessed to obtain at least one data group, the data group including a first floating-point number and a second floating-point number; For any data set, based on the target multiplication mode, floating-point multiplication is performed on the first and second floating-point numbers in the data set to obtain the product between the first and second floating-point numbers in the data set.

22. The method according to claim 21, characterized in that, The method further includes: For any data set, key information is extracted from the first and second floating-point numbers in the data set to obtain key information of the first and second floating-point numbers in the data set. The key information includes the sign, exponent, and mantissa. For any data set, based on the target multiplication mode, floating-point multiplication is performed on the first and second floating-point numbers in the data set to obtain the product between the first and second floating-point numbers in the data set, including: For any data set, based on the target multiplication mode, the key information of the first floating-point number and the key information of the second floating-point number in the data set, floating-point multiplication is performed on the first floating-point number and the second floating-point number in the data set to obtain the product result between the first floating-point number and the second floating-point number in the data set.

23. The method according to claim 22, characterized in that, For any data set, based on the target multiplication mode, key information of the first floating-point number and key information of the second floating-point number in the data set, floating-point multiplication is performed on the first floating-point number and the second floating-point number in the data set to obtain the product result between the first floating-point number and the second floating-point number in the data set, including: For any data set, the sign of the product result is obtained based on the sign of the first floating-point number and the sign of the second floating-point number in the data set; For any data set, the exponent of the product result is obtained based on the target multiplication mode, the exponent of the first floating-point number in the data set, and the exponent of the second floating-point number. For any data set, based on the target multiplication mode, the mantissa of the first floating-point number in the data set, and the mantissa of the second floating-point number, the mantissa of the product result is obtained. The sign, exponent, and mantissa of the product result are used to represent the product result.

24. The method according to claim 23, characterized in that, For any data set, obtaining the sign of the product result based on the sign of the first floating-point number and the sign of the second floating-point number in the data set includes: For any data set, perform an XOR operation on the sign of the first floating-point number and the sign of the second floating-point number in the data set to obtain the sign of the product result; For any data set, obtaining the exponent of the product result based on the target multiplication pattern, the exponent of the first floating-point number in the data set, and the exponent of the second floating-point number includes: For any data set, the target offset, the exponent of the first floating-point number in the data set, and the exponent of the second floating-point number are summed to obtain the exponent of the multiplication result. The target offset is the offset used when storing the floating-point number of the target floating-point number type indicated by the target multiplication mode. For any data set, obtaining the mantissa of the product result based on the target multiplication mode, the mantissa of the first floating-point number in the data set, and the mantissa of the second floating-point number includes: For any data set, based on the target multiplication mode, the mantissas of the first floating-point number and the mantissas of the second floating-point number in the data set are multiplied to obtain the mantissa of the product result.

25. The method according to claim 24, characterized in that, For any data set, based on the target multiplication pattern, the mantissas of the first floating-point number and the mantissas of the second floating-point number in the data set are multiplied to obtain the mantissas of the product result, which include: Receive a first binary sequence and a second binary sequence, wherein the first binary sequence includes a binary sequence of the mantissa of the at least one first symbol, and the second binary sequence includes a binary sequence of the mantissa of the at least one second symbol; Based on the target multiplication pattern, the binary sequence of the mantissa of the first symbol and the binary sequence of the mantissa of the second symbol in the same data group are multiplied to obtain the mantissa of the product result between the first floating-point number and the second floating-point number in the same data group.

26. The method according to claim 23, characterized in that, The method includes: The number of leading zeros in the binary sequence of the mantissa of the product result is obtained by detecting the leading zeros in the mantissa of the product result. Based on the number of leading zeros, the mantissa of the product result is adjusted to obtain the adjusted mantissa of the product result; Based on the number of leading zeros, the exponent of the multiplication result is adjusted to obtain the adjusted exponent of the product result; The sign of the product result, the adjusted exponent of the product result, and the mantissa are used to represent the product result.

27. The method according to claim 26, characterized in that, The adjustment of the mantissa of the product result based on the number of leading zeros, to obtain the adjusted mantissa of the product result, includes: Shift the binary sequence of the mantissa of the product result to the left by the number of leading zeros to obtain the adjusted mantissa of the product result; The adjustment of the exponent of the multiplication result based on the number of leading zeros, to obtain the adjusted exponent of the product result, includes: The exponent of the multiplication result is subtracted from the number of leading zeros to obtain the adjusted exponent of the product result.

28. The method according to any one of claims 23-27, characterized in that, The method further includes: For any data set, based on the target multiplication pattern, the mantissa and exponent of the first floating-point number in the data set, and the mantissa and exponent of the second floating-point number, it is detected whether the product result is an outlier.

29. The method according to any one of claims 21-27, characterized in that, The method further includes: The product result is stored with the bit width of the highest precision floating-point number, wherein the bit width of the target floating-point number type is smaller than the bit width of the highest precision floating-point number.

30. The method according to claim 29, characterized in that, The target floating-point number type is at least one of 16-bit floating-point, 16-bit 8-bit floating-point, or 4-bit floating-point.

31. A computer-readable storage medium, characterized in that, The storage medium stores at least one instruction, which is read by a processor to execute the method as described in any one of claims 21 to 30.

32. A computer program product, characterized in that, It includes one or more instructions, which are read by a processor to perform the method as described in any one of claims 21 to 30.

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