DMA control program optimization methods, apparatus, equipment, media, and products

Abstract

This invention discloses a method, apparatus, device, medium, and product for optimizing a DMA control program. The method includes: acquiring an intermediate representation of the program that matches the DMA control program in a multi-stage pipeline scenario; identifying pairs of equivalent concatenated instructions with reciprocal dominance relationships in the intermediate representation based on the organization logic of each semantic operation instruction; identifying target equivalent concatenated instruction pairs that satisfy optimization conditions among these pairs; and performing impact elimination processing on each target equivalent concatenated instruction pair in the intermediate representation based on the data dependency instructions and all user instructions corresponding to each target equivalent concatenated instruction pair, followed by deleting each target equivalent concatenated instruction pair to optimize the DMA control program. The technical solution of this invention improves the configuration performance of the DMA controller and the efficiency of data transfer tasks, thereby fully utilizing the hardware computing power of the GPU.

Description

Technical Field

[0001] This invention relates to the fields of software development and compilation technology, and in particular to an optimization method, apparatus, device, medium and product for a DMA (Direct Memory Access) control program. Background Technology

[0002] In modern embedded system development, the GPU (Graphics Processing Unit) architecture, with its powerful DMA capabilities, can significantly improve data transfer rates. The GPU computing unit only needs to send initialization, configuration, and trigger instructions to the DMA controller, which will then execute the corresponding data transfer tasks.

[0003] Operators in GPU architecture mostly perform computationally intensive tasks, meaning that computational tasks typically take longer than data transfer tasks. In such cases, it is usually necessary to request and initialize multiple DMA channels. Each DMA channel needs to be configured and operated independently, responsible for performing data transfer tasks in a specific stage.

[0004] In the process of realizing this invention, the inventors discovered that in a multi-stage pipeline scenario, when operator developers build a DMA control program, they need to calculate which stage the execution is currently at and call different DMA channels for configuration and data transfer. The introduction of these judgment statements in the DMA control program will greatly reduce the configuration efficiency of the DMA controller, which will have a significant impact on the performance of data transfer tasks, thereby reducing the computing power utilization of the GPU computing unit and ultimately affecting the execution performance of the DMA control program. Summary of the Invention

[0005] This invention provides a method, apparatus, device, medium, and product for optimizing DMA control programs, in order to solve the problem of poor DMA controller configuration efficiency affecting the execution performance of DMA control programs.

[0006] According to one aspect of the present invention, a method for optimizing a DMA control program is provided, the method comprising:

[0007] Obtain the intermediate representation of the program that matches the DMA control program in a multi-stage pipeline scenario, wherein the intermediate representation of the program includes multiple semantic operation instructions;

[0008] Based on the organization logic of each semantic operation instruction in the intermediate representation of the program, identify each pair of equivalent concatenated instructions with a mutual inverse dominance relationship in the intermediate representation of the program. Among them, the pair of equivalent concatenated instructions includes a pointer to integer instruction and an integer to pointer instruction.

[0009] In each pair of equivalent concatenated instructions, identify the target pair of equivalent concatenated instructions that satisfies the optimization conditions;

[0010] Based on the data dependency instructions corresponding to each target equivalent concatenation instruction pair and all user instructions, the impact elimination processing for each target equivalent concatenation instruction pair is performed in the intermediate program representation, and then each target equivalent concatenation instruction pair is deleted to optimize the DMA control program.

[0011] According to another aspect of the present invention, an optimization apparatus for a DMA control program is also provided, the apparatus comprising:

[0012] The intermediate representation acquisition module is used to acquire the intermediate representation of the program that matches the DMA control program in a multi-stage pipeline scenario. The intermediate representation of the program includes multiple semantic operation instructions.

[0013] The equivalent concatenation instruction pair identification module is used to identify equivalent concatenation instruction pairs with mutual inverse dominance relationships in the intermediate program representation based on the organization logic of each semantic operation instruction in the intermediate program representation. The equivalent concatenation instruction pair includes a pointer-to-integer instruction and an integer-to-pointer instruction.

[0014] The target equivalence concatenation instruction pair identification module is used to identify target equivalence concatenation instruction pairs that satisfy the optimization conditions among each equivalence concatenation instruction pair;

[0015] The target equivalent concatenation instruction pair deletion module is used to perform impact elimination processing on each target equivalent concatenation instruction pair in the intermediate program representation based on the data dependency instructions corresponding to each target equivalent concatenation instruction pair and all user instructions, and then delete each target equivalent concatenation instruction pair to optimize the DMA control program.

[0016] According to another aspect of the present invention, an electronic device is also provided, the electronic device comprising:

[0017] At least one processor; and

[0018] A memory communicatively connected to the at least one processor; wherein,

[0019] The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to execute the DMA control program optimization method according to any embodiment of the present invention.

[0020] According to another aspect of the present invention, a computer-readable storage medium is also provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the DMA control program optimization method described in any embodiment of the present invention.

[0021] According to another aspect of the present invention, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps of an optimization method for a DMA control program as described in any embodiment of the present invention.

[0022] This invention, through obtaining an intermediate program representation matching the DMA control program in a multi-stage pipeline scenario; identifying mutually exclusive concatenated instruction pairs with inverse dominance relationships based on the organization logic of each semantic operation instruction in the intermediate program representation; identifying target concatenated instruction pairs that satisfy optimization conditions among each concatenated instruction pair; and deleting each target concatenated instruction pair after performing impact elimination processing on each target concatenated instruction pair in the intermediate program representation based on the data dependency instructions and all user instructions corresponding to each target concatenated instruction pair, while ensuring the rationality of program transformation, can effectively eliminate concatenated instruction pairs that cannot be handled by existing instruction compilers. After the elimination of the above-mentioned concatenated instruction pairs is completed, various instruction compilers can be called normally to smoothly eliminate and optimize the stack pointer of the DMA channel in the DMA control program. This fundamentally improves the performance of the DMA control program developed in a multi-stage pipeline scenario, enhances the configuration performance of the DMA controller and the efficiency of data transfer tasks, and can fully utilize the hardware computing power of the GPU, effectively improving the computing power utilization rate of the GPU computing unit.

[0023] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of a two-stage DMA data transfer and data computation task applicable to an embodiment of the present invention;

[0026] Figure 2This is a schematic diagram of a multi-stage scenario DMA control program instruction sequence applicable to an embodiment of the present invention;

[0027] Figure 3 This is a flowchart of an optimization method for a DMA control program provided according to an embodiment of the present invention;

[0028] Figure 4 This is a flowchart of another optimization method for a DMA control program provided according to an embodiment of the present invention;

[0029] Figure 5 This is a schematic diagram of the structure of an optimization device for a DMA control program according to an embodiment of the present invention;

[0030] Figure 6 This is a schematic diagram of the structure of an electronic device that implements the optimization method of the DMA control program in the embodiments of the present invention. Detailed Implementation

[0031] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0032] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0033] In order to more clearly describe the technical solutions of the various embodiments of the present invention, the relevant content of the application scenarios to which the various embodiments of the present invention are applicable will be briefly analyzed.

[0034] First, operators in GPU architecture are primarily used to execute computationally intensive tasks, meaning the computational tasks take longer than the data transfer tasks. In this application scenario, it's typically necessary to request and initialize multiple DMA channels. Each DMA channel needs to be independently configured and operate independently to handle the data transfer tasks for a specific stage. Typically, the two stages are arranged as follows: Figure 1 The task execution process is as follows:

[0035] 1. The computing unit first requests two DMA channels, which are used for data transfer between stage0 and stage1 respectively.

[0036] 2. After completing the DMA channel configuration corresponding to stage0, the DMA engine is triggered to perform data transfer operations.

[0037] 3. Repeat the following tasks until all data calculations are complete:

[0038] a) Check whether the instructions for the stage(i-1) computation task have been issued and completed. If completed, call the computation unit to configure the DMA channel corresponding to stage(i) and trigger the DMA engine to perform data transfer.

[0039] b) Check if the data transfer of stage(i-1) is complete. If it is complete, the computing unit starts the calculation of the data corresponding to stage(i-1).

[0040] c) If i equals 2, then reset i to 1; otherwise, increment i by 1 (this step is used to alternately reuse the DMA channels of stage0 and stage1 to ensure that the computation tasks of each stage are completed in an orderly manner).

[0041] It is evident that both the data transport in stage(i) and the data computation in stage(i-1) depend on the completion of the previous round of computation tasks. Specifically, the DMA transport task requires the computation unit to issue configuration and trigger instructions, while the computation task requires the computation unit to execute the calculations. Since these two types of tasks have no data dependency, their instruction issuance processes are executed in parallel and resource contention exists. To improve the computational utilization of the computation unit, the time spent on DMA configuration and data transport must be lower than the time spent by the computation unit to execute the computation tasks, meeting the core performance optimization requirements for this scenario under the GPU architecture.

[0042] However, in more real-world scenarios, the scale of stages is usually larger: on the one hand, operator developers need to track the currently executing stage in real time and call different DMA channels to complete configuration and data transfer. Complex data flow control code will reduce the configuration efficiency of the DMA controller. On the other hand, the larger the stage, the shorter the time consumed by a single round of computation tasks. It is easy for the total time consumed by DMA configuration and transfer to exceed the computation time, which ultimately leads to a significant decrease in the utilization of GPU computing units.

[0043] Programs configuring DMA controllers are typically written in C++ and compiled into assembly code using mainstream compilers such as GCC (GNU Compiler Collection) or LLVM (Low Level Virtual Machine). Taking the LLVM compiler as an example, each DMA controller configuration generates three fixed instructions: obtaining the starting address of the DMA channel on the stack, calculating the address offset of the bit fields, and storing the configuration value at the offset address. These instructions have significant performance drawbacks, specifically: DMA channels occupy stack space, and once stack space usage exceeds a threshold, program performance degrades drastically; the execution efficiency of instructions configuring DMA controller members is extremely low, requiring the execution of three instructions each time: "obtain the stack starting address of the DMA object → calculate the offset → access members"; and the DMA channel occupying stack space hinders the compiler's optimization of program control flow statements, as stack values ​​must be read from memory, resulting in variables susceptible to arbitrary memory-related instructions. Because the compiler cannot guarantee their safety, it disables many compile-time optimization strategies.

[0044] The LLVM general compiler framework typically employs SROA (Scalar Replace Of Aggregates) technology to attempt optimization. However, in the computational unit code scenario of GPU architecture, the optimization effect is limited: on the one hand, the stage size is usually larger, and operator developers need to calculate the currently executing stage in real time and call different DMA channels to complete configuration and data transfer. The complex data flow control code further reduces the configuration efficiency of the DMA controller; on the other hand, the larger the stage size, the shorter the time of a single round of computation task, which can easily lead to the total time spent on DMA configuration and transfer exceeding the computation time, exacerbating performance loss.

[0045] More specifically, complex dataflow code contains numerous control flow statements such as if-else, for loops, and break. In the LLVM intermediate representation, three types of instructions are frequently generated: PtrToInt instructions, used to convert pointer (Ptr) type variables to integer (Int) type variables; IntToPtr instructions, used to convert integer (Int) type variables to pointer (Ptr) type variables; and PHI instructions, used to merge multiple input variables of the same type and output a variable of the same type. Among these, PtrToInt and IntToPtr instructions, if they satisfy a strict cascading relationship (i.e., the only user instruction of a PtrToInt instruction is an IntToPtr instruction), can be optimized away by the LLVM compiler. However, in multi-stage complex scenarios, these two cannot satisfy this strict cascading relationship (also known as a direct cascading relationship), and numerous PHI instructions are inserted between them to merge pointers from different sources.

[0046] Specifically, a typical multi-stage DMA control program instruction sequence is as follows: Figure 2 As shown in the diagram, the instruction sequence described above exhibits a situation where the PtrToInt and IntToPtr instructions do not satisfy the cascading relationship. Typically, a variable defined by a PtrToInt instruction (e.g., %878) is used as an input operand for a PHI instruction (also known as an operand). Even if the output variable of the PHI instruction (e.g., %880) is used as an input operand for the IntToPtr instruction, the output of the PHI instruction is still considered a variable. Consequently, the input operand of the IntToPtr instruction is treated as a variable and cannot be associated with a definite constant stack pointer. In this case, the LLVM compiler cannot eliminate DMA-type stack variables (e.g., %11), leading to performance issues.

[0047] In fact, it is precisely because of the existence of these PtrToInt and IntToPtr instructions in the DMA control program that the SROA technology in the LLVM compiler cannot fully utilize its function, ultimately resulting in poor execution efficiency of the DMA controller's configuration instructions. Accordingly, the embodiments of this invention take the above-mentioned technical problem as a starting point. Considering that since non-directly concatenated PtrToInt and IntToPtr instructions are generated in the multi-stage dataflow code under the GPU architecture, the definition and usage relationship between the instructions becomes uncertain, i.e., variable. Therefore, a new optimization algorithm is proposed to deeply analyze and calculate, further determining whether the above two instructions satisfy a more relaxed equivalence concatenation relationship (also called an indirect concatenation relationship). If satisfied, a special processing mechanism can be used to first eliminate this pair of PtrToInt and IntToPtr instructions while ensuring the legality of program transformation, and then call the mainstream optimization algorithm to perform code optimization. This can effectively eliminate and optimize the stack pointer of the DMA channel in the DMA control program, thereby solving the performance problem existing in the multi-stage dataflow code. This is the main design intention of the embodiments of this invention.

[0048] Figure 3 This is a flowchart illustrating a DMA control program optimization method provided in an embodiment of the present invention. This embodiment is applicable to situations where, before optimizing the DMA control program using a general program code optimization scheme, PtrToInt and IntToPtr instructions in the DMA control program that do not satisfy a direct cascading relationship are effectively eliminated. This method can be executed by a DMA control program optimization device, which can be implemented in hardware and / or software and is generally configurable in various electronic devices. Figure 3 As shown, the method includes:

[0049] S310. Obtain the intermediate representation of the program that matches the DMA control program in the multi-stage pipeline scenario, wherein the intermediate representation of the program includes multiple semantic operation instructions.

[0050] Specifically, the DMA control program in a multi-stage pipeline scenario can be understood as the data flow code used to configure the DMA controller in a multi-stage DMA data transfer scenario under the GPU framework.

[0051] In this embodiment, after the developers have developed the DMA control program for a multi-stage pipeline scenario, they can compile the DMA control program using existing compiler frameworks and obtain an intermediate program representation that matches the DMA control program during the compilation process.

[0052] Semantic operation instructions refer to abstract instructions generated by the compiler between the front-end and back-end, independent of the specific hardware architecture. They are used to accurately describe the computational logic, data flow, and control flow behavior of the program (such as operations, type conversions, branch merging, and memory access), and are the core carrier of compiler analysis and optimization.

[0053] S320. Based on the organization logic of each semantic operation instruction in the intermediate program representation, identify each pair of equivalent concatenated instructions with a mutually exclusive relationship in the intermediate program representation, wherein the pair of equivalent concatenated instructions includes a pointer-to-integer instruction and an integer-to-pointer instruction.

[0054] Among them, the mutual inverse dominance relationship can refer to the mutual inverse instruction relationship consisting of pointer to integer instruction and integer to pointer instruction. The two form an inverse and equivalent conversion link in terms of function, and the whole can realize the equivalent operation of restoring pointer data to pointer data after being converted to integer.

[0055] Pointer-to-integer instructions are abstract operations in the intermediate representation of a program that directly map the memory address (binary value) pointed to by a pointer variable to an equivalent integer value. They only strip away the address semantics of the pointer while retaining its numerical characteristics, without address validity checks, and the number of bits in the result is strongly correlated with the number of bits in the pointer. Integer-to-pointer instructions are abstract operations in the intermediate representation of a program that treat an integer value as a memory address, assign it pointer semantics, and convert it to the corresponding pointer type. They can be used to restore addresses or access hard-coded addresses. Equivalent concatenated instruction pairs refer to a pair of pointer-to-integer instructions and integer-to-pointer instructions that have a mutually inverse relationship.

[0056] It is understandable that, based on the organization logic of each semantic operation instruction in the intermediate representation of the program, the input and output data of the pointer-to-integer instruction and the integer-to-pointer instruction in each semantic operation instruction, as well as the calling relationship between each data and instruction, can be determined. Thus, the pointer-to-integer instruction that converts any pointer data to integer data, and the integer-to-pointer instruction that converts integer data to pointer data, can be determined. Consequently, one or more equivalent concatenated instruction pairs can be determined accordingly.

[0057] S330. In each equivalent concatenation instruction pair, identify the target equivalent concatenation instruction pair that satisfies the optimization conditions.

[0058] The target equivalent concatenation instruction pair can refer to the equivalent concatenation instruction pair that satisfies the optimization conditions among the various equivalent concatenation instruction pairs identified by S320.

[0059] In other words, each embodiment of the present invention needs to identify one or more target equivalent concatenation instruction pairs that cannot be eliminated by the prior art but still satisfy the indirect concatenation relationship in the intermediate representation of the program, and perform specific instruction optimization processing on these identified target equivalent concatenation instruction pairs, such as direct deletion.

[0060] S340. Based on the data dependency instructions corresponding to each target equivalent concatenation instruction pair and all user instructions, perform the impact elimination processing for each target equivalent concatenation instruction pair in the intermediate program representation, and then delete each target equivalent concatenation instruction pair to optimize the DMA control program.

[0061] In this context, data-dependent instructions can refer to instructions that generate pointer data input to a pointer-to-integer instruction in the target equivalent concatenation instruction pair. User instructions can refer to instructions that reference pointer data output by an integer-to-pointer instruction in the target equivalent concatenation instruction pair.

[0062] It is understandable that when optimizing target equivalent concatenated instruction pairs, it will affect the reference or calling relationships between each target equivalent concatenated instruction pair and its corresponding data dependency instructions and all user instructions. Therefore, in the intermediate representation of the program, it is necessary to first eliminate the impact of optimizing each target equivalent concatenated instruction pair, and then delete each target equivalent concatenated instruction pair after the impact is eliminated, so as to finally complete the optimization of the DMA control program.

[0063] This invention, through obtaining an intermediate program representation matching the DMA control program in a multi-stage pipeline scenario; identifying mutually exclusive concatenated instruction pairs with inverse dominance relationships based on the organization logic of each semantic operation instruction in the intermediate program representation; identifying target concatenated instruction pairs that satisfy optimization conditions among each concatenated instruction pair; and deleting each target concatenated instruction pair after performing impact elimination processing on each target concatenated instruction pair in the intermediate program representation based on the data dependency instructions and all user instructions corresponding to each target concatenated instruction pair, while ensuring the rationality of program transformation, can effectively eliminate concatenated instruction pairs that cannot be handled by existing instruction compilers. After the elimination of the above-mentioned concatenated instruction pairs is completed, various instruction compilers can be called normally to smoothly eliminate and optimize the stack pointer of the DMA channel in the DMA control program. This fundamentally improves the performance of the DMA control program developed in a multi-stage pipeline scenario, enhances the configuration performance of the DMA controller and the efficiency of data transfer tasks, and can fully utilize the hardware computing power of the GPU, effectively improving the computing power utilization rate of the GPU computing unit.

[0064] Figure 4This is a flowchart of another DMA control program optimization method provided by an embodiment of the present invention. This embodiment is a further refinement of the above embodiment. In this embodiment, the operation of "identifying the target equivalent concatenation instruction pair" and the operation of "performing the influence elimination processing for each target equivalent concatenation instruction pair in the intermediate representation of the program" are further refined.

[0065] Correspondingly, such as Figure 4 As shown, the method includes:

[0066] S410. Obtain the intermediate representation of the program that matches the DMA control program in the multi-stage pipeline scenario, wherein the intermediate representation of the program includes multiple semantic operation instructions.

[0067] S420. Based on the organization logic of each semantic operation instruction in the intermediate program representation, construct a control flow graph that matches the intermediate program representation, wherein a node in the control flow graph corresponds to a semantic operation instruction in the intermediate program representation.

[0068] The control flow graph can be understood as a directed graph representing the execution path of the DMA control program. Typically, this control flow graph can be a tree structure. That is, the control flow graph can be composed of nodes and edges. Nodes can be understood as semantic operation instructions in the intermediate representation of the program, and edges can be understood as reference relationships or logical execution order between semantic operation instructions.

[0069] It is understandable that the organization logic of each semantic operation instruction in the intermediate representation of the program fully represents the calling relationship between each semantic operation instruction. Each semantic operation instruction is represented by a node, and the calling relationship between each node is represented by the edges between nodes according to the organization logic of each semantic operation instruction in the intermediate representation of the program, thus forming a control flow graph that matches the intermediate representation of the program.

[0070] S430. Analyze the dominance and anti-dominance relationships between nodes in the control flow graph to obtain the set of dominator nodes and the set of anti-dominant nodes corresponding to each node.

[0071] In this context, dominance refers to the relationship between the current node and any path from the entry point of the control program to the current node in the control flow graph. For example, when the control flow graph contains nodes n and d, if all paths from node S0 (representing the entry point of the control program) to node n pass through node d, then node d is said to dominate node n. The dominant node can be the node closer to the entry point of the control program among the two nodes forming a dominance relationship. For instance, if node d dominates node n, then node d is the dominant node of node n.

[0072] The set of dominant nodes can be the union of the current node itself and the dominant nodes of all its predecessor nodes. Here, a predecessor node is a node in the control flow graph that is directly pointed to by a directed edge.

[0073] For example, when the entry node of the control program is S0, the set of dominant nodes {S0}D[n] of a specific node n can be defined as:

[0074] {S0}D[n]={n}∪(∩p∈pred[n]D[p]), for n≠S0.

[0075] Where {n} represents a set containing only node n, ∪ represents the union operation, ∩ represents the intersection operation, ∈ represents belonging, pred[n] represents the predecessor node of node n, p∈pred[n]D[p] represents a set element in the set of all predecessor nodes of node n, and for n≠S0 means that the value of node n is not the entry node S0 of the control program.

[0076] A dominance relationship can refer to the relationship between the current node and any node that must be passed through on any path from the current node to the exit node of the control program in the control flow graph. For example, when the control flow graph contains nodes n and d, if all paths from the current node n to the node E0 representing the exit of the control program pass through node d, then node d is said to be a dominator of node n. A dominator node can be the node closer to the exit node of the control program among the two nodes that constitute a dominance relationship. For example, if node d is a dominator of node n, then node d is a dominator of node n.

[0077] The set of anti-dominant nodes can be the union of the current node itself and the union of the anti-dominant nodes of all its successors. Here, successor nodes are those nodes that the current node directly points to through directed edges in the control flow graph.

[0078] For example, when the exit node of the control program is E0, the set of anti-dominant nodes {E0}Post-D[n] of a specific node n can be defined as:

[0079] {E0}Post-D[n]={n}∪(∪p∈succ[n]D[p]),for n≠E0.

[0080] Where succ[n] represents the successor node of node n, p∈succ[n]D[p] represents a set element in the set of anti-dominant nodes of all successor nodes of node n, and for n≠E0 means that the value of node n is not the program exit node E0.

[0081] It is understandable that by analyzing the path relationships between each node in the control flow graph and the entry and exit nodes of the control program, the dominance and anti-dominance relationships between each node can be determined, thereby obtaining the set of dominator nodes and the set of anti-dominator nodes corresponding to each node.

[0082] S440. Based on the set of dominator nodes and the set of anti-dominator nodes corresponding to each node, select pointer-to-integer instructions and integer-to-pointer instructions that satisfy the preset mutual inverse dominance relationship from each node, and use them as equivalent concatenated instruction pairs.

[0083] The preset reciprocal dominance relationship can be understood as a corresponding dominance and de-dominance relationship. In a simple example, if the pointer-to-integer instruction A and the integer-to-pointer instruction B are determined to be pointer-to-integer and integer-to-pointer instructions that satisfy the preset reciprocal dominance relationship, it means that while pointer-to-integer instruction A dominates integer-to-pointer instruction B, integer-to-pointer instruction B de-dominates pointer-to-integer instruction A.

[0084] It is understandable that the set of dominator nodes and the set of anti-dominator nodes corresponding to each node in the control flow graph contain the dominator nodes and anti-dominator nodes corresponding to all semantic operation instructions. Based on the constraints of the preset mutual dominance relationship, pointer-to-integer instructions and integer-to-pointer instructions that meet the requirements can be selected and formed into corresponding equivalent concatenated instruction pairs, which serve as the operation objects for subsequent optimization processes.

[0085] The inventors discovered through research that for a pointer-to-integer instruction and an integer-to-pointer instruction to form an equivalent concatenated instruction pair, the pointer-to-integer instruction A must be the dominant node of the integer-to-pointer instruction B and at least one multivariate selection instruction C. Simultaneously, the integer-to-pointer instruction B must be the undominant node of the pointer-to-integer instruction A and the aforementioned at least one multivariate selection instruction C. Based on these constraints, one or more equivalent concatenated instruction pairs can ultimately be obtained from the control flow graph.

[0086] Accordingly, in an optional implementation of this embodiment, based on the set of dominator nodes and the set of anti-dominator nodes corresponding to each node, pointer-to-integer instructions and integer-to-pointer instructions that satisfy a preset reciprocal dominance relationship are selected from each node as equivalent concatenated instruction pairs, which may include:

[0087] S4401. Traverse through each node of the control flow graph to obtain a current pointer to integer instruction, and obtain the set of current anti-dominant nodes that match the current pointer to integer instruction.

[0088] Here, the current pointer-to-integer instruction can refer to the pointer-to-integer instruction selected from each node in the control flow graph as the current processing object, serving as the starting point for confirming equivalent concatenated instruction pairs during the optimization process. The current set of anti-dominant nodes can refer to the union of the anti-dominant nodes of the current pointer-to-integer instruction as the current node, including the current node itself and the union of all its successor nodes.

[0089] S4402. Obtain the current integer to pointer instruction identified in the current set of anti-dominant nodes, and obtain the set of current dominant nodes that match the current integer to pointer instruction.

[0090] Here, the current integer-to-pointer instruction can refer to an integer-to-pointer instruction identified in the current set of undominant nodes determined by the current pointer-to-integer instruction. The current set of dominant nodes can refer to the union of the dominant nodes of the current node (with the current integer-to-pointer instruction as the current node) and all its predecessor nodes.

[0091] Understandably, when determining equivalent concatenated instruction pairs, it is necessary to identify matching pointer-to-integer and integer-to-pointer instructions. Instructions of type integer-to-pointer can be selected from the current undominant node set corresponding to the current pointer-to-integer instruction, and used as the current integer-to-pointer instruction. The set of current dominant nodes matching the current integer-to-pointer instruction can then be obtained as the basis for further determining equivalent concatenated instruction pairs.

[0092] S4403. If the current dominator set contains a current pointer to integer instruction, then traverse each node of the control flow graph to obtain multivariate selection instructions that satisfy the defined usage relationship.

[0093] Specifically, if the set of current dominator nodes that matches the current integer to pointer instruction also contains the current pointer to integer instruction, it means that the current pointer to integer instruction and the current integer to pointer instruction satisfy the most basic condition of the preset reciprocal dominance relationship. After that, it is also necessary to determine that there is one or more multivariate selection instructions (i.e., the aforementioned PHI instruction) that also meet the reciprocal dominance relationship between the two.

[0094] Among them, a multi-variable selection instruction can refer to an instruction that selects one integer data from the output integer data of multiple pointer-to-integer instructions as the input data of an integer-to-pointer instruction.

[0095] In a specific example, if a multivariate selection instruction, such as PHI instruction 1, defines (Def) a variable that is actually used by other instructions in the DMA control program, thus forming a clear, static data dependency, then PHI instruction 1 can be understood as a multivariate selection instruction that satisfies the defined usage relationship.

[0096] S4404. If it is determined that the set of the dominant nodes of at least one target multivariate selection instruction contains a current pointer to integer instruction and the set of the dedominant nodes contains a current integer to pointer instruction, then the current pointer to integer instruction and the current integer to pointer instruction form an equivalent concatenated instruction pair.

[0097] Among them, the target multivariate selection instruction can be a multivariate selection instruction in the control flow graph that satisfies the condition that the set of dominant nodes contains the instruction to convert the current pointer to an integer, and the set of anti-dominant nodes contains the instruction to convert the current integer to a pointer. In addition, the above multivariate selection instruction also needs to satisfy the defined usage relationship.

[0098] If one or more target multivariate selection instructions can be further identified for the current pointer to integer instruction and the current integer to pointer instruction identified above, then the current pointer to integer instruction and the current integer to pointer instruction can be combined into an equivalent concatenated instruction pair.

[0099] S4405, Return to the operation of traversing through each node to obtain a current pointer to integer instruction, until all pointer to integer instructions in the control flow graph have been processed.

[0100] Understandably, each pointer-to-integer instruction in the control flow graph can be treated as the current pointer-to-integer instruction, and the corresponding equivalent concatenated instruction pairs can be identified starting from this point, following the steps described above. By iterating through and processing all pointer-to-integer instructions, all equivalent concatenated instruction pairs in the control flow graph can be determined.

[0101] S450. In the intermediate representation of the program, locate the initial definition instruction corresponding to the pointer-to-integer instruction in the current equivalent concatenation instruction pair, and the current definition usage chain pointing from the initial definition instruction to the pointer-to-integer instruction.

[0102] Here, the currently equivalent concatenated instruction pair refers to the pair of equivalent concatenated instructions currently being processed, confirmed by the concatenation relationship between pointer-to-integer instructions and integer-to-pointer instructions. The initial definition instruction refers to the instruction used to explicitly assign a value to the pointer-type data input by the pointer-to-integer instruction for the first time. The current definition-use chain refers to the definition-use chain formed from the initial definition (Def) of the pointer-type data input by the current pointer-to-integer instruction to its eventual passing as an input operand (User) to the pointer-to-integer instruction in the current equivalent concatenated instruction pair.

[0103] Furthermore, in combination Figure 2 If we determine that the two instructions corresponding to the lines containing %878 and %ptr16 together form the current equivalent concatenated instruction pair, we can perform a forward traversal starting from the pointer-to-integer instruction corresponding to %878. Ultimately, we obtain the initial definition instruction for this pointer-to-integer instruction as the alloca instruction corresponding to the line containing %11. Then, we can obtain the current definition usage chain composed of the instructions corresponding to the lines containing %11-%767-%768-%878.

[0104] S460. When it is determined that the initial definition instruction is a unique fixed stack memory allocation instruction and all semantic operation instructions in the current definition usage chain are equivalent transformation instructions, the current equivalent concatenation instruction pair is identified as the target equivalent concatenation instruction pair.

[0105] Fixed stack memory allocation instructions refer to instructions used during program execution to allocate a fixed-size memory space for data or variables in the stack memory region; that is, instructions of the form A0 = alloca ptr. Equivalent transformation instructions refer to instructions that do not change the content at the address pointed to by a pointer.

[0106] Optionally, determining that all semantic operation instructions in the current definition's usage chain are equivalent transformation instructions may include:

[0107] Each semantic operation instruction in the current definition usage chain is matched with a pre-built equivalent transformation instruction library, which includes: bit conversion instructions, address space conversion instructions, and element pointer fetching instructions where all operands are constants;

[0108] If all semantic operation instructions in the current definition use chain fall into the equivalent transformation instruction library, then it is determined that each semantic operation instruction in the current definition use chain is an equivalent transformation instruction.

[0109] Bitcast instructions are instructions that perform specific operations on the binary bits of data (such as bit order adjustment, bit width conversion, and sign bit manipulation) to transform the data's bit-level format or representation. Address space conversion instructions (AddrSpaceCast instructions) are instructions used to map or switch the storage address of data or pointers between different address spaces (such as kernel-mode or user-mode address spaces, and virtual or physical address spaces). Element pointer acquisition instructions (GetElementPtr instructions) are instructions used to calculate and retrieve the memory address of a specific element in a complex data type such as an array or structure, where all operands, including the starting address and data offset, are constants.

[0110] Understandably, when determining whether each semantic operation instruction in the current definition usage chain is an equivalent transformation instruction, it can be matched with a pre-built equivalent transformation instruction library. The equivalent transformation instruction library includes: bit conversion instructions, address space conversion instructions, and element pointer fetching instructions where all operands are constants. That is, all instructions in the equivalent transformation instruction library are instructions that only operate on constants.

[0111] S470. In the current target equivalent concatenation instruction pair, obtain the current target integer to pointer instruction and the current target pointer to integer instruction.

[0112] Here, the current target equivalent concatenation instruction pair can refer to the target equivalent concatenation instruction pair currently undergoing optimization. The current target integer-to-pointer instruction and the current target pointer-to-integer instruction are two instructions contained in this current target equivalent concatenation instruction pair.

[0113] S480. Obtain all currently used user instructions from the intermediate representation of the program for the current target integer to pointer instruction.

[0114] Here, the current user instruction can refer to all semantic operation instructions that output pointer type data using the current target integer-to-pointer instruction.

[0115] Understandably, in order to eliminate the impact of the current target integer to pointer instruction during program optimization, it is necessary to identify all instructions that use pointer type data output by the current target integer to pointer instruction, i.e., the current user instructions, so that the impact of the current user instructions can be eliminated.

[0116] S490. Create a new target variable name and update all current user instructions' references to the current target integer-to-pointer instruction to references to the target variable name.

[0117] As mentioned earlier, since each current user instruction uses the pointer type data output by the current target integer-to-pointer instruction, that is, it references the current target integer-to-pointer instruction. Therefore, in order to remove the current target integer-to-pointer instruction during program optimization, it is necessary to modify the references to the pointer type data output by the current target integer-to-pointer instruction in all current user instructions. For example, they can be uniformly modified to reference a specific target variable name.

[0118] The target variable name can be preset according to actual needs, and this embodiment does not impose any restrictions on it. For example, when the pointer type data output by the current target integer-to-pointer instruction is named ABC, a target variable name of the form ABC_1 can be easily constructed.

[0119] Understandably, when optimizing the current target integer-to-pointer instruction, in order to avoid affecting all current user instructions that reference its output pointer type data, an equivalent target variable name representing its output pointer type data can be created, and the part of the corresponding current user instructions that references the pointer type data output by the current target integer-to-pointer instruction can be replaced.

[0120] S4100: Obtain the current data dependency instruction used to generate the input operand of the current target pointer to integer instruction in the intermediate representation of the program, and copy the instruction corresponding to the current data dependency instruction.

[0121] Here, the current data-dependent instruction can refer to the instruction that generates the operation data for the current target semantic operation instruction input. The instruction copy can refer to a new semantic operation instruction that has the same function as the copied semantic operation instruction, and whose input and output data are identical to the copied semantic operation instruction.

[0122] S4110. Locate the target insertion position in the intermediate representation of the program that can control all current user instructions.

[0123] The target insertion position can refer to a node position that can form a dominant relationship with all current user instructions.

[0124] Optionally, locating the target insertion point in the intermediate representation of the program that can control all current user instructions may include:

[0125] Obtain the definition and usage chain of each current user instruction in the intermediate program representation, and determine the convergence point of each definition and usage chain in the intermediate program representation as the target insertion position.

[0126] The convergence point location can refer to the node location that is included in the definition and usage chain of all currently used user instructions in the intermediate representation of the program.

[0127] S4120. After updating the output operand of the instruction copy using the target variable name, add the updated instruction copy to the target insertion position and delete the current target equivalent concatenation instruction pair from the intermediate representation of the program.

[0128] Specifically, the output operand of this instruction copy refers to the input data used to input the current target pointer to integer instruction, that is, the input operand of the current target pointer to integer instruction.

[0129] In this embodiment, after updating the output operand of the instruction copy using the target variable name, all subsequent current user instructions can be directly controlled by the output data of the instruction copy. That is, all operands input by the current user instructions are associated with the output operand of the instruction copy. At this time, directly deleting the current target equivalent concatenation instruction pair will not affect the syntax correctness of the intermediate representation of the program.

[0130] Optionally, based on the above embodiments, after deleting each target equivalent concatenation instruction pair, it may further include:

[0131] The general DMA control program optimization strategy is invoked to optimize the intermediate representation of the program after the deletion operation is completed, so as to further optimize the newly emerging optimizable instructions after deleting the equivalent concatenated instruction pairs of each target.

[0132] It is understood that after deleting each target equivalent concatenated instruction pair using the DMA control program optimization method of this invention, the general DMA control program optimization strategy can be invoked again to re-optimize the optimizable instructions, thereby achieving a more comprehensive optimization of the DMA control program. For example, deleting all multivariate selection instructions that satisfy the dominance relationship between the current target pointer-to-integer instruction and the current target integer-to-pointer instruction in the current target equivalent concatenated instruction pair.

[0133] The technical solution of this invention proposes a solution to the problem of poor performance of multi-stage data stream programs under GPU architecture. By using the aforementioned optimization algorithm for "equivalent concatenated instruction pairs", equivalent concatenated instruction pairs that meet specific requirements in the DMA program can be eliminated. Then, based on specific supplementary operations, it can be ensured that after eliminating the equivalent concatenated instruction pairs, the stack pointer in the subsequent DMA channel can be further optimized by existing optimization algorithms, thereby fundamentally optimizing the program performance in this scenario.

[0134] Figure 5 This is a schematic diagram of a DMA control program optimization device provided in an embodiment of the present invention. Figure 5As shown, the device includes: a program intermediate representation acquisition module 510, an equivalent concatenation instruction pair identification module 520, a target equivalent concatenation instruction pair identification module 530, and a target equivalent concatenation instruction pair deletion module 540, wherein:

[0135] The intermediate representation acquisition module 510 is used to identify equivalent concatenated instruction pairs with mutual inverse dominance relationships in the intermediate representation of the program according to the organization logic of each semantic operation instruction in the intermediate representation of the program. The equivalent concatenated instruction pairs include a pointer-to-integer instruction and an integer-to-pointer instruction.

[0136] The target equivalence concatenation instruction pair identification module 520 is used to identify target equivalence concatenation instruction pairs that satisfy optimization conditions among various equivalence concatenation instruction pairs.

[0137] The target equivalent concatenation instruction pair deletion module 530 is used to perform impact elimination processing on each target equivalent concatenation instruction pair in the intermediate program representation based on the data dependency instructions corresponding to each target equivalent concatenation instruction pair and all user instructions, and then delete each target equivalent concatenation instruction pair to optimize the DMA control program 540.

[0138] This invention, through obtaining an intermediate program representation matching the DMA control program in a multi-stage pipeline scenario; identifying mutually exclusive concatenated instruction pairs with inverse dominance relationships based on the organization logic of each semantic operation instruction in the intermediate program representation; identifying target concatenated instruction pairs that satisfy optimization conditions among each concatenated instruction pair; and deleting each target concatenated instruction pair after performing impact elimination processing on each target concatenated instruction pair in the intermediate program representation based on the data dependency instructions and all user instructions corresponding to each target concatenated instruction pair, while ensuring the rationality of program transformation, can effectively eliminate concatenated instruction pairs that cannot be handled by existing instruction compilers. After the elimination of the above-mentioned concatenated instruction pairs is completed, various instruction compilers can be called normally to smoothly eliminate and optimize the stack pointer of the DMA channel in the DMA control program. This fundamentally improves the performance of the DMA control program developed in a multi-stage pipeline scenario, enhances the configuration performance of the DMA controller and the efficiency of data transfer tasks, and can fully utilize the hardware computing power of the GPU, effectively improving the computing power utilization rate of the GPU computing unit.

[0139] Optionally, the equivalent concatenation instruction pair identification module 520 may specifically include:

[0140] The control flow graph construction unit is used to construct a control flow graph that matches the intermediate program representation based on the organization logic of each semantic operation instruction in the intermediate program representation. In this control flow graph, a node corresponds to a semantic operation instruction in the intermediate program representation.

[0141] The key set acquisition unit is used to parse the dominance and anti-dominance relationships between nodes in the control flow graph and obtain the set of dominators and anti-dominants corresponding to each node.

[0142] The equivalent concatenation instruction pair filtering unit is used to filter out pointer-to-integer instructions and integer-to-pointer instructions that satisfy a preset mutual inverse domination relationship from each node, based on the set of dominator nodes and the set of anti-dominator nodes corresponding to each node, and to use them as equivalent concatenation instruction pairs.

[0143] Optionally, the equivalent cascade instruction pair filtering unit can be specifically used for:

[0144] Traverse each node in the control flow graph to obtain a current pointer-to-integer instruction, and obtain the set of current de-dominant nodes that match the current pointer-to-integer instruction; obtain the current integer-to-pointer instruction identified in the current de-dominant node set, and obtain the set of current dominant nodes that match the current integer-to-pointer instruction; if the current dominant set contains a current pointer-to-integer instruction, traverse each node in the control flow graph to obtain multivariate selection instructions that satisfy the defined usage relationship; if it is determined that the dominant node set of at least one target multivariate selection instruction contains a current pointer-to-integer instruction, and the de-dominant node set contains a current integer-to-pointer instruction, then determine that the current pointer-to-integer instruction and the current integer-to-pointer instruction form an equivalent concatenated instruction pair; return to execute the operation of traversing each node to obtain a current pointer-to-integer instruction, until all pointer-to-integer instructions in the control flow graph have been processed.

[0145] Optionally, the target equivalent concatenation instruction pair identification module 530 may specifically include:

[0146] The key information locating unit is used to locate, in the intermediate representation of the program, the initial definition instruction corresponding to the pointer-to-integer instruction in the current equivalent concatenated instruction pair, and the current definition usage chain pointing from the initial definition instruction to that pointer-to-integer instruction.

[0147] The target instruction identification unit is used to identify the current equivalent concatenation instruction pair as the target equivalent concatenation instruction pair when it is determined that the initial definition instruction is a unique fixed stack memory allocation instruction and all semantic operation instructions in the current definition usage chain are equivalent transformation instructions.

[0148] Optionally, the key information location unit can be specifically used for:

[0149] Each semantic operation instruction in the current definition usage chain is matched against a pre-built equivalent transformation instruction library, which includes bit conversion instructions, address space conversion instructions, and element pointer fetching instructions where all operands are constants. If all semantic operation instructions in the current definition usage chain fall into the equivalent transformation instruction library, then each semantic operation instruction in the current definition usage chain is determined to be an equivalent transformation instruction.

[0150] Optionally, the target equivalent concatenation instruction pair for the deletion module 540 may specifically include:

[0151] The target instruction acquisition unit is used to acquire the current target integer-to-pointer instruction and the current target pointer-to-integer instruction from the current target equivalent concatenated instruction pair.

[0152] The user instruction acquisition unit is used to acquire all current user instructions from the intermediate representation of the program, including the current target integer to pointer instruction.

[0153] The reference update unit is used to create a new target variable name and update all current user instructions' references to the current target integer-to-pointer instruction to references to the target variable name.

[0154] The instruction copying unit is used to obtain the current data-dependent instruction in the intermediate program representation that is used to generate the input operand of the current target pointer to integer instruction, and to copy the instruction corresponding to the current data-dependent instruction.

[0155] The insertion position determination unit is used to locate the target insertion position in the intermediate representation of the program that can control all current user instructions.

[0156] The actual insertion processing unit is used to update the output operand of the instruction copy with the target variable name, add the updated instruction copy to the target insertion position, and delete the current target equivalent concatenation instruction pair from the intermediate representation of the program.

[0157] Optionally, the insertion position determination unit can be specifically used for:

[0158] Obtain the definition and usage chain of each current user instruction in the intermediate program representation, and determine the convergence point of each definition and usage chain in the intermediate program representation as the target insertion position.

[0159] Optionally, it may also include a general program optimization module for:

[0160] The general DMA control program optimization strategy is invoked to optimize the intermediate representation of the program after the deletion operation is completed, so as to further optimize the newly emerging optimizable instructions after deleting the equivalent concatenated instruction pairs of each target.

[0161] The DMA control program optimization device provided in the embodiments of the present invention can execute the DMA control program optimization method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0162] Figure 6 A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0163] like Figure 6 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0164] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0165] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as performing an optimization method of the DMA control program as described in any embodiment of the present invention.

[0166] That is, to obtain the intermediate representation of the program that matches the DMA control program in a multi-stage pipeline scenario, wherein the intermediate representation of the program includes multiple semantic operation instructions;

[0167] Based on the organization logic of each semantic operation instruction in the intermediate representation of the program, identify each pair of equivalent concatenated instructions with a mutual inverse dominance relationship in the intermediate representation of the program. Among them, the pair of equivalent concatenated instructions includes a pointer to integer instruction and an integer to pointer instruction.

[0168] In each pair of equivalent concatenated instructions, identify the target pair of equivalent concatenated instructions that satisfies the optimization conditions;

[0169] Based on the data dependency instructions corresponding to each target equivalent concatenation instruction pair and all user instructions, the impact elimination processing for each target equivalent concatenation instruction pair is performed in the intermediate program representation, and then each target equivalent concatenation instruction pair is deleted to optimize the DMA control program.

[0170] In some embodiments, the optimization method of the DMA control program as described in any embodiment of the present invention can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the optimization method of the DMA control program as described above in any embodiment of the present invention can be performed. Alternatively, in other embodiments, processor 11 can be configured to perform the optimization method of the DMA control program as described in any other suitable manner (e.g., by means of firmware).

[0171] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0172] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0173] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0174] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0175] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0176] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0177] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0178] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An optimization method for a direct memory access (DMA) control program, characterized by, The method comprises the following steps: acquiring a program intermediate representation matched with a DMA control program in a multi-stage pipeline scene, wherein the program intermediate representation comprises a plurality of semantic operation instructions; identifying, in the program intermediate representation, a pair of equivalent cascade instructions having a mutual inverse dominance relationship according to the organization logic of each semantic operation instruction in the program intermediate representation, wherein the pair of equivalent cascade instructions comprises a pointer-to-integer instruction and an integer-to-pointer instruction; identifying, in each pair of equivalent cascade instructions, a target pair of equivalent cascade instructions satisfying an optimization condition; after performing influence elimination processing on each target pair of equivalent cascade instructions in the program intermediate representation according to data dependency instructions and all user instructions corresponding to each target pair of equivalent cascade instructions, deleting each target pair of equivalent cascade instructions to achieve optimization of the DMA control program.

2. The method of claim 1, wherein, The method of identifying, in the program intermediate representation, a pair of equivalent cascade instructions having a mutual inverse dominance relationship according to the organization logic of each semantic operation instruction in the program intermediate representation comprises: constructing a control flow graph matched with the program intermediate representation according to the organization logic of each semantic operation instruction in the program intermediate representation, wherein one node in the control flow graph corresponds to one semantic operation instruction in the program intermediate representation; parsing the dominance and anti-dominance relationships between the nodes in the control flow graph to acquire a dominator node set and an anti-dominator node set corresponding to each node respectively; screening, in each node, a pointer-to-integer instruction and an integer-to-pointer instruction satisfying a preset mutual inverse dominance relationship as a pair of equivalent cascade instructions according to the dominator node set and the anti-dominator node set corresponding to each node respectively.

3. The method of claim 2, wherein, The method of screening, in each node, a pointer-to-integer instruction and an integer-to-pointer instruction satisfying a preset mutual inverse dominance relationship as a pair of equivalent cascade instructions according to the dominator node set and the anti-dominator node set corresponding to each node respectively comprises: traversing each node in the control flow graph to acquire a current pointer-to-integer instruction and a current anti-dominator node set matched with the current pointer-to-integer instruction; acquiring a current integer-to-pointer instruction identified in the current anti-dominator node set and a current dominator node set matched with the current integer-to-pointer instruction; if the current pointer-to-integer instruction is included in the current dominator set, traversing each node in the control flow graph to acquire a multi-variable selection instruction satisfying a defined use relationship; if it is determined that the dominator node set of at least one target multi-variable selection instruction includes the current pointer-to-integer instruction and the anti-dominator node set includes the current integer-to-pointer instruction, it is determined that the current pointer-to-integer instruction and the current integer-to-pointer instruction form a pair of equivalent cascade instructions; returning to the operation of traversing each node to acquire a current pointer-to-integer instruction until the processing of all pointer-to-integer instructions in the control flow graph is completed.

4. The method of claim 1, wherein, The method of identifying, in each pair of equivalent cascade instructions, a target pair of equivalent cascade instructions satisfying an optimization condition comprises: locating, in the program intermediate representation, an initial definition instruction corresponding to the pointer-to-integer instruction in the current pair of equivalent cascade instructions and a current definition-use chain from the initial definition instruction to the pointer-to-integer instruction; When it is determined that the initial definition instruction is a unique fixed stack memory allocation instruction and each semantic operation instruction in the current definition use chain is an equivalent transformation instruction, the current equivalent cascade instruction pair is identified as a target equivalent cascade instruction pair.

5. The method of claim 4, wherein, The determination that each semantic operation instruction in the current definition use chain is an equivalent transformation instruction comprises: Each semantic operation instruction in the current definition use chain is matched with a pre-constructed equivalent transformation instruction library, wherein the equivalent transformation instruction library includes a bit conversion instruction, an address space conversion instruction, and an element pointer acquisition instruction with all constant operands. If all semantic operation instructions in the current definition use chain fall into the equivalent transformation instruction library, it is determined that each semantic operation instruction in the current definition use chain is an equivalent transformation instruction.

6. The method according to any one of claims 1 to 5, characterized in that, After performing influence elimination processing on each target equivalent cascade instruction pair in the program intermediate representation according to the data dependent instructions and all user instructions corresponding to each target equivalent cascade instruction pair, the target equivalent cascade instruction pair is deleted, comprising: In the current target equivalent cascade instruction pair, a current target integer-to-pointer instruction and a current target pointer-to-integer instruction are obtained. All current user instructions of the current target integer-to-pointer instruction are obtained in the program intermediate representation. A new target variable name is created, and references of all current user instructions to the current target integer-to-pointer instruction are updated to references to the target variable name. A current data dependent instruction for generating an input operand of the current target pointer-to-integer instruction is obtained in the program intermediate representation, and an instruction copy corresponding to the current data dependent instruction is copied. A target insertion position capable of dominating all current user instructions is located in the program intermediate representation. After updating the output operand of the instruction copy using the target variable name, the updated instruction copy is added to the target insertion position, and the current target equivalent cascade instruction pair is deleted from the program intermediate representation.

7. The method of claim 6, wherein, The target insertion position capable of dominating all current user instructions is located in the program intermediate representation, comprising: The definition use chain of each current user instruction is obtained in the program intermediate representation, and the convergence point position of each definition use chain in the program intermediate representation is determined as the target insertion position.

8. The method according to any one of claims 1 to 5, characterized in that, After deleting each target equivalent cascade instruction pair, the method further comprises: A general DMA control program optimization strategy is called to optimize the program intermediate representation after the deletion operation is completed, so as to re-optimize the newly appeared optimizable instructions after deleting each target equivalent cascade instruction pair.

9. An apparatus for optimizing a direct memory access (DMA) control program, the apparatus comprising: Comprise: A program intermediate representation acquisition module is configured to acquire a program intermediate representation matched with a DMA control program in a multi-stage pipeline scenario, wherein the program intermediate representation comprises a plurality of semantic operation instructions. An equivalent cascade instruction pair identification module is configured to identify each equivalent cascade instruction pair having a mutual inverse domination relationship in the program intermediate representation according to an organization logic of each semantic operation instruction in the program intermediate representation, wherein the equivalent cascade instruction pair comprises a pointer-to-integer instruction and an integer-to-pointer instruction. A target equivalent cascade instruction pair identification module is configured to identify a target equivalent cascade instruction pair satisfying an optimization condition from each equivalent cascade instruction pair. The target equivalent cascade instruction pair deletion module is configured to delete each target equivalent cascade instruction pair after performing influence elimination processing for each target equivalent cascade instruction pair in the program intermediate representation according to data dependency instructions respectively corresponding to each target equivalent cascade instruction pair and all user instructions, so as to realize optimization of the DMA control program.

10. An electronic device, comprising: The electronic device includes: at least one processor; and a memory connected to the at least one processor in communication; wherein The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the optimization method of the direct memory access DMA control program according to any one of claims 1-8.

11. A computer readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for enabling the processor to perform the optimization method of the direct memory access DMA control program according to any one of claims 1-8 when executed.

12. A computer program product, characterised in that, The computer program product includes a computer program that, when executed by a processor, implements the optimization method of the direct memory access DMA control program according to any one of claims 1-8.

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