Multi-bit smart erasing method, system, terminal and test chip based on read verification

Abstract

The application provides a multi-bit intelligent erase-write method, system, terminal and test chip based on read verification, which performs integrated cycle read verification and dynamic parameter optimization erase and programming operation on a target RRAM unit in sequence by responding to an external WRITE instruction. In the erase phase, the unit resistance state change is continuously monitored, the voltage amplitude and pulse timing are dynamically optimized based on an intelligent algorithm, and the high resistance state is ensured to be accurately and stably formed. Then, the programming phase is automatically entered, the same closed-loop control mechanism is adopted to realize low resistance state high-precision programming operation, and the instruction execution is terminated after verification. The intelligent erase-write method effectively solves the key technical bottlenecks in the commercial application of RRAM at the circuit design level, including the resistance value dispersion of the storage unit, the narrow read operation window, the read interference sensitivity, the programming success rate fluctuation, the insufficient current limiting control precision, the durability degradation and the data retention failure, and significantly improves and perfects the array consistency and long-term reliability of the RRAM chip.

Description

Technical Field

[0001] This invention relates to the field of analog circuit design technology, and in particular to a multi-bit intelligent erasure and write method, system, terminal and test chip based on read verification. Background Technology

[0002] Resistive Random-Access Memory (RRAM) has become a strong contender for next-generation non-volatile memory due to its significant advantages, such as simple device structure, miniaturized cell size, wide high and low resistance state windows, and ease of 3D integration. However, RRAM technology still faces multiple challenges in its critical stage towards commercial application: the inherent discreteness of resistance state distribution between memory cells leads to narrowing of array-level operation tolerance, and the read operation window is prone to misjudgment due to noise interference; the randomness of conductive filament formation during programming operations causes fluctuations in success rate, especially in multi-value storage modes; erasable and rewritable durability is limited by dielectric layer electromigration and thermal damage accumulation, making it difficult to meet the needs of high-frequency data update scenarios; long-term data retention capability is significantly reduced due to interface state defects and charge trap effects. These core problems are essentially constrained by the dual limitations of the intrinsic properties of device materials and the precision of process technology. Although some performance improvements have been achieved through material system optimization and process improvement, device-level optimization is still unable to completely eliminate the above bottlenecks due to the limited depth of understanding of material mechanisms and the precision of process control. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a multi-bit intelligent erasure and write method, system, terminal and test chip based on read verification, which can solve the technical problems of existing RRAM chips, such as the differences between RRAM storage cells, the window of read operation, read interference, success rate of programming operation, current limit of programming operation, number of erasure and write cycles, data retention time and device defects.

[0004] To achieve the above and other related objectives, the present invention provides a multi-bit intelligent erasure and write method based on read verification. The method includes: responding to a WRITE instruction from an external source, performing an erasure phase process on the current RRAM cell that integrates a read verification loop and an intelligent parameter adjustment mechanism; after the erasure phase is completed, performing a programming phase process on the current RRAM cell that integrates a read verification loop and an intelligent parameter adjustment mechanism, and exiting the WRITE instruction after the programming phase is completed.

[0005] In one embodiment of the present invention, the erasure phase process includes: configuring RESET-related parameters of the current RRAM cell; wherein, the RESET-related parameters include: operating voltage, target write data, pulse width, and reference resistance value; reading the stored data to be RESET operated on in the current RRAM cell using a read verification method; comparing the read data with the target write data to determine whether it meets expectations; if it meets expectations, the erasure phase of the current RRAM cell is completed; if it does not meet expectations, sending the read data to combinational logic for processing to generate RESET operation stimulus data, updating the operating voltage and pulse width to perform RESET operation on the current RRAM cell, and performing read verification again based on the updated RESET-related parameters until the read data meets expectations.

[0006] In one embodiment of the present invention, the programming stage process includes: configuring SET-related parameters of the current RRAM cell; wherein the SET-related parameters include: operating voltage, target write data, pulse width, and reference resistance value; reading the stored data to be SET operated on in the current RRAM cell using a read verification method; comparing the read data with the target write data to determine whether it meets expectations; if it meets expectations, the programming stage is completed; if it does not meet expectations, the read data is sent to combinational logic for processing to generate SET operation stimulus data, and the operating voltage and pulse width are updated to perform SET operation on the current RRAM cell, and read verification is performed again based on the updated SET-related parameters until the read data meets expectations.

[0007] In one embodiment of the present invention, the erase stage process includes: configuring RESET-related parameters of the current RRAM cell according to the pre-stored configuration information in the register; wherein, the RESET-related parameters include: operating voltage, initial pulse width, repeated operating pulse width, and reference resistance value; triggering an external EXECUTE signal to latch the target address and input data of the current RRAM cell; triggering two read verification operations in sequence to read the data on both sides of the differential structure in turn; comparing the input data with the read data to determine whether the 8-bit data meets the expectation; if it meets the expectation, the erase stage is completed; if it does not meet the expectation, the read data is sent to combinational logic for processing to obtain the excitation signals of each terminal required in the RESET operation, and increasing the operating voltage when the current RRAM cell is not undergoing its first RESET operation, performing a RESET operation on the current RRAM cell according to the latched target address, and then performing read verification again according to the updated RESET-related parameters until the read data meets the expectation.

[0008] In one embodiment of the present invention, the programming stage process includes: configuring the SET-related parameters of the current RRAM cell according to the pre-stored configuration information in the register; wherein, the SET-related parameters include: the gate voltage of the select transistor, the operating voltage, the initial pulse width, the limiting current, and the reference resistance value; triggering an external EXECUTE signal to latch the target address and input data; triggering two read verification operations in sequence to read the data on both sides of the differential structure in turn; comparing the input data with the read data to determine whether the 8-bit data meets the expectation; if it meets the expectation, the programming stage is completed; if it does not meet the expectation, the read data is sent to combinational logic for processing to obtain the excitation signals of each terminal required in the SET operation, and increasing the operating voltage when the current RRAM cell is not performing the first SET operation, performing the SET operation on the current RRAM cell according to the latched target address, and then performing read verification again according to the updated SET-related parameters until the read data meets the expectation.

[0009] In one embodiment of the present invention, after the erasure phase of the current RRAM cell is completed, a flag signal is returned. When the flag is pulled high, the programming phase process is executed for the current RRAM cell. After each RESET operation on the current RRAM cell, a counter is used to count, and when the RESET operation of the RRAM cell reaches the configured value, the erasure phase process is terminated and a RESET failure flag signal is returned. When the flag is pulled high, the current RRAM cell continues to execute the programming phase process.

[0010] In one embodiment of the present invention, after the programming phase of the current RRAM cell is completed, a flag signal is returned. When the signal is pulled high, the WRITE instruction is exited. After each SET operation on the current RRAM cell, a counter is used to count, and when the SET operation of the RRAM cell reaches the configured value, the erase phase process is terminated and a SET failure flag signal is returned.

[0011] To achieve the above and other related objectives, the present invention provides a multi-bit intelligent erasure and write system based on read verification, comprising: an erasure phase control module, used to respond to an external WRITE command and execute an erasure phase process integrating a read verification loop and an intelligent parameter adjustment mechanism on the current RRAM cell; and a programming phase control module, connected to the erasure phase control module, used to execute a programming phase process integrating a read verification loop and an intelligent parameter adjustment mechanism on the current RRAM cell after the erasure phase is completed, and to exit the WRITE command after the programming phase is completed.

[0012] To achieve the above and other related objectives, the present invention provides an electronic terminal, comprising: one or more memories and one or more processors; the one or more memories are used to store a computer program; the one or more processors are connected to the memories and are used to run the computer program to execute the read-verification-based multi-bit intelligent erasure and write method.

[0013] To achieve the above and other related objectives, the present invention provides a test chip, comprising: multiple RRAM cells and the read-verification-based multi-bit intelligent erase / write system.

[0014] As described above, this invention is a multi-bit intelligent erase / write method, system, terminal, and test chip based on read verification, which has the following beneficial effects: This invention, in response to an external WRITE command, sequentially performs erase and programming operations on the target RRAM cell, integrating cyclic read verification and dynamic parameter optimization. During the erase phase, the cell resistance state change is continuously monitored, and the voltage amplitude and pulse timing are dynamically optimized based on an intelligent algorithm to ensure accurate and stable formation of a high-resistance state. Subsequently, it automatically transitions to the programming phase, employing the same closed-loop control mechanism to achieve high-precision programming operations in a low-resistance state, and terminates instruction execution after successful verification. This invention effectively solves key technical bottlenecks in the commercial application of RRAM at the circuit design level through an intelligent erase / write method, including core issues such as the discreteness of memory cell resistance values, narrow read operation windows, sensitivity to read interference, fluctuations in programming success rates, insufficient current limiting control accuracy, durability degradation, and data retention failure, significantly improving and perfecting the array consistency and long-term reliability of RRAM chips. Attached Figure Description

[0015] Figure 1 The diagram shown is a flowchart of a multi-bit intelligent erasing and writing method based on read verification according to an embodiment of the present invention.

[0016] Figure 2 The diagram shown is a flowchart of the Write algorithm according to an embodiment of the present invention.

[0017] Figure 3 The diagram shown is a flowchart of the intelligent RESET algorithm in one embodiment of the present invention.

[0018] Figure 4 This is a schematic representation of the combinational logic truth value for data processing in a RESET operation according to an embodiment of the present invention.

[0019] Figure 5 The diagram shown is a specific timing diagram of the RESET intelligent algorithm implementation in one embodiment of the present invention.

[0020] Figure 6 The diagram shown is a flowchart of the intelligent SET algorithm according to an embodiment of the present invention.

[0021] Figure 7 This is a schematic representation of the combinational logic truth value in the SET operation of an embodiment of the present invention.

[0022] Figure 8 The diagram shown is a specific timing diagram of the SET intelligent algorithm implementation in one embodiment of the present invention.

[0023] Figure 9 The chart shown is a comparison of the performance and reliability of the algorithm of the present invention and traditional algorithm products in one embodiment of the present invention.

[0024] Figure 10 The diagram shown is a structural schematic of a multi-bit intelligent erasing and writing system based on read verification according to an embodiment of the present invention.

[0025] Figure 11 The diagram shown is a structural schematic of an electronic terminal according to an embodiment of the present invention.

[0026] Figure 12 The diagram shown is a schematic representation of the structure of a test chip according to an embodiment of the present invention. Detailed Implementation

[0027] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0028] It should be noted that in the following description, reference is made to the accompanying drawings, which illustrate several embodiments of the invention. It should be understood that other embodiments may also be used, and changes in mechanical composition, structure, electrical system, and operation may be made without departing from the spirit and scope of the invention. The following detailed description should not be considered limiting, and the scope of the embodiments of the invention is defined only by the claims of the published patents. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. Spatially related terms, such as “upper,” “lower,” “left,” “right,” “below,” “below,” “lower part,” “above,” “upper part,” etc., may be used herein to illustrate the relationship between one element or feature shown in the figures and another element or feature.

[0029] Throughout this specification, when it is said that a part is "connected" to another part, this includes not only "direct connection" but also "indirect connection" by placing other elements in between. Furthermore, when it is said that a part "includes" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather means that other constituent elements may also be included.

[0030] The terms "first," "second," and "third," etc., used herein are for the purpose of describing various parts, components, regions, layers, and / or segments, but are not limiting. These terms are used only to distinguish one part, component, region, layer, or segment from others. Therefore, the "first part," "component," "region," "layer," or "segment" described below may refer to a "second part," "component," "region," "layer," or "segment" without departing from the scope of this invention.

[0031] Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, operation, element, component, item, kind, and / or group, but do not preclude the presence, occurrence, or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition arise only when combinations of elements, functions, or operations are inherently mutually exclusive in some manner.

[0032] This invention provides a multi-bit intelligent erase / write method based on read verification. By responding to an external WRITE command, it sequentially performs erase and programming operations on the target RRAM cell, integrating cyclic read verification and dynamic parameter optimization. During the erase phase, it continuously monitors the cell's resistance state change and dynamically optimizes the voltage amplitude and pulse timing based on an intelligent algorithm to ensure accurate and stable formation of a high-resistance state. Subsequently, it automatically transitions to the programming phase, employing the same closed-loop control mechanism to achieve high-precision programming operations in a low-resistance state, and terminates instruction execution after successful verification. This invention effectively solves key technical bottlenecks in the commercial application of RRAM at the circuit design level through its intelligent erase / write method, including core issues such as the dispersion of memory cell resistance values, narrow read operation windows, sensitivity to read interference, fluctuating programming success rates, insufficient current limiting control accuracy, durability degradation, and data retention failure. It significantly improves and enhances the array consistency and long-term reliability of RRAM chips.

[0033] The present invention will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can readily implement it. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0034] like Figure 1 This document presents a flowchart illustrating a multi-bit intelligent erasing and writing method based on read verification, as described in an embodiment of the present invention.

[0035] The method includes:

[0036] Step S1: In response to the WRITE instruction from the outside, execute the erase phase process of the current RRAM cell with integrated read verification loop and intelligent parameter adjustment mechanism.

[0037] Specifically, upon receiving an external WRITE instruction, the erase phase of the current RRAM cell is initiated first. This phase does not simply perform an erase operation with fixed parameters, but rather incorporates a closed-loop control system that includes a read verification loop and intelligent parameter adjustment.

[0038] Step S2: After the erase phase is completed, the programming phase process with integrated read verification loop and intelligent parameter adjustment mechanism is executed on the current RRAM cell, and the WRITE instruction is exited after the programming phase is completed.

[0039] This invention provides a Write algorithm, which includes an erasure phase process and a programming phase process, and will now be described in conjunction with the following embodiments.

[0040] In one embodiment, such as Figure 2 The erase phase of the Write algorithm includes:

[0041] Step 11: Upon receiving an external WRITE instruction, first retrieve the RESET operation parameters required for the current RRAM cell from the configuration register and complete the latching. These parameters include:

[0042] Operating voltage: controls the voltage amplitude during erasure, directly affecting the rate of resistance change;

[0043] Target data to be written: The resistance state to be achieved after the erase operation;

[0044] Pulse width: Defines the duration of voltage application, and together with the operating voltage, determines the erasure energy;

[0045] Margin Read Adjustable Reference Resistor: A resistance comparison threshold used in the read verification phase, which can be dynamically adjusted to improve verification accuracy.

[0046] Step S12: Read the stored data of the current RRAM cell that will undergo a RESET operation using the read verification method; read the stored data of the current RRAM cell using the margin read method. This method enhances signal contrast during reading by setting an adjustable reference resistor (such as a threshold higher / lower than the target resistor), reduces misjudgments caused by noise or process deviations, and ensures the accuracy of the read data.

[0047] Step S13: Compare the read data with the target written data to determine if it meets expectations; compare the read stored data with the target written data bit by bit; if they match, it means that the cell is in the target resistance state (e.g., successfully erased to a low resistance state), the erasure stage is complete, and the subsequent programming stage can be entered; if they do not match, it means that the current resistance has not reached the target, and a RESET operation needs to be triggered to adjust the resistance state, and the adjustment process in step S14 is entered.

[0048] Step S14: If the data is inconsistent, the read data is sent to combinational logic for processing to generate new RESET operation stimulus data. Different strategies are adopted depending on whether it is the first RESET operation:

[0049] The first RESET operation: The RESET operation is performed directly based on the initial parameters, without any adjustment.

[0050] Non-first RESET operation: Update the operating voltage and pulse width (e.g., increase the voltage to speed up the RESET or decrease the voltage to avoid overshoot), and then perform the RESET operation.

[0051] After the operation is completed, return to step S12 (the read verification step in the erase phase) to re-perform the read verification, forming a closed loop of "operation, verification, and adjustment". The loop continues until the data is consistent or the preset maximum number of iterations is reached.

[0052] In one embodiment, such as Figure 2 The programming phase process in the Write algorithm includes:

[0053] Step S15: After the erase phase is completed, retrieve and latch the SET operation parameters required for the current RRAM cell from the configuration register, including:

[0054] Operating voltage: The voltage amplitude when SET is applied, which directly affects the rate at which the resistor transitions from a high resistance state to a low resistance state;

[0055] Target data to be written: The resistance state to be achieved after the programming operation;

[0056] Pulse width: Defines the duration of voltage application, and together with the operating voltage, determines the SET energy;

[0057] Reference resistance value: The resistance comparison threshold used in the verification phase, which can be dynamically adjusted to improve verification accuracy.

[0058] Step S16: Read the stored data of the current RRAM cell that will undergo a SET operation using the read verification method; read the stored data of the current RRAM cell using the margin read method. This method enhances signal contrast during reading by setting a reference resistor value (such as a threshold close to the target resistor), reducing misjudgments caused by noise or process deviations.

[0059] Step S17: Compare the read data with the target written data to determine if it meets expectations; compare the read stored data with the target written data bit by bit: if they match, it means that the cell is in the target resistance state (e.g., successfully SET to high resistance state), and the programming stage is completed; if they do not match, it means that the current resistance has not reached the target, and the SET operation needs to be triggered to adjust the resistance state, and the adjustment process in step S18 is entered.

[0060] Step S18: If the data is inconsistent, the read data will be sent to combinational logic processing to generate new SET operation stimulus data. Different strategies will be adopted depending on whether it is the first SET operation:

[0061] First SET operation: The SET operation is performed directly based on the initial parameters, without any adjustment;

[0062] Non-first SET operation: Update the operating voltage and pulse width (e.g., increase the voltage to speed up SET or decrease the voltage to avoid overshoot), and then perform the SET operation.

[0063] After the operation is completed, return to step S16 (the read verification step in the programming phase) to re-perform the read verification, forming a closed loop of "operation, verification, and adjustment". The loop continues until the data is consistent or the preset maximum number of iterations is reached.

[0064] As shown above, the Write algorithm prevents RRAM cells from being damaged by overcurrent by dynamically limiting the peak operating current during erase (RESET) and program (SET) operations. It also implements pre-write read verification and write verification; that is, before performing a RESET / SET operation, the current cell resistance state is read via margin read. After the operation, the resistance state is read again via margin read and compared with the target data, reducing the risk of erroneous operations and ensuring that each operation accurately reaches the target state. Furthermore, it adapts to the individual differences of different RRAM cells (such as process variations and aging characteristics), achieving precise control.

[0065] To meet the requirements of more precise erasure operations, this invention provides an intelligent RESET algorithm, which will be described in conjunction with the following specific embodiments.

[0066] In one embodiment, such as Figure 3 The erasure phase of the intelligent RESET algorithm includes:

[0067] Step S21: After the external WRITE signal goes high, the system first enters the parameter configuration stage, configuring the RESET-related parameters of the current RRAM cell according to the pre-stored configuration information in the register; wherein, the RESET-related parameters include:

[0068] Operating voltage: Controls the voltage amplitude during RESET operation, directly affecting the rate and effectiveness of the resistor's transition from a low-resistance state to a high-resistance state. A preset voltage value is read from the register; the default voltage is used for the first operation, and subsequent operations are dynamically adjusted based on verification results.

[0069] Initial pulse width: The duration of the voltage application during the first RESET operation, ensuring thorough erasure. A preset initial pulse width is read from the register; the default pulse width is used for the first operation, and subsequent operations are dynamically adjusted based on verification results.

[0070] Repeated operation pulse width: The duration of the voltage application in subsequent RESET operations to avoid over-erasing. Considering that the pulse width of the first RESET operation is relatively long, even for cells that fail to RESET, they have undergone a certain degree of erasure. Therefore, the voltage pulse applied during repeated RESET operations must be controlled to a shorter width. From the perspective of the test chip, we have also made this voltage pulse parameter configurable.

[0071] Reference resistance value: The resistance comparison threshold used in the read verification stage to determine whether the state after erasure meets expectations.

[0072] Step S22: After the parameters are configured, the external EXECUTE signal triggers the latching of the target address and input data to ensure that the operation target is clear and to avoid misoperation caused by address drift or data error.

[0073] Step S23: Trigger two margin read operations in sequence. Based on the latched address, compare the selected storage cell with the configured reference resistor and read the data from both sides of the differential structure in turn.

[0074] Step S24: Compare the input data with the read data to determine if the 8-bit data matches the expectation; specifically, compare the read 8-bit data with the input data bit by bit. If they match completely, the erasure is successful, and the programmable stage begins; if there is a difference, the RESET adjustment process is triggered, and step S25 is executed.

[0075] Step S25: Send the read data to combinational logic for processing to obtain the excitation signals required for each terminal in the RESET operation; specifically, such as... Figure 4 The figure shows the combinational logic truth table for data processing during the RESET operation. Using the control signal D and the storage state Q / QB as inputs, it dynamically determines the bias combination of the bit line (BL) and source line (SL): When D is low, regardless of the storage state, BL / SL maintains no effective voltage difference, preserving the current data; when D is high and triggers a reset, the system intelligently selects the BL / SL bias direction based on the real-time state of Q / QB, driving the storage cell to a high-resistivity state by precisely applying an electric field or Joule heating effect, while avoiding ineffective stress damage to the dielectric layer, thus achieving reliable state-aware reset and device protection.

[0076] Different strategies are adopted depending on whether it is the first RESET operation:

[0077] The first RESET operation: The RESET operation is performed directly based on the initial parameters, without any adjustment.

[0078] Non-first RESET operation: Increase the operating voltage to enhance the erase intensity while keeping the pulse width short (to avoid over-erasing). For example, if the resistance does not reach the target after the first erase, increase the voltage to accelerate the erase; if it is close to the target, maintain or fine-tune the parameters.

[0079] Step S26: In step S22, the target address of the current RRAM cell is latched when the EXECUTE signal is triggered, ensuring that the RESET operation in step S26 is accurately applied to the target cell, avoiding interference between adjacent cells due to address drift or erroneous operation, and ensuring operational reliability. Based on the excitation signal (such as voltage amplitude, pulse sequence, timing control) generated by combinational logic processing, a RESET operation is applied to the RRAM cell corresponding to the latched address. Operation parameters (such as voltage and pulse width) are updated in real time based on the previous read verification result. After the operation is completed, the process returns to step S22 for read verification based on the updated RESET parameters until the read data matches expectations. This loop continues until the data is consistent or the preset maximum number of iterations is reached.

[0080] In one embodiment, when an external WRITE instruction triggers an erase operation, the erase count is initialized; an erase pulse is applied to the current RRAM cell embedding, and the counter automatically increments by 1 upon completion. If the erase phase ends and the counter has not reached the maximum allowed count, the system pulls the "RESET completion flag" high, triggering the subsequent programming phase. If the counter reaches the maximum count but the resistance requirement is still not met, and further erasure is required, the system pulls the "RESET failure flag" high, but does not terminate the process; instead, the programming phase is allowed to continue, with the verification mechanism of the programming phase determining whether to retry.

[0081] like Figure 5The specific timing diagram for the RESET intelligent algorithm implementation is as follows: After the EXECUTE signal is triggered, the system first completes the default parameter configuration (voltage, pulse width, etc.), then starts the erase operation and simultaneously starts a counter to record the number of operations; if the erase verification fails and the maximum number of retries is not reached, the parameters are dynamically adjusted (such as increasing the voltage and shortening the pulse width) to enter the retry stage, and closed-loop verification is performed until success or the maximum number of attempts is reached; if the erase failure flag is set, the system continues to execute the subsequent write process and adopts a compensation strategy. The entire process achieves non-blocking coordination between stages through flag triggering and state machine switching, ensuring fault tolerance and reliability.

[0082] The intelligent RESET algorithm uses a longer pulse width for the first RESET operation to ensure that low-resistance cells are fully converted to high-resistance states, reducing incomplete erasure due to process deviations. After the first operation, the cells are partially erased, and subsequent operations switch to shorter pulses to prevent resistance overshoot or dielectric breakdown caused by excessively long pulses, thus extending cell lifespan. The pulse width and voltage value are pre-stored in registers and can be dynamically modified to adapt to different testing environments. For process deviations, erase efficiency is optimized by adjusting parameters, reducing screening costs in production testing. After each RESET operation, it automatically returns to the read verification stage, comparing the read data with the target value to determine success. If it fails, parameters are dynamically adjusted based on the verification results (e.g., shortening the pulse width, increasing the voltage) until the target state is reached. By modifying parameters, the safe window for cell erasure (e.g., minimum effective pulse width, maximum withstand voltage) can be quickly located, optimizing mass production parameters.

[0083] To meet the requirements of precise programming operations, this invention provides an intelligent SET algorithm, which will now be described in conjunction with the following specific embodiments.

[0084] In one embodiment, such as Figure 6 The programming phase of the intelligent SET algorithm includes:

[0085] Step S31: After the RESET operation is completed, a flag signal will be returned. After this signal goes high, the SET-related parameters of the current RRAM cell will be configured according to the pre-stored configuration information in the register; wherein, the RESET-related parameters include:

[0086] Gate voltage of the selector: controls the selection state of the control unit, ensuring effective connection of the unit during operation.

[0087] Operating voltage: controls the voltage amplitude during SET; reads the preset voltage value from the register, uses the default voltage for the first operation, and dynamically adjusts it based on the verification results thereafter.

[0088] Initial pulse width: The duration of voltage application during the first SET operation. A preset initial pulse width is read from the register; the default pulse width is used for the first operation, and subsequent operations are dynamically adjusted based on verification results.

[0089] Repeated operation pulse width: The voltage application time of subsequent SET operations. Considering that the pulse width of the first SET operation is relatively long, even for cells that fail to SET, they have undergone a certain degree of writing. Therefore, the voltage pulse applied during repeated SET operations must be controlled to a shorter width. From the perspective of the test chip, we have also made the pulse width configurable.

[0090] Current limiting: Set a safe current threshold to prevent overcurrent damage to the unit, monitor the current in real time and dynamically adjust the voltage / pulse.

[0091] Reference resistance value: The resistance comparison threshold used in the verification phase to determine whether the programmed state meets expectations.

[0092] Step S32: After the parameters are configured, the external EXECUTE signal triggers the latching of the target address and input data to ensure that the SET operation target is clear and to avoid misoperation caused by address drift or data error.

[0093] Step S33: Trigger two margin read operations in sequence. Based on the latched address, compare the selected storage cell with the configured reference resistor and read the data from both sides of the differential structure in turn.

[0094] Step S34: Compare the input data with the read data to determine if the 8-bit data matches the expectation; specifically, compare the read 8-bit data with the input data bit by bit. If they match completely, the write is successful; if there is a difference, the SET adjustment process is triggered, and step S35 is executed.

[0095] Step S35: The read data is sent to combinational logic for processing to obtain the excitation signals required for each terminal in the RESET operation; such as Figure 7This is the combinational logic truth table for data processing in the SET operation. It takes the memory state Q / QB and the operation enable signal D as inputs to dynamically determine the bias combination of the bit line (BL) and source line (SL). When D=0 (non-SET mode), regardless of the Q / QB state, the BL / SL bias combination remains invalid (NA) or at its default value, avoiding the application of effective operating voltage to the memory cell. When D=1 (SET mode activated), the system intelligently selects the bias strategy based on the current Q / QB state: if the memory cell is in an operable state (e.g., Q / QB=0 / 1 or 1 / 0), a specific BL / SL voltage combination is applied to drive low-impedance writing; if the state is an invalid combination (e.g., Q / QB=0 / 0 or 1 / 1), it is marked as NA, indicating no operation is required or the state is unreachable. This state-aware bias control achieves precise and reliable SET operation while avoiding unnecessary stress damage.

[0096] Different strategies are adopted depending on whether it is the first RESET operation:

[0097] First SET operation: The SET operation is performed directly based on the initial parameters, without any adjustment;

[0098] Non-first SET operation: Increase the operating voltage to enhance write strength while keeping the pulse width short;

[0099] Step S36: In step S32, when the EXECUTE signal is triggered, the target address of the current RRAM cell has been latched. Based on the latched address and the excitation signal generated by combinational logic processing, a SET operation is performed on the current RRAM cell. Then, based on the updated SET-related parameters, the process returns to step S32 to perform read verification until the read data meets expectations.

[0100] In one embodiment, when an external WRITE instruction triggers a programming operation, the programming count is initialized; a programming pulse is applied to the current RRAM cell embedding, and the counter automatically increments by 1 upon completion. If the programming phase ends and the counter has not reached the maximum allowed count, the system pulls the "SET completion flag" high and exits the WRITE instruction. If the counter reaches the maximum count but the resistance requirement is still not met and writing needs to continue, the system pulls the "SET failure flag" high.

[0101] like Figure 8The following is a specific timing diagram for the implementation of the SET intelligent algorithm. After the RESET flag signal (RESET_DONE) is triggered, the system synchronously starts the SET operation based on the clock CLK. First, the default parameter configuration (voltage, pulse width, etc.) is completed, and then the SET operation is started and the counter is started synchronously to record the number of operations. If the SET verification fails and the maximum number of retries is not reached, the parameters are dynamically adjusted (such as increasing the voltage and shortening the pulse width) to enter the retry stage. The closed-loop verification continues until success or the maximum number of attempts is reached. The parameter adjustment is not activated before the first operation. The multi-stage seamless switching is achieved through signal cascading and state latching, which ultimately ensures that the data is accurately programmed into the low-impedance state.

[0102] The intelligent SET algorithm uses a longer pulse width for the first SET operation to ensure that low-resistance cells are fully converted to high-resistance states, reducing incomplete programming due to process deviations. After the first operation, the cell is partially programmed, and subsequent operations switch to shorter pulses to prevent resistor overshoot or dielectric breakdown caused by excessively long pulses, thus extending cell lifespan. Pulse width and voltage values ​​are pre-stored in registers and can be dynamically modified to adapt to different testing environments. For process deviations, programming efficiency is optimized by adjusting parameters, reducing screening costs in production testing. After each SET operation, it automatically returns to the read verification stage, comparing the read data with the target value to determine success. If it fails, parameters are dynamically adjusted based on the verification results (e.g., shortening the pulse width, increasing the voltage) until the target state is reached. By modifying parameters, the safe window for cell programming (e.g., minimum effective pulse width, maximum withstand voltage) is quickly located, optimizing mass production parameters.

[0103] This invention innovatively integrates an intelligent algorithm system within the existing technological framework. Through optimization of multiple technologies, the cycle durability and data retention time of RRAM storage cells can be further improved. Compared to write operations without auxiliary technologies, the estimated cycle durability of RRAM cells can be improved by more than one order of magnitude. Figure 9 As shown, accelerated lifetime comparison tests based on 3000 samples demonstrate that the storage cell using this patented algorithm exhibits significant advantages in key parameters such as initial resistance uniformity and residual current (low resistance Ion / high resistance Ioff) after high-cycle fatigue. This verifies the effective suppression of dielectric layer damage accumulation and the long-term stability guarantee of the resistance window by the intelligent algorithm, providing key technical support for high-reliability in-memory computing and persistent storage applications.

[0104] Similar to the principles of the above embodiments, the present invention provides a multi-bit intelligent erasing and writing system based on read verification.

[0105] The following specific embodiments are provided in conjunction with the accompanying drawings:

[0106] like Figure 10This diagram illustrates the structure of a multi-bit intelligent erasing and writing system based on read verification, according to an embodiment of the present invention. The system includes:

[0107] Erasure phase control module 1 is used to respond to the WRITE command from the outside and execute the erase phase process of the current RRAM cell with an integrated read verification loop and intelligent parameter adjustment mechanism.

[0108] The programming stage control module 2 is connected to the erasure stage control module 1. It is used to execute the programming stage process of the current RRAM cell with integrated read verification loop and intelligent parameter adjustment mechanism after the erasure stage is completed, and exit the WRITE instruction after the programming stage is completed.

[0109] Since the implementation principle of the multi-bit intelligent erasure and write system based on read verification has been described in the foregoing embodiments, it will not be repeated here.

[0110] The multi-bit intelligent erasure and write method based on read verification provided in this invention can be implemented on the terminal side or the server side. For the hardware structure of the electronic terminal, please refer to [link to relevant documentation]. Figure 11 This is a schematic diagram of an optional hardware structure of an electronic terminal 1000 provided in an embodiment of the present invention. The electronic terminal 1000 can be a mobile phone, computer device, tablet device, personal digital processing device, factory back-end processing device, etc. The electronic terminal 1000 includes: at least one processor 1001, a memory 1002, at least one network interface 10010, and a user interface 1009. The various components in the device are coupled together through a bus system 1005. It is understood that the bus system 1005 is used to realize the connection and communication between these components. In addition to a data bus, the bus system 1005 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 11 The general will label all buses as bus systems.

[0111] The user interface 1009 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0112] It is understood that memory 1002 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.

[0113] In this embodiment of the invention, the memory 1002 is used to store various types of data to support the operation of the electronic terminal 1000. Examples of this data include: any executable program that operates on the electronic terminal 1000, such as the operating system 10021 and application programs 10022; the operating system 10021 contains various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application program 10022 may contain various applications, such as a media player, browser, etc., for implementing various application services. The multi-bit intelligent erasure and write method based on read verification provided in this embodiment of the invention can be included in the application program 10022.

[0114] The methods disclosed in the above embodiments of the present invention can be applied to or implemented by the processor 1001. The processor 1001 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in the processor 1001 or by instructions in the form of software. The processor 1001 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 1001 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor 1001 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in a memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0115] In an exemplary embodiment, the electronic terminal 1000 may be used by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs) to execute the aforementioned method.

[0116] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented using computer program-related hardware. The aforementioned computer program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0117] In the embodiments provided in this application, the computer-readable and writable storage medium may include read-only memory, random access memory, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, flash memory, USB flash drive, portable hard drive, or any other medium capable of storing desired program code in the form of instructions or data structures and accessible by a computer. Additionally, any connection may be appropriately referred to as a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. However, it should be understood that computer-readable and writable storage media and data storage media do not include connections, carrier waves, signals, or other transient media, but are intended for non-transient, tangible storage media. The disks and optical discs used in the application include compact optical discs (CDs), laser optical discs, optical discs, digital multifunction optical discs (DVDs), floppy disks, and Blu-ray discs, where disks typically copy data magnetically, while optical discs use lasers to copy data optically.

[0118] like Figure 12 A schematic diagram of a test chip according to an embodiment of the present invention is shown. This test chip integrates multiple resistive random access memory (RRAM) storage cells and is equipped with the multi-bit intelligent erase / write control system based on the closed-loop read verification mechanism described above, forming a test architecture with intelligent operation capabilities.

[0119] A multi-bit intelligent erasure and write system based on read verification includes:

[0120] The erase phase control module is used to respond to the WRITE command from the outside and execute the erase phase process of the current RRAM cell with an integrated read verification loop and intelligent parameter adjustment mechanism.

[0121] The programming phase control module, connected to the erase phase control module, is used to execute a programming phase process that integrates a read verification loop and intelligent parameter adjustment mechanism on the current RRAM cell after the erase phase is completed, and exits the WRITE instruction after the programming phase is completed.

[0122] In summary, the multi-bit intelligent erase / write method, system, terminal, and test chip based on read verification of the present invention, by responding to external WRITE commands, sequentially performs erase and programming operations on the target RRAM cell by integrating cyclic read verification and dynamic parameter optimization. During the erase phase, the cell resistance state changes are continuously monitored, and the voltage amplitude and pulse timing are dynamically optimized based on intelligent algorithms to ensure accurate and stable formation of the high-resistance state. Subsequently, the system automatically transitions to the programming phase, employing the same closed-loop control mechanism to achieve high-precision programming operations in the low-resistance state, and terminates command execution after successful verification. This invention effectively solves key technical bottlenecks in the commercial application of RRAM at the circuit design level through intelligent erase / write methods, including core issues such as memory cell resistance dispersion, narrow read operation window, sensitivity to read interference, fluctuating programming success rate, insufficient current limiting control accuracy, durability degradation, and data retention failure, significantly improving and perfecting the array consistency and long-term reliability of RRAM chips. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0123] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A multi-bit smart overwriting method based on read verification, characterized in that, The method comprises: In response to a WRITE instruction from the outside, performing an erase phase process of an integrated read verification cycle and intelligent parameter adjustment mechanism on the current RRAM cell; After the completion of the erase phase, performing a programming phase process of the integrated read verification cycle and intelligent parameter adjustment mechanism on the current RRAM cell, and after the completion of the programming phase, exiting the WRITE instruction; During the erase phase, continuously monitoring the cell resistance state change, dynamically optimizing the voltage amplitude and pulse timing based on the intelligent algorithm, and ensuring the accurate and stable formation of the high resistance state; then automatically switching to the programming phase, and using the same closed-loop control mechanism to realize the high-precision programming operation of the low resistance state, and terminating the instruction execution after verification.

2. The read-verification based multi-bit smart overwriting method as claimed in claim 1, wherein, The erase phase process comprises: Configuring RESET related parameters of the current RRAM cell; wherein the RESET related parameters comprise: operating voltage, target write data, pulse width and reference resistance value; Reading out the stored data to be subjected to the RESET operation of the current RRAM cell in a read verification manner; Comparing the read data with the target write data to determine whether it meets the expectation; If it meets the expectation, the erase phase of the current RRAM cell is completed; If it does not meet the expectation, sending the read data to a combinational logic for processing to generate excitation data of the RESET operation, updating the operating voltage and pulse width to perform the RESET operation on the current RRAM cell, and performing read verification again according to the updated RESET related parameters until the read data meets the expectation.

3. The read-verification based multi-bit smart overwriting method as claimed in claim 2, wherein, The programming phase process comprises: Configuring SET related parameters of the current RRAM cell; wherein the SET related parameters comprise: operating voltage, target write data, pulse width and reference resistance value; Reading out the stored data to be subjected to the SET operation of the current RRAM cell in a read verification manner; Comparing the read data with the target write data to determine whether it meets the expectation; If it meets the expectation, the programming phase is completed; If it does not meet the expectation, sending the read data to a combinational logic for processing to generate excitation data of the SET operation, updating the operating voltage and pulse width to perform the SET operation on the current RRAM cell, and performing read verification again according to the updated SET related parameters until the read data meets the expectation.

4. The read-verification based multi-bit smart overwriting method as claimed in claim 1, wherein, The erase phase process comprises: Configuring RESET related parameters of the current RRAM cell according to the pre-stored configuration information of the register; wherein the RESET related parameters comprise: operating voltage, initial pulse width, repeated operation pulse width and reference resistance value; Triggering the latch of the target address and input data of the current RRAM cell by an external EXECUTE signal; Triggering two read verification operations in sequence, and reading out the data on both sides of the differential structure in sequence; Comparing the input data with the read data to determine whether the 8-bit data meets the expectation; If it meets the expectation, the erase phase is completed; If not as expected, the read data is sent to the combinational logic for processing to obtain the excitation signals of each terminal required in the RESET operation, and the operation voltage is raised in the case of non-first RESET operation of the current RRAM cell. The RESET operation is performed on the current RRAM cell according to the latched target address, and then read verification is performed again according to the updated RESET related parameters until the read data is as expected.

5. The read-verification based multi-bit smart overwriting method according to claim 1 or 4, wherein, The programming phase process includes: According to the register pre-stored configuration information, the SET related parameters of the current RRAM cell are configured; wherein the SET related parameters include: the gate voltage of the gating tube, the operation voltage, the initial pulse width, the limit current and the reference resistance value; The external EXECUTE signal triggers, and the target address and the input data are latched; The two read verification operations are triggered in sequence, and the data on both sides of the differential structure is read out in turn; The input data and the read data are compared to determine whether the 8-bit data is as expected; If as expected, the programming phase is completed; If not as expected, the read data is sent to the combinational logic for processing to obtain the excitation signals of each terminal required in the SET operation, and the operation voltage is raised in the case of non-first SET operation of the current RRAM cell. The SET operation is performed on the current RRAM cell according to the latched target address, and then read verification is performed again according to the updated SET related parameters until the read data is as expected.

6. The read-verification based multi-bit smart overwriting method as claimed in claim 4, wherein, After the erase phase of the current RRAM cell is completed, a flag signal is returned, which is pulled high after the current RRAM cell executes the programming phase process; after each RESET operation on the current RRAM cell, a counter is used for counting, and when the RESET operation of the RRAM cell reaches the configured value, the erase phase process is terminated, and a RESET failure flag signal is returned. After the RESET failure flag signal is pulled high, the current RRAM cell continues to execute the programming phase process.

7. The read-verification based multi-bit smart overwriting method as claimed in claim 5, wherein, After the programming phase of the current RRAM cell is completed, a flag signal is returned, which is pulled high after the current RRAM cell executes the programming phase process; after each SET operation on the current RRAM cell, a counter is used for counting, and when the SET operation of the RRAM cell reaches the configured value, the erase phase process is terminated, and a SET failure flag signal is returned.

8. A read-verify based multi-bit smart overwriting system, characterized in that, The system includes: The erase phase control module is used for executing the erase phase process of the integrated read verification cycle and intelligent parameter adjustment mechanism on the current RRAM cell in response to the WRITE instruction from the outside; The programming phase control module is connected to the erase phase control module, and is used for executing the programming phase process of the integrated read verification cycle and intelligent parameter adjustment mechanism on the current RRAM cell after the completion of the erase phase, and exiting the WRITE instruction after the completion of the programming phase. The resistance state change of the cell is continuously monitored in the erase phase, the voltage amplitude and pulse timing are dynamically optimized based on the intelligent algorithm, and the high resistance state is accurately and stably formed; then the programming phase is automatically entered, the same closed-loop control mechanism is adopted to realize the low resistance state high-precision programming operation, and the instruction execution is terminated after the verification is passed.

9. An electronic terminal, characterized in that It includes: one or more memories and one or more processors; the one or more memories to store a computer program; the one or more processors, coupled to the memories, to execute the computer program to perform the method of any one of claims 1-7.

10. A test chip, characterized by comprising: a plurality of RRAM cells and a read-verification based multi-bit smart-erase system as claimed in claim 8.

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