Deployment method of spiking neural network on neuromorphic hardware

Abstract

The invention discloses a method for deploying a spiking neural network on neuromorphic hardware, and belongs to the technical field of collaborative design of neural network software and hardware. In order to solve the problem of high delay of spiking neural network deployment under different hardware topological structures and routing algorithms, modeling is mainly carried out on a mapping scheme of a neural network between hardware cores under the constraint of preset hardware parameters; and performing iterative optimization on the initial deployment scheme through the deployment scheme selection strategy to meet the response time constraint. The method can be suitable for various hardware architecture and route combinations, response time after deployment is effectively shortened, and system operation efficiency is improved.

Description

Technical Field

[0001] This invention belongs to the field of neural network hardware and software co-design technology, specifically relating to a method for deploying a spiking neural network on neuromorphic hardware. Background Technology

[0002] In the modeling of spiking neural networks (SNNs), A. Das et al. proposed a framework for pruning neurons and deploying SNNs on neuromorphic hardware (NH) in 2018. Their work aimed to reduce the number of spiking ...

[0003] In 2020, A. Balaji et al. proposed the FIT (Fixed-Input Transmission) technique, which normalizes multi-input neurons into a FIT neuron sequence consisting of multi-input, single-output neurons. This technique abandons the previous practice of pruning synapses of neurons with excessively large numbers of synapses when deploying SNNs to NH (Network Neural Networks) to adapt to hardware constraints. This technique allows neurons that were previously impossible to deploy to hardware to be deployed on the crossbar, improving the average accuracy of the model. In the same year, A. Balaji et al. were the first to consider inter-chip topology, introducing a 2D network topology. They used greedy algorithms and particle swarm optimization to optimize the number of pulses during normalization and the deployment of clusters in the 2D network topology, thus improving latency and energy consumption. A. Balaji et al. also found that previous methods were mainly geared towards offline learning and did not control the time for exploring the design space. In online learning scenarios, how to achieve real-time deployment and redeployment of adaptive neural networks on NH in a shorter time, at the cost of acceptable performance degradation, is also a problem worthy of research. The authors proposed a strategy combining a greedy algorithm and a hill-climbing algorithm. The results show that the algorithm can complete the exploration of the deployment design space in an average of 1 / 780 of the time, with only a 6.25% performance loss.

[0004] S. Song et al. introduced a design process that incorporates buffer size as a variable into the modeling and deployment of SNNs. This process also includes steps such as normalization, clustering, and deployment. Modeling was performed using a Synchronous Data Flow Graph (SDFG) without considering the topology. The particle swarm optimization algorithm was combined with SDFG, where the former was used to update different buffer sizes, and the latter was used to estimate the deployment throughput after specifying the buffer size.

[0005] C. Xiao et al. used a spiking convolutional neural network derived from a convolutional neural network, employing the same framework and the NSGA-II algorithm to find the optimal cluster-core deployment scheme. Their algorithm showed significant improvements in both congestion and energy consumption.

[0006] O. Jin et al. proposed a method for deploying ultra-large-scale SNN applications to NyS networks, aiming to reduce energy consumption, latency, and on-chip network communication congestion. This method first uses Hilbert curves to solve the initial deployment scheme. Secondly, they developed a Force Directed algorithm to optimize the deployment scheme. Their method optimizes metrics such as energy consumption, average latency, maximum latency, average congestion, and maximum congestion.

[0007] NH typically contains a large number of in-memory, independently parallelizable neuromorphic cores. These cores contain computational blocks and routing nodes for communication over internal interconnects. Each computational block consists of crossbars and buffer spaces. The input synapses of spiking neurons correspond to the horizontal edges of the crossbars; the pulse signal is read from the buffer space and used in computation. The spiking neuron itself corresponds to the vertical column of crosspoints on the crossbars. The output synapses of spiking neurons correspond to the vertical edges of the crossbars, sending the computed pulses to the routing nodes, such as... Figure 1 As shown.

[0008] Different manufacturers' NH chips may employ different neuromorphic core topologies and routing algorithms. For example, the neuromorphic core topologies of chips such as IBM's TrueNorth chip and Tsinghua University's Tianjic chip both adopt a 2D-mesh structure. This invention uses N, S, W, and E to represent routes to the north, south, west, and east in a 2D-mesh structure, respectively, and uses two consecutive directions to represent changes in routing direction, such as NW representing a change from north to west. Common routing algorithms in 2D-mesh on-chip networks include: (a) XY routing: The packet must first be routed along the W / E direction, and then along the N / S direction, such as... Figure 2 As shown in Figure (a); (b) WF route (West-First): routes between NW and SW are disabled, as shown in Figure (a). Figure 2 As shown in Figure (b), blue routes are allowed, and red routes are blocked (the same applies below); (c) NL routes (North-Last): routes between NW and NE are blocked, as shown... Figure 2 As shown in diagram (c); (d) NF routing (Negative-First): Routes between NW and ES are disabled, as shown in... Figure 2 As shown in Figure (d); (e) OE routing (Odd-Even): Odd columns prohibit routes to EN and NW, and even columns prohibit routes to ES and SW, as shown in Figure (d). Figure 2 The two diagrams marked (e) are shown. XY routing is deterministic, with only one possible route; other routing algorithms are adaptive, with multiple valid routes possible, allowing the selection of a more suitable path based on congestion levels on the interconnect. Different routing algorithms lead to different packet flows within the interconnect, affecting the response time of the SNN deployment scheme.

[0009] For 3D-mesh topologies, this invention only examines the default routing algorithm XYZ (similar to the XY routing algorithm in 2D networks). The Neurogrid chip developed by Stanford University communicates between cores via tree routing; for this topology, this invention only examines the routing algorithm for the shortest path between two leaves of a binary tree. Intel's Loihi chip employs a hierarchical 2D-mesh structure between cores; for its first-level routing (2D-mesh shape), this invention only examines the default routing algorithm XY. The three architectures are described below. Figure 3 The three figures (a) to (c) are shown in the text.

[0010] Existing work on SNN modeling and deployment largely focuses on standardizing SNNs and improving clustering efficiency to increase throughput, without considering the impact of neuromorphic core topology and routing algorithms on response time during the modeling process. This prevents researchers from quickly obtaining deployment response times based on deployment plans. Furthermore, with the development of neuromorphic cores, increasingly diverse topologies and routing algorithms have emerged. To simulate hardware platforms with different architectures, researchers often need to rewrite the underlying code of the hardware platform according to their specific requirements. Summary of the Invention

[0011] This invention aims to address how to incorporate the impact of the nimble neural network (NH) topology and routing algorithm on response time during SNN modeling, and how to ensure that this impact has a practical effect on response time in the SDFG (Synchronous Data Flow Graph). Furthermore, the deployment process involves technical aspects such as neuron normalization, neuron clustering methods, and SDFG response time calculation. To address this, this invention proposes a method for deploying nimble neural networks (NHs) on neuromorphic hardware based on synchronous data flow graphs. It combines and integrates various mainstream neuromorphic core topologies and their corresponding routing algorithms, utilizing SDFG to model and optimize the deployment of SNNs on NHs. This method eliminates the need for simulating NHs with different topologies and routing algorithms, and avoids rewriting the underlying code. It allows for rapid acquisition of deployment response time and enables the selection and iteration of deployment schemes with superior response times based on a selection strategy.

[0012] The technical solution adopted by the present invention to achieve the above objectives is as follows:

[0013] A method for deploying a spiking neural network on neuromorphic hardware includes the following steps:

[0014] 1) For the spiking neural network (SNN) to be deployed, the neurons and synaptic connections in the SNN are normalized to obtain a normalized SNN;

[0015] 2) Cluster the neurons of the normalized SNN to obtain the first mapping relationship;

[0016] 3) Based on the structural information, routing algorithm and connection constraints of the neuromorphic hardware NH, the first mapping relationship is mapped to multiple neuromorphic cores to obtain an initial deployment scheme;

[0017] 4) Model the initial deployment scheme in the synchronous data flow graph SDFG and calculate the response time of the initial deployment scheme;

[0018] 5) When the response time does not meet the preset constraints, the initial deployment scheme is iteratively optimized based on the deployment scheme optimization algorithm to generate an updated deployment scheme, and step 4) is repeated until the response time meets the preset constraints or the number of executions reaches the maximum number of executions constraint.

[0019] Furthermore, the normalization process in step 1) includes: normalizing neurons in the SNN whose number of inputs exceeds the hardware constraints of the computation block into a sequence of neurons that meet the constraints.

[0020] Furthermore, the clustering method in step 2) includes: using the maximum resource utilization rate of the existing cluster as an indicator, a greedy algorithm is used to group neurons, and each group, as a cluster, will be deployed on a computational block of a neuromorphic core in subsequent steps.

[0021] Furthermore, in step 3), the structural information of NH includes the core topology of NH, the inter-core communication bandwidth and delay parameters; the core topology of NH includes a two-dimensional grid, a three-dimensional grid, a tree structure or a hierarchical two-dimensional grid; the routing algorithm includes deterministic routing and adaptive routing.

[0022] Furthermore, in step 4), the SDFG uses compute blocks and inter-core communication as nodes and inter-core communication relationships as edges. Both types of nodes are associated with latency attributes. The latency attribute of the compute block node is related to the hardware's compute latency, while the latency attribute of the inter-core communication node is related to the hardware's communication latency.

[0023] Furthermore, the method for calculating the response time in step 4) includes: determining the execution order of each node in SDFG, calculating the total latency of each path based on the node's latency, and using the latency of the longest path as the response time.

[0024] Furthermore, the deployment scheme optimization algorithm in step 5) adopts any one of the following: random search algorithm, particle swarm optimization algorithm, and genetic algorithm.

[0025] Furthermore, the genetic algorithm includes the following steps: generating multiple deployment scheme individuals, using the response time of the deployment scheme individuals as the fitness value, generating a new generation of deployment scheme individuals based on crossover and mutation operations, and selecting individuals with higher fitness values ​​to enter the next generation.

[0026] Furthermore, the preset constraints mentioned in step 5) include the expected response time.

[0027] Furthermore, after obtaining a deployment scheme that meets the preset constraints in step 5), the correspondence between the computation blocks and the neuromorphic core under the deployment scheme is output as a deployment mapping file.

[0028] The beneficial effects achieved by this invention are as follows:

[0029] 1. This invention can perform parameterized description and modeling of the core inter-topology and routing algorithm of NH, supporting multiple topology types such as two-dimensional mesh, three-dimensional mesh, tree structure, and hierarchical two-dimensional mesh, as well as multiple routing algorithms such as XY, WF, NL, NF, OE, and XYZ, thereby adapting to the deployment requirements of different hardware architectures.

[0030] 2. This invention can reflect the impact of different combinations of topologies and routing algorithms on the response time of neural network deployment under the same hardware parameters. Among multiple combinations, the structure with better response time can be selected, especially in 3D networks, hierarchical 2D networks and other structures, which can significantly reduce latency.

[0031] 3. This invention provides multiple deployment scheme optimization algorithms, including random search, particle swarm optimization (PSO) and genetic algorithm (GA), which can select the appropriate algorithm according to the size of the neural network and the optimization objective, thereby improving the efficiency of response time optimization and the quality of optimization results.

[0032] 4. In this invention, the random search algorithm can effectively reduce the latency of small-scale networks in a short time, while particle swarm optimization and genetic algorithm are more suitable for optimizing the latency of large-scale networks and can explore better optimal latency values.

[0033] 5. The deployment optimization process of this invention can model and optimize unpreset topologies and routing algorithms, thus expanding the applicability and versatility of the method.

[0034] 6. Compared with existing methods, the present invention can achieve better response time performance in most topology and routing algorithm combinations, and can still generate usable deployment schemes in hardware architectures where existing methods cannot be directly applied. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the architecture of neuromorphic hardware.

[0036] Figure 2 This is a schematic diagram of common routing algorithms in 2D-mesh on-chip networks.

[0037] Figure 3 This is a schematic diagram of the 3D network, tree, and hierarchical 2D network topology of neuromorphic hardware.

[0038] Figure 4 This is a flowchart of the method for deploying the spiking neural network of the present invention on neuromorphic hardware.

[0039] Figure 5 Example diagram for normalized SNN.

[0040] Figure 6 This is an example diagram for a synchronized data flow graph.

[0041] Figure 7 An example diagram illustrating the process of modeling a synchronous data flow graph.

[0042] Figure 8 Histogram showing the impact of different topologies and routing algorithms on response time.

[0043] Figure 9 Histogram showing the impact of algorithm selection on response time in a fully connected SNN deployment scheme.

[0044] Figure 10 This diagram illustrates how different topologies and routing algorithms affect response time. Detailed Implementation

[0045] To make the various technical features, advantages, or effects of the present invention more apparent and understandable, detailed descriptions are provided below through embodiments.

[0046] 1. Overall Method Flow

[0047] This example proposes a method for deploying spiking neural networks on neuromorphic hardware, aiming to find a deployment scheme that meets response time constraints. The processing flow of this invention is as follows: Figure 4 As shown, the process mainly consists of two stages: SNN clustering and deployment for solving. According to the processing flow, this invention includes the following processing steps:

[0048] Step 1: Input preparation: Take the SNN to be deployed, NH, and routing algorithm (ra) as input to prepare for subsequent cluster and deployment solutions.

[0049] Step 2: SNN Normalization: Normalize the neurons in the SNN by splitting neurons with too many input synapses into several neuron sequences that do not exceed the constraint value.

[0050] Step 3: SNN Clustering: Based on the normalized neurons, the neurons are clustered according to the computation block capacity and resource utilization to obtain the clustered spiking neural network (CSNN). The number of neurons in each cluster meets the hardware constraint on the number of neurons in the computation block.

[0051] Step 4: Deployment Scheme Selection: Deploy CSNN on NH and generate the initial cluster deployment scheme matrix M. c Each cluster is assigned a computational block to the corresponding neuromorphic core.

[0052] Step 5: SDFG Modeling: Combining the routing algorithm ra, the CSNN cluster deployment scheme M is... c The model on NH is a synchronous data flow graph G (SDFG G). During the modeling process, both "cluster" and "inter-cluster connection" nodes are represented as SDFG nodes, and the execution time of the nodes is determined by the computation latency and routing transmission latency.

[0053] Step 6: Response time calculation: Calculate the response time lat of G using the SDFG response time solution algorithm, which is expressed as lat = Lat(G).

[0054] Step 7: Deployment scheme iterative optimization: Determine whether lat meets the given response time constraint T. If lat ≤ T, then the current cluster deployment scheme M is optimized. cIt can be used directly; if lat > T, then select a strategy based on the deployment plan for M. c Iterative optimization is performed. Optional optimization algorithms include random search, particle swarm optimization, or genetic algorithms. M is updated in each iteration. c Then, it is remodeled as SDFG and the response time is calculated. This process is repeated until the response time constraint is met.

[0055] Step 8: Neuron Deployment Scheme Generation: Based on the cluster deployment scheme M that satisfies the response time constraint c Generate the corresponding SNN neuron deployment scheme M and output the final deployment result, where L(M,ra)≤T is guaranteed.

[0056] 2. SNN Clustering Stage

[0057] Considering that the computational cost of directly deploying the entire SNN to NH would be too large, and taking into account the characteristics of the computation blocks themselves, the method of this invention first performs cluster processing on the entire SNN, and then deploys each cluster to NH.

[0058] During clustering, the SNN needs to be normalized because the computation blocks have hardware constraints on input and output. Let con be the maximum number of neurons that can be deployed on each computation block. n The maximum number of input synapses that each computation block can receive is con s First, for input synapses with a number exceeding con s The neurons are normalized. Assume con s =3, now there is a neuron with 5 input synapses, such as Figure 5 As shown in Figure (a) (highlighted in red), it is normalized into a neuron sequence with no more than 3 input synapses. The normalized result is as follows. Figure 5 As shown in Figure (b), the original neuron is divided into a sequence of neurons consisting of no more than three input synapses (highlighted in red).

[0059] After normalizing the SNN, a greedy algorithm is used to generate cluster schemes, with maximum resource utilization as the optimization metric. Resource utilization is defined as the ratio of the number of used crossover points to the total number of crossover points. Figure 5 As shown in Figure (c), its resource utilization rate is 2 / 3. The SNN after clustering is denoted as CSNN=(C,C C W C ), where C represents the set of clusters, C C W represents the set of connections between clusters. C This represents the set of workloads for a cluster, i.e., the number of pulses issued by each cluster.

[0060] The SNN clustering algorithm is as follows:

[0061]

[0062]

[0063] First, initialize the cluster set C and the inter-cluster connection set C. C Given an empty set (line 1), for all normalized neurons n∈N (lines 2-10), check if there exists an existing cluster c∈C that can accommodate the neuron and still satisfy the constraints con of the computational block after its addition. n and con s If a cluster exists, add neuron n to cluster c and update the cluster's resource utilization; otherwise, create a new cluster c = {n}, update its resource utilization, and add this cluster to the cluster set C. All clusters are sorted according to their resource utilization (line 9) in descending order to prioritize clusters with higher resource utilization.

[0064] After cluster allocation is completed, the initial workload W for inter-cluster connections will be... C (c c Set the value to 0 (line 11). Then iterate through the normalized synapses s∈S (lines 12-16). For each synapse, if its source neuron and target neuron belong to different clusters c1 and c2 respectively and c1≠c2, then add the synapse as an inter-cluster connection (ICC) to C. C (If not already joined), and add its load W(s) to the workload W of the inter-cluster connection. C In (c1→c2) (line 14), the final returned clustered spiking neural network CSNN = (C,C C W C (line 17).

[0065] 3. Deployment and Solution

[0066] This stage aims to obtain a neuron deployment scheme M that meets the given requirements using NH, the routing algorithm ra, and the CSNN obtained above.

[0067] The deployment and solution process is described in the following algorithm:

[0068]

[0069]

[0070] First, based on CSNN and NH, each cluster is deployed on its corresponding computing core, resulting in the initial cluster deployment scheme M. c (Line 1). Then, based on the topology of CSNN and NH, and the cluster deployment scheme M... cBased on the routing algorithm ra, construct SDFG G (line 2), and calculate its response time lat = Lat(G) using the SDFG response time solution algorithm (lines 2-3). During the iteration process, if the response time does not meet the expected constraint but does not exceed the maximum number of iterations, select a strategy for cluster deployment scheme M according to the preset deployment scheme. c Update the settings and repeat the SDFG construction and response time calculation steps (lines 5-10) until a cluster deployment scheme that meets the expected response time is obtained. Finally, based on the obtained cluster deployment scheme M... c With CSNN, generate a complete neuron deployment scheme M (line 11).

[0071] The deployment and solution process specifically includes the following steps:

[0072] 3.1 Deployment Scheme Selection

[0073] Given a SNN and response time constraints, we first find feasible deployment schemes for its corresponding CSNN, thus obtaining feasible deployment schemes for the SNN. The deployment schemes of the CSNN onto the NH can be represented as a matrix. in This indicates that cluster i is deployed on core j, and vice versa. Since each neuron is deployed to exactly one cluster, matrix M... c The sum of the rows is 1, that is... Meanwhile, since at most one cluster can be deployed on each computing block (otherwise multiple clusters could be merged into a single cluster, contradicting the strategy of "maximizing resource utilization" during clustering), matrix M c The sum of the columns is no more than 1, that is...

[0074] For iterative optimization of the deployment scheme, this invention employs common random search algorithms, particle swarm optimization algorithms, and genetic algorithms.

[0075] The random search algorithm randomly swaps clusters on two cores during each exploration of the deployment space (provided that at least one of the two cores already has a deployed cluster). That is, for cluster a, there are clusters on cores x and y. In the updated candidate cluster deployment scheme Furthermore, if cluster b is deployed on core y, it will be migrated to core x. Each iteration retains the deployment scheme with the shorter response time.

[0076] The particle swarm optimization algorithm first generates several cluster deployment schemes M. cEach particle is called a "particle," and all particles form a "particle swarm." The entire particle swarm shares the optimal cluster deployment scheme that has been explored. In each iteration, each particle, based on its current deployment scheme, moves towards the historical optimal scheme of the particle swarm and its own historical optimal scheme in a certain proportion, while always satisfying the aforementioned row and column constraints.

[0077] The genetic algorithm also first generates several cluster deployment schemes M. c Each set of genes is called a "gene," and all genes constitute the "parent generation." During each update, genes in the parent generation are paired up, and while ensuring the row and column constraints are met, the deployment schemes of some of their parent clusters are swapped with a certain probability. Then, the deployment schemes of some clusters of the new genes are mutated with a certain probability, resulting in a new set of genes called the "child generation." Genes in the child generation are selected (repeatedly), with genes having a shorter response time having a higher probability of being selected. The selected set of genes becomes the new parent generation and enters the next round of iterative selection for cluster deployment schemes.

[0078] 3.2 SDFG Modeling

[0079] An SDFG (Supply-Dependent Architecture Group) consists of nodes (actors) and directed edges (channels), where nodes represent functional units and directed edges represent data transmission paths. The amount (rate) of input and output data for each node is annotated in the graph as part of the node definition; the initial amount of data on each edge is also annotated, such as... Figure 6 As shown. A node can be executed (fired) as soon as all input data arrives. For example, node B in the graph cannot be executed because it only has one initial data point D on its incoming edge.

[0080] A homogeneous synchronous data flow graph (HSDFG) is a special form of SDFG where the input and output rates of each node are both 1. If there exists a sequence of nodes containing all nodes of an HSDFG such that executing these nodes sequentially allows the HSDFG to return to its initial state, then each node in the HSDFG in this sequence appears exactly once. The total time required for all nodes in an SDFG to complete their respective execution counts (1 in the HSDFG) is called the latency. This invention uses HSDFG to model the deployment problem of SNNs on NH and to analyze the post-deployment latency.

[0081] For SDFG G, this invention employs the following algorithm to calculate the response time lat: First, a topological sort sequence is generated based on the depth of nodes in graph G from shallow to deep. Each node in the topological sort is examined sequentially. If a node has no incoming edges, the response time Δ(v) for data to reach that node is equal to the node's own execution time. If a node has incoming edges, its response time Δ(v) for data to reach that node is equal to the node's own execution time plus the maximum response time Δ(u) among all its predecessor nodes. Specifically, considering that even if a loop exists during pulse transmission during deployment, NH will still perform calculations, this invention removes back edges when calculating the response time of graph G to ensure that a topological sort can be generated based on node depth. The final response time is denoted as lat = Lat(G).

[0082] This process is based on the given cluster deployment scheme M c The topology NH and routing algorithm ra are used to model the CSNN deployment problem as SDFG and calculate its response time. The following section uses... Figure 7 The following figure illustrates the SDFG modeling process, where (a) is a schematic diagram of SDFG G, showing only some nodes; (b) is a schematic diagram of pulse transmission quantity determination; and (c) is a schematic diagram of execution time determination.

[0083] First, during the modeling process, both "clusters" and "inter-cluster connections" are modeled as nodes in the SDFG, such as... Figure 7 As shown in Figure (a). The execution time of the "cluster" node corresponds to its computational latency, which is determined by the parameters of NH; while the execution time of the "inter-cluster connection" node will be described in detail below.

[0084] Then, based on the CSNN and cluster deployment scheme M c Determine the routing path for "inter-cluster connections" in NH, such as Figure 7 As shown in Figure (b), assume that NH adopts a two-dimensional network topology and uses the XY-routing algorithm for data transmission. Taking clusters c0 and c6 deployed on cores core8 and core2 respectively as an example, the "inter-cluster connection" node corresponding to c0→c6 is denoted as c10. Therefore, the data flow path between the cores can be determined as core8→core9→core10→core6→core2.

[0085] After traversing all "inter-cluster connections," the pulse transmission volume on each routing path on NH can be obtained. Finally, the execution time of the "inter-cluster connection" node is calculated based on the bandwidth of each path. For example, in Figure 7 In diagram (c), assuming a bandwidth of 200 spikes / week, the execution time of node c10 is... That is, 7 times the transmission delay in the hardware parameters.

[0086] 3.3 Obtain the neuron deployment scheme based on the cluster deployment scheme.

[0087] The CSNN obtained during the clustering process is (C,C) C W C In the diagram, set C records the neurons n∈N contained in each cluster c∈C. Therefore, after obtaining the cluster deployment scheme M... c Then, based on the affiliation of neurons within each cluster, a specific deployment scheme for each neuron can be generated, namely neuron deployment scheme M, thereby completing the mapping from cluster-level deployment to neuron-level deployment.

[0088] Experimental test:

[0089] This experiment implemented the method proposed in this invention using Python on a Linux system and conducted experiments on a machine with a 2.50GHz CPU and 512GB of memory. The aim is to answer the following questions through these experiments:

[0090] Q1. Investigate the impact of topology and routing algorithm on the optimized response time;

[0091] Q2. Investigate the impact of deployment strategy selection (random search, particle swarm optimization, genetics) on response time;

[0092] Q3. Comparison with related work on response time metrics.

[0093] 1. In response to question Q1, this part of the experiment sets up multiple neural networks and hardware platforms with different architectures or routing algorithms to explore the impact of different topologies and routing algorithms on the optimized response time.

[0094] Figure 8 Figures (a) to (e) illustrate the impact of various topologies and routing algorithms—2D-mesh+XY, 2D-mesh+WF, 2D-mesh+NL, 2D-mesh+NF, 2D-mesh+OE, 3D-mesh (+default XYZ), tree (+default), and hierarchical 2D-mesh (+default XY)—on the optimized response time. The data shows that, based on the latency of 2D-mesh+XY, the average latency of the other seven experimental groups were 102.28%, 103.15%, 103.03%, 103.84%, 77.45%, 102.15%, and 82.94%, respectively.

[0095] In the experimental setup, this invention demonstrates the change in response time of SNNs with the same structure when deployed with different combinations of "neuromorphic core topology and routing algorithms". The data shows that, under the same hardware parameters, the topology of 3D-network and hierarchical 2D-network is more conducive to reducing the overall deployment delay than other combinations.

[0096] 2. In response to question Q2, this part of the experiment sets up multiple datasets, neural networks, topology structures and routing algorithms to explore the effect of deployment scheme selection strategy on latency optimization.

[0097] For a fully connected SNN, the latency after optimization using random search, particle swarm optimization, and genetic algorithm became 81.13%, 86.88%, and 81.08% of the initial latency, respectively (the initial latency of particle swarm optimization and genetic algorithm is the lowest latency among the initial populations). Figure 9 As shown in Figures (a) to (c); for CNNSNN, the optimized latency of the three algorithms is 90.84%, 89.31%, and 89.76% of the initial latency; for LeNet-5, the optimized latency of the three algorithms is 84.13%, 76.68%, and 78.11% of the initial latency; for AlexNet, the optimized latency of the three algorithms is 92.83%, 84.70%, and 75.36% of the initial latency; and for ResNet-18, the optimized latency of the three algorithms is 97.43%, 84.05%, and 87.41% of the initial latency. The optimization time required for the three algorithms roughly follows the ratio of the number of independent variables in the algorithm, for example, 1:50 (number of PSO particles):100 (number of GA genes) in this case.

[0098] Data shows that among the three optimization algorithms, random search, due to its high randomness, can more effectively reduce the latency of small-scale networks in a short time, but the optimal latency it finds is relatively poor; particle swarm optimization and genetic algorithms are more suitable for reducing the latency of large-scale networks, and the optimal latency they find is also better.

[0099] 3. Regarding question Q3, in this part of the experiment, the average delay represents the algebraic average of the delays on all edges after the SNN is deployed on NH; the maximum delay represents the maximum value of the delay on a single edge when a pulse is transmitted in NH; and the longest delay represents the delay on the path with the longest sum of delays when a pulse is transmitted in NH (i.e., the delay obtained by Algorithm 1). The deployment scheme of this invention uses the longest delay as an indicator, therefore, the longest delay was added as an indicator in the related work during the experiment.

[0100] Compared with other deployment schemes, although the longest latency (response time) obtained by this invention in the "2D+XY" group averaged 133.66%, 115.47%, and 119.91% across the seven experimental groups, only this invention can model and select deployment schemes for other topologies and routing algorithms. Even for topologies and routing algorithms not considered in this invention, it can still model them and select deployment schemes. Taking "fully connected SNN + MNIST dataset + genetic algorithm" as an example, the impact of deployment scheme selection algorithms on response time in different groups is as follows... Figure 10 As shown.

[0101] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Appropriate modifications or equivalent substitutions made by those skilled in the art to the technical solutions of the present invention should be covered within the protection scope of the present invention, which is defined by the claims.

Claims

1. A method for deploying a spiking neural network on neuromorphic hardware, characterized in that, Includes the following steps: 1) For the spiking neural network (SNN) to be deployed, the neurons and synaptic connections in the SNN are normalized to obtain a normalized SNN; 2) Cluster the neurons of the normalized SNN to obtain the first mapping relationship; 3) Based on the structural information, routing algorithm and connection constraints of the neuromorphic hardware NH, the first mapping relationship is mapped to multiple neuromorphic cores to obtain an initial deployment scheme; 4) Model the initial deployment scheme in the synchronous data flow graph SDFG and calculate the response time of the initial deployment scheme; 5) When the response time does not meet the preset constraints, the initial deployment scheme is iteratively optimized based on the deployment scheme optimization algorithm to generate an updated deployment scheme, and step 4) is repeated until the response time meets the preset constraints or the number of executions reaches the maximum number of executions constraint.

2. The method as described in claim 1, characterized in that, The normalization process in step 1) includes: normalizing neurons in the SNN whose number of inputs exceeds the hardware constraints of the computation block into a sequence of neurons that meet the constraints.

3. The method as described in claim 1, characterized in that, The clustering method in step 2) includes: using the maximum resource utilization rate of the existing cluster as an indicator, a greedy algorithm is used to group neurons, and each group, as a cluster, will be deployed on a computational block of a neuromorphic core in subsequent steps.

4. The method as described in claim 1, characterized in that, In step 3), the structural information of NH includes the core topology of NH, the inter-core communication bandwidth, and the delay parameters; the core topology of NH includes a two-dimensional mesh, a three-dimensional mesh, a tree structure, or a hierarchical two-dimensional mesh. Routing algorithms include deterministic routing and adaptive routing.

5. The method as described in claim 1, characterized in that, In step 4), the SDFG uses compute blocks and inter-core communication as nodes and inter-core communication relationships as edges. Both types of nodes are associated with latency attributes. The latency attribute of compute block nodes is related to the hardware's compute latency, while the latency attribute of inter-core communication nodes is related to the hardware's communication latency.

6. The method as described in claim 5, characterized in that, The method for calculating the response time in step 4) includes: determining the execution order of each node in SDFG, calculating the total latency of each path based on the node latency, and using the latency of the longest path as the response time.

7. The method as described in claim 1, characterized in that, The deployment scheme optimization algorithm in step 5) can be any one of the following: random search algorithm, particle swarm optimization algorithm, or genetic algorithm.

8. The method as described in claim 7, characterized in that, The genetic algorithm includes the following steps: generating multiple deployment scheme individuals, using the response time of the deployment scheme individuals as the fitness value, generating a new generation of deployment scheme individuals based on crossover and mutation operations, and selecting individuals with higher fitness values ​​to enter the next generation.

9. The method as described in claim 1, characterized in that, The preset constraints mentioned in step 5) include the expected response time.

10. The method as described in claim 1 or 9, characterized in that, After obtaining a deployment scheme that meets the preset constraints in step 5), the correspondence between the computation blocks and the neuromorphic core under the deployment scheme is output as a deployment mapping file.

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