Control circuit, image compensation control device and display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a control circuit, an image compensation control device and a display panel. The control circuit comprises a picture detection module configured to convert a refresh rate in the plurality of display parameters into a corresponding trigger voltage when it is determined according to the plurality of display parameters that a current display picture is an abnormal picture; a hysteresis comparison module configured to output a corresponding switch control signal according to a comparison result of the trigger voltage and a preset hysteresis interval; and a switch module configured to turn on or turn off a signal path between the picture compensation output end and the rear-stage load in response to the switch control signal. Therefore, the application sets a stable buffer interval for the start and stop of the ICA function through the cooperative work of the picture detection module, the hysteresis comparison module and the switch module, and eliminates the problems of frequent switching of the ICA function and picture flickering caused by the fluctuation of the refresh rate and other parameters near the critical value.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display driving, and particularly relates to a control circuit, an image compensation control device and a display panel. BACKGROUND

[0002] In the field of display technology, crosstalk, green screen and other abnormal picture problems are common display defects. To deal with these problems, the prior art usually integrates ICA (Image Compensation Algorithm) in the timing controller, that is, dynamically adjusting the liquid crystal polarity arrangement mode when abnormal pictures are detected to suppress the in-plane coupling effect, thereby improving the picture quality.

[0003] The current ICA function opening and closing mechanism relies on real-time detection of the area and gray scale value of the abnormal picture area and comparison with the preset threshold value; since crosstalk problems are more pronounced at high refresh rates, ICA usually needs to be started when the refresh rate reaches a certain threshold value. However, due to the instability of front-end data transmission, the refresh rate is prone to frequent fluctuations near the critical value (such as when the set value is M, M and M-1 are both critical points), causing the ICA function to repeatedly switch between the on and off states, and this frequent state change will cause picture flickering, seriously affecting the user experience.

[0004] It can be seen that the ICA function of the related technology has the problems of frequent opening and closing when the refresh rate is near the critical value, thereby causing picture flickering on the screen and reducing the stability of the display picture. SUMMARY

[0005] The present application provides a control circuit, an image compensation control device and a display panel, which sets a stable buffer interval for the start and stop of the ICA function through the cooperative work of the picture detection module, the hysteresis comparison module and the switching module, greatly improves the stability and reliability of the start and stop of the ICA function, eliminates the frequent switching of the ICA function and picture flickering caused by the fluctuation of parameters such as refresh rate near the critical value, and thereby significantly improves the visual perception and user experience of the display picture.

[0006] In a first aspect, the embodiments of the present application provide a control circuit, which comprises: a picture detection module configured to detect a plurality of display parameters of a current display picture, and convert a refresh rate in the plurality of display parameters into a corresponding trigger voltage when it is determined that the current display picture is an abnormal picture according to the plurality of display parameters; a hysteresis comparison module, an input end of the hysteresis comparison module being connected to the picture detection module, the hysteresis comparison module being configured to receive the trigger voltage and output a corresponding switch control signal according to a comparison result of the trigger voltage and a preset hysteresis interval; and a switch module, a control end of the switch module being connected to an output end of the hysteresis comparison module, a first connection end of the switch module being connected to a picture compensation output end, and a second connection end of the switch module being connected to a subsequent load, the switch module being configured to turn on or turn off a signal path between the picture compensation output end and the subsequent load in response to the switch control signal.

[0007] In a second aspect, the embodiments of the present application provide an image compensation control device, which is applied to a display panel, the display panel comprising N display partitions, and one display partition corresponding to one data driving circuit; the image compensation control device comprising: a total control circuit, the total control circuit being the control circuit, and being configured to generate a whole-area control signal based on display parameters of the display panel; N partition control circuits, each partition control circuit being the control circuit; each partition control circuit being configured to generate a partition control signal based on display parameters of a corresponding display partition; and a mode switching circuit, which is coupled to a mode output end, the total control circuit, the N partition control circuits and the N data driving circuits; the mode switching circuit being configured to input the whole-area control signal to the N data driving circuits in response to an externally input first mode selection signal, and input a partition control signal generated by an i-th partition control circuit to an i-th data driving circuit in response to an externally input second mode selection signal, where i = 1,..., N.

[0008] In a third aspect, the embodiments of the present application provide a display panel, which comprises a display area and a non-display area, the display area comprising a pixel array; the non-display area comprising a timing controller, a source driving circuit and an image compensation control device, the image compensation control device being electrically connected to the timing controller and the source driving circuit respectively.

[0009] The technical scheme provided by the present application has at least the following beneficial effects:

[0010] This application uses a screen detection module to detect and determine in real time whether there are any abnormalities in the current display screen. When an abnormal screen is detected, the refresh rate parameter of that screen is converted into a corresponding trigger voltage and output to the hysteresis comparison module. The hysteresis comparison module introduces a hysteresis range with upper and lower thresholds to perform anti-jitter judgment on the trigger voltage, effectively filtering out frequent fluctuations in the refresh rate near the critical value and outputting a stable switching control signal. The switching module responds to this control signal, precisely turning on or off the signal path from the image compensation output to the subsequent drive circuit, achieving hard enable control of the ICA function. Therefore, this application integrates screen detection, intelligent decision-making, and precise execution through the collaborative work of the screen detection module, hysteresis comparison module, and switching module, constructing a closed-loop control that is responsive, stable in judgment, and reliable in execution. Furthermore, by introducing a refresh rate-based hysteresis comparison control mechanism, a stable buffer zone is set for the start and stop of the ICA function, greatly improving the stability and reliability of the ICA function's start and stop, eliminating the frequent switching of the ICA function and screen flickering caused by fluctuations in parameters such as refresh rate near the critical value, thereby significantly improving the visual experience and user experience of the displayed screen. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0012] Figure 1 The diagram shown is a schematic diagram of a control circuit provided in an embodiment of this application.

[0013] Figure 2 The diagram shown is a circuit diagram of the first type of hysteresis comparison module provided in an embodiment of this application.

[0014] Figure 3 The diagram shown is a schematic diagram of the first voltage transmission characteristic provided in the embodiment of this application.

[0015] Figure 4 The diagram shown is a circuit diagram of the second type of hysteresis comparison module provided in an embodiment of this application.

[0016] Figure 5 The diagram shown is a schematic diagram of the second voltage transmission characteristic provided in the embodiment of this application.

[0017] Figure 6 The diagram shown is a circuit diagram of the third type of hysteresis comparison module provided in an embodiment of this application.

[0018] Figure 7The diagram shown is a schematic diagram of the third voltage transmission characteristic provided in the embodiment of this application.

[0019] Figure 8 The diagram shown is a circuit diagram of the fourth hysteresis comparison module provided in an embodiment of this application.

[0020] Figure 9 The diagram shown is a schematic diagram of the fourth voltage transmission characteristic provided in the embodiments of this application.

[0021] Figure 10 The diagram shown is a structural schematic of the first image compensation control device provided in the embodiment of this application.

[0022] Figure 11 The diagram shown is a structural schematic of the second image compensation control device provided in the embodiment of this application.

[0023] Figure 12 The diagram shown is a structural schematic of the third image compensation control device provided in the embodiments of this application.

[0024] Figure 13 The diagram shown is a circuit diagram of a frequency comparator provided in an embodiment of this application.

[0025] Figure 14 The diagram shown is a structural schematic of the fourth image compensation control device provided in the embodiments of this application.

[0026] Figure 15 The diagram shown is a structural schematic of the fifth image compensation control device provided in the embodiments of this application.

[0027] Explanation of reference numerals in the attached figures:

[0028] 100. Control circuit; 110. Image detection module; 120. Hysteresis comparison module; 130. Switch module; 200. Image compensation output terminal; 210. Whole area compensation output terminal; 220. First zone compensation output terminal; 230. Second zone compensation output terminal; 240. Third zone compensation output terminal;

[0029] 300. Image compensation control device; 310. Main control circuit; 320. Zone control circuit; 330. Mode switching circuit; 340. First frequency comparator; 350. Second frequency comparator; 360. Proportion determination circuit;

[0030] 400, Mode output terminal; 500, Data drive circuit; 600, Subsequent stage load;

[0031] T0, Switching transistor; T1, First transistor; T2, Second transistor; T3, Third transistor; T4, Fourth transistor; Q1, First switching transistor; Q2, Second switching transistor; Q3, Third switching transistor; Q4, Fourth switching transistor; R1, First resistor; R2, Second resistor; R3, Third resistor; R4, Fourth resistor; VDz, Zener diode; U0, Comparator; U1, First OR gate; U2, Second OR gate; U3, AND gate; Vf1, Refresh rate output terminal of the first display zone; Vf2, Refresh rate output terminal of the second display zone; Vf3, Refresh rate output terminal of the third display zone; Ur, Reference voltage terminal; VDD, Power supply terminal. Detailed Implementation

[0032] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0033] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0034] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0035] Firstly, embodiments of this application provide a control circuit, specifically including the following embodiments:

[0036] Figure 1 The diagram shown is a structural schematic of a control circuit 100 provided in an embodiment of this application; as follows: Figure 1 As shown, the control circuit 100 includes a screen detection module 110, which is configured to detect multiple display parameters of the current display screen, and when it is determined that the current display screen is an abnormal screen based on the multiple display parameters, convert the refresh rate among the multiple display parameters into a corresponding trigger voltage.

[0037] It should be noted that the control circuit 100 in this embodiment can be applied in the display panel, mainly controlling the opening and closing of the ICA function; the screen detection module 110 can be integrated in the timing controller, and through the built-in algorithm or hardware circuit, it can detect multiple display parameters of the current display screen in real time. The multiple display parameters include at least the area of ​​the abnormal area, the grayscale value of the area, and the screen refresh rate.

[0038] Optionally, the image detection module 110 internally presets an area threshold and a grayscale threshold. Only when the detected area and grayscale simultaneously exceed their respective thresholds will the image detection module 110 determine that the current displayed image is an abnormal image; otherwise, it determines that the current displayed image is a normal image. Further, after determining that it is an abnormal image, the image detection module 110 linearly converts the refresh rate into an analog trigger voltage (Ui) through a data converter (e.g., a digital-to-analog converter DAC or a voltage-controlled oscillator VCO). For example, the higher the refresh rate, the higher the output trigger voltage Ui value. It can be seen that this embodiment integrates the information of whether image compensation is needed and the refresh rate into a voltage signal through the image detection module 110, realizing the transformation from complex image parameters to a single, quantifiable electrical signal, laying the foundation for subsequent accurate judgment.

[0039] like Figure 1 As shown, the control circuit 100 of this embodiment also includes a hysteresis comparison module 120. The input terminal of the hysteresis comparison module 120 is connected to the screen detection module 110. The hysteresis comparison module 120 is configured to receive the trigger voltage and output a corresponding switch control signal based on the comparison result between the trigger voltage and the preset hysteresis interval.

[0040] It should be noted that the hysteresis comparison module 120 in this embodiment receives the trigger voltage Ui from the screen detection module 110 and compares it with a preset hysteresis interval. The preset hysteresis interval is defined by an on threshold voltage (V_high) and an off threshold voltage (V_low), where V_high > V_low. Specifically, when the trigger voltage Ui rises from low and first reaches or exceeds the on threshold voltage V_high, the module's output state flips, outputting a first-level switching control signal (e.g., a low level transitioning to a high level). Thereafter, if Ui fluctuates between V_high and V_low, the output state remains unchanged. Only when Ui falls from high and first reaches or falls below V_low does the module's output state flip again, outputting a second-level switching control signal (e.g., a high level transitioning to a low level). By introducing the preset hysteresis interval, frequent switching caused by minute signal fluctuations at a single critical point is eliminated, thereby preventing screen flicker.

[0041] In this embodiment, the control circuit 100 further includes a switch module 130. The control terminal of the switch module 130 is connected to the output terminal of the hysteresis comparison module 120. The first connection terminal of the switch module 130 is connected to the image compensation output terminal 200. The second connection terminal of the switch module 130 is connected to the downstream load 600. The switch module 130 is configured to respond to a switch control signal to turn on or off the signal path between the image compensation output terminal 200 and the downstream load 600.

[0042] It should be noted that the switch module 130 in this embodiment can be implemented by a single switching device, such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Its control terminal receives the switch control signal output from the hysteresis comparator module 120. Its first connection terminal is connected to the image compensation output terminal 200, which is directly connected to the hardware output of the ICA function algorithm within the system. Its second connection terminal is connected to the downstream load 600, which can be a corresponding control pin of a source driver chip (Source IC). When the switch control signal is valid (e.g., high level), the switch module 130 is turned on, establishing a signal path; when the signal is invalid (e.g., low level), the switch module 130 is turned off, disconnecting the signal path.

[0043] In this embodiment, the switch module 130 is connected in series between the ICA function module and the source driver chip that ultimately performs compensation, acting as an electronic switch. It realizes hard on / off control of the ICA function output signal. Its direct effect is that when the switch is off, even if the ICA algorithm is still running internally, its compensation signal cannot be applied to the panel, thereby ensuring that compensation is only enabled when necessary, avoiding the side effects and power consumption that may be caused by unnecessary compensation.

[0044] The specific working principle of the control circuit 100 provided in this embodiment is as follows:

[0045] (1) After the system is powered on, the screen detection module 110 continuously monitors the display screen.

[0046] (2) When a large area of ​​abnormal image with high grayscale appears, the module determines that compensation is required and converts the current refresh rate into the trigger voltage Ui output.

[0047] (3) The hysteresis comparison module 120 compares Ui with the hysteresis interval [V_low, V_high]. If the refresh rate is very high, Ui≥V_high, the hysteresis comparison module 120 outputs a high-level signal, and the switch module 130 is turned on, so that the output signal of the ICA function can be transmitted to the subsequent load 600 (source driver chip) through the turned-on switch module 130, driving the liquid crystal molecules to change the polarity arrangement and implement image compensation.

[0048] (4) If the picture quality improves or the refresh rate drops slightly, causing Ui to fall back, but as long as Ui is still above V_low, the hysteresis comparator module 120 will maintain a high level output, the switch will remain on, and the ICA function will continue to be effective; only when the refresh rate drops significantly, making Ui ≤ V_low, will the hysteresis comparator module 120 output a low level, the switch module 130 will turn off, completely cutting off the transmission path of the ICA signal, and the compensation will stop.

[0049] (5) After that, if the refresh rate increases again, it must reach V_high again before compensation will be enabled again.

[0050] In summary, this application uses the screen detection module 110 to detect and determine in real time whether there is an abnormality in the current display screen. When an abnormal screen is determined, the refresh rate parameter of the screen is converted into a corresponding trigger voltage and output to the hysteresis comparison module 120. The trigger voltage is judged by the hysteresis range with upper and lower thresholds introduced by the hysteresis comparison module 120, effectively filtering out frequent fluctuations in the refresh rate near the critical value, and outputting a stable switching control signal. The switching module 130 responds to the control signal, accurately turning on or off the signal path from the image compensation output to the subsequent driving circuit, thereby realizing the hard enable control of the ICA function. Therefore, this application integrates screen detection, intelligent decision-making, and precise execution through the collaborative work of the screen detection module 110, the hysteresis comparison module 120, and the switch module 130, constructing a closed-loop control that is responsive, stable in judgment, and reliable in execution. Furthermore, by introducing a refresh rate-based hysteresis comparison control mechanism, a stable buffer is set for the start and stop of the ICA function, greatly improving the stability and reliability of the ICA function's start and stop, eliminating the problem of frequent switching of the ICA function and screen flicker caused by fluctuations in parameters such as refresh rate near critical values, thereby significantly improving the visual experience and user experience of the displayed screen.

[0051] In one embodiment, the screen detection module 110 is further configured to: when determining that the current display screen is a normal screen based on multiple display parameters, output a preset voltage to the hysteresis comparison module 120, so that the hysteresis comparison module 120 controls the switch module 130 to disconnect the signal path according to the preset voltage.

[0052] It should be noted that the screen detection module 110 in this embodiment has dual judgment logic, which includes a primary decision unit (e.g., composed of a comparator U0 and logic gates) for determining whether the screen is abnormal. This decision unit continuously performs logical operations (such as AND operations) on the comparison results of the detected abnormal area area and grayscale value with their respective thresholds. Specifically, when the screen is determined to be abnormal: the module performs the operation as described in the above embodiment and outputs a trigger voltage Ui corresponding to the refresh rate; when the screen is determined to be normal (i.e., either the area or grayscale value does not meet the standard): the module ignores the current refresh rate value and forcibly outputs a fixed preset voltage. This preset voltage is set to a value much lower than the hysteresis comparison module 120's shut-off threshold, such as 0V or a constant low-level voltage V_low - ΔV.

[0053] The screen detection module 110 in this embodiment ensures that in any non-abnormal screen scenario, no matter how high the refresh rate, as long as the screen content itself does not have any abnormalities that need to be compensated, the ICA function will not be activated. This conforms to the fundamental principle of on-demand compensation in display drivers, thereby achieving higher reliability, lower power consumption, and better overall image quality.

[0054] In one embodiment, the hysteresis comparison module 120 includes a comparator U0, a first resistor R1, and a second resistor R2; the first input terminal of the comparator U0 serves as the input terminal of the hysteresis comparison module 120, and the output terminal of the comparator U0 serves as the output terminal of the hysteresis comparison module 120; the first terminal of the first resistor R1 is connected to the reference voltage terminal Ur, and the second terminal of the first resistor R1 is connected to the second input terminal of the comparator U0; the first terminal of the second resistor R2 is connected to the second terminal of the first resistor R1, and the second terminal of the second resistor R2 is connected to the output terminal of the comparator U0.

[0055] Optionally, the hysteresis comparator module 120 further includes a third resistor R3, a fourth resistor R4, and a Zener diode VDz; the first end of the third resistor R3 serves as the input terminal of the hysteresis comparator module 120, and the second end of the third resistor R3 is connected to the first input terminal of the comparator U0; the first end of the fourth resistor R4 is connected to the output terminal of the comparator U0, and the second end of the fourth resistor R4 serves as the output terminal of the hysteresis comparator module 120; the first end of the Zener diode VDz is connected to the second end of the fourth resistor R4, and the second end of the Zener diode VDz is grounded.

[0056] It should be noted that in this embodiment, the reference voltage terminal Ur can be ground or the reference voltage output terminal. The first input terminal of comparator U0 can be a non-inverting input terminal, in which case the second input terminal is an inverting output terminal; alternatively, the first input terminal of comparator U0 can be an inverting input terminal, in which case the second input terminal is a non-inverting input terminal. Here, embodiments of the hysteresis comparison module 120 under different combinations are explained:

[0057] (1) Case 1: such as Figure 2 As shown, the reference voltage terminal Ur is ground (reference voltage Ur=0), and the first input terminal of comparator U0 is the inverting input terminal (-). The voltage transfer characteristic is as follows: Figure 3 As shown, Figure 3 In this context, +UT represents the threshold for opening the hysteresis interval, and -UT represents the threshold for closing the hysteresis interval. The Zener diode VDz provides a stable voltage Uz for the output voltage Uo.

[0058] The specific working principle of the hysteresis comparison module 120 in this embodiment is as follows: ① From a positive perspective, when Ui < +UT, Uo outputs a high level; when Ui > +UT, Uo outputs a low level; ② From a negative perspective, when Ui > -UT, Uo outputs a low level; when Ui < -UT, Uo outputs a high level; thus, a hysteresis region (+UT - (-UT)) = 2UT is formed by positive and negative.

[0059] In this embodiment, the switching module 130 is a P-type MOSFET switching transistor. Therefore: ① When the trigger voltage Ui is less than +UT, the output is high, the switching transistor is off, and the ICA is off; when it increases to Ui > +UT, the output is low, the switching transistor is on, and the ICA is on; further increases maintain the on state. ② If the trigger voltage is lower than +UT, since Ui is still > -UT, Uo maintains a low output, so the ICA is on; only when it continues to decrease to Ui < -UT does Uo output a high level, the switching transistor is off, and the ICA is off; further decreases maintain the off state.

[0060] In this embodiment, the opening threshold +UT = +Uo×R1 / (R2+R1) = +Uz×R1 / (R2+R1) and the closing threshold -UT = -Uo×R1 / (R2+R1) = -Uz×R1 / (R2+R1). Therefore, this embodiment can achieve different hysteresis ranges and thus different hysteresis magnitudes by modifying the ratio of the first resistor R1 and the second resistor R2 or the regulated voltage Uz.

[0061] (2) Case 2: such as Figure 4 As shown, the reference voltage terminal Ur is connected to the reference voltage source (Ur≠0), and the first input terminal of comparator U0 is the inverting input terminal (-). The voltage transfer characteristic is as follows. Figure 5 As shown; this embodiment, by introducing a reference voltage Ur, can achieve asymmetric shift of the hysteresis interval. Its voltage transfer characteristic curve is parallel to Case 1, but the overall curve is shifted along the voltage axis. The operating logic is exactly the same as Case 1, only the threshold voltage changes.

[0062] Switch control logic: exactly the same as in case one.

[0063] The threshold for enabling UT is calculated as follows: +UT = Ur × R2 / (R1+R2) + Uz × R1 / (R1+R2); the threshold for disabling UT is calculated as -UT = Ur × R2 / (R1+R2) - Uz × R1 / (R1+R2). The hysteresis center point is Ur × R2 / (R1+R2). By adjusting Ur, the specific hysteresis interval position required for different application scenarios can be matched.

[0064] (3) Case 3: such as Figure 6 As shown, the reference voltage terminal Ur is grounded (Ur=0), and the first input terminal of comparator U0 is the positive input terminal (+). The voltage transfer characteristic is as follows. Figure 7 As shown; this embodiment constitutes an in-phase hysteresis comparator U0, whose output state flips in the opposite phase to that in case one; specifically:

[0065] ① Forward process (Ui increases from low to high): When Ui < -UT, Uo outputs a low level (≈ -Uz); ​​when Ui > -UT, Uo flips to a high level (≈ +Uz); when Ui increases below -UT, the output remains at a low level.

[0066] ② Negative process (Ui decreases from high to low): When Ui < +UT, Uo maintains the already flipped high level (≈ +Uz); when Ui > +UT, Uo flips to low level (≈ -Uz); ​​when Ui decreases above +UT, the output remains at a high level.

[0067] Switch control logic (requires replacing the switch module 130 with an N-MOS transistor): Due to the reversed output logic, an N-MOS transistor must be used. When Uo outputs a high level, the N-MOS transistor is turned on, enabling the ICA; when it outputs a low level, it is turned off. Specifically:

[0068] ① Enable process: When Ui increases to exceed -UT, Uo jumps to a high level, N-MOS turns on, and ICA is enabled.

[0069] ② Shutdown process: When Ui drops below +UT, Uo jumps to low level, N-MOS is turned off, and ICA is turned off.

[0070] Threshold calculation:

[0071] The turn-on threshold (for N-MOS) is +Ut = +Uz × R1 / (R2+R1);

[0072] The shutdown threshold (for N-MOS) is -Ut = -Uz × R1 / (R2+R1).

[0073] It should be noted that this formula is the same as Case 1, but its physical meaning has changed due to the different input phase and the type of switching transistor.

[0074] (4) Case 4: such as Figure 8 As shown, the reference voltage terminal Ur is connected to the reference voltage source (Ur≠0), and the first input terminal of comparator U0 is the positive input terminal (+). The voltage transfer characteristic is as follows. Figure 9 As shown; this embodiment combines the features of Case 2 and Case 3, and can both move the hysteresis interval and have in-phase output characteristics.

[0075] Operating principle: The voltage transfer characteristic curve of case three is shifted along the voltage axis. The operating logic is the same as that of case three.

[0076] Switch control logic: Same as case 3, but requires the use of an N-MOS transistor.

[0077] Threshold calculation:

[0078] Turn-on threshold (for N-MOS) + UT = Vref × R2 / (R1+R2) + Uz × R1 / (R1+R2);

[0079] The shutdown threshold (for N-MOS) is: -UT = Vref × R2 / (R1+R2) - Uz × R1 / (R1+R2).

[0080] It should be noted that this configuration has the ability to adjust the position of the hysteresis interval and control in phase, making it the most flexible.

[0081] Secondly, embodiments of this application provide an image compensation control device 300, specifically including the following embodiments:

[0082] Figure 10 The diagram shown is a structural schematic of the first image compensation control device provided in this application embodiment; as follows: Figure 10 As shown, the image compensation control device 300 of this embodiment is applied to a display panel, which includes N display zones, and each display zone corresponds to a data drive circuit 500. With the increasing sophistication of current market products, more display devices adopt zoned refresh rates, using different refresh rates in different areas according to image requirements to achieve better energy efficiency. Image distortion is more severe at high refresh rates, while it is slight or nonexistent at low refresh rates. Therefore, this embodiment adds separate control functions to the ICA of different refresh areas, allowing them to switch between a global unified mode and a zone-specific mode as needed. The image compensation output terminal 200 of this embodiment includes, but is not limited to, a whole-zone compensation output terminal 210, a first zone compensation output terminal 220, a second zone compensation output terminal 230, and a third zone compensation output terminal 240.

[0083] Specifically, the image compensation control device 300 in this embodiment includes a main control circuit 310, which is a specific instance of the control circuit 100 in the above embodiment. It is configured to generate a whole-area control signal based on the display parameters of the display panel. It should be noted that the screen detection module 110 in the main control circuit 310 of this embodiment detects the area of ​​abnormal regions, grayscale, and global refresh rate (when all zone refresh rates are consistent) or representative refresh rate of the entire display panel. Its hysteresis comparison module 120 generates a whole-area control signal based on this comprehensive information. This whole-area control signal represents a global perspective on whether and when to enable the ICA function. Therefore, the main control circuit 310 provides a unified ICA control strategy based on the global screen condition, ensuring that the ICA state of the entire screen is synchronized when the full-screen refresh rate is consistent. This not only avoids visual fragmentation caused by inconsistent compensation in different areas but also reduces power consumption.

[0084] Optionally, the image compensation control device 300 of this embodiment further includes N partition control circuits 320, each partition control circuit 320 being a specific instance of the control circuit 100 in the above embodiment; each partition control circuit 320 is configured to generate a partition control signal based on the display parameters of the corresponding display partition. It should be noted that each partition control circuit 320 is a complete and autonomous ICA decision unit, configured to work only based on the display parameters of the specific display partition it is responsible for: that is, the screen detection module 110 of each partition control circuit 320 only detects the abnormal area area, grayscale, and local refresh rate of the corresponding partition; the hysteresis comparison module 120 of each partition control circuit 320 independently generates a partition control signal for that partition; therefore, the N partition control circuits 320 enable each display partition to independently decide whether to enable ICA compensation according to its own actual situation (whether there is an anomaly, high or low refresh rate), realizing fine control of the ICA function with on-demand allocation and precise compensation, which is particularly suitable for partition refresh scenarios.

[0085] Optionally, the image compensation control device 300 of this embodiment further includes a mode switching circuit 330, coupled to the mode output terminal 400, the main control circuit 310, the N partition control circuits 320, and the N data driving circuits 500; the mode switching circuit 330 is configured to input the whole area control signal to the N data driving circuits 500 in response to a first mode selection signal input from an external source; and to input the partition control signal generated by the i-th partition control circuit 320 to the i-th data driving circuit 500 in response to a second mode selection signal input from an external source, where i=1,...,N.

[0086] It should be noted that the mode output terminal 400 in this embodiment can be the output terminal of an external circuit or another output terminal with mode recognition function in the image compensation control device 300; the mode selection signal output by the mode output terminal 400 includes a first mode selection signal for indicating that the display panel is currently in the whole area refresh mode, and a second mode selection signal for indicating that the display panel is currently in the partition refresh mode.

[0087] In this embodiment, the mode switching circuit 330 routes the correct control signal to the corresponding data driving circuit 500 based on the mode selection signal. Specifically:

[0088] (1) When the first mode selection signal is valid, the mode switching circuit 330 simultaneously inputs the whole area control signal generated by the main control circuit 310 to all N data drive circuits 500. At this time, the ICA state of the entire screen is uniformly determined by the main control circuit 310.

[0089] (2) When the second mode selection signal is valid, the mode switching circuit 330 inputs the partition control signal generated by the i-th partition control circuit 320 to the i-th data drive circuit 500. At this time, the ICA state of each partition is independently controlled by its own partition control circuit 320.

[0090] Therefore, this embodiment enables the ICA control system to dynamically adapt to different operating modes of the display device (global refresh or partition refresh) through the mode switching circuit 330, always maintaining the optimal compensation strategy; and supports two operating modes through a single hardware architecture, eliminating the need to design independent control circuits 100 for each mode, thus saving chip area and cost. This embodiment ensures a smooth transition of ICA function control in different display modes, avoiding screen jitter or flickering caused by mode switching.

[0091] The specific working principle of the image compensation control device 300 provided in this embodiment is as follows:

[0092] (1) After system initialization, the main control circuit 310 and all partition control circuits 320 work in parallel, continuously generating their respective whole-area control signals and partition control signals based on global and local information.

[0093] (2) The timing controller determines and outputs the corresponding mode selection signal to the mode switching circuit 330 based on the current display content and working status.

[0094] (3) The mode switching circuit 330 switches the signal path in real time according to the received mode command: ① In whole-area refresh scenarios such as watching movies or browsing web pages, the mode switching circuit 330 broadcasts the command of the main control circuit 310 to all partitions to achieve unified control. ② In partition refresh scenarios such as games or videos, the mode switching circuit 330 sends the decisions of each partition control circuit 320 to the area it is responsible for to achieve independent control.

[0095] (4) Finally, the control signal selected by the mode switching circuit 330 reaches the data driving circuit 500 to control the final execution of the ICA function.

[0096] This embodiment constructs an intelligent image compensation control device 300 that combines centralized management and distributed control through the coordinated operation of the main control circuit 310, multiple partition control circuits 320, and mode switching circuit 330. It creatively solves the control adaptation problem of ICA function in the new generation of partition refresh display technology, enabling the ICA function to intelligently select the optimal control strategy in both global unified refresh and partition independent refresh modes. While effectively eliminating crosstalk and flicker, it achieves the best balance between power consumption and image quality, greatly improving the overall user experience of partition refresh display devices.

[0097] Figure 11 The diagram shown is a structural schematic of the second image compensation control device provided in an embodiment of this application; as shown Figure 11 As shown, the mode switching circuit 330 includes: N first transistors T1, the control terminal of the first transistor T1 is connected to the mode output terminal 400, the first terminal of the first transistor T1 is connected to the output terminal of the partition control circuit 320, and the second terminal of the first transistor T1 is connected to the data driving circuit 500.

[0098] Optionally, the mode switching circuit 330 of this embodiment further includes N-1 second transistors T2. The control terminal of each second transistor T2 is connected to the mode output terminal 400. The first terminal of the first second transistor T2 is connected to the output terminal of the main control circuit 310 and the first data driving circuit 500, respectively. The first terminal of the j-th second transistor T2 is connected to the second terminal of the (j-1)-th second transistor T2 and the j-th data driving circuit 500, respectively. The second terminal of the (N-1)-th second transistor T2 is connected to the N-th data driving circuit 500; where j=2,...,N-1; the turn-on voltages of the first transistor T1 and the second transistor T2 are opposite.

[0099] Here, taking N=3, with the first transistor T1 being a PMOS transistor and the second transistor T2 being an NMOS transistor as an example, combined with... Figure 11 The working principle of the mode switching circuit 330 in this embodiment will be described in detail below:

[0100] (1) Global control mode, that is: the output signal S of the mode output terminal 400 is high level (that is, the first mode selection signal is valid).

[0101] All first transistors T1 are disconnected when the control terminal is high, thereby disconnecting the signal paths between all partition control circuits 320 and partition data drive circuits 500; all second transistors T2 are turned on when the control terminal is high, and the whole-area control signal generated by the main control circuit 310 acts on the data drive circuit 500 corresponding to each display partition, realizing the ICA function to be turned on or off uniformly throughout the entire screen.

[0102] (2) Partition control mode, that is: the output signal S of the mode output terminal 400 is low (that is, the second mode selection signal is valid).

[0103] All second transistors T2 are turned off when the control terminal is low, thus disconnecting the signal path between the main control circuit 310 and the partition data drive circuit 500; all first transistors T1 are turned on when the control terminal is low, so that the partition control signal generated by each partition control circuit 320 is sent to the corresponding partition data drive circuit 500, so that each display partition receives its own independent partition control signal, and the ICA function is independently controlled in each partition without affecting each other.

[0104] This embodiment provides a specific and feasible implementation of the mode switching circuit 330. Through N first transistors T1 and N-1 second transistors T2 connected in a chain, and with complementary control signals, a reliable switching between global unified control and zone-independent control is clearly and clearly achieved.

[0105] Figure 12 The diagram shown is a structural schematic of the third image compensation control device provided in this application embodiment; as follows: Figure 12 As shown, when the N display partitions include a first display partition, a second display partition, and a third display partition, the image compensation control device 300 further includes: a first frequency comparator 340, the first input terminal of the first frequency comparator 340 is connected to the refresh rate output terminal Vf1 of the first display partition, the second input terminal of the first frequency comparator 340 is connected to the refresh rate output terminal Vf2 of the second display partition, and the output terminal of the first frequency comparator 340 is connected to the control terminal of the first transistor T1, the control terminal of the second transistor T1, and the control terminal of the first transistor T2, respectively.

[0106] Optionally, the image compensation control device 300 further includes: a second frequency comparator 350, the first input terminal of the second frequency comparator 350 being connected to the refresh rate output terminal Vf2 of the second display zone, the second input terminal of the second frequency comparator 350 being connected to the refresh rate output terminal Vf3 of the third display zone, and the output terminal of the second frequency comparator 350 being connected to the control terminal of the third first transistor T1 and the control terminal of the second second transistor T2, respectively.

[0107] It should be noted that each frequency comparator in this implementation compares the refresh rates of two adjacent partitions in real time. When the refresh rates of the two partitions are the same, it outputs a valid control signal to trigger the following intelligent behaviors: (1) When the refresh rates are the same: the frequency comparator outputs a valid level to control the corresponding first transistor T1 to turn off and the second transistor T2 to turn on; (2) When the refresh rates are different: the frequency comparator outputs an invalid level to control the corresponding first transistor T1 to turn on and the second transistor T2 to turn off.

[0108] This embodiment is in Figure 11 Based on the two basic modes shown, a more intelligent dynamic group control is implemented. The specific working principle is as follows:

[0109] (1) Scenario 1: All partitions have the same refresh rate

[0110] The first frequency comparator 340 detects that the refresh rates of the first display partition and the second display partition are the same and outputs a valid signal C_AB. The second frequency comparator 350 detects that the refresh rates of the second display partition and the third display partition are the same and outputs a valid signal C_BC. Then all the first transistors T1 are turned off and all the second transistors T2 are turned on. The image compensation control device 300 automatically enters the global control mode, and the three partitions share the whole-area control signal of the total control circuit 310.

[0111] (2) Scenario 2: The first and second display partitions have the same refresh rate, while the third display partition has a different refresh rate.

[0112] The first frequency comparator 340 outputs a valid signal C_AB, and the second frequency comparator 350 outputs an invalid signal C_BC. As a result, the first and second first transistors T1 are both turned off, the third first transistor T1 is turned on, the first second transistor T2 is turned on, and the second second transistor T2 is turned off. Therefore, the first and second display zones share the overall control signal through the turned-on first second transistor T2, and the third display zone receives the corresponding independent control signal through the turned-on third first transistor T1, thereby realizing a hybrid mode of unified control of the first and second display zones and independent control of the third display zone.

[0113] (3) Scenario 3: The refresh rates of the three display partitions are different.

[0114] The first frequency comparator 340 outputs an invalid signal C_AB, the second frequency comparator 350 outputs an invalid signal C_BC, all first transistors T1 are turned on, all second transistors T2 are turned off, and the image compensation control device 300 automatically enters the full partition control mode, where each partition is independently controlled by its own control circuit 100.

[0115] This embodiment introduces a frequency comparator U0 to achieve a technical improvement in switching from a fixed mode to intelligent dynamic grouping. This adaptive control strategy not only improves the system's efficiency but also significantly enhances the display device's image quality and power consumption control capabilities in different application scenarios, representing a new direction in the development of image compensation control technology.

[0116] In one embodiment, such as Figure 13 As shown, the first frequency comparator 340 includes: a first switch Q1, a second switch Q2, a third switch Q3, and a fourth switch Q4. Specifically, the control terminal of the first switch Q1 serves as the first input terminal of the first frequency comparator 340, the first terminal of the first switch Q1 serves as the output terminal of the first frequency comparator 340, and the second terminal of the first switch Q1 is connected to the power supply terminal VDD. The control terminal of the second switch Q2 serves as the second input terminal of the first frequency comparator 340, and the first terminal of the second switch Q2 is connected to the power supply terminal VDD. The control terminal of the third switch Q3 is connected to the control terminal of the second switch Q2, and the first terminal of the third switch Q3 is connected to the second terminal of the second switch Q2. The control terminal of the fourth switch Q4 is connected to the control terminal of the first switch Q1, the first terminal of the fourth switch Q4 is connected to the second terminal of the third switch Q3, and the second terminal of the fourth switch Q4 is grounded.

[0117] It should be noted that in this embodiment, the first switch Q1 and the fourth switch Q4 are controlled by the refresh rate output terminal Vf1 of the first display partition, and the second switch Q2 and the third switch Q3 are controlled by the refresh rate output terminal Vf2 of the second display partition, thus forming two parallel control paths. The specific working principle is as follows:

[0118] (1) Case 1, Vf1 outputs high level, Vf2 outputs high level: the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4 are all turned on, thus outputting a high level.

[0119] (2) Case 2, Vf1 outputs high level and Vf2 outputs low level: the first switch Q1 is turned on, the second switch Q2 is turned off, the third switch Q3 is turned off and the fourth switch Q4 is turned on, thus outputting a high level.

[0120] (3) Case 3, Vf1 outputs low level and Vf2 outputs high level: the first switch Q1 is off, the second switch Q2 is on, the third switch Q3 is on and the fourth switch Q4 is off, thus outputting a low level.

[0121] (4) Case 4, Vf1 outputs low level, Vf2 outputs low level: the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4 are all turned off, thus outputting a high level.

[0122] In this embodiment, the first frequency comparator 340 implements the frequency comparison function of two input signals through four switching transistors. It outputs a high level when the frequency of the first display zone is not lower than the frequency of the second display zone; otherwise, it outputs a low level. This simple comparison logic, combined with the subsequent control circuit 100, realizes intelligent detection and dynamic grouping control of the display zone refresh rate, providing key technical support for the adaptive optimization of the image compensation system. Furthermore, the specific circuit structure of the second frequency comparator 350 in this embodiment is the same as that of the first frequency comparator 340, and will not be described again here.

[0123] Figure 14 The diagram shown is a structural schematic of the fourth image compensation control device provided in this application embodiment; as follows: Figure 14 As shown, the image compensation control device 300 in Figure 11 In addition, it also includes: a percentage determination circuit 360, which is connected to the refresh rate output terminal of each display partition, the main control circuit 310 and the mode switching circuit 330 respectively, and is configured to output a mode switching decision signal based on the percentage of the number of partitions in the N display partitions that are in the high refresh rate state; the mode switching decision signal is used to control the conduction state of the mode switching circuit 330 with the main control circuit 310 and the mode output terminal 400 respectively.

[0124] It should be noted that the image compensation control device in this embodiment may include the following functional modules:

[0125] (1) Refresh rate status detection unit: connected to the refresh rate output terminal of each display partition, and monitors the refresh rate status of each partition in real time. This unit compares the refresh rate with the preset high refresh rate threshold, determines whether each partition is in a high refresh rate state, and outputs the corresponding digital signal (e.g., high refresh rate = 1, low refresh rate = 0).

[0126] (2) Percentage Calculation and Decision Unit: Receives refresh rate status signals from all partitions, calculates the percentage of partitions currently in a high refresh rate state, and outputs a mode switching decision signal according to a preset hysteresis strategy. This unit contains the following core logic: ① When the percentage of high refresh rate partitions reaches or exceeds the first threshold, the output decision signal enables global ICA mode; ② When the percentage of high refresh rate partitions reaches or falls below the second threshold, the output decision signal enables partition ICA mode; ③ When the percentage is between the first and second thresholds, the current mode state remains unchanged; where the first threshold is greater than the second threshold, forming a decision hysteresis interval.

[0127] Here, taking N=3, the first threshold as 2 / 3, and the second threshold as 1 / 3 as an example, the working principle of the image compensation control device 300 in this embodiment is as follows:

[0128] (1) Conditional path for switching from partition mode to global mode: The initial state is partition ICA mode; when the number of high refresh rate partitions increases from 1 to 2, the proportion increases from 1 / 3 to 2 / 3; when the proportion reaches the first threshold (2 / 3), the proportion judgment circuit 360 outputs the mode switching decision signal; the mode switching circuit 330 responds to this signal and switches to global ICA mode; all partitions are subject to the unified control of the general control circuit 310.

[0129] (2) Conditional path for switching from global mode to partition mode: The initial state is global ICA mode; when the number of high refresh rate partitions decreases from 2 to 1, the proportion decreases from 2 / 3 to 1 / 3; when the proportion reaches the second threshold (1 / 3), the proportion judgment circuit 360 outputs the mode switching decision signal; the mode switching circuit 330 responds to this signal and switches to partition ICA mode; each partition is independently controlled by the corresponding partition control circuit 320.

[0130] (3) Hysteresis hold mode: When the system is in global ICA mode, even if the proportion of high refresh rate partitions decreases from 3 to 2 (the proportion decreases from 100% to 67%), as long as the proportion is still between 2 / 3 and 1 / 3, global ICA mode is maintained; when the system is in partition ICA mode, even if the proportion of high refresh rate partitions increases from 1 to 2 (the proportion increases from 33% to 67%), as long as the proportion is still between 1 / 3 and 2 / 3, partition ICA mode is maintained.

[0131] This embodiment introduces a proportion judgment circuit 360 to achieve intelligent mode decision-making based on the proportion of high refresh rate areas, enabling the image compensation control device 300 to have scene adaptation capabilities. This innovative control strategy not only solves the limitations of traditional fixed mode switching but also ensures the stability of system operation through a hysteresis mechanism, representing an important direction for the development of image compensation technology towards intelligence and adaptability.

[0132] Figure 15 The diagram shown is a structural schematic of the fifth image compensation control device provided in this application embodiment; as follows: Figure 15 As shown, when there are N display zones including a first display zone, a second display zone, and a third display zone, the percentage determination circuit 360 includes a first OR gate U1, a second OR gate U2, an AND gate U3, a third transistor T3, and a fourth transistor T4. Specifically, the first input terminal of the first OR gate U1 is connected to the refresh rate output terminal Vf1 of the first display zone, and the second input terminal of the first OR gate U1 is connected to the refresh rate output terminal Vf2 of the second display zone; the first input terminal of the second OR gate U2 is connected to the refresh rate output terminal Vf2 of the second display zone, and the second input terminal of the second OR gate U2 is connected to the refresh rate output terminal Vf3 of the third display zone. The two input terminals of AND gate U3 are connected to the output terminals of the first OR gate U1 and the second OR gate U2, respectively. The control terminal of the third transistor T3 is connected to the output terminal of AND gate U3, the first terminal of the third transistor T3 is connected to the mode output terminal 400, and the second terminal of the third transistor T3 is connected to the mode switching circuit 330. The control terminal of the fourth transistor T4 is connected to the output terminal of AND gate U3, the first terminal of the fourth transistor T4 is connected to the output terminal of the main control circuit 310, and the second terminal of the fourth transistor T4 is connected to the mode switching circuit 330. The turn-on voltages of the third transistor T3 and the fourth transistor T4 are opposite.

[0133] It should be noted that the percentage determination circuit 360 in this embodiment uses logic gate combinations and transistor switches to achieve intelligent judgment and mode control of the high refresh rate state of the three display zones. The specific working principle is as follows:

[0134] (1) Signal acquisition and preliminary processing: The first OR gate U1 monitors the high refresh rate status of the first and second display partitions in real time, and the second OR gate U2 monitors the high refresh rate status of the second and third display partitions in real time. This cross-detection design ensures that the high refresh rate status of any two adjacent partitions can be accurately identified.

[0135] (2) Proportion judgment logic: AND gate U3 performs AND operation on the outputs of two OR gates. That is, AND gate U3 outputs a high level if and only if at least two partitions are in a high refresh rate state.

[0136] (3) Mode switching execution: ① When AND gate U3 outputs a high level (high refresh rate ≥ 2 / 3), the third transistor T3 is turned on, transmitting the control signal from the mode output terminal 400 to the mode switching circuit 330, and the fourth transistor T4 is turned off, blocking the signal path of the main control circuit 310, and the system switches to global ICA mode. ② When AND gate U3 outputs a low level (high refresh rate ≤ 1 / 3): the third transistor T3 is turned off, blocking the control signal from the mode output terminal 400; the fourth transistor T4 is turned on, transmitting the whole-area control signal from the main control circuit 310 to the mode switching circuit 330, and the system switches to partition ICA mode.

[0137] (4) Hysteresis characteristics: Through the complementary switching action of the third transistor T3 and the fourth transistor T4, a natural hysteresis interval is formed between the 1 / 3 and 2 / 3 ratio points. The system will remain stable in the current mode until the number of high refresh rate partitions crosses the set ratio threshold.

[0138] The proportion determination circuit 360 in this embodiment achieves intelligent mode decision-making based on the proportion of high refresh rate areas through ingenious logic gate combination and transistor switching design. This circuit is not only simple and inexpensive to implement in hardware, but also possesses accurate judgment capabilities and reliable anti-jitter characteristics, providing crucial support for the stable and efficient operation of the image compensation control device 300 in various complex display scenarios.

[0139] Thirdly, embodiments of this application provide a display panel including a display area and a non-display area. The display area includes a pixel array; the non-display area includes a timing controller, a source drive circuit, and the aforementioned image compensation control device. The image compensation control device is electrically connected to the timing controller and the source drive circuit, respectively.

[0140] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0141] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0142] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A control circuit, characterized in that, The control circuit includes: The screen detection module is configured to detect multiple display parameters of the currently displayed screen, and when it is determined that the current displayed screen is an abnormal screen based on the multiple display parameters, convert the refresh rate among the multiple display parameters into a corresponding trigger voltage; it is also configured to: when it is determined that the current displayed screen is a normal screen based on the multiple display parameters, output a preset voltage to a hysteresis comparison module, causing the hysteresis comparison module to control a switching module to disconnect the signal path according to the preset voltage; wherein, the screen detection module linearly converts the refresh rate into an analog trigger voltage through a data converter; A hysteresis comparison module, the input of which is connected to the image detection module, is configured to receive the trigger voltage and output a corresponding switch control signal based on the comparison result of the trigger voltage and a preset hysteresis interval. A switch module is provided, wherein the control terminal of the switch module is connected to the output terminal of the hysteresis comparison module, the first connection terminal of the switch module is connected to the image compensation output terminal, and the second connection terminal of the switch module is connected to the downstream load. The switch module is configured to respond to the switch control signal to turn on or off the signal path between the image compensation output terminal and the downstream load.

2. The control circuit according to claim 1, characterized in that, The hysteresis comparison module includes: A comparator, wherein the first input terminal of the comparator serves as the input terminal of the hysteresis comparison module, and the output terminal of the comparator serves as the output terminal of the hysteresis comparison module; A first resistor, the first end of which is connected to a reference voltage terminal, and the second end of which is connected to the second input terminal of the comparator; The second resistor has its first end connected to the second end of the first resistor, and its second end connected to the output of the comparator.

3. The control circuit according to claim 2, characterized in that, The hysteresis comparison module also includes: The third resistor has its first end serving as the input terminal of the hysteresis comparator module, and its second end connected to the first input terminal of the comparator. The fourth resistor has its first end connected to the output of the comparator and its second end serving as the output of the hysteresis comparator module. A Zener diode, wherein the first terminal of the Zener diode is connected to the second terminal of the fourth resistor, and the second terminal of the Zener diode is grounded.

4. An image compensation control device, characterized in that, It is applied to a display panel, which includes N display zones, and each display zone corresponds to a data driving circuit; The image compensation control device includes: A main control circuit, which is the control circuit according to any one of claims 1-3, is configured to generate a whole-area control signal based on the display parameters of the display panel; N partition control circuits, each partition control circuit being the control circuit described in any one of claims 1-3; each partition control circuit is configured to generate a partition control signal based on the display parameters of the corresponding display partition; A mode switching circuit is coupled to the mode output terminal, the main control circuit, the N partition control circuits, and the N data drive circuits. The mode switching circuit is configured to input the whole-area control signal to the N data drive circuits in response to a first mode selection signal input from an external input; and to input the partition control signal generated by the i-th partition control circuit to the i-th data drive circuit in response to a second mode selection signal input from an external input, where i=1,...,N.

5. The image compensation control device according to claim 4, characterized in that, The mode switching circuit includes: N first transistors, the control terminal of the first transistor is connected to the mode output terminal, the first terminal of the first transistor is connected to the output terminal of the partition control circuit, and the second terminal of the first transistor is connected to the data driving circuit. There are N-1 second transistors, with the control terminal of each second transistor connected to the mode output terminal. The first terminal of the first second transistor is connected to the output terminal of the main control circuit and the first data driving circuit. The first terminal of the j-th second transistor is connected to the second terminal of the (j-1)-th second transistor and the j-th data driving circuit. The second terminal of the (N-1)-th second transistor is connected to the N-th data driving circuit. Where j = 2, ..., N-1, the turn-on voltages of the first and second transistors are opposite.

6. The image compensation control device according to claim 5, characterized in that, When the N display zones include a first display zone, a second display zone, and a third display zone, the image compensation control device further includes: A first frequency comparator has its first input terminal connected to the refresh rate output terminal of the first display partition, its second input terminal connected to the refresh rate output terminal of the second display partition, and its output terminal connected to the control terminals of the first first transistor, the second first transistor, and the first second transistor, respectively. The second frequency comparator has its first input terminal connected to the refresh rate output terminal of the second display partition, its second input terminal connected to the refresh rate output terminal of the third display partition, and its output terminal connected to the control terminal of the third first transistor and the control terminal of the second second transistor, respectively.

7. The image compensation control device according to claim 4, characterized in that, The image compensation control device further includes: The percentage determination circuit is connected to the refresh rate output terminal of each display partition, the main control circuit, and the mode switching circuit, respectively. It is configured to output a mode switching decision signal based on the percentage of partitions in the N display partitions that are in a high refresh rate state. The mode switching decision signal is used to control the conduction state of the mode switching circuit with the main control circuit and the mode output terminal, respectively.

8. The image compensation control device according to claim 7, characterized in that, When the N display partitions include a first display partition, a second display partition, and a third display partition, the percentage determination circuit includes: A first OR gate, wherein the first input terminal of the first OR gate is connected to the refresh rate output terminal of the first display partition, and the second input terminal of the first OR gate is connected to the refresh rate output terminal of the second display partition; The second OR gate has its first input connected to the refresh rate output of the second display zone, and its second input connected to the refresh rate output of the third display zone. The AND gate, wherein the two input terminals of the AND gate are respectively connected to the output terminals of the first OR gate and the second OR gate; The third transistor has its control terminal connected to the output terminal of the AND gate, its first terminal connected to the mode output terminal, and its second terminal connected to the mode switching circuit. The fourth transistor has its control terminal connected to the output terminal of the AND gate, its first terminal connected to the output terminal of the main control circuit, and its second terminal connected to the mode switching circuit. The turn-on voltages of the third transistor and the fourth transistor are opposite.

9. A display panel, comprising a display area and a non-display area, characterized in that, The display area includes a pixel array; The non-display area includes a timing controller, a source drive circuit, and an image compensation control device as described in any one of claims 4-8, wherein the image compensation control device is electrically connected to the timing controller and the source drive circuit, respectively.

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