Adaptive method for efficient readout of retention degraded NAND data

Abstract

The present disclosure relates to an adaptive method for efficiently reading out retention degraded NAND data. A method of operating a computing device having a solid state drive (SSD) is provided that includes obtaining a pre-existing read retry table, the read retry table including a sequential list of voltage index sets for reading flash memory of the SSD; determining aging parameters of the SSD; identifying a retry voltage index set from the sequential list based on the aging parameter; and reading the flash memory using the retry voltage index set.

Description

Technical Field

[0001] This disclosure relates to a method for controlling a computing device having a solid-state drive (SSD) including flash memory. Background Technology

[0002] SSDs (such as NAND or NOR-based memory devices) offer significantly faster read and write speeds compared to hard drives in computing devices. However, like any other type of storage medium, the information stored in flash memory can be corrupted due to degradation. One mechanism of degradation in flash memory is charge loss, which causes bit read errors when reading from the flash. Effective methods to compensate for charge loss require ensuring accurate memory reads and maintaining full utilization of the flash memory. Summary of the Invention

[0003] In general, one or more embodiments of the present invention relate to a method of operating a computing device having a solid-state drive (SSD). The method includes: obtaining a pre-existing read retry table, the read retry table including an ordered list of voltage index sets for reading flash memory of the SSD; determining aging parameters of the SSD; identifying a retry voltage index set from the ordered list based on the aging parameters; and using the retry voltage index set to read the flash memory.

[0004] In general, one or more embodiments of the present invention relate to a non-transitory computer-readable medium (CRM) storing computer-readable program code for operating a computing device having an SSD. The computer-readable program code enables the computing device to: obtain a pre-existing read retry table, the read retry table including an ordered list of voltage index sets for reading flash memory of the SSD; determine aging parameters of the SSD; identify a retry voltage index set from the ordered list based on the aging parameters; and use the retry voltage index set to read the flash memory.

[0005] Generally, one or more embodiments of the present invention relate to a computer device comprising: a solid-state drive (SSD) including flash memory; and a processor configured to read the flash memory. The processor is configured to: obtain a pre-existing read retry table, the read retry table including an ordered list of voltage index sets for reading the flash memory; determine aging parameters of the SSD; identify a retry voltage index set from the ordered list based on the aging parameters; and use the retry voltage indexes to read the flash memory.

[0006] Other aspects of the invention will become apparent from the following description and the appended claims. Attached Figure Description

[0007] Figure 1A A perspective view of a computing device according to one or more embodiments of the present invention is shown.

[0008] Figure 1B The invention illustrates one or more embodiments thereof. Figure 1A A schematic diagram of the various sub-components of the computing device.

[0009] Figure 1C The invention illustrates one or more embodiments thereof. Figure 1A A schematic diagram of a sub-component of an SSD in a computing device.

[0010] Figure 2A A schematic diagram of an SSD's flash memory cell is shown.

[0011] Figure 2B A graph showing a typical readout and a degraded readout from flash memory is shown.

[0012] Figure 2C A pre-existing read retry table for reading flash memory is shown.

[0013] Figures 3A to 3B A flowchart of a method according to one or more embodiments of the present invention is shown.

[0014] Figure 4 Examples of retry patterns generated according to one or more implementations are shown.

[0015] Figure 5 Non-limiting examples of read retry processing workflows according to one or more implementations are shown. Detailed Implementation

[0016] Specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. For consistency, the same elements in the various drawings are indicated by the same reference numerals.

[0017] In the following detailed description of embodiments of the invention, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.

[0018] To counteract read degradation and maintain SSD functionality, conventional solutions employ read retry processing with iterative voltage settings to reread any portion of the flash memory containing bit read errors. As described further in detail below, embodiments of the present invention utilize one or more adaptive read retry voltage index sets (i.e., their patterns) to improve read retry processing, which enhances the speed and efficiency of read retry processing.

[0019] Figure 1AA perspective view of a computing device 10 according to one or more embodiments of the present invention is shown.

[0020] The computing device 10 (e.g., a laptop PC, tablet PC, desktop PC, convertible PC) is equipped with at least one SSD. Embodiments of the present invention can be implemented on virtually any type of computing device 10, regardless of the platform used. For example, the computing device 10 can be one or more mobile devices (e.g., laptop computers, smartphones, personal digital assistants, tablet computers, or other mobile devices), desktop computers, servers, blade servers in server chassis, or any other type of computing device that includes at least minimum processing power, memory, and input and output devices to perform one or more embodiments of the present invention.

[0021] Figure 1B The invention illustrates one or more embodiments thereof. Figure 1A A schematic diagram of the various sub-components of the computing device 10.

[0022] The computing device 10 includes a motherboard MB having multiple sub-components. Sub-components mounted on the motherboard MB may include a central processing unit (CPU) 12, memory 14, a graphics processing unit (GPU) 16 (e.g., a video subsystem), a chipset 18, firmware memory 20, an embedded controller 22, power control circuitry 24, and a storage device 26 (e.g., a hard disk drive (HDD) or a solid-state drive (SSD)). The computing device 10 may also include a fan and a power supply unit.

[0023] In one or more embodiments, the above-mentioned sub-components of computing device 10 may be omitted, included in multiple numbers, combined into a single sub-component (e.g., a processor acting as a controller for one or more sub-components), and / or disposed in other parts of computing device 10. For example, the SSD described herein may be a separate component in the configuration of computing device 10, an embedded component (e.g., part of storage device 26), any combination of the above, or any suitable implementation.

[0024] Additionally, it should be understood that other sub-components besides those listed above (e.g., peripheral devices, removable components, external power supply devices) may be included internally or externally as sub-components of the computing device 10 without departing from the scope of this disclosure. For example, although the following implementation is described with respect to an internal SSD, the present invention is applicable to any type of SSD (e.g., an external SSD) connected to the computing device 10.

[0025] As discussed above, embodiments of the present invention can be implemented on virtually any type of computing device 10. For example, computing device 10 may include one or more computer processors, associated memory (e.g., random access memory (RAM), cache memory, flash memory), one or more storage devices, and many other elements and functions. The computer processor may be an integrated circuit for processing instructions. For example, the computer processor may be one or more cores or microcores of a processor. Computing device 10 may also include one or more input devices, such as a camera, a touchscreen, a keyboard, a mouse, a microphone, a touchpad, an electronic pen, or any other type of input device. Furthermore, computing device 10 may include one or more output devices, such as a projector, a display screen (e.g., an OLED display or other pixel-addressable display device), external storage devices, or any other output device. One or more output devices may be the same as or different from the input devices. Computing device 10 may be connected to a network (e.g., a local area network (LAN), a wide area network (WAN) such as the Internet, a mobile network, or any other type of network) via a network interface connection (not shown). Input and output devices may be connected locally or remotely (e.g., via a network) to the computer processor, memory, and storage devices. There are many different types of computing devices 10, and the aforementioned sub-components of computing devices 10 may take other forms.

[0026] Software instructions in the form of computer-readable program code for carrying out embodiments of the present invention may be stored wholly or partially, temporarily or permanently, on a non-transitory computer-readable medium, such as a CD, DVD, storage device, floppy disk, magnetic tape, flash memory, physical memory, or any other computer-readable storage medium. Specifically, the software instructions may correspond to computer-readable program code that, when executed by a processor, is configured to carry out embodiments of the present invention.

[0027] Figure 1C The invention illustrates one or more embodiments thereof. Figure 1A A schematic diagram of the SSD sub-component of the computing device 10.

[0028] In one or more embodiments, the storage device 26 is an SSD, which includes a processor 261 (e.g., a controller) and one or more units of flash memory 262 (i.e., flash memory devices). Each flash memory 262 includes a plurality of flash memory cells 200 (e.g., NAND devices, NOR devices), which are described below. Figure 2A A further detailed description is provided. For example, the flash memory device 262 may be organized as pages and / or blocks of flash memory cells 200.

[0029] Processor 261 controls reading from and writing to flash memory 262. In one or more embodiments, another processor of computing device 10 (e.g., CPU processor 12, GPU processor 16, integrated circuit, remote processing device) may control reading from and writing to flash memory 262. The SSD may also include firmware used by processor 261 for reading from and writing to flash memory 262.

[0030] Figure 2A A schematic diagram of the flash memory cell 200 of the SSD is shown.

[0031] The SSD includes multiple flash memory cells 200 to retain information. Each flash memory cell 200 includes a substrate 202 having a source 204 and a drain 206. A control gate 208 is used to control charge carriers in a storage layer 212 (e.g., a charge trap, a floating gate). A gate oxide film 210 and a tunnel oxide film 211 isolate the storage layer 212 from the control gate 208 and the substrate 202, respectively.

[0032] The data retention capability of flash memory cell 200 may degrade as the flash memory cell 200 ages. One mechanism of degradation is the over-time charge loss of the storage layer 212 through the tunnel oxide film 211. Charge loss can be affected by various parameters, such as the number of program / erase cycles of the flash memory cell 200, the SSD temperature, and / or operating time (e.g., time elapsed since power-on). Over time, as more electrons leak through the tunnel oxide film 211, the amount of charge remaining in the floating gate or charge trap decreases. Therefore, the voltage threshold required for correctly reading the flash memory cell 200 needs to be shifted from its original value, such as... Figure 2B As shown.

[0033] Figure 2B A graph showing ideal readout and degraded readout from flash memory cell 200 is presented.

[0034] exist Figure 2B In the top diagram, the ideal readout includes multiple programming states P (e.g., bit sequences) that are fully distinguished by multiple voltage thresholds Vth (i.e., voltage index sets). In other words, the voltage read from flash memory 262 can be compared with the voltage index set to determine the programming state or stored value of flash memory 262.

[0035] exist Figure 2BIn the bottom diagram, charge loss in flash memory 262 leads to degraded reads and bit read errors. Due to charge loss in storage layer 212, reads from flash memory 262 are shifted / clustered to the left, causing the distribution of a given programming state to cross the original voltage threshold. Any lower portion of the distribution of each programming state that crosses the original voltage threshold level is misread as an adjacent programming state. The SSD firmware can perform read retry processing to attempt to reread the expected programming state of flash memory 262 by compensating for the change in voltage read.

[0036] Figure 2C A pre-existing read retry table 250 for reading flash memory 262 is shown.

[0037] Standard read retry processing uses read retry table 250, which includes a predefined sequential list of voltage index sets for reading flash memory 262. To accommodate variations in voltage reads, a new threshold set is established for each voltage index set to distinguish expected programming states. Figure 2C As shown, a conventional read retry table 250 may include dozens of separate voltage index sets (i.e., each row of the read retry table). The SSD's firmware sequentially uses each voltage index set of the read retry table 250 to reread the flash memory 262 until the bit read error is resolved. However, this conventional method may take too long to complete before the original bit read error causes a problem with the computing device 10 (e.g., application / operating system hang, "blue screen of death").

[0038] As described in further detail below, embodiments of the present invention utilize one or more adaptive read retry voltage index sets (i.e., their patterns) to improve conventional read retry processing, which enhance the speed and efficiency of the read retry processing. In one or more embodiments, aging parameters of the SSD are determined to characterize the amount of degradation in the flash memory. Based on the aging parameters, an appropriate voltage index set can be selected from the conventional read retry table 250 to read the flash memory 262 without lengthy iterative processing.

[0039] Figure 3A A flowchart of a method 300 according to one or more embodiments of the present invention is shown.

[0040] At 310, the processor (e.g., processor 261 of the SSD, processor 12 of the computing device 10, or any processor connected to the SSD) obtains a pre-existing read retry table 250, which includes a sequential list of voltage index sets for reading the flash memory 262. The pre-existing read retry table 250 may be stored in the memory of the SSD's firmware.

[0041] At position 320, the processor determines the SSD's aging parameters. See below for details. Figure 3B In further detail, various different methods can be used to determine aging parameters.

[0042] At 330, the processor identifies the set of retry voltage indices from a sequential list in a pre-existing read retry table 250 based on aging parameters.

[0043] Optionally, at 340, the processor generates one or more retry patterns. Each retry pattern includes multiple sets of voltage indices identified from a sequence list based on one or more aging parameters. The retry pattern defines a set of retry voltage indices from the sequence list, which can be used sequentially in reread operations without having to determine a new set of retry voltage indices after each failure.

[0044] In some implementations, each entry in the retry mode (i.e., the voltage index set) corresponds to a different element of the aging parameter (e.g., one entry corresponds to a P / E cycle-based aging parameter, and another entry corresponds to a temperature-based aging parameter) or a different aging parameter. In some implementations, the retry modes may be listed in order of importance based on the corresponding aging parameters. The retry mode may include the retry voltage index set of the first sequential entry identified as the first retry mode at 330.

[0045] In one or more embodiments, the processor can generate a predetermined number of retry patterns. A set of retry patterns can be used sequentially in a reread operation without having to determine a new retry pattern after each failure. In some embodiments, the predetermined number of retry patterns can be listed sequentially based on the importance of the aging parameters used to generate the corresponding retry patterns.

[0046] At 350, the processor uses the retry voltage index set on the SSD to read the flash memory. In an implementation with retry modes, the processor may use entries of the retry modes sequentially (e.g., starting with the retry voltage index set identified at 330). In an implementation with multiple retry modes, the processor may use a list of retry modes sequentially (e.g., starting with the first retry mode generated at 340).

[0047] Figure 3B A flowchart of a method 320 according to one or more embodiments of the present invention is shown. As discussed above, method 320 involves determining aging parameters of an SSD.

[0048] At 322, the processor identifies the type of aging parameter to be determined. As discussed above, the aging of the SSD (or one or more flash memory devices 262 or one or more flash memory cells 200) can be characterized by several parameters. For example, the number of program / erase (P / E) cycles of the flash memory device 262 or flash memory cell 200 may be related to the amount of degradation. Similarly, ambient temperature and / or elapsed operating time may be related to the amount of degradation.

[0049] Under different operating conditions of the computing device 10, a single aging parameter can provide a more accurate characterization of the amount of degradation. For example, under consistent use, the elapsed operating time can provide an accurate estimate of degradation. However, when use varies greatly in time or intensity, direct measurement of the P / E cycle can provide a more accurate estimate of degradation.

[0050] When the processor identifies the P / E cycle as the aging parameter to be determined at 322, the processing continues to 323.

[0051] When the processor identifies the elapsed time as the aging parameter to be determined at 322, the processing continues to 324.

[0052] Once the processor identifies the temperature at 322 as the aging parameter to be determined, processing continues to 325.

[0053] At 323, the processor determines the number of P / E cycles for flash memory 262. The number of P / E cycles can be determined based on a specific portion of flash memory 262 being read (e.g., flash memory device 262, pages, blocks, or cells 200 of flash memory 262). Alternatively, the number of P / E cycles can be a statistical approximation of one or more portions or all portions of the SSD (e.g., average, mean, median, or mode).

[0054] At 324, the processor determines the time elapsed since the SSD was enabled. The elapsed time can be a measurement of the operation time of a specific portion of the SSD being read (e.g., flash memory device 262, pages or blocks of flash memory device 262, flash memory cell 200) or the entire SSD.

[0055] In one or more embodiments, the processor obtains a Non-Volatile Memory Fast (NVMe) timestamp from the Basic Input / Output System (BIOS) of the computing device 10. Based on the NVMe timestamp (e.g., the identifier 0Eh), the processor can calculate the elapsed operation time (e.g., the elapsed operation time of the following: SSD, flash memory device 262, pages or blocks of flash memory device 262, flash memory cell 200) by counting the elapsed time since the host was enabled.

[0056] At 325, the processor determines the temperature of the SSD from a sensor. The sensor may be a thermometer (e.g., a thermocouple) incorporated into or located on or near the SSD. In some embodiments, the sensor may be positioned within the computing device 10 at a distance from the SSD to estimate the SSD's temperature.

[0057] At 326, the processor determines and outputs aging parameters based on one or more types of input information determined at 323 to 325. Aging parameters can take many forms.

[0058] In some implementations, the aging parameters are index values ​​(e.g., row number / tag) of a pre-existing read retry table determined based on information obtained at positions 323 to 325. The information obtained at positions 323 to 325 can be converted into aging parameters using one or more algorithms, equations, associations, transformations, logic trees, etc. For example, multiplying the elapsed time determined at position 324 by the probability of increased degradation per unit of time can generate an estimate of the degradation amount. The degradation amount can be associated with one or more rows of a pre-existing read retry table 250, with one or more indices of said rows output as aging parameters.

[0059] In some implementations, the aging parameters are based on multiple types of input information obtained at points 323 to 325 (e.g., method 320 may include multiple iterations of points 323 to 325 executed in series or in parallel). For example, the temperature determined at 325 may be combined with the number of P / E cycles determined at 323 to determine the aging parameters. When the degradation due to P / E cycles depends on temperature, including both types of input information from 323 and 325 can more accurately estimate the amount of degradation and provide more suitable aging parameters.

[0060] In some implementations, the aging parameters include multiple entries (e.g., multiple index values ​​of a pre-existing read retry table, each index value based on one or more measurements). As discussed above, the processor can utilize one or more types of information determined at 323 to 325 to determine a set of estimates of the degradation amount. Therefore, the aging parameters can include multiple entries based on each type of information and / or different combinations of each type of information (e.g., individual indexes of a pre-existing read retry table 250). See below regarding... Figure 4 As discussed in further detail, in some implementations, multiple entries can be used to generate a retry mode that includes multiple sets of voltage indexes (e.g., multiple entries corresponding to aging parameters).

[0061] In some implementations, the aging parameters include direct measurements of information obtained at points 323 to 325 (e.g., the number of P / E cycles, elapsed time, temperature), rather than corresponding index values ​​from a pre-existing read retry table 250. This direct measurement can be converted to a corresponding index value from the pre-existing read retry table 250 at a later time (e.g., at point 350 during the SSD read process).

[0062] Figures 3A to 3B One or more individual processes shown in the flowchart may be omitted, repeated, combined, and / or executed in an order different from that shown in this disclosure (e.g., parallelization). For example, the “end” of a method may be directly connected to the “begin” to execute the method cyclically. Alternatively or additionally, one or more processes may be combined in one or more embodiments.

[0063] Each process can be implemented by hardware (e.g., circuitry, physical components), software (e.g., programming on a non-transitory computer-readable medium, machine code), or any combination thereof. Processes can be performed actively or passively. For example, according to one or more embodiments of the invention, some steps can be performed using polling-based intervals and / or can be event / interrupt driven. Additional processing can be performed. Therefore, the scope of the invention should not be limited to... Figures 3A to 3B The specific layout restrictions described in the text.

[0064] Figure 4 Examples of retry patterns generated according to one or more implementations are shown.

[0065] In the following non-limiting example, the pre-existing read retry table 250 includes a predefined sequential list of voltage index sets for reading flash memory 262. A regular read retry method would iterate through the voltage index sets in the sequential list (i.e., try RR-1, then RR-2, RR-3, etc.).

[0066] In one or more embodiments, according to 323 to 325 above, the computing device 10 performs a series of determinations on the number of P / E cycles, temperature, and elapsed time. Each of these determinations is associated with a corresponding index in a pre-existing read retry table 250. In this non-limiting example, the number of P / E cycles indicates the level of degradation that can be compensated for using a voltage index set labeled RR-5, the temperature indicates the level of degradation that can be compensated for using a voltage index set labeled RR-6, and the elapsed time indicates the level of degradation that can be compensated for using a voltage index set labeled RR-8. In other words, the aging parameters can be a list (RR-5, RR-6, RR-8). Alternatively, the aging parameters can be a list of corresponding measurements.

[0067] In some embodiments, the computing device 10 may generate a retry pattern 400 based on aging parameters. In this non-limiting example, the retry pattern includes a first retry voltage index set, a second retry voltage index set, and a third retry voltage index set corresponding to RR-5, RR-6, and RR-8 in a pre-existing read retry table 250, respectively. Therefore, the read retry method according to one or more embodiments of the present invention will traverse the voltage index sets in the retry pattern 400 (i.e., try RR-5, then RR-6, then RR-8).

[0068] Retry mode 400 can be an ordered list based on the priority of metrics used to determine one or more aging parameters. For example, the first sequential entry of the retry mode can be selected based on the number of program / erase (P / E) cycles of the flash memory 262, as P / E cycles are likely the most important consideration for estimating degradation. The second sequential entry of the retry mode can be selected based on the SSD's temperature or the SSD's elapsed operating time (depending on which metric is more important for estimating degradation). Information regarding the relative level of importance can be determined when determining the aging parameters, can be predefined, or can be determined at any appropriate time (e.g., at startup, reboot, application start-up, process start-up, or hardware and / or software configuration change).

[0069] Figure 5 Non-limiting examples of read retry processing workflows according to one or more implementations are shown.

[0070] Initially, the host initialization boot process of the computing device initiates and enables timestamps (e.g., NVMe timestamps) in the computing device's BIOS. If the enabling process fails, the BIOS will retry enabling timestamps until it succeeds.

[0071] In one or more implementations, one or more aging parameters of the SSD are determined when the SSD is powered on (e.g., during the startup of the computing device, or when an external SSD is installed). Alternatively, one or more aging parameters may be determined in response to the execution of a predetermined process of the computing device (e.g., startup, restart, application start-up, process start-up, hardware and / or software configuration change).

[0072] Based on one or more aging parameters, one or more retry patterns are generated. In some implementations, this may include identifying a single set of retry voltage indexes from a pre-existing read retry table (e.g., retry patterns comprising a single entry). In some implementations, as described above regarding... Figure 4The retry modes include one or more entries based on different aging parameters of the SSD (e.g., different measurements or elements in the aging parameters). One or more retry modes may be stored in the SSD's memory (e.g., in firmware) or in the memory of the computing device 10.

[0073] When the host requests data from the SSD, it determines whether read retry processing is needed (e.g., a bit read error is detected). If read retry processing is not needed, the SSD is read and the data is sent to the host. When read retry processing is needed, a retry voltage index set is selected from one or more retry modes to attempt to reread the data. If the first reread attempt fails (i.e., data without bit read errors cannot be generated using the first retry voltage index set), the next retry voltage index set is selected and used to attempt to reread the data until the SSD is successfully read.

[0074] While this specification includes a limited number of examples of aging parameters, it should be understood that any suitable metric can be used as an aging parameter or for determining aging parameters. Therefore, embodiments of the invention should not be limited to the non-limiting examples above.

[0075] One or more embodiments of the present invention may have one or more of the following improvements to the computing device: fast flash data read speed; reduced use of computing resources (processing attempts) during read retry processing; and improved consumer functionality by preventing unexpected errors during read retry processing (e.g., application / operating system timeouts, "blue screen of death").

[0076] While this disclosure has been described with reference to a limited number of embodiments, those skilled in the art who benefit from this disclosure will understand that various other embodiments can be devised without departing from the scope of the invention. Therefore, the scope of the invention should be defined only by the appended claims.

Claims

1. A method of operating a computing device having a solid-state drive (SSD), the method comprising: Obtain a pre-existing read retry table, which includes an ordered list of voltage index sets for reading the flash memory of the SSD; Determine the aging parameters of the SSD; Based on the aging parameters, identify the retry voltage index set from the sequence list; as well as The flash memory is read using the retry voltage index set.

2. The method according to claim 1, further comprising: Determine the number of program / erase P / E cycles for the flash memory. The aging parameter is based on the number of programming / erasing P / E cycles of the flash memory.

3. The method according to claim 2, in, The number of P / E cycles is determined based on the pages or blocks of the flash memory or the flash memory cells of the flash memory.

4. The method according to claim 1, further comprising: Determine the time elapsed since the SSD was enabled. The aging parameter is based on the elapsed time at the SSD, the flash memory, a page or block of the flash memory, or a flash cell of the flash memory.

5. The method according to claim 4, further comprising: Obtain a fast timestamp from the non-volatile memory of the computing device’s basic input / output system; as well as Calculate the elapsed time.

6. The method according to claim 1, further comprising: The temperature of the SSD is determined from the sensor. The aging parameters are based on the temperature.

7. The method according to claim 1, further comprising: A first retry pattern is generated, which includes multiple sets of voltage indexes from the sequence list. Wherein, the first sequential entry of the first retry mode is the retry voltage index set. The flash memory is read using sequential entries of the first retry mode, starting from the retry voltage index set.

8. The method according to claim 7, in, Each entry in the first retry mode is based on a different aging parameter of the SSD.

9. The method according to claim 8, in, The first sequence entry of the first retry mode is selected based on the number of programming / erasing P / E cycles of the flash memory.

10. The method according to claim 9, in, The second sequence entry of the first retry mode is selected based on the temperature of the SSD.

11. The method according to claim 9, in, The second sequence entry for the first retry mode is selected based on the time elapsed since the SSD was enabled.

12. The method of claim 7, further comprising: Generate a predetermined number of retry patterns, wherein the predetermined number of retry patterns includes the first retry pattern. Each retry mode includes multiple sets of voltage indexes from the sequence list. The predetermined number of retry modes, starting from the first retry mode, are used sequentially when reading the flash memory.

13. The method according to claim 7, in, The first retry mode is generated in response to the execution of a predetermined process by the computing device.

14. The method according to claim 13, in, The predetermined process is the startup of the computing device.

15. A non-transitory computer-readable medium (CRM) storing computer-readable program code for operating a computing device having a solid-state drive (SSD), the computer-readable program code causing the computing device to: Obtain a pre-existing read retry table, which includes an ordered list of voltage index sets for reading the flash memory of the SSD; Determine the aging parameters of the SSD; Identify a retry voltage index set from the sequence list based on the aging parameters; and use the retry voltage index set to read the flash memory.

16. A computing device, comprising: Solid-state drives (SSDs) include flash memory; as well as A processor configured to read the flash memory, The processor is configured as follows: Obtain a pre-existing read retry table, which includes an ordered list of voltage index sets for reading the flash memory; Determine the aging parameters of the SSD; Based on the aging parameters, a set of retry voltage indices is identified from the sequence list; and The flash memory is read using the retry voltage index set.

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