SSD (Solid State Disk) testing method

Abstract

The invention discloses an SSD (Solid State Disk) testing method, which relates to the technical field of hard disk testing and comprises the following steps of executing preparation before testing and environment initialization; carrying out multi-dimensional performance index collection; data integrity verification and abnormal clustering analysis are implemented; and carrying out dynamic threshold determination and reliability scoring based on load characteristics. According to the method, test conditions of different batches of SSDs are ensured to be consistent through uniform test baseline configuration and environment initialization, bandwidth, delay and scheduling behaviors of the SSDs under sequential, random and high-concurrency scenes can be truly reflected through a multi-dimensional performance index acquisition method, and the performance of the SSDs is improved through CRC-64 verification and abnormal clustering analysis. According to the method, medium degradation, controller abnormity and cross-block errors can be subjected to structured recognition, reliability evaluation can be adaptively adjusted along with real-time loads through a dynamic threshold judgment mechanism based on load characteristics, and the performance degradation trend in a high-pressure scene is accurately captured.

Description

Technical Field

[0001] This invention relates to the field of hard disk testing technology, and in particular to a testing method for SSD solid-state drives. Background Technology

[0002] With the widespread application of solid-state drives (SSDs) in data centers, personal computing platforms, and industrial systems, their performance stability and data reliability have become key indicators for measuring the quality of storage devices. Existing SSD testing methods mostly focus on collecting basic performance parameters such as bandwidth and latency. However, in real-world business scenarios, SSD performance is not only affected by sequential / random access modes, but also by multiple factors such as thread contention, controller scheduling strategies, and the aging state of flash memory media.

[0003] On the other hand, traditional data integrity testing typically relies on simple read / write verification, making it difficult to identify early, subtle degradation phenomena in NAND media, such as bit flips, localized damage, and complex hidden dangers like cross-block error clustering. Furthermore, existing testing systems often lack the ability to perform structured analysis of erroneous behavior, making it difficult to distinguish between different types of fault sources, such as controller malfunctions, channel interference, and media aging.

[0004] Furthermore, under high concurrency and high load conditions, SSD performance may experience transient degradation, increased latency spikes, or scheduling strategy failures. However, traditional testing often uses fixed thresholds to judge performance anomalies, failing to adaptively adjust the judgment criteria based on real-time operating load, making it difficult to accurately and promptly identify performance degradation under high load.

[0005] Therefore, there is an urgent need for a comprehensive testing method that can simultaneously cover test environment initialization, multi-dimensional performance collection, data integrity analysis, error clustering and judgment, and dynamic reliability assessment based on load characteristics, in order to improve test accuracy, sensitivity and adaptability to actual business scenarios. Summary of the Invention

[0006] The purpose of this invention is to provide a testing method for SSD solid-state drives to solve the problems mentioned in the background art.

[0007] To achieve the above objectives, the present invention provides the following technical solution: an SSD solid-state drive testing method, comprising the following steps: Step 1: Perform pre-test preparation and environment initialization; Step 2: Collect multi-dimensional performance indicators; Step 3: Perform data integrity verification and anomaly clustering analysis; Step 4: Conduct dynamic threshold determination and reliability scoring based on load characteristics.

[0008] Preferably, step 1 includes: Establish a baseline configuration for the test environment, which includes power supply noise limit, interface protocol version, temperature range and queue depth parameters to ensure consistency of test conditions. Perform low-level formatting and block table erasure on the SSD under test to restore all physical blocks to their original clean page state; Load the test task description file, which includes an IO mode set, data distribution strategy, read / write ratio and number of concurrent threads, to form a multi-dimensional test load matrix.

[0009] Preferably, the test load matrix includes: Combinations of IO modes include sequential read, sequential write, random read, and random write; The data pattern set includes fixed pattern, pseudo-random pattern, all-zero pattern and entropy controllable pattern; The combined dimension of the number of concurrent threads and the queue depth is used to construct high-concurrency pressure scenarios.

[0010] Preferably, step 2 includes: Sequential access tests were performed with a fixed block size to collect average bandwidth, maximum bandwidth, and bandwidth jitter coefficient. Generate a random addressing load and sample delay sequences at different queue depths; The kurtosis K of the delayed sample sequence Ln is calculated using the following formula: ; Where N is the number of samples, and Li is the latency of the i-th access. σ represents the average delay, σ represents the standard deviation of the delay, and the peak value K is used to characterize delay spikes and scheduling anomalies.

[0011] Preferably, the process of generating random addressing load includes: The I / O arrival sequence is randomly generated using a Poisson process to simulate common bursts of server access. I / O randomization is performed based on thread contention, resulting in a non-uniform distribution of access patterns; Set a threshold for switching across logical blocks to dynamically switch the workload between continuous writing of large files and frequent writing of small files.

[0012] Preferably, step 3 includes: Perform CRC-64 verification on the written data and compare it with the original check value to identify bit flips and storage medium instability. Analyze the clustering of failed verification addresses and statistically analyze address locality through continuous error windows; Anomaly clustering vectors are constructed and an error cluster is formed using a density clustering algorithm to distinguish between controller anomalies and NAND media aging phenomena.

[0013] Preferably, the anomaly clustering vector includes: Construct a cluster element Ei = {address offset, error cycle, block erase / write count, channel number}; Normalization is used to make the characteristics of different batches of SSDs comparable; Cluster labels are compared with historical records to identify cross-batch consistency defects.

[0014] Preferably, the error cluster analysis includes: Statistical analysis is performed on the clustered error cluster centers to generate a cluster center feature set Cj = {error density, address span, recurrence period, and distribution of the associated channel}; Cluster separation index is calculated based on cluster center feature set to evaluate the independence between different error modes; By comparing cluster separation with historical stable samples, we can identify whether anomalous clusters belong to potential early degradation patterns.

[0015] Preferably, step 4 includes: A basic reliability score is constructed based on bandwidth fluctuation, latency kurtosis, and error rate. The reliability score is weighted according to the load type and the controller scheduling depth; The formula for dynamic threshold determination is as follows: ; Among them, T d T0 is the dynamic threshold, α is the initial threshold, α is the weighting coefficient, and ΔR is the real-time reliability offset, used to characterize the degradation trend of SSD under stress load.

[0016] Preferably, the weighting process includes: Identify I / O access characteristics, including sequentiality, read-write ratio, and queue depth; Calculate the parallel write correction factor based on the controller's parallelism and the number of channels; The media degradation weight is set according to the NAND type to reflect the impact of long-term aging factors.

[0017] The technical effects and advantages of this invention are as follows: This invention ensures consistent testing conditions for different batches of SSDs through unified test baseline configuration and environment initialization. Its multi-dimensional performance indicator acquisition method accurately reflects the bandwidth, latency, and scheduling behavior of SSDs under sequential, random, and high-concurrency scenarios. CRC-64 verification and anomaly clustering analysis enable structured identification of media degradation, controller anomalies, and cross-block errors. A dynamic threshold determination mechanism based on load characteristics allows reliability evaluation to adaptively adjust with real-time load, accurately capturing performance degradation trends under high-pressure scenarios. The overall method offers comprehensive test coverage, quantifiable results, and high sensitivity, effectively improving the scientific rigor, accuracy, and practical application guidance value of SSD testing. Attached Figure Description

[0018] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the method flow of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] This invention provides, for example Figure 1 The SSD solid-state drive testing method shown includes the following steps: Step 1: Perform pre-test preparation and environment initialization; Step 1 includes: Establish a baseline configuration for the test environment, including power supply noise limit, interface protocol version, temperature range and queue depth parameters, to ensure consistency of test conditions. Perform low-level formatting and block table erasure on the SSD under test to restore all physical blocks to their original clean page state; Load the test task description file, which includes the IO mode set, data distribution strategy, read / write ratio and number of concurrent threads, forming a multi-dimensional test load matrix.

[0021] The test load matrix includes: Combinations of IO modes include sequential read, sequential write, random read, and random write; The data pattern set includes fixed pattern, pseudo-random pattern, all-zero pattern and entropy controllable pattern; A combined dimension consisting of the number of concurrent threads and the queue depth is used to construct high-concurrency pressure scenarios; In a preferred embodiment of the present invention, step 1 ensures that the subsequent performance acquisition and reliability analysis processes have a stable and reproducible operating foundation by initializing the test environment and the SSD under test. First, a baseline configuration for the test environment is established to ensure that different batches of SSDs are compared under uniform conditions. The baseline configuration includes the upper limit of power supply noise (to limit the interference of external power fluctuations on the controller behavior), interface protocol version (to avoid compatibility deviations caused by protocol differences), temperature range (a key factor affecting the controller's thermal performance), and queue depth parameter (bound to the multi-threaded test model). Through this configuration, a unified test running environment can be built at the system level, thereby avoiding performance data distortion caused by changes in the external environment. Subsequently, a low-level format and block table erase operation is performed on the SSD under test to bring the flash memory media into a clean page state. This step can clear the existing write amplification history, garbage collection traces and user data, so that the test process can reflect the real physical read and write capabilities of the SSD as much as possible, without being affected by old data residue. At the same time, the L2P mapping structure inside the controller is also restored to the initial state during this process to ensure that the addressing path of subsequent random access tests remains consistent. Next, the test task description file is loaded. The description file contains parameters such as IO mode set, data distribution strategy, read / write ratio and number of concurrent threads, which are used to define the load combination that needs to be covered during the test. By reading this file, the test system can automatically generate a multi-dimensional load sequence to realize integrated verification of the behavior of SSD under different access modes. In this embodiment, the test load matrix serves as the core structure of the task description file, comprehensively covering the performance of the SSD in typical operating scenarios; the test load matrix includes three dimensions: Combinations of IO modes are used to simulate different use cases, ranging from sequential reading and writing of large files to random access of small blocks. A set of data patterns is used to verify the controller compression behavior, deduplication characteristics, and error sensitivity of SSDs under different entropy levels and data patterns. The combined dimension of concurrent thread count and queue depth is used to construct a complete test path from low concurrency to high pressure scenarios, thereby evaluating the upper limit capabilities of the SSD controller scheduling algorithm and channel parallelism. By organically combining the baseline configuration, media initialization, and load matrix construction described above, this embodiment provides a standardized, repeatable, and quantifiable testing foundation for subsequent steps such as performance acquisition, latency analysis, and error clustering. A unified baseline configuration ensures the comparability of test results for different SSDs, effectively avoiding performance deviations caused by environmental fluctuations. Low-level formatting and block table erasure eliminate historical write traces, allowing performance tests to reflect the true physical capabilities of the SSD and improving the accuracy of latency and bandwidth measurements. By combining multiple dimensions of the test load matrix to cover various real-world usage scenarios such as sequential, random, large files, small files, and high concurrency, it helps to comprehensively evaluate the SSD's scheduling strategy, channel parallelism, and stability under different data modes. This provides a clean, reproducible, and statistically significant test foundation for subsequent steps, thereby enhancing the credibility of cluster analysis, performance judgment, and reliability assessment.

[0022] Step 2: Collect multi-dimensional performance indicators; Step 2 includes: Sequential access tests were performed with a fixed block size to collect average bandwidth, maximum bandwidth, and bandwidth jitter coefficient. Generate a random addressing load and sample delay sequences at different queue depths; The kurtosis K of the delayed sample sequence Ln is calculated using the following formula: ; Where N is the number of samples, and Li is the latency of the i-th access. σ represents the average delay, σ represents the standard deviation of the delay, and the peak value K is used to characterize delay spikes and scheduling anomalies.

[0023] The process of generating random addressing load includes: The I / O arrival sequence is randomly generated using a Poisson process to simulate common bursts of server access. I / O randomization is performed based on thread contention, resulting in a non-uniform distribution of access patterns; Set a cross-logic block jump threshold to dynamically switch the load between continuous writing of large files and frequent writing of small files. In a preferred embodiment of the present invention, step 2 collects SSD performance indicators from multiple dimensions to comprehensively reflect its bandwidth stability, latency behavior and scheduling strategy characteristics under different access modes and different load conditions. First, sequential access tests are performed on the SSD with a fixed block size (e.g., 4KB or 128KB) to allow the controller to operate under minimal addressing interference. During the test, average bandwidth, maximum bandwidth, and bandwidth jitter coefficient are collected to evaluate the channel parallelism and caching strategy efficiency of the SSD in continuous read and write scenarios. Sequential access is an important means of verifying the controller's prefetch algorithm, write merging strategy, and cache hit rate, and therefore can be used as a data source for benchmark performance. Subsequently, a random addressing load is generated to simulate random access scenarios commonly found in servers, databases, and high-concurrency applications. In this embodiment, the latency sequence Ln is sampled in stages by changing the queue depth (QD=1 / 4 / 8 / 16 / 32, etc.) to obtain latency behavior under different pressure levels. Since the controller needs to frequently schedule flash channels and perform address mapping and garbage collection related operations during random access, this process can truly reflect the complexity of the SSD scheduling system. During the delay sampling process, this embodiment calculates the kurtosis K of the collected delay sequence Ln to characterize the frequency of peak events in the delay distribution. When the kurtosis K is high, it indicates strong delay burstiness and large scheduling fluctuations, reflecting the performance jitter problem that the SSD controller may have under stress scenarios. In the random addressing load generation process, this embodiment uses the Poisson process to generate the IO arrival sequence to simulate the burst load characteristics common in data centers, thereby injecting randomness in the time dimension. Then, IO randomization is performed according to the competition relationship between threads, so that the access distribution presents a non-uniform pattern, further increasing the challenge of the load to the controller scheduling algorithm. In addition, by setting a cross-logic block jump threshold, the load can switch between large-span sequential writes and dense small-block random writes, thereby simulating the alternation of different file operation types in real business. Through the above structured load generation method, this embodiment can apply comprehensive pressure to the SSD controller in the spatial, temporal, and access mode dimensions, so that the collected latency, bandwidth, and jitter data more realistically reflect the device's intrinsic performance characteristics. Sequential access testing accurately reflects the SSD's basic channel bandwidth, caching strategy, and write merging efficiency, ensuring the stability of benchmark performance indicators. Random access testing samples latency sequences at different queue depths, exposing bottlenecks and contention behaviors in the controller's scheduling strategy. This helps identify performance degradation characteristics under high load. The kurtosis K statistic can intuitively quantify the frequency of latency spikes, improving the ability to identify latency anomalies, scheduling fluctuations, and internal GC (garbage collection) behavior. Through Poisson processes, thread contention randomization, and cross-logic block jump design, the generated random addressing load is closer to real business scenarios, making the test results more valuable for actual deployment. The overall testing process can build a multi-dimensional, repeatable, and quantifiable performance evaluation system, providing high-quality input data for subsequent error clustering analysis and reliability scoring.

[0024] Step 3: Perform data integrity verification and anomaly clustering analysis; Step 3 includes: Perform CRC-64 verification on the written data and compare it with the original check value to identify bit flips and storage medium instability. Analyze the clustering of failed verification addresses and statistically analyze address locality through continuous error windows; Anomaly clustering vectors are constructed and an error cluster is formed using a density clustering algorithm to distinguish between controller anomalies and NAND media aging phenomena.

[0025] The abnormal clustering vectors include: Construct a cluster element Ei = {address offset, error cycle, block erase / write count, channel number}; Normalization is used to make the characteristics of different batches of SSDs comparable; Cluster labels are compared with historical records to identify cross-batch consistency defects.

[0026] Error cluster analysis includes: Statistical analysis is performed on the clustered error cluster centers to generate a cluster center feature set Cj = {error density, address span, recurrence period, and distribution of the associated channel}; Cluster separation index is calculated based on cluster center feature set to evaluate the independence between different error modes; Based on the comparison of cluster separation degree with historical stable samples, identify whether abnormal clusters belong to potential early degradation patterns; In a preferred embodiment of the present invention, step 3 verifies the data integrity of the SSD and performs cluster analysis on the erroneous behavior to identify controller anomalies, media degradation, and cross-batch consistency defects. First, CRC-64 verification is performed on the data written to the SSD. By comparing the currently calculated check value with the original check value block by block, data anomalies caused by bit flips, random noise interference, and NAND cell drift are identified. CRC-64 verification has the characteristics of high verification strength and low false positive rate, and is suitable for fine integrity testing of high-density NAND media. Through this step, minor errors that occur in the media during operation can be accurately identified, which are often difficult to capture in traditional read and write performance tests. Subsequently, cluster analysis is performed on the failed verification addresses. In this embodiment, a continuous error window mechanism is used to statistically analyze the local distribution of error addresses. If errors occur frequently within a specific address range, it may indicate that the flash memory block has physical anomalies such as local damage, gate leakage, or unstable writing. The continuous error window mechanism can effectively identify whether there are concentrated bad blocks or channel-level interference, providing a basis for distinguishing between random noise and structural errors. Based on this, this embodiment constructs an anomaly clustering vector Ei and uses it for error pattern clustering. The vector Ei consists of address offset, error cycle, number of block erase / write cycles, and the channel number where the error occurs. It can describe error characteristics from four perspectives: logical space, time dimension, media wear degree, and hardware distribution. The vector Ei is normalized to make data from different SSD batches and different capacity models comparable in the same feature space. Then, a density clustering algorithm (such as DBSCAN) is used to automatically form error clusters to distinguish different types of error sources such as controller scheduling anomalies, channel interference, and single block degradation. To improve the interpretability of clustering results, this embodiment further performs center analysis on the clustered error clusters. By statistically analyzing the cluster centers of each error cluster, a feature set Cj is generated, which includes key indicators such as error density, address span, recurrence period and distribution of the channel to which it belongs. This feature set can reflect the distribution characteristics of error clusters in terms of spatial concentration, cross-block range, temporal recurrence pattern and hardware channel level. After obtaining the cluster center characteristics, this embodiment calculates the cluster separation index to measure the independence between different error modes, determine whether the error clusters have significant differences or overlap, and finally compare the cluster separation with historical normal samples to identify early degradation patterns, abnormal cluster evolution trends and batch-level consistency defects. This analysis can help determine whether the error source has a latent or spreading trend, thus providing a key basis for reliability assessment. Leveraging the high-strength CRC-64 verification mechanism, it can accurately detect minute bit flips and potentially unstable cells in NAND media, improving the accuracy of data integrity analysis. Through a continuous error window mechanism, it can effectively identify local clustering of errors, thereby distinguishing between random noise and structural media degradation, providing spatial localization capabilities for error source analysis. It constructs a clustering vector Ei containing four-dimensional features of space, time, wear, and channel, and performs density clustering on it, which can automatically classify different types of error modes such as controller anomalies, block-level degradation, and channel interference. Through the statistics of the cluster center feature set Cj, each type of error cluster has a clear "feature fingerprint", significantly improving the interpretability of error modes. By calculating the cluster separation index and comparing it with historical records, it can identify potential early degradation patterns and expose potential reliability hazards that SSDs may encounter during long-term use. The overall analysis process provides high-quality structured input data for subsequent steps of dynamic threshold determination and reliability scoring, making the overall testing system intelligent, automated, and traceable.

[0027] Step 4: Conduct dynamic threshold determination and reliability scoring based on load characteristics.

[0028] Step 4 includes: A basic reliability score is constructed based on bandwidth fluctuation, latency kurtosis, and error rate. The reliability score is weighted according to the load type and the controller scheduling depth; The formula for dynamic threshold determination is as follows: ; Among them, T d T0 is the dynamic threshold, α is the initial threshold, α is the weighting coefficient, and ΔR is the real-time reliability offset, used to characterize the degradation trend of SSD under stress load.

[0029] The weighting process includes: Identify I / O access characteristics, including sequentiality, read-write ratio, and queue depth; Calculate the parallel write correction factor based on the controller's parallelism and the number of channels; Set media degradation weights according to NAND type to reflect the effects of long-term aging factors; In a preferred embodiment of the present invention, step 4 constructs an SSD reliability scoring model based on multi-dimensional performance indicators and load characteristics, and combines a dynamic threshold mechanism to identify the performance degradation behavior of the device under stress scenarios. First, based on the key indicators such as bandwidth fluctuation coefficient, latency kurtosis, and cumulative error rate obtained in steps 2 and 3, a basic reliability score is constructed. Bandwidth fluctuation can reflect the stability of the controller's data path; latency kurtosis can characterize the burst behavior of the scheduling algorithm in high-contention scenarios; and the error rate directly reflects the integrity performance of the NAND medium and the controller. By normalizing and weighting the sum of these three types of indicators, a basic health score of the device can be obtained, providing a static reference framework for subsequent dynamic evaluation. Subsequently, based on the load type (sequential read, sequential write, random read, random write) and the current scheduling depth of the controller during actual testing, the basic reliability score is weighted and corrected. This embodiment identifies IO access characteristics, including parameters such as sequentiality, read-write ratio, and queue depth, and infers the internal scheduling pressure of the controller based on these characteristics. For example, under high QD conditions, the controller needs to execute a large number of parallel tasks. This state can expose scheduling bottlenecks and the limits of cache management strategies. In addition, this embodiment calculates a parallel write correction coefficient based on the controller's parallelism and number of channels to characterize the controller's stability performance under multi-channel scheduling. Furthermore, in order to take into account factors related to SSD lifespan, this embodiment sets media degradation weights according to NAND type (such as TLC, QLC or PLC). Different NAND processes have significant differences in charge retention capability, write lifespan and degradation curves. By introducing degradation weights, the reliability score can be made closer to the actual lifespan characteristics of the device. After obtaining the weighted reliability score, this embodiment performs dynamic threshold determination. △R can be calculated from the difference between the basic reliability score and the instantaneous performance index, which is used to characterize the performance degradation degree of the SSD under the current load. If Td deviates significantly from the baseline level, it indicates that the SSD has shown an early degradation trend or scheduling abnormality in the current scenario, and it is necessary to further confirm whether there is a risk of device failure. Through the above process, this embodiment adds load characteristics, adaptive weighting and real-time offset analysis to the benchmark performance model, realizing dynamic reliability evaluation in complex scenarios; The fundamental scoring system, which integrates bandwidth fluctuations, latency peaks, and error rates, quantifies the health status of SSDs, avoiding the uncertainty of manual judgment. A weighted mechanism based on load characteristics and controller scheduling depth ensures that reliability scores reflect device performance in real-world business scenarios, rather than relying on a single benchmark test. By introducing media degradation weights related to NAND technology, the overall scoring system adapts to the lifespan decay patterns of different NAND types, improving model universality. A dynamic threshold formula combined with real-time reliability offset ΔR enables the system to capture immediate performance degradation of SSDs under high concurrency and high-pressure scenarios, enhancing early anomaly detection capabilities. Adaptive threshold adjustment (Td) automatically adapts to different load states, SSD models, and test conditions, making reliability assessment results more robust and reliable. The overall scoring mechanism helps identify potentially unstable devices early in the testing phase, providing a scientific basis for quality screening and subsequent batch consistency analysis.

[0030] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for testing SSD solid-state drives, characterized in that, Includes the following steps: Step 1: Perform pre-test preparation and environment initialization; Step 2: Collect multi-dimensional performance indicators; Step 3: Perform data integrity verification and anomaly clustering analysis; Step 4: Conduct dynamic threshold determination and reliability scoring based on load characteristics.

2. The SSD solid-state drive testing method according to claim 1, characterized in that, Step 1 includes: Establish a baseline configuration for the test environment, which includes power supply noise limit, interface protocol version, temperature range and queue depth parameters to ensure consistency of test conditions. Perform low-level formatting and block table erasure on the SSD under test to restore all physical blocks to their original clean page state; Load the test task description file, which includes an IO mode set, data distribution strategy, read / write ratio and number of concurrent threads, to form a multi-dimensional test load matrix.

3. The SSD solid-state drive testing method according to claim 2, characterized in that, The test load matrix includes: Combinations of IO modes include sequential read, sequential write, random read, and random write; The data pattern set includes fixed pattern, pseudo-random pattern, all-zero pattern and entropy controllable pattern; The combined dimension of the number of concurrent threads and the queue depth is used to construct high-concurrency pressure scenarios.

4. The SSD solid-state drive testing method according to claim 1, characterized in that, Step 2 includes: Sequential access tests were performed with a fixed block size to collect average bandwidth, maximum bandwidth, and bandwidth jitter coefficient. Generate a random addressing load and sample delay sequences at different queue depths; The kurtosis K of the delayed sample sequence Ln is calculated using the following formula: ； Where N is the number of samples, and Li is the latency of the i-th access. σ represents the average delay, σ represents the standard deviation of the delay, and the peak value K is used to characterize delay spikes and scheduling anomalies.

5. The SSD solid-state drive testing method according to claim 4, characterized in that, The process of generating random addressing load includes: The I / O arrival sequence is randomly generated using a Poisson process to simulate common bursts of server access. I / O randomization is performed based on thread contention, resulting in a non-uniform distribution of access patterns; Set a threshold for switching across logical blocks to dynamically switch the workload between continuous writing of large files and frequent writing of small files.

6. The SSD solid-state drive testing method according to claim 1, characterized in that, Step 3 includes: Perform CRC-64 verification on the written data and compare it with the original check value to identify bit flips and storage medium instability. Analyze the clustering of failed verification addresses and statistically analyze address locality through continuous error windows; Anomaly clustering vectors are constructed and an error cluster is formed using a density clustering algorithm to distinguish between controller anomalies and NAND media aging phenomena.

7. The SSD solid-state drive testing method according to claim 6, characterized in that, The abnormal clustering vector includes: Construct a cluster element Ei = {address offset, error cycle, block erase / write count, channel number}; Normalization is used to make the characteristics of different batches of SSDs comparable; Cluster labels are compared with historical records to identify cross-batch consistency defects.

8. The SSD solid-state drive testing method according to claim 6, characterized in that, The error cluster analysis includes: Statistical analysis is performed on the clustered error cluster centers to generate a cluster center feature set Cj = {error density, address span, recurrence period, and distribution of the associated channel}; Cluster separation index is calculated based on cluster center feature set to evaluate the independence between different error modes; By comparing cluster separation with historical stable samples, we can identify whether anomalous clusters belong to potential early degradation patterns.

9. The SSD solid-state drive testing method according to claim 1, characterized in that, Step 4 includes: A basic reliability score is constructed based on bandwidth fluctuation, latency kurtosis, and error rate. The reliability score is weighted according to the load type and the controller scheduling depth; The formula for dynamic threshold determination is as follows: ； Among them, T d T0 is the dynamic threshold, α is the initial threshold, α is the weighting coefficient, and ΔR is the real-time reliability offset, used to characterize the degradation trend of SSD under stress load.

10. The SSD solid-state drive testing method according to claim 9, characterized in that, The weighting process includes: Identify I / O access characteristics, including sequentiality, read-write ratio, and queue depth; Calculate the parallel write correction factor based on the controller's parallelism and the number of channels; The media degradation weight is set according to the NAND type to reflect the impact of long-term aging factors.

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