Conversion control circuit for controlling stackable multi-phase power converter

Abstract

A switching control circuit for controlling a stackable multi-phase power converter is provided. The conversion control circuit comprises a main control transfer end, a main control transfer trigger signal and a main control transfer trigger signal, wherein the main control transfer trigger signal is coupled to a plurality of main control transfer ends of a plurality of conversion control circuits which are connected in parallel; the main control transfer circuit is used for generating or receiving a main control transfer trigger signal through a main control transfer end, and the main control transfer trigger signal is generated according to the output voltage or the output current or the pulse width modulation related signal of the output power supply; when the master transfer trigger signal is switched to an enabling state, the conversion control circuit performs a phase sequence replacement program, and the phase sequence replacement program comprises the following steps: the master transfer circuit triggers a plurality of stackable sub-converters, the master role of the stackable sub-converter that originally acts as a master circuit is transferred to another of the plurality of stackable sub-converters.

Description

TECHNICAL FIELD

[0001] The present invention relates to a switching control circuit for controlling a stackable multiphase power converter, and in particular to a switching control circuit for controlling a stackable multiphase power converter capable of distributing switching stress. BACKGROUND

[0002] Figure 1A is a circuit schematic diagram showing a known switching control circuit and a stackable multiphase power converter controlled thereby. Figure 1B is a signal waveform diagram showing relevant signals of the switching control circuit and the stackable multiphase power converter controlled thereby. Figure 1A The main converter of the known stackable multiphase power converter is a fixed-phase converter. When the load varies to cause the phase to increase or decrease, the main converter has to bear more current (in absolute value, as shown in the encircled portion of the following figure), thus causing the life of the main converter to be greatly reduced compared to the lives of the converters of other phases. Figure 1B

[0003] In view of the above, the present invention proposes a switching control circuit for controlling a stackable multiphase power converter capable of distributing switching stress. SUMMARY

[0004] In one aspect, the present invention provides a switching control circuit for controlling a stackable multiphase power converter, wherein the stackable multiphase power converter comprises a plurality of stackable sub-converters, wherein each of the plurality of stackable sub-converters comprises a power stage circuit and a corresponding switching control circuit, wherein the plurality of power stage circuits corresponding to the plurality of stackable sub-converters are coupled in parallel to each other to generate an output power to a load, wherein the switching control circuit is configured to control at least one switch of the power stage circuit to switch a corresponding inductor, thereby generating the output power, the switching control circuit comprising: a master transfer terminal, wherein a master transfer trigger signal is coupled to a plurality of master transfer terminals of a plurality of switching control circuits coupled in parallel to each other; and a master transfer circuit configured to generate or receive the master transfer trigger signal through the master transfer terminal, wherein the master transfer trigger signal is generated according to an output voltage or an output current or a pulse width modulation related signal of the output power; wherein the switching control circuit is configured as a master circuit or a slave circuit, wherein when the master transfer trigger signal is switched to an enabled state, the switching control circuit performs a phase sequence replacement procedure, wherein the phase sequence replacement procedure comprises: the master transfer circuit triggers the master role of a stackable sub-converter originally acting as the master circuit among the plurality of stackable sub-converters to be transferred to another one of the plurality of stackable sub-converters.

[0005] ​In one embodiment, the phase sequence replacement procedure further comprises triggering, by the master transfer circuit, a slave phase sequence transfer of a slave phase sequence of the stackable sub-converter originally serving as the slave circuit to another one of the stackable sub-converters other than the another one.

[0006] In one embodiment, the master transfer circuit switches the master transfer trigger signal to the enabled state when a state change occurs in the stackable multiphase power converter or a predetermined time elapses or a cumulative number of state changes exceeds a number threshold or an instruction is received from outside.

[0007] In one embodiment, the state change comprises a load state change, a voltage change, a current change, a phase number change, and / or a frequency change of the pulse width modulation related signal.

[0008] In one embodiment, the load state change comprises a change from a heavy load state to a light load state or a change from a light load state to a heavy load state; wherein the voltage change comprises an output voltage change or a target voltage change of the output voltage; wherein the phase number change comprises a start-up phase number change; wherein the frequency change of the pulse width modulation related signal comprises a change from a high frequency to a low frequency or a change from a low frequency to a high frequency; and / or wherein the current change comprises a total current exceeding a preset threshold.

[0009] In one embodiment, the state change is detected by the master circuit.

[0010] In one embodiment, the conversion control circuit further comprises a counter configured to accumulate the cumulative number of state changes.

[0011] In one embodiment, the master transfer circuit determines the predetermined time according to a fixed frequency clock count.

[0012] In one embodiment, the master transfer circuit determines the predetermined time according to the pulse width modulation related signal configured to control the at least one switch of the power stage circuit.

[0013] In one embodiment, the phase sequence replacement procedure replaces the master role of the stackable sub-converter originally serving as the master circuit to the another one of the stackable sub-converters in a random sequence manner or in a preset sequence manner.

[0014] In one embodiment, the conversion control circuit further includes: a modulation trigger terminal, wherein a modulation trigger signal is coupled to a plurality of modulation trigger terminals of a plurality of conversion control circuits connected in parallel; wherein the modulation trigger signal includes a plurality of pulses, wherein the plurality of pulses includes a first pulse, wherein the first pulse is used to be continuously counted to a count value, wherein when the count value corresponds to a phase sequence number of the conversion control circuit, the conversion control circuit enables the power stage circuit to generate the output power supply.

[0015] In one embodiment, the conversion control circuit further includes: a modulation trigger terminal, wherein a modulation trigger signal is coupled to multiple modulation trigger terminals of multiple conversion control circuits connected in parallel; wherein the modulation trigger signal includes multiple pulses, wherein the multiple pulses include a first pulse and multiple second pulses that are different from the first pulse in electrical characteristics, wherein the first pulse is used to be continuously counted to a count value, and the second pulses are used as the master control transfer trigger signal, wherein when the count value corresponds to a phase sequence number of the conversion control circuit, the conversion control circuit enables the power stage circuit to generate the output power supply; wherein the modulation trigger terminal and the master control transfer terminal are the same terminal.

[0016] In one embodiment, the plurality of pulses further includes a third pulse, which serves as a count reset signal to reset and start counting the count value.

[0017] In one embodiment, the electrical characteristic includes a voltage level or pulse width.

[0018] In one embodiment, the master control transfer trigger signal is generated by the master control circuit or by an external device.

[0019] The advantages of this invention are that it can distribute the switching stress to each sub-converter, reduce potential phase imbalance and long-term reliability issues.

[0020] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, features and effects achieved by the present invention. Attached Figure Description

[0021] Figure 1A This is a circuit diagram showing a known conversion control circuit and the stackable multiphase power converter it controls.

[0022] Figure 1B It is a display Figure 1A A schematic diagram of the signal waveforms of the conversion control circuit and the related signals of the stackable multiphase power converter it controls.

[0023] Figure 2AThis is a circuit diagram showing a conversion control circuit and a stackable multiphase power converter controlled by the present invention.

[0024] Figure 2B This is a circuit diagram showing a conversion control circuit and a stackable multiphase power converter controlled by the present invention, according to another embodiment of the present invention.

[0025] Figure 3A This is a circuit block diagram showing the conversion control circuit according to an embodiment of the present invention.

[0026] Figure 3B This is a circuit block diagram showing the conversion control circuit according to another embodiment of the present invention.

[0027] Figure 3C This is a circuit block diagram showing a circuit for generating a predetermined time according to an embodiment of the present invention.

[0028] Figure 3D This is a circuit block diagram showing a circuit for generating a predetermined time according to another embodiment of the present invention.

[0029] Figure 3E This is a circuit diagram of a counter used to count changes in state, according to an embodiment of the present invention.

[0030] Figure 4 This is a circuit block diagram showing the conversion control circuit according to another embodiment of the present invention.

[0031] Figures 5A-5B This is a schematic diagram of signal waveforms showing the relevant signals of the conversion control circuit and the stackable multiphase power converter controlled by it, according to another embodiment of the present invention.

[0032] Figures 6-7 This is a schematic diagram of signal waveforms showing the relevant signals of the conversion control circuit and the stackable multiphase power converter controlled by it, according to another embodiment of the present invention.

[0033] Figures 8-10 This is a schematic diagram of signal waveforms showing the relevant signals of the conversion control circuit and the stackable multiphase power converter controlled by it, according to an embodiment of the present invention.

[0034] Explanation of symbols in the diagram

[0035] 10, 20, 30, 40: Power stage circuits

[0036] 100: Stackable Multiphase Power Converter

[0037] 101, 102, 103, 104: Stackable subconverters

[0038] 12: Modulation trigger circuit

[0039] 14: Main control transfer circuit

[0040] 15, 25, 35, 45, 400: Conversion control circuit

[0041] 16, 26, 36, 46: Drivers

[0042] 230, 240: Counters

[0043] 50: External devices

[0044] 99: Load

[0045] CLK: Fixed Frequency Clock

[0046] Cnt_pls: Counting trigger pulse

[0047] Ico: Output capacitor current

[0048] Io: Output current

[0049] Isum: Total current

[0050] L1, L2, L3, LN: Inductors

[0051] NX: Count value

[0052] R#: Master Control Transfer Terminal

[0053] RST_pls: Count reset pulse

[0054] RT, RT': Master control transfer trigger signals

[0055] RT_pls: Master control transfer trigger pulse

[0056] Spw, Spw0, Spw1, Spw2, SpwN: Pulse width modulation signals

[0057] SW0, SW1, SW2, SW3, SWN: Switching node voltages

[0058] t1, t2, t3, t4, t5, t6: Time points

[0059] T#: Modulation trigger terminal

[0060] Tp: Booking time

[0061] TRIG, TRIG': Modulation trigger signal

[0062] VIN: Input voltage

[0063] VOUT, Vo: Output voltage

[0064] Vth1, Vth2, Vth3: Level thresholds Detailed Implementation

[0065] The accompanying drawings in this invention are all schematic and are mainly intended to show the coupling relationship between various circuits and the relationship between various signal waveforms. The circuits, signal waveforms and frequencies are not drawn to scale.

[0066] Figure 2A This is a circuit diagram illustrating a conversion control circuit and a stackable multiphase power converter controlled by the present invention, according to an embodiment of the present invention. Figure 2A As shown, the conversion control circuits 15, 25, 35, and 45 of the present invention are used to control the stackable multiphase power converter 100. The stackable multiphase power converter 100 includes a plurality of stackable sub-converters 101, 102, 103, and 104. Each of the plurality of stackable sub-converters 101, 102, 103, and 104 includes a corresponding power stage circuit 10, 20, 30, or 40 and a corresponding conversion control circuit 15, 25, 35, or 45. The plurality of power stage circuits 10, 20, 30, and 40 corresponding to the plurality of stackable sub-converters 101, 102, 103, and 104 are connected in parallel and coupled to each other to generate output power to the load 99. The conversion control circuits 15, 25, 35, and 45 are used to generate pulse width modulation signals Spw0~SpwN to control at least one switch of the corresponding power stage circuits 10, 20, 30, and 40 to switch the corresponding inductors L1, L2, L3…LN, thereby generating the output power. The conversion control circuits 15, 25, 35, and 45 include a main control transfer terminal R# and a modulation trigger terminal T#.

[0067] The master control transfer trigger signal RT is coupled to multiple master control transfer terminals R# of multiple parallel-connected conversion control circuits 15, 25, 35, and 45. The modulation trigger signal TRIG is coupled to multiple modulation trigger terminals T# of multiple parallel-connected conversion control circuits 15, 25, 35, and 45. In one embodiment, the conversion control circuits 15, 25, 35, and 45 can be configured as master control circuits or slave circuits. When the master control transfer trigger signal RT switches to the enabled state, the conversion control circuits 15, 25, 35, and 45 perform a phase sequence switching procedure. In one embodiment, the master control transfer trigger signal RT is generated by the master control circuit.

[0068] Figure 2B This is a circuit diagram illustrating a conversion control circuit and a stackable multiphase power converter controlled by the present invention, according to another embodiment of the invention. This embodiment is similar to... Figure 2A The difference in this embodiment is that the modulation trigger terminal T# and the master control transfer terminal are combined into the same terminal. In other words, both the master control transfer trigger signal RT and the modulation trigger signal TRIG are transmitted and received through the modulation trigger terminal T#.

[0069] Figure 3A This is a circuit block diagram of a switching control circuit according to an embodiment of the present invention. In this embodiment, the main control transfer terminal R# and the modulation trigger terminal T# are separate terminals. Figure 3A As shown, the conversion control circuit 400 includes a main control transfer circuit 14 and a modulation trigger circuit 12. It should be noted that the conversion control circuit 400 can be corresponding to... Figure 2A One of the conversion control circuits 15, 25, 35 and 45.

[0070] When the switching control circuit 400 is configured as the master control circuit, the modulation trigger circuit 12 generates a modulation trigger signal TRIG through the modulation trigger terminal T#. When the switching control circuit 400 is configured as a slave circuit, the modulation trigger circuit 12 receives the modulation trigger signal TRIG through the modulation trigger terminal T#. The modulation trigger circuit 12 generates a pulse width modulation signal Spw based on the triggering of the modulation trigger signal TRIG or its related signal, which can correspond to the aforementioned pulse width modulation signals Spw0, Spw1, Spw2...SpwN.

[0071] When the conversion control circuit 400 is configured as a master control circuit, the master control transfer circuit 14 generates a master control transfer trigger signal RT through the master control transfer terminal R# based on the output voltage Vo or output current Io of the output power supply, or based on a pulse width modulation related signal (e.g., TRIG), to initiate the phase sequence switching procedure. On the other hand, when the conversion control circuit 400 is configured as a slave circuit, the master control transfer circuit 14 receives the master control transfer trigger signal RT through the master control transfer terminal R#, and performs the phase sequence switching procedure based on the triggering of the master control transfer trigger signal RT.

[0072] When the stackable multiphase power converter 100 undergoes a state change, or the cumulative number of state changes exceeds a threshold, or when an external command is received, the master control transfer circuit 14, configured as the master control circuit, switches the master control transfer trigger signal RT to the enabled state (e.g., by generating a pulse). The aforementioned state changes include load state changes, voltage changes, current changes, phase number changes, and / or pulse width modulation signal frequency changes. Load state changes include changing from a heavy load state to a light load state or from a light load state to a heavy load state. Voltage changes include changes in output voltage or changes in the target output voltage. Current changes include changes in total current. Phase number changes include changes in the activation phase number. Pulse width modulation signal frequency changes include changing from a high frequency to a low frequency or from a low frequency to a high frequency.

[0073] Figure 3EThis is a circuit diagram illustrating a counter for counting state changes according to an embodiment of the present invention. In one embodiment, a master control transfer circuit 14 configured as the master control circuit accumulates the cumulative number of state changes. When the cumulative number of state changes exceeds a threshold (e.g., via...),... Figure 3E The counter 240 (which triggers a count based on a state change) generates a trigger pulse on the master control transfer trigger signal RT. In one embodiment, the aforementioned count threshold can be any integer greater than or equal to 1.

[0074] Figure 3B This is a circuit block diagram showing a conversion control circuit according to an embodiment of the present invention. This embodiment is similar to... Figure 3A The embodiment differs in that the modulation trigger terminal and the master control transfer terminal are combined into a single terminal (i.e., a shared modulation trigger terminal T#). Specifically, the modulation trigger signal TRIG generated or received through the modulation trigger terminal T# can contain various pulses, including a counting trigger pulse Cnt_pls, a counting reset pulse RST_pls, and a master control transfer trigger pulse RT_pls, the details of which are described later. In this embodiment, the master control transfer trigger signal RT' is transmitted between the modulation trigger circuit 12 and the master control transfer circuit 14' to indicate the triggering of the phase sequence changing procedure.

[0075] Figure 3C This is a circuit block diagram showing a circuit for generating a predetermined time according to an embodiment of the present invention. Figure 3C As shown, in one embodiment, the master control transfer circuit 14 includes a counter 230 for counting based on a pulse width modulation related signal (e.g., TRIG or its related signal) to determine a predetermined time Tp.

[0076] Figure 3D This is a circuit block diagram showing a circuit for generating a predetermined time according to another embodiment of the present invention. For example... Figure 3D As shown, in another embodiment, counter 230 is used to count according to a fixed frequency clock CLK to determine a predetermined time Tp.

[0077] Figure 4 This is a circuit block diagram of a switching control circuit according to another embodiment of the present invention. This embodiment is similar to... Figure 2A The difference in this embodiment is that the master control transfer trigger signal RT is generated by an external device 50.

[0078] Figure 5A This is a schematic diagram of signal waveforms showing the conversion control circuit and related signals of the stackable multiphase power converter controlled by it, according to an embodiment of the present invention. The count value NX, modulation trigger signal TRIG, and switching node voltages SW0, SW1, SW2, and SW3 are displayed. Figure 5AIn this embodiment, there is an independent master control transfer terminal R#, and therefore an independent master control transfer trigger signal RT. For example... Figure 5A As shown, in this embodiment, the multiple pulses of the modulation trigger signal TRIG include a counting trigger pulse Cnt_pls and a counting reset pulse RST_pls. The counting trigger pulse Cnt_pls is used to be continuously counted to a count value NX. Please also refer to... Figure 5A and Figure 2B When the count value NX corresponds to the phase sequence number of the conversion control circuits 15, 25, 35, or 45, the conversion control circuits 15, 25, 35, or 45 enable the corresponding power stage circuits 10, 20, 30, or 40 to generate output power. It should be noted that in this embodiment, the initial phase sequence number of conversion control circuit 15 is 0, the initial phase sequence number of conversion control circuit 25 is 1, the initial phase sequence number of conversion control circuit 35 is 2, and the initial phase sequence number of conversion control circuit 45 is 3. The aforementioned counting trigger pulse Cnt_pls and counting reset pulse RST_pls, for example, have different electrical characteristics, which may include the voltage level of the pulse of the modulation trigger signal TRIG, or the pulse width, as detailed below.

[0079] Please continue reading. Figure 5A In this embodiment, the counting reset pulse RST_pls and the counting trigger pulse Cnt_pls are distinguished by the voltage level of the pulse. Figure 5A As shown, the voltage level of the count reset pulse RST_pls is higher, while the voltage level of the count trigger pulse Cnt_pls is lower. The count reset pulse RST_pls is used to reset and start counting the count value NX. It should be noted that the count reset pulse RST_pls is also considered as the count trigger pulse Cnt_pls.

[0080] The aforementioned phase sequence replacement procedure includes: the master control transfer circuit 14 triggers the transfer of the master control role of the stackable sub-converter that originally served as the master control circuit among the multiple stackable sub-converters 101, 102, 103 and 104 to another of the multiple stackable sub-converters 101, 102, 103 and 104.

[0081] Please refer to the following at the same time Figure 5A , Figure 3A and Figure 2A At time t1, the stackable sub-converter 101 assumes the master control role of the main control circuit. At time t4, the master control transfer trigger signal RT generates a pulse, indicating the initiation of a phase sequence switching procedure. Therefore, at time t5, the master control role is transferred to the stackable sub-converter 102. The phase sequence switching procedure is repeated whenever the master control transfer trigger signal RT generates a pulse. The timing of the phase sequence switching procedure indicated by the generation of the pulse in the master control transfer trigger signal RT is described above.

[0082] In one embodiment, the phase sequence switching procedure transfers the control role of a stackable sub-converter 101, 102, 103, and 104 that originally served as the main control circuit to another stackable sub-converter 101, 102, 103, and 104 in a preset order. In another embodiment, the phase sequence switching procedure transfers the control role of a stackable sub-converter 101, 102, 103, and 104 that originally served as the main control circuit to another stackable sub-converter 101, 102, 103, and 104 in a random order.

[0083] Figure 5B This is a schematic diagram of signal waveforms showing the conversion control circuit and related signals of the stackable multiphase power converter controlled by it, according to an embodiment of the present invention. This embodiment has an independent master control transfer terminal R#, and therefore an independent master control transfer trigger signal RT. This embodiment is similar to... Figure 5A The embodiment differs in that, in this embodiment, the pulse width is used to distinguish between the count reset pulse RST_pls and the count trigger pulse Cnt_pls. For example... Figure 5B As shown, the pulse width of the count reset pulse RST_pls is wider, while the pulse width of the count trigger pulse Cnt_pls is narrower.

[0084] Figure 6 This is a schematic diagram of signal waveforms showing the conversion control circuit and related signals of the stackable multiphase power converter controlled by it, according to another embodiment of the present invention. Figure 6 As shown, when the stackable multiphase power converter 100 has elapsed for a predetermined time Tp, the main control transfer circuit 14 switches the main control transfer trigger signal RT to the enabled state, generating a pulse, thereby indicating that a phase sequence replacement procedure needs to be performed.

[0085] Figure 7 This is a schematic diagram of signal waveforms showing the conversion control circuit and related signals of the stackable multiphase power converter controlled by it, according to another embodiment of the present invention. Figure 7 As shown, in one embodiment, the aforementioned change in total current includes the total current Isum exceeding, for example, decreasing to below a preset threshold Ith. In other words, when the total current Isum decreases to below the preset threshold Ith, the master control transfer trigger signal RT switches to the enable level. In another embodiment, the aforementioned change in total current may also include the total current Isum increasing to above the preset threshold Ith.

[0086] Figure 8This is a schematic diagram of signal waveforms showing the conversion control circuit and related signals of the stackable multiphase power converter controlled by it, according to an embodiment of the present invention. In this embodiment, the modulation trigger terminal T# and the main control transfer terminal are the same terminal. In other words, in this embodiment, the multiple pulses of the modulation trigger signal TRIG generated or received by the modulation trigger terminal T# also include a main control transfer trigger pulse RT_pls that is different in voltage level from the counting trigger pulse Cnt_pls and the counting reset pulse RST_pls. The main control transfer trigger pulse RT_pls corresponds to the aforementioned main control transfer trigger signal RT.

[0087] Specifically, Figure 8 The master control transfer pulse RT_pls, count reset pulse RST_pls, and count trigger pulse Cnt_pls shown are generated by superimposing pulses of different levels from the master control circuit. Figure 8 The diagram shows a TRIG signal with three pulses that are different in voltage level.

[0088] On the other hand, when the switching control circuit is configured as a slave circuit, it can determine the different pulses mentioned above based on the level thresholds Vth1, Vth2, and Vth3. When the voltage level of the pulse of the modulation trigger signal TRIG is higher than the level threshold Vth1, the switching control circuit will determine it as the count reset pulse RST_pls. When the voltage level of the pulse of the modulation trigger signal TRIG is between the level thresholds Vth1 and Vth2, the switching control circuit will determine it as the count trigger pulse Cnt_pls. When the voltage level of the pulse of the modulation trigger signal TRIG is between the level thresholds Vth2 and Vth3, the switching control circuit will determine it as the master control transfer trigger pulse RT_pls.

[0089] like Figure 8 As shown, the counting trigger pulse Cnt_pls is used to continuously count to the count value NX. The counting reset pulse RST_pls is used to reset and start counting at the count value NX. The master control transfer trigger pulse RT_pls is used as the master control transfer trigger signal RT.

[0090] Figure 9 This is a schematic diagram of signal waveforms showing the conversion control circuit and related signals of the stackable multiphase power converter controlled by it, according to an embodiment of the present invention. This embodiment is related to... Figure 7 The embodiment is similar, except that the modulation trigger terminal T# and the master control transfer terminal are the same terminal in this embodiment. Therefore, the modulation trigger signal TRIG includes the master control transfer trigger pulse RT_pls. For the operation of the master control transfer trigger pulse RT_pls, please refer to [link to relevant documentation]. Figure 7 Explanation.

[0091] Figure 10This is a schematic diagram of signal waveforms showing the conversion control circuit and related signals of the stackable multiphase power converter controlled by it, according to an embodiment of the present invention. This embodiment is similar to... Figure 8 The embodiment differs in that, in this embodiment, the different pulses included in the modulation trigger signal TRIG have different pulse widths.

[0092] In summary, this invention can distribute switching stress to each sub-converter by transferring the main control circuit, thereby mitigating potential phase imbalance and long-term reliability issues.

[0093] The present invention has been described above with reference to preferred embodiments. However, the above description is only intended to facilitate understanding of the invention by those skilled in the art and is not intended to limit the scope of the invention. The described embodiments are not limited to individual application and can also be used in combination. For example, two or more embodiments can be used in combination, and some components of one embodiment can be used to replace corresponding components in another embodiment. Furthermore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations. For example, the phrase "processing or calculating based on a signal or generating an output result" in the present invention is not limited to the signal itself, but also includes, when necessary, performing voltage-to-current conversion, current-to-voltage conversion, and / or proportional conversion on the signal, and then processing or calculating based on the converted signal to generate an output result. Therefore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations, and there are many ways to combine them, which will not be listed here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A conversion control circuit for controlling a stackable multiphase power converter, wherein the stackable multiphase power converter includes a plurality of stackable sub-converters, each of the plurality of stackable sub-converters including a power stage circuit and a corresponding conversion control circuit, wherein the plurality of power stage circuits corresponding to the plurality of stackable sub-converters are connected in parallel and coupled to each other to generate an output power supply to a load, wherein the conversion control circuit is used to control at least one switch of the power stage circuit to switch a corresponding inductor, thereby generating the output power supply, the conversion control circuit comprising: A master control transfer terminal, wherein a master control transfer trigger signal is coupled to multiple master control transfer terminals of multiple conversion control circuits connected in parallel; and A master control transfer circuit is used to generate or receive a master control transfer trigger signal through the master control transfer terminal, wherein the master control transfer trigger signal is generated according to an output voltage or an output current or a pulse width modulation related signal of the output power supply; The conversion control circuit is configured as a master control circuit or a slave circuit. When the master control transfer trigger signal switches to the enabled state, the conversion control circuit performs a phase sequence replacement procedure, which includes: The master control transfer circuit triggers the transfer of the master control role of the stackable sub-converter that originally served as the master control circuit to another of the stackable sub-converters.

2. The conversion control circuit as described in claim 1, wherein, The phase sequence switching procedure also includes: triggering the master control transfer circuit to transfer the slave phase sequence of the stackable sub-converter that originally served as the slave circuit to another one of the stackable sub-converters besides the other one.

3. The conversion control circuit as described in claim 1, wherein, When the stackable multiphase power converter undergoes a state change, or after a predetermined time, or when the cumulative number of state changes exceeds a threshold, or when an instruction is received from the outside, the master control transfer circuit switches the master control transfer trigger signal to the enabled state.

4. The conversion control circuit as described in claim 3, wherein, This state change includes changes in load state, voltage, current, phase number, and / or frequency of the pulse width modulation-related signal.

5. The conversion control circuit as described in claim 3, wherein, The load state change includes changing from a heavy load state to a light load state or from a light load state to a heavy load state; wherein the voltage change includes an output voltage change or a target voltage change of the output voltage; wherein the phase number change includes a start-up phase number change; wherein the frequency change of the pulse width modulation related signal includes changing from a high frequency to a low frequency or from a low frequency to a high frequency; and / or wherein the current change includes the total current exceeding a preset threshold.

6. The conversion control circuit as described in claim 3, wherein, This state change is detected by the main control circuit.

7. The conversion control circuit as described in claim 3, wherein, It also includes a counter to accumulate the cumulative number of times the state has changed.

8. The conversion control circuit as described in claim 3, wherein, The master control transfer circuit determines the predetermined time by counting according to a fixed frequency clock.

9. The conversion control circuit as described in claim 3, wherein, The master control transfer circuit determines the predetermined time based on the pulse width modulation related signal count, wherein the pulse width modulation related signal is used to control the at least one switch of the power stage circuit.

10. The conversion control circuit as described in claim 1, wherein, The phase sequence replacement procedure transfers the master control role of the stackable sub-converter that originally served as the master control circuit to another stackable sub-converter in a random or preset order.

11. The conversion control circuit as described in claim 1, wherein, Also includes: A modulation trigger terminal, wherein a modulation trigger signal is coupled to multiple modulation trigger terminals of multiple conversion control circuits connected in parallel; The modulation trigger signal includes multiple pulses, including a first pulse, which is continuously counted to a count value. When the count value corresponds to a phase sequence number of the conversion control circuit, the conversion control circuit enables the power stage circuit to generate the output power.

12. The conversion control circuit as described in claim 1, wherein, Also includes: A modulation trigger terminal, wherein a modulation trigger signal is coupled to multiple modulation trigger terminals of multiple conversion control circuits connected in parallel; The modulation trigger signal includes multiple pulses, including a first pulse and multiple second pulses that are different from the first pulse in electrical characteristics. The first pulse is used to be continuously counted as a count value, and the second pulses are used as the master control transfer trigger signal. When the count value corresponds to a phase sequence number of the conversion control circuit, the conversion control circuit enables the power stage circuit to generate the output power. The modulation trigger terminal and the main control transfer terminal are the same terminal.

13. The conversion control circuit as described in claim 11 or 12, wherein, The plurality of pulses also includes a third pulse, which serves as a count reset signal to reset and restart the counting of the count value.

14. The conversion control circuit as described in claim 10, wherein, This electrical characteristic includes voltage level or pulse width.

15. The conversion control circuit as described in claim 1, wherein, The master control transfer trigger signal is generated by the master control circuit or by an external device.

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