Primary-side drive protection circuit and method, pulse control circuit, resonant converter

Abstract

The application discloses a primary side driving protection circuit and method, a pulse control circuit and a resonant converter. The primary side driving protection circuit comprises an abnormality detection circuit, which detects whether a rising edge loss and / or a falling edge loss exists in a lower tube driving signal output by a digital timing logic circuit through an analog delay circuit; and a logic reset circuit, which performs logic operation on an output signal of the abnormality detection circuit and outputs a reset pulse to control the digital timing logic circuit to reset. The application detects whether a rising edge loss or a falling edge loss exists in a lower tube driving signal output by a primary side digital timing logic circuit through an analog delay circuit, and controls the primary side digital timing logic circuit to reset in time through a logic reset circuit. Since the analog delay circuit and the logic reset circuit do not have a latch function, the application can resist space particle radiation or other unexpected interference, so that the LLC resonant converter can recover normal work in time and can be applied to the aerospace field.

Description

Technical Field

[0001] This invention relates to the field of resonant converter technology, and more specifically, to a primary-side drive protection circuit and method, a pulse control circuit, and a resonant converter, which can operate stably under space particle radiation or other unexpected interference conditions, such as in the aerospace field. Background Technology

[0002] The LLC resonant converter is a high-efficiency switching power supply topology that uses closed-loop feedback control of switching devices and LC resonant circuits to achieve high-frequency operation. By adjusting the switching frequency, the output voltage can be adjusted, which can simultaneously meet the requirements of aerospace design for high power output and high transmission efficiency.

[0003] LLC resonant converters are generally used as follows Figure 1a The pulse frequency modulation (PFM) circuit shown is used for control. The positive input of comparator CMP1 is connected to the ramp voltage Ramp, and the negative input VC is connected to the error signal EAO. Its output is connected to the digital sequential logic circuit L1, which controls the upper transistor drive signal prout1 and the lower transistor drive signal prout2. Prout1 and prout2 drive the upper power transistor Q1 and the lower power transistor Q2, respectively. Prout2 controls the current source to charge the capacitor, thus initiating the rise of Ramp. Figure 1b It shows Figure 1a Waveform diagrams of each signal are shown in the reference diagram. Figure 1a and 1b Initially, the upper transistor drive signal `prout1` is high, and the lower transistor drive signal `prout2` is low. The Ramp starts to rise, and the pulse frequency modulation signal (pfm) output by comparator CMP1 is low. When the Ramp rises above the EAO voltage, the pfm output by comparator CMP1 changes from low to high. After passing through the digital sequential logic circuit L1, the upper transistor drive signal `prout1` changes from high to low, and the lower transistor drive signal `prout2` changes from low to high. The Ramp is reset to 0. The digital sequential logic circuit L1 records the duration of the high level of `prout1` and starts timing. When the duration of the high level of `prout2` equals the duration of the high level of `prout1`, `prout2` changes from high to low, and `prout1` changes from low to high. The Ramp starts to rise again and begins the next switching cycle. This process repeats, allowing the LLC resonant converter to output drive signals `prout1` and `prout2` with a 50% duty cycle. This control circuit ensures that the transformer excitation currents are equal in magnitude when they are in opposite phases by guaranteeing that the turn-on times of prout1 and prout2 are precisely equal. This avoids the phenomenon of transformer bias due to current imbalance, thereby improving the reliability and service life of the transformer.

[0004] exist Figure 1aIn this circuit, the upper transistor drive signal `prout1` is mainly generated by analog circuits such as comparators. It lacks digital sequential logic units such as latches and D flip-flops, resulting in strong anti-interference and error correction capabilities. It is less prone to logic errors, and even if errors occur, they are corrected promptly without locking up. The high level of the lower transistor drive signal `prout2` is obtained by timing the high level of `prout1` using the digital sequential logic circuit L1. In the aerospace field, under conditions of space particle radiation or other unexpected interference, the digital sequential logic circuit L1 is prone to random logic errors and latching errors. This can lead to a digital logic error output state in `prout2`, causing the LLC resonant converter output voltage to drop or the switching state to lock up, resulting in dangerous situations such as device burnout and affecting device reliability and lifespan. Summary of the Invention

[0005] In view of this, the main objective of the present invention is to provide a primary-side drive protection circuit and method, a pulse control circuit, and a resonant converter, in order to at least partially solve at least one of the above-mentioned technical problems.

[0006] To address the aforementioned technical problems, the first aspect of this invention provides a primary-side drive protection circuit for use in the pulse control circuit of a resonant converter, comprising: an abnormality detection circuit and a reset circuit, wherein:

[0007] An anomaly detection circuit uses an analog delay circuit to detect whether the rising edge and / or falling edge of the lower transistor drive signal output by the digital sequential logic circuit is lost.

[0008] The logic reset circuit performs a logic operation on the output signal of the fault detection circuit to output a reset pulse when the rising edge and / or falling edge of the current transistor drive signal is lost, thereby controlling the digital sequential logic circuit to reset.

[0009] According to a preferred embodiment of the present invention, the anomaly detection circuit includes:

[0010] A first detection circuit includes: an anomaly detection comparator and a first analog delay circuit. The first analog delay circuit delays the output signal of the anomaly detection comparator for a first predetermined time before outputting it to a logic reset circuit. When the output signal of the anomaly detection comparator flips, and the output signal remains unchanged after being delayed for the first predetermined time by the first analog delay circuit, it indicates that the rising edge of the lower transistor drive signal has been lost. And / or a second detection circuit includes: a second analog delay circuit connected to the lower transistor drive signal. The second analog delay circuit delays the lower transistor drive signal for a second predetermined time before outputting it to a logic reset circuit. When the high-level duration of the lower transistor drive signal exceeds a preset delay time of the second analog delay circuit, it indicates that the falling edge of the lower transistor drive signal has been lost.

[0011] According to a preferred embodiment of the present invention, the logic reset circuit further includes: a third analog delay circuit, which outputs an end reset pulse after delaying the reset pulse for a third predetermined time to control the digital timing logic circuit to end the reset.

[0012] According to a preferred embodiment of the present invention, the anomaly detection circuit includes: a first detection circuit and a second detection circuit; the pulse control circuit of the resonant converter includes: a ramp signal generator controlled by a lower transistor drive signal, the output terminal of the ramp signal generator being connected to the positive input terminal of a first comparator, the negative input terminal of the first comparator being connected to an error signal, and the output terminal of the first comparator being connected to the input terminal of a digital sequential logic circuit.

[0013] In the first detection circuit, the positive input terminal of the anomaly detection comparator is connected to the positive input terminal of the first comparator, and the negative input terminal is connected to the negative input terminal of the first comparator via a bias voltage. The output terminal of the anomaly detection comparator and the output terminal of the first comparator are connected to the input terminal of the first analog delay circuit via a first logic gate circuit. The output terminal of the first analog delay circuit is connected to a logic reset circuit.

[0014] In the second detection circuit, the second analog delay circuit is connected to the lower transistor drive signal.

[0015] According to a preferred embodiment of the present invention, the logic reset circuit includes: a second logic gate circuit connected to the output terminal of the first analog delay circuit and the output terminal of the second analog delay circuit, wherein when the current transistor drive signal has a rising edge loss or a falling edge loss, the second logic gate circuit outputs a reset pulse to control the digital timing logic circuit to reset.

[0016] According to a preferred embodiment of the present invention, the logic reset circuit further includes: a third analog delay circuit disposed between the second logic gate circuit and the digital sequential logic circuit, wherein when the digital sequential logic circuit is reset, the third analog delay circuit outputs an end reset pulse to control the digital sequential logic circuit to end the reset.

[0017] According to a preferred embodiment of the present invention, the analog delay circuit includes: a charging and discharging circuit and a comparator, wherein: the output terminal of the charging and discharging circuit is connected to the positive input terminal of the comparator, and the reference voltage is connected to the negative input terminal of the comparator; the charging and discharging circuit is composed of a current source and a capacitor, or the charging and discharging circuit is composed of a resistor and a capacitor.

[0018] To solve the above-mentioned technical problems, a second aspect of the present invention provides a pulse control circuit, comprising the primary-side drive protection circuit described in any one of the above-mentioned claims.

[0019] To solve the above-mentioned technical problems, a third aspect of the present invention provides a resonant converter comprising the pulse control circuit described above.

[0020] To address the aforementioned technical problems, a fourth aspect of the present invention provides a primary-side drive protection method for use in the pulse control circuit of a resonant converter, comprising:

[0021] The analog delay circuit is used to detect whether the rising edge and / or falling edge of the lower transistor drive signal output by the digital sequential logic circuit is lost.

[0022] When the current transistor drive signal experiences a loss of rising edge and / or falling edge, the output signal of the fault detection circuit is logically processed to output a reset pulse to control the digital timing logic circuit to reset.

[0023] In summary, the anomaly detection circuit of this invention detects whether the rising edge or falling edge of the lower transistor drive signal output by the primary-side digital sequential logic circuit is lost through an analog delay circuit; and promptly controls the primary-side digital sequential logic circuit to reset through a logic reset circuit. Since neither the analog delay circuit nor the logic reset circuit has a latching function, it can resist interference from space particle radiation or other unexpected interference. Therefore, in the event of chaos in the primary-side digital sequential logic circuit due to space particle radiation or other unexpected interference, it can promptly reset the primary-side digital sequential logic circuit, thereby enabling the LLC resonant converter to quickly return to normal operation and protecting the LLC resonant converter from dangerous situations such as output voltage loss or switch lock-up leading to device burnout. This significantly improves the reliability and lifespan of the LLC resonant controller, extending its application to aerospace systems. Attached Figure Description

[0024] To make the technical problems solved by this invention, the technical means adopted, and the technical effects achieved clearer, specific embodiments of this invention will be described in detail below with reference to the accompanying drawings. However, it should be noted that the drawings described below are merely drawings of exemplary embodiments of this invention. Those skilled in the art can obtain drawings of other embodiments based on these drawings without any creative effort.

[0025] Figure 1a This is a circuit diagram of the pulse frequency modulation control circuit for an existing LLC resonant converter.

[0026] Figure 1b This is a waveform diagram of pulse frequency modulation control for an existing LLC resonant converter.

[0027] Figure 2 This is a primary-side drive protection circuit diagram provided in an embodiment of the present invention.

[0028] Figure 3This is a simulated rising edge delay circuit diagram provided in an embodiment of the present invention.

[0029] Figure 4a When the digital logic sequential circuit is working normally Figure 2 The control waveform diagram.

[0030] Figure 4b When a logic error occurs normally in a digital logic sequential circuit, causing the signal of the upper transistor to be lost at the rising edge... Figure 2 The control waveform diagram.

[0031] Figure 4c When a logic error occurs normally in a digital logic sequential circuit, causing the signal of the upper transistor to be lost on the falling edge... Figure 2 The control waveform diagram.

[0032] Figure 5 This is a flowchart illustrating a primary-side driven protection method provided in an embodiment of the present invention. Detailed Implementation

[0033] Subject to the inventive concept, the structures, performance, effects or other features described in a particular embodiment may be combined in any suitable manner with one or more other embodiments.

[0034] In the description of specific embodiments, detailed descriptions of structures, performance, effects, or other features are provided to enable those skilled in the art to fully understand the embodiments. However, it is not excluded that those skilled in the art can implement the present invention under certain circumstances with technical solutions that do not contain the above-described structures, performance, effects, or other features. The figures in the accompanying drawings are merely illustrative examples and do not imply that the solutions of the present invention must include all the contents, operations, and steps shown in the figures, nor do they imply that they must be performed in the order shown in the figures.

[0035] Before describing the technical solution of this invention, the technical terms involved in this invention will be explained first:

[0036] LLC: In an LLC resonant converter, LLC is short for a resonant circuit consisting of two inductors and one capacitor. These three components are the resonant inductor (Lr), the magnetizing inductor (Lm), and the resonant capacitor (Cr).

[0037] DCX: The DCX resonant converter is a resonant circuit consisting of two inductors and one capacitor. Its control method is open-loop control, with a fixed switching frequency achieving a fixed gain for both the input and output voltages; the output voltage varies with the input voltage.

[0038] PWM: Pulse Width Modulation, the output voltage changes with the duty cycle.

[0039] PFM: Pulse Frequency Modulation, the output voltage changes with the output frequency.

[0040] refer to Figure 1a If a digital logic error occurs in the sequential logic circuit L1, the drive signal prout2 of the lower transistor will also experience a digital logic error. There are three main situations in which the drive signal prout2 of the lower transistor experiences a digital logic error:

[0041] The prout2 timer fails to start: In this situation, after prout1 changes from high to low, prout2 cannot change from low to high. Prout2 remaining low prevents the lower power transistor from turning on. Because prout2 remains low, prout1 cannot detect the falling edge of prout2 from high to low, so prout1 also cannot turn on, resulting in a low output. The LLC resonant converter is locked in the off state of both power transistors, causing an abnormal power loss in the output voltage.

[0042] The prout2 timer starts working normally, but it fails to stop. In this situation, prout2 remains high, and the lower power transistor remains on. Because prout2 is always high, prout1 cannot detect the falling edge of prout2, so prout1 also cannot turn on. The LLC resonant converter is locked in the state where the upper power transistor is off and the lower power transistor is on. This causes the lower power transistor to continuously provide a short-circuit discharge path to ground for the output load and inductor, which can easily lead to overcurrent burnout of the lower power transistor and transformer, and voltage drop at the output.

[0043] The digital sequential logic circuit fails to exit the idle state due to an abnormal state transition, resulting in a logic lock-up state. In this case, prout2 may be locked at a low level as in (1) or at a high level as in (2).

[0044] Based on the above analysis, it can be seen that when a digital logic error occurs in the lower transistor drive signal prout2, the rising edge of prout2 will not be detected (prout2 is locked at a low level) or the falling edge will not be detected (prout2 is locked at a high level). Based on this, the present invention designs an anomaly detection circuit to detect whether the rising edge and / or falling edge of the lower transistor drive signal output by the digital sequential logic circuit is lost, thereby confirming whether a digital logic error has occurred in the digital sequential logic circuit. The logic reset circuit controls the digital sequential logic circuit to reset in time so as to restart the LLC resonant converter.

[0045] Based on the above analysis, embodiments of the present invention provide a primary-side drive protection circuit for use in the pulse control circuit of a resonant converter, comprising: an abnormality detection circuit and a reset circuit, wherein:

[0046] The anomaly detection circuit uses an analog delay circuit to detect whether the rising edge and / or falling edge of the lower transistor drive signal output by the digital sequential logic circuit is lost.

[0047] The logic reset circuit performs a logic operation on the output signal of the fault detection circuit to output a reset pulse when the rising edge and / or falling edge of the current transistor drive signal is lost, thereby controlling the digital sequential logic circuit to reset.

[0048] In this embodiment, the anomaly detection circuit can be configured to detect only whether the rising edge of the lower transistor drive signal output by the digital sequential logic circuit is lost. In this case, the logic reset circuit is configured to perform a logical operation on the output signal of the anomaly detection circuit and output a reset pulse to control the reset of the digital sequential logic circuit when the rising edge of the lower transistor drive signal is lost. Alternatively, the anomaly detection circuit can be configured to detect only whether the falling edge of the lower transistor drive signal output by the digital sequential logic circuit is lost. In this case, the logic reset circuit is configured to perform a logical operation on the output signal of the anomaly detection circuit and output a reset pulse to control the reset of the digital sequential logic circuit when the falling edge of the lower transistor drive signal is lost. Furthermore, the anomaly detection circuit can be configured to simultaneously detect whether the rising edge or falling edge of the lower transistor drive signal output by the digital sequential logic circuit is lost. In this case, the logic reset circuit is configured to perform a logical operation on the output signal of the anomaly detection circuit and output a reset pulse to control the reset of the digital sequential logic circuit when the rising edge or falling edge of the lower transistor drive signal is lost.

[0049] For example, the analog delay circuit includes a charging / discharging circuit and a comparator, wherein: the output terminal of the charging / discharging circuit is connected to the positive input terminal of the comparator, and the reference voltage is connected to the negative input terminal of the comparator; the charging / discharging circuit is composed of a current source and a capacitor, or the charging / discharging circuit is composed of a resistor and a capacitor.

[0050] Furthermore, to ensure that the LLC resonant converter resumes normal operation after the digital sequential logic circuit is reset, the logic reset circuit also includes: a third analog delay circuit, which delays the reset pulse for a third predetermined time before outputting the end reset pulse to control the digital sequential logic circuit to end the reset. After the reset is complete, the upper-side control signal and the lower-side control signal continue to drive the output according to the preset function, and the LLC resonant converter resumes normal operation.

[0051] In one possible implementation, the anomaly detection circuit is configured to detect only whether the rising edge of the lower transistor drive signal output by the digital sequential logic circuit is lost. In this case, the detection circuit includes only a first detection circuit. Specifically, the first detection circuit includes an anomaly detection comparator and a first analog delay circuit. The first analog delay circuit delays the output signal of the anomaly detection comparator for a first predetermined time before outputting it to the logic reset circuit. When the output signal of the anomaly detection comparator flips, and the output signal remains unchanged after being delayed by the first analog delay circuit for the first predetermined time, it indicates that the rising edge of the lower transistor drive signal has been lost. Optionally, the pulse control circuit of the resonant converter includes: a ramp signal generator controlled by a lower transistor drive signal, the output of the ramp signal generator being connected to the positive input of a first comparator, the negative input of the first comparator being connected to an error signal, and the output of the first comparator being connected to the input of a digital sequential logic circuit; then in the first detection circuit, the positive input of the anomaly detection comparator is connected to the positive input of the first comparator, the negative input is connected to the negative input of the first comparator via a bias voltage, the output of the anomaly detection comparator and the output of the first comparator are connected to the input of the first analog delay circuit via a first logic gate circuit, and the output of the first analog delay circuit is connected to a logic reset circuit.

[0052] Correspondingly, the logic reset circuit includes a second logic gate circuit connected to the output of the first analog delay circuit and other signals. When the rising edge of the current transistor drive signal is lost, the second logic gate circuit outputs a reset pulse to control the digital sequential logic circuit to reset. The specific second logic gate circuit and other signals can be configured according to the actual circuit. For example, the second logic gate circuit can be an OR gate (NOR), and the other signals can be reference signals. The output of the first analog delay circuit is connected to one input of the OR gate (NOR), and the reference signal is input to the other input of the NOR gate. Whenever the first analog rising edge delay circuit outputs an abnormal signal indicating a lost rising edge, the NOR gate outputs a reset pulse to control the digital sequential logic circuit to reset. Preferably, the output of the second logic gate circuit can also be connected to the digital sequential logic circuit after being delayed by a third analog delay circuit. When the digital sequential logic circuit resets, the output signal of the first analog delay circuit flips. This flipped signal is then delayed by the second logic gate circuit and the third analog delay circuit before outputting an end reset pulse to control the digital sequential logic circuit to end the reset. After the reset is complete, the upper transistor control signal and the lower transistor control signal continue to drive the output according to the preset function. The LLC resonant converter resumes normal operation.

[0053] In one possible implementation, the anomaly detection circuit is configured to detect only whether the falling edge of the lower transistor drive signal output by the digital sequential logic circuit is lost. In this case, the detection circuit only includes a second detection circuit. The second detection circuit includes a second analog delay circuit connected to the lower transistor drive signal. The second analog delay circuit delays the lower transistor drive signal for a second predetermined time before outputting it to the logic reset circuit. When the high-level duration of the lower transistor drive signal exceeds the preset delay time of the second analog delay circuit, it indicates that the falling edge of the lower transistor drive signal has been lost.

[0054] The logic reset circuit includes a second logic gate circuit connected to the output of the second analog delay circuit and other signals. When the falling edge of the current transistor drive signal is lost, the second logic gate circuit outputs a reset pulse to control the digital sequential logic circuit to reset. The specific second logic gate circuit and other signals used can be configured according to the actual circuit. For example, the second logic gate circuit can be an OR gate (NOR), and the other signals can be reference signals. The output of the second analog delay circuit is connected to one input of the OR gate (NOR), and the reference signal is input to the other input of the NOR gate. Whenever the second analog rising delay circuit outputs an abnormal signal indicating a lost falling edge, the NOR gate outputs a reset pulse to control the digital sequential logic circuit to reset. Preferably, the output of the second logic gate circuit can also be delayed by a third analog delay circuit and then connected to the digital sequential logic circuit. When the digital sequential logic circuit resets, the output signal of the second analog delay circuit flips. This flipped signal is then delayed by the second logic gate circuit and the third analog delay circuit before outputting an end reset pulse to control the digital sequential logic circuit to end the reset. After the reset is complete, the upper transistor control signal and the lower transistor control signal continue to drive the output according to the preset function. The LLC resonant converter resumes normal operation.

[0055] In a preferred embodiment, the anomaly detection circuit is configured to simultaneously detect whether the rising edge loss anomaly or the falling edge loss anomaly exists in the lower transistor drive signal output by the digital sequential logic circuit. The detection circuit includes a first detection circuit and a second detection circuit. For example... Figure 2 This primary-side drive protection circuit, used in the pulse control circuit of the resonant converter, includes: an abnormality detection circuit and a logic reset circuit, wherein:

[0056] The pulse control circuit of the resonant converter includes: a ramp signal generator controlled by the drive signal of the lower transistor; the output of the ramp signal generator is connected to the positive input of a first comparator CMP1 (PFM comparator); the negative input of the first comparator CMP1 is connected to an error signal EAO; and the output of the first comparator CMP1 is connected to the input of a digital sequential logic circuit L1. Figure 2The ramp signal generator includes a current source, one end of which is connected to a power supply, and the other end of which is connected to the negative terminal of the current source via a charging / discharging circuit. A ramp signal Ramp is output between the current source and the discharging circuit. The charging / discharging circuit includes a charging / discharging capacitor and a discharge control signal output terminal connected in parallel with the charging / discharging capacitor. The discharge control signal output terminal outputs a lower transistor drive signal prout2.

[0057] The anomaly detection circuit includes:

[0058] The first detection circuit includes: an anomaly detection comparator CMP2 and a first analog delay circuit T1. The positive input terminal of the anomaly detection comparator CMP2 is connected to the positive input terminal of the first comparator CMP1, and the negative input terminal is connected to the negative input terminal of the first comparator CMP1 via a bias voltage VOS. The output terminals of the anomaly detection comparator CMP2 and the first comparator CMP1 are connected to the input terminal of the first analog delay circuit T1 via a first logic gate circuit. The output terminal of the first analog delay circuit T1 is connected to a logic reset circuit. Wherein, CMP1 and CMP2 are both PFM comparators, and the first logic gate circuit is an AND gate circuit.

[0059] The second detection circuit includes a second analog delay circuit connected to the lower transistor drive signal prout2.

[0060] The logic reset circuit includes a second logic gate connected to the output of the first analog delay circuit T1 and the output of the second analog delay circuit T2. The second logic gate is connected to the digital sequential logic circuit via a third analog delay circuit T3. The second logic gate is a NOR gate. The logic reset circuit performs a NOR operation between the output signal of the first analog delay circuit T1 and the output signal of the second analog delay circuit T2. When the lower transistor drive signal prout2 experiences a rising edge loss and / or a falling edge loss, a low-level valid reset pulse is generated at the low-level valid logic reset node rstn_logic to control the reset of the digital sequential logic circuit L1. After the digital sequential logic circuit L1 is reset, it outputs the initial states prout1 and prout2. After passing through the pulse control circuit of the resonant transformer, the abnormality detection circuit, the NOR operation of the logic reset circuit, and the rising edge delay of the third analog delay circuit T3, a high-level signal is generated at the low-level valid logic reset node rstn_logic to control the digital sequential logic circuit L1 to end the reset.

[0061] In the above examples, the first / second / third analog delay circuits use analog methods to achieve continuous signal output and do not have latching functions. Therefore, they have strong anti-interference characteristics and can avoid logic errors or state lock-ups caused by latching state errors in digital sequential logic circuits. For example, as shown... Figure 3The first / second / third analog delay circuit may include: a charge / discharge circuit and a comparator CMP3, wherein: the output of the charge / discharge circuit is connected to the positive input of the comparator CMP3, the reference voltage vref is connected to the negative input of the comparator CMP3, and the comparator CMP3 outputs a delay signal Timer_done. The charge / discharge circuit may be as follows: Figure 3 The first / second / third analog delay circuit can be composed of a current source and a capacitor, using the input signal IN as the discharge control signal to control the charging and discharging process; or it can be composed of a resistor and a capacitor, using the input signal IN as the discharge control signal to control the charging and discharging process. In another example, the first / second / third analog delay circuit may include a combination of an inverted input signal and a falling edge delay unit. The delay time of the input signal for the first / second / third analog delay circuit can be configured according to actual needs.

[0062] The following is based on Figure 2 Taking this as an example, the process of detecting whether the rising edge or falling edge of the lower transistor drive signal output by the digital sequential logic circuit of the present invention is described in detail. Specifically: the first analog delay circuit T1 and the second analog delay circuit T3 can delay the input signal by 1.5μs, and the second analog delay circuit T2 can delay the input signal by 30μs. The positive input terminal of comparator CMP1 is connected to the ramp signal Ramp, and the negative input terminal of comparator CMP1 is connected to EAO. Ramp can be generated by a ramp signal generator; the high level of probe2 is obtained by timing the high level time of probe1 through the digital sequential logic circuit L1.

[0063] (1) Normal operating state of digital sequential logic circuit L1: The waveforms of each signal (Ramp, EAO, prout1, prout2, and rstn_logic) in the circuit are shown in the figure. Figure 4a As shown. Reference Figure 2 and Figure 4a The current source charges the capacitor, causing the ramp to rise. Initially, probe1 is high and probe2 is low. As the ramp begins to rise, the output pfm of comparator CMP1 is low. When the ramp exceeds the EAO voltage, the CMP1 output changes from low to high. After passing through the digital sequential logic circuit L1, the upper transistor drive signal probe1 changes from high to low, and the lower transistor drive signal probe2 changes from low to high. The ramp voltage is reset to 0. The digital sequential logic circuit L1 records the duration of the probe1 high level and starts timing. When the duration of the probe2 high level equals the duration of the probe1 high level, probe2 changes from high to low, and probe1 changes from low to high. The ramp begins to rise again and the next switching cycle begins. The node rstn_logic is not working and its output is always high; the digital sequential logic circuit L1 does not need to be reset.

[0064] A logic error occurred in digital sequential logic circuit L1, and the rising edge of prout2 was lost. The waveforms of each signal in the circuit (Ramp, EAO, prout1, prout2, and rstn_logic) are shown below. Figure 4b As shown in the reference above. Figure 2 and Figure 4b Initially, the ramp starts to rise, with prout1 high and prout2 low. The output pfm of CMP1 is low, and the output pfm_vos of CMP2 is low. When the ramp voltage rises above the EAO voltage, the CMP1 output changes from low to high, driving prout1 from high to low. However, the lower transistor's driving signal prout2 remains low and does not rise. The ramp voltage continues to rise. When it reaches a Vos voltage higher than EAO, CMP2 flips, and the CMP2 output voltage pfm_vos changes from low to high, indicating an abnormal rising edge of prout2. After a 1.5μs delay by the T1 rising edge delayer, pfm_vos remains high, confirming that the rising edge of prout2 has been lost. The T1 output changes from low to high, the logic of the rstn_logic node changes from high to low, and all digital units in the L1 digital sequential logic circuit are reset to their initial state. Both prout1 and prout2 output low simultaneously. The ramp is pulled low. The outputs pfm and pfm_vos of CMP1 and CMP2 simultaneously change from high to low. The output of T1 immediately goes high, and after a 1.5μs delay (T3), the logic of node rstn_logic goes high. A 1.5μs low-level reset pulse is generated on node rstn_logic. After the reset, prout1 and pout2 continue to drive the outputs according to their preset functions. The LLC converter resumes normal operation.

[0065] A logic error occurred in the digital sequential logic circuit L1, and the falling edge of prout2 was lost. The waveforms of each signal in the circuit (Ramp, EAO, prout1, prout2, and rstn_logic) are shown below. Figure 4c As shown. Reference Figure 2 and Figure 4cWhen `prout2` transitions from low to high, the digital sequential logic circuit L1 begins timing. Once the high-level duration of `prout2` equals the high-level duration of `prout1`, `prout2` cannot transition from high to low and continues to output high. After `prout2`'s high-level output exceeds 30μs, it undergoes a second analog delay circuit T2 (30μs delay), at which point T2 outputs high. The node `rstn_logic` outputs low, resetting all digital units in the digital sequential logic circuit L1. When `prout2` transitions from high to low, `prout1` remains low. After a delay of T3 (1.5μs), the node `rstn_logic` outputs high, ending the reset. After the reset, `prout1` and `prout2` continue driving the output according to their preset functions. The LLC converter resumes normal operation.

[0066] Based on the above-described primary-side drive protection circuit, this embodiment of the invention also provides a pulse control circuit, including any one of the primary-side drive protection circuits described above.

[0067] Based on the above pulse control circuit, this embodiment of the invention also provides a resonant converter, which includes the above pulse control circuit.

[0068] Figure 5 This is a flowchart illustrating a primary-side driven protection method provided in an embodiment of the present invention. Figure 5 As shown, based on the above-described primary-side drive protection circuit, this embodiment of the invention also provides a primary-side drive protection method for use in the pulse control circuit of a resonant converter, comprising:

[0069] S1. Detect whether the rising edge and / or falling edge of the lower transistor drive signal output by the digital sequential logic circuit is lost by using an analog delay circuit.

[0070] S2. When the current transistor drive signal has a rising edge loss and / or a falling edge loss, the output signal of the abnormality detection circuit is logically operated to output a reset pulse to control the digital timing logic circuit to reset.

[0071] In one possible implementation, in step S1, the rise edge of the lower transistor drive signal output by the digital sequential logic circuit is lost by using an anomaly detection comparator and a first analog delay circuit. The first analog delay circuit outputs the output signal of the anomaly detection comparator to the logic reset circuit after delaying it for a first predetermined time. When the output signal of the anomaly detection comparator flips and remains unchanged after being delayed for a first predetermined time by the first analog delay circuit, it indicates that the rise edge of the lower transistor drive signal has been lost.

[0072] And / or, the second analog delay circuit connected to the lower transistor drive signal detects whether the lower transistor drive signal output by the digital sequential logic circuit has lost its falling edge. The second analog delay circuit delays the lower transistor drive signal for a second predetermined time and outputs it to the logic reset circuit. When the high level duration of the lower transistor drive signal exceeds the preset delay time of the second analog delay circuit, it indicates that the falling edge of the lower transistor drive signal has been lost.

[0073] Furthermore, the method also includes: delaying the reset pulse for a third predetermined time and then outputting an end reset pulse to control the digital timing logic circuit to end the reset.

[0074] In summary, the anomaly detection circuit of this invention detects whether the rising edge or falling edge of the lower transistor drive signal output by the primary-side digital sequential logic circuit is lost through an analog delay circuit; the logic reset circuit promptly controls the primary-side digital sequential logic circuit to reset when the rising edge or falling edge of the lower transistor drive signal is lost. This invention detects whether the rising edge or falling edge of the lower transistor drive signal output by the primary-side digital sequential logic circuit is lost through an analog delay circuit and promptly controls the primary-side digital sequential logic circuit to reset. Since neither the analog delay circuit nor the logic reset circuit has a latching function, it can resist interference from space particle radiation or other unexpected interference. Therefore, in the event of confusion in the primary-side digital sequential logic circuit due to space particle radiation or other unexpected interference, it can promptly reset the primary-side digital sequential logic circuit, thereby enabling the LLC resonant converter to quickly return to normal operation and protecting the LLC resonant converter from dangerous situations such as output voltage loss or switch lock-up leading to device burnout. This significantly improves the reliability and service life of the LLC resonant controller, extending its application to aerospace systems.

[0075] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the present invention is not inherently related to any specific computer, virtual device, or electronic device, and various general-purpose devices can also implement the present invention. The above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A primary-side drive protection circuit, characterized by, The pulse control circuit used in the resonant converter includes: an abnormality detection circuit and a reset circuit, wherein: An anomaly detection circuit uses an analog delay circuit to detect whether the rising edge and / or falling edge of the lower transistor drive signal output by the digital sequential logic circuit is lost. The logic reset circuit performs a logic operation on the output signal of the fault detection circuit to output a reset pulse to control the digital sequential logic circuit to reset when the rising edge and / or falling edge of the current transistor drive signal is lost. The anomaly detection circuit includes a first detection circuit and a second detection circuit; The first detection circuit includes an anomaly detection comparator and a first analog delay circuit. The first analog delay circuit delays the output signal of the anomaly detection comparator for a first predetermined time and then outputs it to the logic reset circuit. When the output signal of the anomaly detection comparator flips and remains unchanged after being delayed for the first predetermined time by the first analog delay circuit, it indicates that the rising edge of the lower transistor drive signal is lost. The second detection circuit includes a second analog delay circuit connected to the lower transistor drive signal. The second analog delay circuit delays the lower transistor drive signal for a second predetermined time and outputs it to the logic reset circuit. When the high-level duration of the lower transistor drive signal exceeds the preset delay time of the second analog delay circuit, it indicates that the falling edge of the lower transistor drive signal is lost.

2. The primary side drive protection circuit of claim 1, wherein, The logic reset circuit further includes: a third analog delay circuit, which delays the reset pulse for a third predetermined time and then outputs an end reset pulse to control the digital timing logic circuit to end the reset.

3. The primary-side drive protection circuit according to claim 1, characterized in that, The anomaly detection circuit includes: a first detection circuit and a second detection circuit; the pulse control circuit of the resonant converter includes: a ramp signal generator controlled by a lower transistor drive signal, the output terminal of the ramp signal generator is connected to the positive input terminal of a first comparator, the negative input terminal of the first comparator is connected to an error signal, and the output terminal of the first comparator is connected to the input terminal of a digital sequential logic circuit. In the first detection circuit, the positive input terminal of the anomaly detection comparator is connected to the positive input terminal of the first comparator, and the negative input terminal is connected to the negative input terminal of the first comparator via a bias voltage. The output terminal of the anomaly detection comparator and the output terminal of the first comparator are connected to the input terminal of the first analog delay circuit via a first logic gate circuit. The output terminal of the first analog delay circuit is connected to a logic reset circuit. In the second detection circuit, the second analog delay circuit is connected to the lower transistor drive signal.

4. The primary-side drive protection circuit according to claim 3, characterized in that, The logic reset circuit includes a second logic gate circuit connected to the output terminals of the first analog delay circuit and the second analog delay circuit. When the current transistor drive signal experiences a loss of rising edge or falling edge, the second logic gate circuit outputs a reset pulse to control the digital timing logic circuit to reset.

5. The primary-side drive protection circuit according to claim 4, characterized in that, The logic reset circuit further includes a third analog delay circuit located between the second logic gate circuit and the digital sequential logic circuit. When the digital sequential logic circuit is reset, the third analog delay circuit outputs an end reset pulse to control the digital sequential logic circuit to end the reset.

6. The primary-side drive protection circuit according to claim 1, characterized in that, The analog delay circuit includes a charging / discharging circuit and a comparator, wherein the output of the charging / discharging circuit is connected to the positive input of the comparator, and the reference voltage is connected to the negative input of the comparator; the charging / discharging circuit consists of a current source and a capacitor, or the charging / discharging circuit consists of a resistor and a capacitor.

7. A pulse control circuit, characterized in that, Includes the primary-side drive protection circuit as described in any one of claims 1 to 6.

8. A resonant converter, characterized in that, It includes the pulse control circuit as described in claim 7.

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