Active capacitance circuit with high and low clamping positions and power conversion chip of power supply

Abstract

The invention provides an active capacitor circuit with high and low clamping and a power supply power conversion chip. The active capacitor circuit comprises an input node, an active capacitor circuit, a low clamping circuit and a high clamping circuit. The input node is connected with the output end of the error amplifier, the active capacitor circuit is composed of an amplifying unit, a first resistor, a second resistor and an original capacitor, the original capacitor is equivalent to a large capacitor through a current shunting structure, and main loop frequency compensation is achieved; the amplification unit controls the current regulation transistor to form a feedback path, and the low-position clamping circuit clamps the lower limit of the output voltage to a preset low threshold value to prevent from climbing from zero potential during starting; the high-level clamping circuit clamps the upper limit to a preset high threshold, avoiding delay approaching the supply voltage. And the high and low clamping synergistic effect obviously accelerates the zero response speed of the loop. A large capacitor and a compensation pin do not need to be externally connected, the area of a peripheral device and a chip is reduced, the cost is reduced, the parasitic influence is eliminated, and the circuit is suitable for a high-integration-level DC-DC power supply chip.

Description

Technical Field

[0001] This application relates to the field of power management integrated circuit technology, and in particular to an active capacitor circuit with high and low clamping and a power conversion chip. Background Technology

[0002] With the continuous development of power management technology, DC-DC (Direct Current to Direct Current) converters are widely used in various electronic devices to achieve efficient energy conversion between different voltage levels. In switching power supply systems, in order to ensure the stability of the output voltage and dynamic response performance, frequency compensation of the control loop is usually required to ensure that the system can operate stably under various operating conditions.

[0003] Traditional compensation schemes often use off-chip passive components. However, this approach requires additional capacitors and resistors to be placed outside the chip, and dedicated compensation pins to be brought out. This not only increases the layout area of ​​the printed circuit board (PCB) but also raises material costs and assembly complexity. Furthermore, the parameters of external components are susceptible to factors such as temperature and aging, further affecting the long-term reliability of the system.

[0004] Therefore, in the existing technology, DC-DC power conversion compensation generally adopts off-chip large capacitor series resistor compensation, which adds an extra chip pin and peripheral devices, increasing cost and inconvenience. Summary of the Invention

[0005] The purpose of this application is to provide an active capacitor circuit with high and low clamping and a power conversion chip to alleviate the above-mentioned technical problems existing in the prior art.

[0006] In a first aspect, the present invention provides an active capacitor circuit with high and low clamping, comprising: an input node, an active capacitor circuit, a low-position clamping circuit, and a high-position clamping circuit; The input node is connected to the output of the error amplifier inside the power conversion chip; The active capacitor circuit includes an amplification unit, a first resistor, a second resistor, and an intrinsic capacitor. The first input terminal of the amplification unit is coupled to the input node through the first resistor, the second input terminal of the amplification unit is connected to the output terminal of the amplification unit, and the output terminal of the amplification unit is connected to the input node through the second resistor. The intrinsic capacitor is connected between the first input terminal of the amplification unit and ground. The active capacitor circuit is used to perform frequency compensation on the output voltage of the error amplifier. The output terminal of the amplifier unit is connected to the control electrode of the current regulating transistor. The first path terminal of the current regulating transistor is connected to the power supply terminal, and the second path terminal is connected between the second resistor and the second input terminal of the amplifier unit, forming a current feedback path so that the original capacitor is equivalent to the enlarged capacitor. The first terminal of the low-level clamping circuit is connected to the input node, the second terminal is connected to the power supply terminal, and the third terminal is grounded. The low-level clamping circuit is used to clamp the lower limit of the output voltage of the error amplifier at a preset low voltage threshold. The first terminal of the high-level clamping circuit is connected to the input node, the second terminal is connected to the power supply terminal, the third terminal is connected to the reference voltage terminal, and the fourth terminal is grounded. The high-level clamping circuit is used to clamp the upper limit of the output voltage of the error amplifier at a preset high voltage threshold.

[0007] In an optional implementation, the resistance values ​​of the first resistor and the second resistor are integer multiples of each other, and both are zero-temperature-drift resistors.

[0008] In an optional implementation, the intrinsic capacitor is a zero-temperature-drift capacitor or a low-temperature-drift capacitor.

[0009] In an optional implementation, the amplifier is a high-gain operational amplifier whose common-mode input range covers the output voltage variation range of the error amplifier.

[0010] In an optional implementation, the low-level clamping circuit includes a first bias current source, a first MOS transistor, and a second MOS transistor; One end of the first bias current source is connected to the power supply terminal, and the other end of the first bias current source is connected to the gate of the second MOS transistor. The source of the second MOS transistor is connected to the input node, and the drain of the second MOS transistor is connected to the power supply terminal. The gate of the first MOS transistor is connected to the input node, the drain of the first MOS transistor is connected to the gate of the second MOS transistor, and the source of the first MOS transistor is grounded.

[0011] In an optional implementation, the preset low voltage threshold is not less than the threshold voltage of the first MOS transistor.

[0012] In an optional implementation, the high-level clamping circuit includes a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a second bias current source, and a tail current source. One end of the second bias current source is connected to the source of the third MOS transistor and the gate of the fifth MOS transistor, respectively, and the other end of the second bias current source is grounded. One end of the tail current source is connected to the source of the fifth MOS transistor and the source of the sixth MOS transistor, respectively, and the other end of the tail current source is grounded. The gate of the third MOS transistor is connected to the input node, and the drain of the third MOS transistor is connected to the power supply terminal. The drain of the fifth MOS transistor is connected to the gate of the fourth MOS transistor and the drain of the eighth MOS transistor, respectively. The source of the fourth MOS transistor is connected to the input node, and the drain of the fourth MOS transistor is grounded. The source of the eighth MOS transistor is connected to the power supply terminal, and the gate of the eighth MOS transistor is connected to the gate of the seventh MOS transistor and the drain of the sixth MOS transistor, respectively. The source of the seventh MOS transistor is connected to the power supply terminal, the drain of the seventh MOS transistor is connected to the drain of the sixth MOS transistor, and the gate of the sixth MOS transistor is connected to the reference voltage terminal.

[0013] In an optional implementation, a reference voltage source is also included; The reference voltage source is connected between the power supply terminal and the reference voltage terminal; the reference voltage source is used to provide a reference voltage for the high-position clamping circuit.

[0014] In an optional implementation, the preset high voltage threshold is no higher than the sum of the reference voltage and the gate-source voltage of the third MOS transistor.

[0015] In a second aspect, the present invention provides a power conversion chip, including a main loop, an error amplifier, and an active capacitor circuit with high and low clamping as described in any of the foregoing embodiments. The inverting input of the error amplifier is connected to the feedback voltage output of the main loop, the non-inverting input of the error amplifier is connected to the reference voltage output of the main loop, and the output of the error amplifier is connected to the input node of the active capacitor circuit with high and low clamping. The error amplifier is used to amplify the error between the feedback voltage and the reference voltage of the main loop. An active capacitor circuit with high and low clamping is used to perform frequency compensation and voltage clamping on the output voltage of the error amplifier.

[0016] The active capacitor circuit with high and low clamping provided in this application and the power conversion chip work together with the amplification unit, the first resistor, the second resistor and the intrinsic capacitor in the active capacitor circuit to make the small intrinsic capacitor equivalent to a large capacitor by using a current shunt mechanism. This effectively replaces the large external compensation capacitor required in traditional solutions, thereby eliminating the need for additional chip pins and peripheral components, reducing system cost and packaging complexity. At the same time, the active capacitor integrated on-chip avoids the impact of pin parasitic inductance on loop stability, improving compensation accuracy and reliability. The low-clamping circuit and the high-clamping circuit limit the input node voltage between preset low voltage thresholds and high voltage thresholds, respectively, avoiding the long delay charging process when the compensation node starts from power supply or ground potential, significantly accelerating the loop response speed from zero and improving dynamic performance. The overall structure achieves high-performance frequency compensation without significantly increasing the chip area, meeting the design requirements of highly integrated power management chips. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 A circuit diagram of an active capacitor circuit with high and low clamping provided for an embodiment of this application; Figure 2 A block diagram of a power conversion chip provided in an embodiment of this application; Figure 3 This is a flowchart illustrating a frequency compensation method within a power management chip, as provided in an embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0022] This application provides an active capacitor circuit with high and low clamping. See also... Figure 1 As shown, the active capacitor circuit with high and low clamping includes: an input node, an active capacitor circuit, a low-clamping circuit, and a high-clamping circuit. Among them, The input node is connected to the output of the error amplifier inside the power converter chip. It is used to receive the output signal of the error amplifier (EA) inside the power converter chip. As a key node for frequency compensation, its voltage change directly affects the stability and dynamic response of the main loop.

[0023] The active capacitor circuit includes an amplification unit, a first resistor, a second resistor, and a source capacitor. The first input terminal of the amplification unit is coupled to the input node through the first resistor, the second input terminal of the amplification unit is connected to the output terminal of the amplification unit, and the output terminal of the amplification unit is connected to the input node through the second resistor. The source capacitor is connected between the first input terminal of the amplification unit and ground. The active capacitor circuit is used to perform frequency compensation on the output voltage of the error amplifier. This structure utilizes the virtual short characteristic of the amplification unit, making the current flowing through the first and second resistors inversely proportional to their resistance values, thereby achieving current shunting of the input current. That is, only a portion of the current flows into the source capacitor for charging and discharging. Based on the relationship between the first and second resistors, the capacitance value of the source capacitor is amplified to determine the equivalent capacitance, achieving the effect of simulating a large capacitor with a small capacitor, and completing the frequency compensation function of the error amplifier output voltage.

[0024] Furthermore, the output terminal of the amplification unit is connected to the control electrode (such as the gate) of the current regulating transistor, the first path terminal (such as the source) of the current regulating transistor is connected to the power supply terminal, and the second path terminal (such as the drain) is connected between the second power supply and the second input terminal of the amplification unit, forming a current feedback path so that the original capacitor is equivalent to an enlarged capacitor, thereby helping to enhance the output stability of the amplification unit and ensure the accuracy and consistency of the equivalent characteristics of the active capacitor.

[0025] In one embodiment, the aforementioned current-regulating transistor refers to a MOS transistor used to enhance the output drive capability or adjust the bias of the amplifier.

[0026] The low-level clamping circuit has three connection terminals: the first terminal of the low-level clamping circuit is connected to the input node, the second terminal is connected to the power supply terminal, and the third terminal is grounded. The low-level clamping circuit is used to clamp the lower limit of the output voltage of the error amplifier at a preset low voltage threshold. It works with the MOS transistor through a bias current source to turn on the pull-up device when the input node voltage is too low, clamping the lower limit of the voltage at the preset low voltage threshold, preventing the node voltage from starting from zero potential and causing response delay.

[0027] The high-level clamping circuit has four connection terminals: the first terminal is connected to the input node, the second terminal is connected to the power supply terminal, the third terminal is connected to the reference voltage terminal (Vh), and the fourth terminal is grounded. The high-level clamping circuit is used to clamp the upper limit of the error amplifier's output voltage at a preset high voltage threshold. Through a comparator structure composed of a tail current source and a MOSFET, the high-level clamping circuit activates a pull-down mechanism when the input node voltage is too high, clamping the upper voltage limit to the preset high voltage threshold and preventing the node voltage from approaching the power supply voltage, which would cause slow charging.

[0028] The active capacitor circuit with high and low clamping provided in this application realizes the function of small on-chip capacitors replacing large-capacity external capacitors through the active capacitor structure, without the need for additional pins and external components, thus improving the integration. At the same time, the high and low clamping circuits work together to limit the operating voltage range of the compensation node to a reasonable range, significantly accelerating the system's response speed from a zero starting state and optimizing the loop dynamic performance.

[0029] For ease of understanding, the active capacitor circuit with high and low clamping provided in this application will be described in detail below.

[0030] In one embodiment, in the active capacitor circuit, the amplification unit (high-gain operational amplifier), together with the first resistor and the second resistor, forms a feedback network. The capacitance value equivalent to that generated by the original capacitor through this feedback network is: C 等效 = C1×(1 + R2 / R1) Among them, C 等效 R1 is the equivalent capacitance value, C2 is the intrinsic capacitance value, R1 is the first resistor, and R2 is the second resistor.

[0031] By making the resistance values ​​of the first and second resistors integer multiples of each other, the accuracy of calculating the multiples of the equivalent capacitance is improved, while the controllability of the calculation is also enhanced.

[0032] The first and second resistors mentioned above are zero-temperature-drift resistors. The selection and application of these resistors can avoid the problem of resistance value drift caused by changes in ambient temperature or chip heating during actual circuit operation, which would disrupt the fixed ratio between the second and first resistors. This ensures that the ratio between the second and first resistors remains constant throughout the entire operating temperature range, preventing the equivalent capacitance from fluctuating with temperature, maintaining stable frequency compensation performance, preventing abnormal equivalent capacitance caused by temperature drift, avoiding phase shift or amplitude distortion of the error amplifier output voltage, and ensuring the reliability of the coordinated operation of the high and low clamping circuits and the main loop.

[0033] To further ensure that the capacitance value of the intrinsic capacitor remains constant across the entire operating temperature range, thereby guaranteeing C... 等效 The amplification factor is precisely controllable, avoiding compensation parameters caused by temperature drift. In one implementation, the original capacitor can be a zero-temperature-drift capacitor or a low-temperature-drift capacitor.

[0034] Zero-temperature-drift capacitors can use temperature-compensated dielectrics (such as C0G / NP0 material) with a temperature coefficient controlled within ±30ppm / ℃ (capacitance change ≤±0.3% over the entire temperature range). Low-temperature-drift capacitors can use high-performance dielectrics (such as X7R material) with a temperature coefficient controlled within ±15% (operating temperature range -55℃ to 125℃).

[0035] Furthermore, the amplifier used in the above circuit can be a high-gain operational amplifier. The common-mode input range of the high-gain operational amplifier covers the output voltage variation range of the error amplifier. That is, the high-gain operational amplifier (hereinafter referred to as "op-amp") in this embodiment has its own effective common-mode input voltage operating range, which completely includes the dynamic variation range of the error amplifier (EA) output voltage under all operating conditions, such as normal operation and high / low clamping triggering. Thus, the op-amp can maintain a linear operating state when the EA output voltage fluctuates arbitrarily, avoiding the offset of compensation parameters and signal distortion caused by op-amp characteristic failure. This ensures the reliability of the cooperative operation with the high / low clamping circuit and guarantees the stability and controllability of the EA output voltage.

[0036] The low-level clamping circuit in this optional embodiment is mainly used to limit the lower limit of the output voltage of the error amplifier (EA), preventing the common-mode input of the amplification unit (high-gain operational amplifier) ​​of the active capacitor circuit (which may exceed the limit due to excessively low EA output voltage, causing signal distortion, or causing subsequent power devices to operate abnormally due to low voltage stress. This low-level clamping circuit achieves active clamping of the EA output voltage through the coordinated operation of a first bias current source, a first MOS transistor (M1), and a second MOS transistor (M2), resulting in a simplified structure and rapid response.

[0037] One end of the first bias current source is connected to the power supply terminal, and the other end is connected to the gate of the second MOS transistor. This first bias current source is used to provide a stable bias current, which provides a reference potential for the gate of M2 through a constant current, determines the reference level of the low-level clamping threshold, and ensures that the gate potential of M2 is not affected by circuit noise.

[0038] The second MOS transistor M2 is a PMOS transistor, with its source connected to the input node (i.e., the EA output terminal) and its drain connected to the power supply terminal (Vdd). The current direction of the PMOS transistor is from the source to the drain. When it is turned on, it transfers the high potential of the power supply terminal to the EA output terminal, thereby realizing the rapid pull-up of the EA voltage.

[0039] The first MOS transistor M1 is an NMOS transistor, with its gate connected to the input node (EA output terminal). The drain of the first MOS transistor is connected to the gate of the second MOS transistor, and the source of the first MOS transistor is grounded. The NMOS transistor M1 detects the output state of EA through the gate voltage and is used for low-level clamping trigger control. The on and off states of M1 directly determine the operating mode of M2.

[0040] In practical applications, when the EA output voltage is within the normal operating range (above the low-level clamping threshold), the gate voltage of M1 (i.e., the EA output voltage) is higher, V GS1=V EA -0>V thn (Threshold voltage of NMOS), M1 is turned on. After M1 is turned on, its drain potential is pulled close to ground potential (source potential), causing the gate potential V of M2 to rise. G2 ≈0V. At this time, the V of M2 is approximately 0V. G2 = V G2 – V EA (Because of V) EA (Normal and above ground potential), V GS2 >V thp (PMOS threshold is negative), M2 is cut off, and the low-level clamping circuit does not affect the normal output of EA.

[0041] When the output voltage of EA drops below the low-level clamping threshold, the gate voltage V of M1... EA Decrease, causing V GS1 =V EA -0 <V thn M1 is turned off. After M1 is turned off, the constant current of the first bias current source no longer flows to ground through M1, but instead flows to the gate of M2, causing the gate potential V of M2 to be lowered. G2 Gradually pull it up to near the power supply voltage (Vdd). At this time, the V of M2... GS2 = V G2 - V EA =Vdd - V EA (Because of V) EA Too low, Vdd - V EA Satisfy V GS2 <V thp M2 is turned on.

[0042] After M2 is turned on, the high potential at the power supply terminal (Vdd) is transferred to the output terminal EA through the source-drain path of M2, causing Vdd to... EA It was quickly pulled up. When V EA When it rises above the low-level clamping threshold, the V of M1 GS1 When the conduction condition is met again, M1 turns on again, the gate potential of M2 is pulled low, M2 turns off, and the low-level clamping circuit stops operating. Afterwards, V... EA It will stabilize above the low-level clamping threshold, thereby limiting the lower limit of the EA output voltage.

[0043] In one implementation, a preset low voltage threshold is set to be no less than the threshold voltage of the first MOS transistor. This preset high voltage threshold is the core trigger reference for the high-level clamping circuit, i.e., the highest effective operating voltage allowed by the error amplifier (EA) output voltage. EAWhen the voltage rises above this threshold, the high-level clamping circuit must immediately initiate clamping action, using the fourth MOS transistor (M4, PMOS transistor) to clamp V. EA Quickly release to a safe range.

[0044] The high-level clamping circuit described in this embodiment is used to precisely limit the maximum value of the output voltage of the error amplifier (EA), preventing excessively high EA output voltage from causing the common-mode input of the active capacitor circuit's amplification unit (high-gain operational amplifier) ​​to exceed the limit, signal distortion, or damage to subsequent power devices due to overvoltage stress. This high-level clamping circuit includes a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a second bias current source, and a tail current source, specifically: One end of the second bias current source is connected to the source of the third MOS transistor M3 and the gate of the fifth MOS transistor M5, respectively, and the other end of the second bias current source is grounded. It is mainly used to provide a constant bias current. The second bias current source provides a stable reference potential for the gate of M5, while ensuring the current path when M3 is turned on, and avoiding false triggering caused by noise interference.

[0045] One end of the tail current source is connected to the source of the fifth MOS transistor M5 and the source of the sixth MOS transistor M6, respectively, while the other end of the tail current source is grounded, serving as a constant current bias unit for the M5-M6 differential pair. The constant tail current provided by the tail current source ensures that the differential pair operates in the saturation region, thereby improving the accuracy of the differential comparison.

[0046] The third MOS transistor, M3, is an NMOS transistor. Its gate is connected to the input node (EA output terminal), its drain is connected to the power supply terminal Vdd, and its source is connected to the second bias current source. M3 serves as the EA voltage sensing device, and its on / off state is used to directly characterize the level of the EA output voltage, thereby enabling state monitoring for clamp triggering.

[0047] The fifth MOS transistor, M5, is an NMOS transistor. Its drain is connected to the gate of the fourth MOS transistor and the drain of the eighth MOS transistor, respectively. M5 and M6 form a differential amplifier pair. The gate of M5 is connected to the second bias current source (controlled by M3), and the gate of M6 is connected to the reference voltage terminal (Vh). The drains of both are connected to the current mirror unit. By differentially comparing the "gate potential of M5 (reflecting the EA voltage)" with the "reference voltage Vh (preset high threshold reference)", the voltage difference is converted into a current difference, providing a signal for clamping control.

[0048] The fourth MOS transistor M4 is a PMOS transistor, with its source connected to the input node. Its drain is grounded, and its gate is connected to the drains of M5 and M8. When turned on, it rapidly discharges any excessive voltage output by EA to ground, achieving overvoltage clamping.

[0049] The source of the eighth MOS transistor M8 is connected to the power supply terminal, and the gate of the eighth MOS transistor is connected to the gate of the seventh MOS transistor and the drain of the sixth MOS transistor, respectively. The source of the seventh MOS transistor M7 is connected to the power supply terminal, the drain of the seventh MOS transistor is connected to the drain of the sixth MOS transistor, and the gate of the sixth MOS transistor is connected to the reference voltage terminal.

[0050] Both M7 and M8 use PMOS transistors to form a current mirror unit. Their gates are connected together, and their sources are both connected to the power supply (Vdd). The drain of M8 is connected to the drain of M5 and the gate of M4. By replicating the drain current of M6 to the output of M8, the current difference of the differential pair is converted into a potential change in the gate of M4, achieving precise control of clamp triggering.

[0051] When the output voltage of EA is within the normal range (below the preset high voltage threshold), the gate voltage V of M3... EA With the conduction conditions met, M3 reliably turns on. After M3 turns on, the current from the second bias current source flows through M3 to the power supply terminal, pulling the gate potential of M5 down to near ground potential. At this time, the V of M5... GS5 <V thn M5 is off. Simultaneously, the gate of M6 is connected to the reference voltage Vh. GS6 >V thn When M6 is turned on, its drain current flows through M7 to form a reference current. The current mirror formed by M7 and M8 replicates this reference current, but because M5 is turned off, M8 has no effective current output, and the gate potential of M4 is pulled close to the power supply voltage (Vdd). At this time, the Vdd of M4... GS4 = V G4 - V EA = Vdd - V EA (V) EA Normal, Vdd - V EA It is a positive value, greater than V. thp When M4 is cut off, the high-level clamping circuit does not interfere with the normal output of EA.

[0052] When the output voltage of EA is lower than the preset high voltage threshold, the gate voltage V of M3... EAWith the conduction conditions met, M3 reliably turns on. After M3 turns on, the current from the second bias current source flows through M3 to the power supply terminal, pulling the gate potential of M5 down to near ground potential. At this time, the V of M5... GS5 <V thn M5 is off. Simultaneously, the gate of M6 is connected to the reference voltage Vh. GS6 >V thn When M6 is turned on, its drain current flows through M7 to form a reference current. The current mirror formed by M7 and M8 replicates this reference current, but because M5 is turned off, M8 has no effective current output, and the gate potential of M4 is pulled close to the power supply voltage. At this time, the V of M4... GS4 =V G4 - V EA = Vdd - V EA When M4 is cut off, the high-level clamping circuit does not interfere with the normal output of EA.

[0053] As the output voltage of EA is pulled low, when V EA When the voltage threshold is below, the gate potential of M5 decreases accordingly, the drain current of M5 decreases to balance the current of M6, the current output from M8 to the gate of M4 weakens, and the gate potential of M4 rises again. GS4 >V thp M4 is cut off. At this time, the output voltage of EA stops discharging and stabilizes within the normal range. The high-level clamping circuit returns to standby mode, completing one clamping cycle.

[0054] Furthermore, a reference voltage source is included between the power supply terminal and the reference voltage terminal to provide a reference voltage for the high-level clamping circuit. As shown in the circuit diagram, the output terminal of the reference voltage source is directly connected to the gate of M6, providing a stable comparison standard for the differential pair composed of M5 and M6. When the output voltage of the error amplifier does not exceed this reference voltage, M6 is turned on, and its drain current is replicated by the current mirror unit composed of M7 and M8. Since M5 is turned off and there is no path, M4 remains off. When the output voltage of the error amplifier exceeds this reference voltage, the differential pair generates a current difference, which is converted into a change in the gate potential of M4 by the current mirror unit, triggering M4 to turn on to discharge the excessive voltage and achieve precise clamping.

[0055] In one embodiment, the aforementioned preset high voltage threshold is not higher than the sum of the reference voltage and the gate-source voltage of the third MOS transistor. By setting this preset high voltage threshold, when the output voltage of the error amplifier rises to the preset value, M3 can still remain reliably turned on, thereby continuously pulling down the gate potential of M5, making it lower than the reference voltage connected to the gate of M6, thus forming an effective voltage difference.

[0056] In summary, the voltage at the output node of EA is controlled within (V) by the combined use of low-clamping and high-clamping circuits. th —V gs +V h The range between these values ​​includes the normal output voltage range of EA, which allows the active capacitor to perform frequency compensation for the main loop normally. At the same time, it ensures that the voltage of the active capacitor compensation node at the EA output node does not have to change from 0 or Vdd, thus accelerating the loop's zero-response.

[0057] Based on the above-described active capacitor circuit with high and low clamping, this application also provides a power conversion chip, see [link to relevant documentation]. Figure 2 As shown, the circuit includes a main loop, an error amplifier, and an active capacitor circuit with high and low clamping as described in any of the preceding embodiments. The main loop is the core component of the power conversion chip, responsible for generating a feedback voltage and a reference voltage. The feedback voltage and reference voltage generated by the main loop are input to the inverting input and non-inverting input of the error amplifier, respectively. The error amplifier generates an error signal by comparing these two voltages.

[0058] The inverting input of the error amplifier is connected to the feedback voltage output of the main loop, the non-inverting input of the error amplifier is connected to the reference voltage output of the main loop, and the output of the error amplifier is connected to the input node with a high / low clamping active capacitor circuit. The error amplifier is used to amplify the error between the feedback voltage and the reference voltage of the main loop and output it to the input node with a high / low clamping active capacitor circuit.

[0059] An active capacitor circuit with high and low clamping is used to perform frequency compensation on the output voltage of the error amplifier to ensure system stability and response speed. Simultaneously, this circuit also clamps the output voltage of the error amplifier at high and low voltages to prevent the output voltage from exceeding preset upper and lower limits, thereby protecting the system from overvoltage or undervoltage effects.

[0060] The power conversion chip provided in this embodiment achieves a fully on-chip design for main loop frequency compensation by integrating an active capacitor circuit with high and low clamping. While ensuring system stability, it improves response speed, saves chip area and external component costs, and is suitable for power management integrated circuit application scenarios with high integration and high performance requirements.

[0061] Furthermore, based on the aforementioned active capacitor circuit with high and low clamping, this application also provides a frequency compensation method within the power management chip, see [link to relevant documentation]. Figure 3 As shown, the method mainly includes the following steps: S310 distributes the output current of the error amplifier through a shunt path formed by the first resistor and the second resistor, so that the current flowing through the first resistor charges the intrinsic capacitor connected between the first input terminal of the amplifier and ground.

[0062] In this circuit, the first resistor R1 is connected between the output terminal of EA and the first input terminal of the operational amplifier OP, and the second resistor R2 is connected between the output terminal of EA and the second input terminal of OP, forming a parallel shunt branch. Utilizing the virtual short characteristic of the operational amplifier OP, the voltages at its two input terminals are equal, thus ensuring that the voltages across R1 and R2 are the same, and the current flowing through them is inversely proportional to their resistance values. Therefore, the total output current of EA is proportionally distributed between R1 and R2, with only a portion of the current (i.e., the current flowing through R1) used to charge and discharge the intrinsic capacitor C1 connected between the first input terminal of OP and ground. Since the charging current on C1 is effectively shunted by R2, the load current requirement of the EA output node is effectively reduced, achieving capacitive amplification.

[0063] S320 uses an amplifier drive current regulating transistor to adjust the current in the feedback branch so that the intrinsic capacitor presents an equivalently increased capacitance at the output of the error amplifier.

[0064] Specifically, under the action of the operational amplifier, when the voltage across C1 changes, the required charging and discharging current is mainly provided by the OP rather than entirely from the output of EA. This allows EA to complete the same voltage change process by providing only a small signal current. This equivalent capacitance can be used to compensate for the low-frequency poles of the main loop, improve the phase margin of the system, and ensure closed-loop stability.

[0065] The S330 clamps the lower limit of the output voltage to a preset low voltage threshold through a low-level clamping circuit and clamps the upper limit of the output voltage to a preset high level through a high-level clamping circuit. The operating voltage range after clamping is determined based on the preset low voltage threshold and the preset high level.

[0066] Specifically, the low-level clamping circuit includes a pull-down structure composed of a bias current source I1, a PMOS transistor M2, and an NMOS transistor M1. When the output voltage of EA approaches zero, M2 turns on and quickly raises the voltage to above the threshold voltage Vth of M1, achieving low-level clamping. The high-level clamping circuit includes a pull-up control structure composed of a tail current source I3, a reference voltage Vh, and M3 to M5. When the output voltage of EA approaches the power supply voltage VDD, M4 turns on and pulls the voltage down to Vh. h + V GS3 Horizontal, to achieve high-level clamping.

[0067] S340 performs internal frequency compensation for the power management chip based on the equivalent increased capacitance and the clamped operating voltage range.

[0068] In summary, the frequency compensation method provided in this embodiment achieves a high-performance, fast-response fully integrated frequency compensation solution without increasing chip area. It is suitable for highly integrated DC-DC converters, SoC power modules, and other analog integrated circuit scenarios that require on-chip compensation.

[0069] In the description of this application, it should be noted that the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0070] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A high-low clamp active capacitor circuit, comprising: The application relates to a power supply power conversion chip, which comprises an input node, an active capacitor circuit, a low-bit clamping circuit and a high-bit clamping circuit. The input node is connected to the output end of an error amplifier in the power supply power conversion chip. The active capacitor circuit comprises an amplification unit, a first resistor, a second resistor and a local source capacitor; the first input end of the amplification unit is coupled to the input node through the first resistor; the second input end of the amplification unit is connected to the output end of the amplification unit; and the output end of the amplification unit is connected to the input node through the second resistor. The local source capacitor is connected between the first input end of the amplification unit and the ground; and the active capacitor circuit is used for frequency compensation of the output voltage of the error amplifier. The output end of the amplification unit is connected to the control electrode of a current regulating transistor; the first passage end of the current regulating transistor is connected to the power supply end; and the second passage end is connected between the second resistor and the second input end of the amplification unit, thereby forming a current feedback path, so that the local source capacitor is equivalent to a capacitor with increased capacitance. The first end of the low-bit clamping circuit is connected to the input node; the second end is connected to the power supply end; and the third end is grounded; and the low-bit clamping circuit is used for clamping the lower limit of the output voltage of the error amplifier to a preset low voltage threshold. The first end of the high-bit clamping circuit is connected to the input node; the second end is connected to the power supply end; the third end is connected to a reference voltage end; and the fourth end is grounded; and the high-bit clamping circuit is used for clamping the upper limit of the output voltage of the error amplifier to a preset high voltage threshold. The resistance values of the first resistor and the second resistor are in an integer multiple relationship, and both are zero-temperature-drift resistors.

2. The high-low clamp active capacitance circuit of claim 1, wherein, The local source capacitor is a zero-temperature-drift capacitor or a low-temperature-drift capacitor.

3. The high-low clamp active capacitance circuit of claim 1, wherein, The amplifier is a high-gain operational amplifier, and the common-mode input range of the high-gain operational amplifier covers the output voltage variation range of the error amplifier.

4. The high-low clamp active capacitance circuit of claim 1, wherein, The low-bit clamping circuit comprises a first bias current source, a first MOS transistor and a second MOS transistor.

5. The high-low clamp active capacitance circuit of claim 1, wherein, One end of the first bias current source is connected to the power supply end; and the other end of the first bias current source is connected to the gate of the second MOS transistor. The source of the second MOS transistor is connected to the input node; and the drain of the second MOS transistor is connected to the power supply end. The gate of the first MOS transistor is connected to the input node; the drain of the first MOS transistor is connected to the gate of the second MOS transistor; and the source of the first MOS transistor is grounded. The preset low voltage threshold is not less than the threshold voltage of the first MOS transistor.

6. The high-low clamp active capacitance circuit of claim 5, wherein, The high-bit clamping circuit comprises a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a second bias current source and a tail current source.

7. The high-low clamp active capacitance circuit of claim 1, wherein, One end of the second bias current source is connected to the source of the third MOS transistor and the gate of the fifth MOS transistor; and the other end of the second bias current source is grounded. ​ One end of the tail current source is connected with the source of the fifth MOS transistor and the source of the sixth MOS transistor respectively, and the other end of the tail current source is grounded; The gate of the third MOS transistor is connected with the input node, and the drain of the third MOS transistor is connected with the power terminal; The drain of the fifth MOS transistor is connected with the gate of the fourth MOS transistor and the drain of the eighth MOS transistor respectively; The source of the fourth MOS transistor is connected with the input node, and the drain of the fourth MOS transistor is grounded; The source of the eighth MOS transistor is connected with the power terminal, and the gate of the eighth MOS transistor is connected with the gate of the seventh MOS transistor and the drain of the sixth MOS transistor respectively; The source of the seventh MOS transistor is connected with the power terminal, the drain of the seventh MOS transistor is connected with the drain of the sixth MOS transistor, and the gate of the sixth MOS transistor is connected with the reference voltage terminal.

8. The active capacitance circuit of claim 7, wherein, A reference voltage source is further included; The reference voltage source is connected between the power terminal and the reference voltage terminal, and is used to provide a reference voltage for the high-level clamp circuit.

9. The high-low clamp active capacitance circuit of claim 8, wherein, The preset high voltage threshold is not higher than the sum of the reference voltage and the gate-source voltage of the third MOS transistor.

10. A power supply power conversion chip, characterized by, The main loop, the error amplifier, and the active capacitor circuit with high and low clamping as claimed in any one of claims 1-9 are included; The inverting input terminal of the error amplifier is connected with the feedback voltage output terminal of the main loop, the non-inverting input terminal of the error amplifier is connected with the reference voltage output terminal of the main loop, and the output terminal of the error amplifier is connected with the input node of the active capacitor circuit with high and low clamping; The error amplifier is used to amplify the error between the feedback voltage and the reference voltage of the main loop; The active capacitor circuit with high and low clamping is used to perform frequency compensation and voltage clamping on the output voltage of the error amplifier.

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