Double-sampling Sigma-Delta modulator with chopping
By using a dual-sampling Sigma-Delta modulator with chopping, the contradiction between low power consumption and high accuracy of the Sigma-Delta modulator is resolved, achieving high-precision signal detection while reducing power consumption and improving the system's noise immunity.
Patent Information
- Application Number
- CN202511451137.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-11
- Publication Date
- 2026-01-13
AI Technical Summary
Existing Sigma-Delta modulators present a trade-off between low power consumption and high precision. Traditional methods that improve precision can increase power consumption or system instability, making it difficult to meet the needs of the sensing field.
A dual-sampling Sigma-Delta modulator with chopping is adopted, including a first-stage and a second-stage integrator, a passive adder, a quantizer, and a digital-to-analog converter. The sampling rate is improved through dual sampling and chopping, 1/f noise and offset voltage are eliminated, and power consumption is reduced.
It improves the system's noise immunity, reduces power consumption, and is suitable for high-precision signal detection.
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Figure CN121333318A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and more particularly to a dual-sampling Sigma-Delta modulator with chopping. Background Technology
[0002] High-precision analog-to-digital converters (ADCs) serve as a bridge between analog and digital signals, playing a crucial role in modern sensor systems, precision measurement equipment, and medical electronic devices. Sigma-delta ADCs, with their oversampling technology and noise shaping characteristics, have become the preferred solution for high-precision sensing and detection systems, and their performance directly affects the measurement accuracy and energy efficiency of the entire system.
[0003] With the rapid development of low-power and high-precision applications such as portable medical devices and IoT sensors, traditional modulator architectures face severe challenges: on the one hand, the inherent 1 / f noise and offset voltage of analog circuits limit the improvement of the signal-to-noise ratio of the signal link; on the other hand, traditional methods of improving accuracy by oversampling or increasing the modulator order will lead to increased power consumption or system instability. This contradiction between accuracy and power consumption has prompted researchers to seek new technical paths. Summary of the Invention
[0004] This application provides a chopper-equipped dual-sampling Sigma-Delta modulator to address the problem that existing Sigma-Delta modulators cannot simultaneously meet the requirements of low power consumption and high accuracy in the sensing field. The chopper-equipped dual-sampling Sigma-Delta modulator provided in this application includes: a first-stage integrator, a second-stage integrator, a passive adder, a quantizer, and a digital-to-analog converter.
[0005] The first-stage integrator is connected to the second-stage integrator, the second-stage integrator is connected to the passive adder, the passive adder is connected to the quantizer, and the quantizer is connected to the digital-to-analog converter.
[0006] The first-stage integrator receives the original input signal and performs double sampling and chopping on the original input signal to obtain the first output signal. The original input signal is a differential signal.
[0007] The second-stage integrator receives the first output signal and samples and integrates it to obtain the second output signal.
[0008] The passive adder is used to receive the second output signal and add the second output signal to the original input signal to obtain the third output signal;
[0009] The quantizer is used to quantize the third output signal to obtain the fourth output signal;
[0010] The digital-to-analog converter is used to convert the fourth output signal from digital to analog and input the converted signal to the first-stage integrator.
[0011] Optionally, the first-stage integrator includes: a sampling module, an integration module, and a chopper module. The sampling module includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and a first capacitor. The first input terminal of the differential signal is connected to the first switch and the sixth switch, the second switch and the sixth switch are connected, the second input terminal of the differential signal is connected to the first switch and the sixth switch, the first capacitor is connected to the first switch, the second switch is connected to the first switch, the sixth switch and the seventh switch are connected, and the input terminal of the common-mode signal is connected to the seventh switch.
[0012] The integration module includes: a first switch, a second switch, a fifth switch, a second capacitor, and an operational amplifier;
[0013] The chopper module includes: a third switch and a fourth switch.
[0014] Optionally, with the sixth switch closed and the seventh switch open, the first switch is closed and the second switch is opened to obtain the first sampled integral signal;
[0015] With the sixth switch closed and the seventh switch open, the first switch is opened and the second switch is closed to obtain the second sampled integral signal.
[0016] Optionally, the digital-to-analog converter includes: a first switch, a second switch, an eighth switch, a ninth switch, a third capacitor, a first feedback voltage signal input terminal, a second feedback voltage signal input terminal, and a third feedback voltage signal input terminal;
[0017] Disconnect the first switch and close the second switch. When the quantizer output is high, the eighth switch closes and the ninth switch opens. The digital-to-analog converter feeds back a negative voltage to the first-stage integrator.
[0018] Disconnect the first switch and close the second switch. When the quantizer output is low, the ninth switch closes and the eighth switch opens, and the digital-to-analog converter feeds back a positive voltage to the first-stage integrator.
[0019] Optionally, the second-stage integrator includes: a first switch, a second switch, a fifth switch, a fourth capacitor, a fifth capacitor, and an operational amplifier;
[0020] With the first switch closed and the second switch open, the second-stage integrator is in the sampling state;
[0021] With the first switch open and the second switch closed, the second-stage integrator is in the integration state.
[0022] Optionally, the quantizer includes a comparator and an RS latch, wherein the comparator includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, a thirteenth MOSFET, a fourteenth MOSFET, a fifteenth MOSFET, a sixteenth MOSFET, a seventeenth MOSFET, and a first enable signal input terminal;
[0023] The RS latch includes: an eighteenth MOS transistor, a nineteenth MOS transistor, a second enable signal input terminal, and a third enable signal input terminal.
[0024] Optionally, the comparator is in the working state when the first enable signal is high, and in the off state when the first enable signal is low.
[0025] Optionally, when the second enable signal is low, the second-stage integrator is in integration mode and the latch input is enabled; when the second enable signal is high, the second-stage integrator is in sampling mode, the latch input is disabled, and the latch is in latching mode.
[0026] This application provides a chopper-equipped dual-sampling Sigma-Delta modulator, comprising: a first-stage integrator, a second-stage integrator, a passive adder, a quantizer, and a digital-to-analog converter (DAC). The first-stage integrator receives the original input signal and performs dual sampling and chopping on it to obtain a first output signal. The second-stage integrator receives the first output signal and performs sampling and integration on it to obtain a second output signal. The passive adder receives the second output signal and adds it to the original input signal to obtain a third output signal. The quantizer quantizes the third output signal to obtain a fourth output signal. The DAC performs digital-to-analog conversion on the fourth output signal and inputs the converted signal to the first-stage integrator. This improves the system's noise immunity, reduces power consumption, and is suitable for high-precision signal detection. Attached Figure Description
[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0028] Figure 1 A schematic diagram of a chopper-equipped dual-sampling Sigma-Delta modulator topology provided in an embodiment of this application;
[0029] Figure 2 A schematic diagram of the circuit structure of the first-stage integrator provided in the embodiments of this application;
[0030] Figure 3 This is a schematic diagram of the circuit structure of the second-stage integrator provided in an embodiment of this application;
[0031] Figure 4 A schematic diagram of the circuit structure of the quantizer provided in an embodiment of this application.
[0032] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0033] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0034] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein.
[0035] In this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.
[0036] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.
[0037] Figure 1 This is a schematic diagram of a chopper-equipped dual-sampling Sigma-Delta modulator topology provided in an embodiment of this application. Figure 1As shown, this embodiment provides a dual-sampling Sigma-Delta modulator with chopper, including: a first-stage integrator 1, a second-stage integrator 2, a passive adder 3, a quantizer 4, and a digital-to-analog converter 5; the first-stage integrator 1 and the second-stage integrator 2 are connected, the second-stage integrator 2 is connected to the passive adder 3, the passive adder 3 is connected to the quantizer 4, and the quantizer 4 is connected to the digital-to-analog converter 5.
[0038] The first-stage integrator 1 is used to receive the original input signal and perform double sampling and chopping processing on the original input signal to obtain the first output signal, wherein the original input signal is a differential signal;
[0039] The second-stage integrator 2 is used to receive the first output signal, sample and integrate the first output signal to obtain the second output signal;
[0040] The passive adder 3 is used to receive the second output signal and add the second output signal to the original input signal to obtain the third output signal;
[0041] Quantizer 4 is used to quantize the third output signal to obtain the fourth output signal;
[0042] The digital-to-analog converter 5 is used to perform digital-to-analog conversion on the fourth output signal and input the converted signal to the first-stage integrator 1.
[0043] like Figure 1 As shown, a1, b1, b2, c1, c2, and c3 are topology coefficients, including feedback coefficients, feedforward coefficients, and input coefficients, used for dynamic scaling of the system to prevent operational amplifier output saturation in the integrator from causing system instability. Each coefficient is designed to ensure that its corresponding circuit meets the performance requirements of the modulator circuit.
[0044] Figure 2 A schematic diagram of the circuit structure of the first-stage integrator provided in the embodiments of this application is shown below. Figure 2 As shown, the first-stage integrator includes: a sampling module, an integration module, and a chopper module;
[0045] The sampling module includes: a first switch S0, a second switch S1, a third switch S2, a fourth switch S3, a fifth switch S4, a sixth switch S5, a seventh switch S5', and a first capacitor C. S The first input terminal VI0 of the differential signal is connected to the first switch S0 and the sixth switch S5, and the second switch S1 is connected to the sixth switch S5. The second input terminal VI1 of the differential signal is connected to the first switch S0 and the sixth switch S5, and the first capacitor C... SThe first switch S0 is connected to the second switch S1, the sixth switch S5 is connected to the seventh switch S5', and the common-mode signal input terminal VI2 is connected to the seventh switch S5'. The first capacitor C... S For sampling capacitor;
[0046] The integration module includes: a first switch S0, a second switch S1, a fifth switch S4, and a second capacitor C. I And operational amplifier, second capacitor C I It is an integrating capacitor;
[0047] The chopper module includes: a third switch S2 and a fourth switch S3, wherein the frequency of the third switch S2 and the fourth switch S3 is 1 / 2 times the frequency of S1 / S2, and is used to eliminate 1 / f noise and offset voltage of the operational amplifier;
[0048] The first switch S0 and the second switch S1 are two-phase non-overlapping clocks, and the fifth switch S4 is the reset clock. This embodiment adopts a dual-sampling mode. The sixth switch S5 is closed, and the seventh switch S5' is open. In phase 1, the first switch S0 is closed and the second switch S1 is open. In phase 2, the first switch S0 is open and the second switch S1 is closed. Sampling and integration operations are performed in both phase 1 and phase 2, so its equivalent sampling rate is twice the clock rate, effectively improving the sampling rate. Therefore, the transfer function of the first-stage integrator is:
[0049]
[0050] in, For output signal, For input signal, For sampling capacitor, It is an integrating capacitor.
[0051] The digital-to-analog converter includes: a first switch S0, a second switch S1, an eighth switch D_FB, a ninth switch DN_FB, and a third capacitor. The system includes a first feedback voltage signal input terminal VI3, a second feedback voltage signal input terminal VI4, and a third feedback voltage signal input terminal VI5, wherein the third capacitor... For feedback capacitor;
[0052] Understandably, the ninth switch DN_FB and the eighth switch D_FB are only effective when switch S0 is open, at which time the second switch S1 is closed. When the quantizer 4 output is high, the eighth switch D_FB is closed, the ninth switch DN_FB is open, and the digital-to-analog converter 5 feeds back a negative voltage to the first-stage integrator 1; when the quantizer 4 output is low, the ninth switch DN_FB is closed, the eighth switch D_FB is open, and the digital-to-analog converter 5 feeds back a positive voltage to the first-stage integrator 1.
[0053] Figure 3 This is a schematic diagram of the circuit structure of the second-stage integrator provided in an embodiment of this application, as shown below. Figure 3 As shown, the second-stage integrator includes: a first switch S0, a second switch S1, a fifth switch S4, a fourth capacitor C1, a fifth capacitor C2, and an operational amplifier.
[0054] Wherein, VP and VN are the differential output signals of the first-stage integrator 1, VREF is the input common-mode voltage of the second-stage integrator 2, VOP and VON are the differential output signals of the second-stage integrator 2, the first switch S0 and the second switch S1 are two-phase non-overlapping clocks, and the fifth switch S4 is the reset clock. When the first switch S0 is closed and the second switch S1 is open, the second-stage integrator 2 is in the sampling state. When the first switch S0 is open and the second switch S1 is closed, the second-stage integrator 2 is in the integration state.
[0055] Figure 4 A schematic diagram of the circuit structure of the quantizer provided in the embodiments of this application is shown below. Figure 4 As shown, the quantizer includes a comparator and an RS latch. The comparator includes: a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, a twelfth MOSFET M12, a thirteenth MOSFET M13, a fourteenth MOSFET M14, a fifteenth MOSFET M15, a sixteenth MOSFET M16, a seventeenth MOSFET M17, and a first enable signal input terminal ENP0. The RS latch includes: an eighteenth MOSFET M18, a nineteenth MOSFET M19, a second enable signal input terminal ENN1, and a third enable signal input terminal ENP1.
[0056] Specifically, VP1 and VN1 are the input differential signals of quantizer 4, VOUT is the output signal of quantizer 4, and AVDD is the power supply voltage. When the first enable signal ENP0 is high, the comparator is in working state; when the first enable signal ENP0 is low, the NIBI tail current source path is closed, M13 / M15 is turned on, and when turned on, the drain terminals of M13 / M15 are pulled to the AVDD level, and the comparator function is turned off.
[0057] The second enable signal ENN1 and the third enable signal ENP1 are inverted and serve as the enable signals for the RS latch. The timing of the second enable signal ENN1 is consistent with that of the first switch S0. When the second enable signal ENN1 is low, the second-stage integrator 2 is in the integration state, the latch input enable is turned on, and the quantizer 4 outputs a high or low level response based on the integrated output level of the second-stage integrator 2. When the second enable signal ENN1 is high, the second-stage integrator 2 is in the sampling state, the latch input enable is turned off, the latch is in the latching state, and the quantizer 4 retains the last quantizer output corresponding to the integration state of the second-stage integrator 2.
[0058] This application provides a chopper-equipped dual-sampling Sigma-Delta modulator, comprising: a first-stage integrator, a second-stage integrator, a passive adder, a quantizer, and a digital-to-analog converter (DAC). The first-stage integrator receives the original input signal and performs dual sampling and chopping on it to obtain a first output signal. The second-stage integrator receives the first output signal and performs sampling and integration on it to obtain a second output signal. The passive adder receives the second output signal and adds it to the original input signal to obtain a third output signal. The quantizer quantizes the third output signal to obtain a fourth output signal. The DAC performs digital-to-analog conversion on the fourth output signal and inputs the converted signal to the first-stage integrator. This improves the system's noise immunity, reduces power consumption, and is suitable for high-precision signal detection.
[0059] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.
[0060] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. A dual-sampling Sigma-Delta modulator with chopping, characterized in that, include: First-stage integrator, second-stage integrator, passive adder, quantizer, and digital-to-analog converter; The first-stage integrator is connected to the second-stage integrator, the second-stage integrator is connected to the passive adder, the passive adder is connected to the quantizer, and the quantizer is connected to the digital-to-analog converter. The first-stage integrator receives the original input signal and performs double sampling and chopping on the original input signal to obtain the first output signal. The original input signal is a differential signal. The second-stage integrator receives the first output signal and samples and integrates it to obtain the second output signal. The passive adder is used to receive the second output signal and add the second output signal to the original input signal to obtain the third output signal; The quantizer is used to quantize the third output signal to obtain the fourth output signal; The digital-to-analog converter is used to convert the fourth output signal from digital to analog and input the converted signal to the first-stage integrator.
2. The dual-sampling Sigma-Delta modulator with chopper according to claim 1, characterized in that, The first-stage integrator includes a sampling module, an integration module, and a chopper module. The sampling module includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and a first capacitor. The first input terminal of the differential signal is connected to the first switch and the sixth switch, the second switch and the sixth switch are connected, the second input terminal of the differential signal is connected to the first switch and the sixth switch, the first capacitor is connected to the first switch, the second switch is connected to the first switch, the sixth switch and the seventh switch are connected, and the input terminal of the common-mode signal is connected to the seventh switch. The integration module includes: a first switch, a second switch, a fifth switch, a second capacitor, and an operational amplifier; The chopper module includes: a third switch and a fourth switch.
3. A dual-sampling Sigma-Delta modulator with chopping according to claim 2, characterized in that, With the sixth switch closed and the seventh switch open, the first switch is closed and the second switch is opened to obtain the first sampled integral signal. With the sixth switch closed and the seventh switch open, the first switch is opened and the second switch is closed to obtain the second sampled integral signal.
4. A dual-sampling Sigma-Delta modulator with chopping according to claim 2, characterized in that, The digital-to-analog converter includes: a first switch, a second switch, an eighth switch, a ninth switch, a third capacitor, a first feedback voltage signal input terminal, a second feedback voltage signal input terminal, and a third feedback voltage signal input terminal; Disconnect the first switch and close the second switch. When the quantizer output is high, the eighth switch closes and the ninth switch opens. The digital-to-analog converter feeds back a negative voltage to the first-stage integrator. Disconnect the first switch and close the second switch. When the quantizer output is low, the ninth switch closes and the eighth switch opens, and the digital-to-analog converter feeds back a positive voltage to the first-stage integrator.
5. A dual-sampling Sigma-Delta modulator with chopping according to claim 2, characterized in that, The second-stage integrator includes: a first switch, a second switch, a fifth switch, a fourth capacitor, a fifth capacitor, and an operational amplifier; With the first switch closed and the second switch open, the second-stage integrator is in the sampling state; With the first switch open and the second switch closed, the second-stage integrator is in the integration state.
6. A dual-sampling Sigma-Delta modulator with chopping according to claim 1, characterized in that, The quantizer includes a comparator and an RS latch. The comparator includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, a thirteenth MOSFET, a fourteenth MOSFET, a fifteenth MOSFET, a sixteenth MOSFET, a seventeenth MOSFET, and a first enable signal input terminal. The RS latch includes: an eighteenth MOS transistor, a nineteenth MOS transistor, a second enable signal input terminal, and a third enable signal input terminal.
7. A dual-sampling Sigma-Delta modulator with chopping according to claim 6, characterized in that, The comparator is in the working state when the first enable signal is high; the comparator is in the off state when the first enable signal is low.
8. A dual-sampling Sigma-Delta modulator with chopping according to claim 6, characterized in that, When the second enable signal is low, the second-stage integrator is in integration mode and the latch input enable is on; when the second enable signal is high, the second-stage integrator is in sampling mode, the latch input enable is off, and the latch is in latching mode.