Groove type power device and preparation method thereof

Abstract

The invention relates to a trench type power device and a preparation method thereof, and the method comprises the steps: providing a semiconductor substrate, and forming an epitaxial layer at one side of the semiconductor substrate; forming a plurality of first grooves in the epitaxial layer; forming a first shielding region opposite to the epitaxial layer in conductive type on the epitaxial layer on the side wall and the bottom of the first groove; forming a second shielding region on the epitaxial layer at the bottom of the first shielding region, wherein the second shielding region is connected with the bottom of the first shielding region, has the same conduction type and is spaced from the bottom of the epitaxial layer; a filling structure layer comprising a first dielectric layer and a second dielectric layer which are arranged in a stacked mode is formed in the first groove, the first dielectric layer covers the inner wall of the first groove, the second dielectric layer covers the first dielectric layer and fills the first groove, the second dielectric layer is made of a semiconductor material, and the forbidden bandwidth of the second dielectric layer is not smaller than that of the epitaxial layer; forming a second groove between two adjacent first grooves; and forming a gate structure layer in the second groove. According to the trench type power device and the preparation method thereof, the voltage withstanding level of the device is remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a trench power device and a preparation method thereof. BACKGROUND

[0002] With the increasing demand for high efficiency, high power density and high reliability power conversion in the fields of new energy vehicles, renewable energy power generation, photovoltaic systems, energy storage equipment and rail transit, traditional silicon-based power devices (such as silicon MOSFET and IGBT) have been difficult to meet the development requirements of the new generation of power electronic systems due to the limitations of voltage resistance, switching speed and temperature resistance. Silicon carbide (SiC) has become a key material for realizing high-performance power electronic devices due to its high breakdown field, high thermal conductivity and high electron saturation drift speed. SiC MOSFET based on SiC, especially trench gate structure, can effectively reduce the on-resistance and improve the power density of the device due to its higher channel mobility and higher cell density, and has become the mainstream technology in medium and high voltage application scenarios.

[0003] However, there is a structural corner at the bottom of the trench of the trench gate type SiC MOSFET, and this area is prone to form a serious electric field concentration under high voltage working conditions, so that the gate oxide layer covering it bears a much higher electric field stress than other areas, resulting in reliability problems such as gate oxide breakdown, charge trapping and interface state degradation, which become the main bottleneck restricting the long-term stable operation of such devices.

[0004] To alleviate the electric field concentration at the bottom of the trench, the prior art generally sets a deep ion implantation region with a conductivity type opposite to that of the epitaxial layer at the bottom of the trench to disperse the local electric field, thereby reducing the electric field strength of the gate oxide layer and improving the reliability of the device. The preparation process of the existing deep ion region mainly includes a deep trench etching combined with implantation scheme and a high-energy ion implantation scheme. The former requires etching a deep and wide trench structure, which is highly dependent on the precision of the etching equipment and the thick hard mask material, and the process is complex and prone to introduce problems such as rough sidewall; the latter does not need to etch a deep trench, but needs to use a high-energy implantation equipment with a power higher than 200 keV, which brings high cost, serious lattice damage and the process difficulty of subsequent high-temperature annealing, and high-temperature annealing may cause doping diffusion and interface state deterioration, affecting the yield and reliability of the device.

[0005] In summary, the existing electric field regulation scheme of the trench gate type SiC MOSFET has problems such as high equipment cost, complex process, difficulty in damage repair and insufficient reliability, which is difficult to meet the large-scale application requirements of high-performance SiC devices, and therefore a new device structure and preparation method are needed to overcome the limitations of the prior art. SUMMARY

[0006] Therefore, it is necessary to provide a trench power device and a preparation method thereof to solve the problems of complex process, high equipment requirement, serious lattice damage and limited device reliability in the prior art.

[0007] To achieve the above-mentioned purpose, in one aspect, the application provides a preparation method of a trench power device, comprising the following steps:

[0008] providing a semiconductor substrate, and forming an epitaxial layer on one side of the semiconductor substrate;

[0009] forming a plurality of first trenches arranged at intervals in the epitaxial layer;

[0010] performing ion implantation on the epitaxial layer located on the side wall and the bottom of the first trench to form a first shielding region, the conductive type of the first shielding region being opposite to the conductive type of the epitaxial layer;

[0011] performing ion implantation on the epitaxial layer located at the bottom of the first shielding region to form a second shielding region, wherein the top of the second shielding region is connected with the bottom of the first shielding region, the implantation depth of the second shielding region is greater than the implantation depth of the first shielding region, the doping concentration of the first shielding region is greater than the doping concentration of the second shielding region, the conductive type of the first shielding region and the second shielding region is the same, and the bottom of the second shielding region is arranged at intervals with the bottom of the epitaxial layer;

[0012] forming a filling structure layer in the first trench, the filling structure layer comprising a first dielectric layer and a second dielectric layer arranged in layers, the first dielectric layer covering the inner wall of the first trench, the second dielectric layer covering the first dielectric layer and filling the first trench, the second dielectric layer being a semiconductor material and the band gap of the second dielectric layer being not less than the band gap of the epitaxial layer;

[0013] forming a second trench between two adjacent first trenches;

[0014] forming a gate structure layer in the second trench.

[0015] In one embodiment, the forming of the filling structure layer in the first trench comprises:

[0016] forming a first dielectric material layer covering the inner wall of the first trench and located on the side of the epitaxial layer away from the semiconductor substrate;

[0017] forming a second dielectric material layer filling the first trench and covering the first dielectric material layer;

[0018] removing the first dielectric material layer and the second dielectric material layer from a side of the epitaxial layer away from the semiconductor substrate to obtain the first dielectric layer and the second dielectric layer, the first dielectric layer covering the first trench sidewall, and the second dielectric layer covering the first dielectric layer and filling the first trench, the first dielectric layer and the second dielectric layer forming the filling structure layer.

[0019] In one of the embodiments, the material of the epitaxial layer comprises silicon carbide; the material of the first dielectric layer comprises silicon dioxide or silicon nitride; and the material of the second dielectric layer comprises silicon carbide, gallium nitride or gallium oxide.

[0020] In one of the embodiments, forming the second trench between two adjacent first trenches comprises:

[0021] forming a patterned first photoresist layer, wherein the first photoresist layer covers the filling structure layer and exposes the epitaxial layer between two adjacent first trenches;

[0022] etching the exposed epitaxial layer between two adjacent first trenches based on the patterned first photoresist layer to obtain the second trench;

[0023] removing the patterned first photoresist layer.

[0024] In one of the embodiments, ion implantation is performed in the epitaxial layer at the bottom of the first shielding area to form a second shielding area, which comprises:

[0025] adjusting the semiconductor substrate to be inclined at a preset angle, wherein the preset angle is determined according to the crystal direction of the epitaxial layer;

[0026] forming the second shielding area in the epitaxial layer at the bottom of the first trench based on the preset angle and a preset implantation temperature, wherein the preset implantation temperature ranges from 20℃ to 30℃, and the preset angle ranges from 4 degrees to 8 degrees.

[0027] In one of the embodiments, after forming the gate structure layer in the second trench, it further comprises:

[0028] forming a first electrode layer electrically connected to the first shielding area and a second electrode layer electrically connected to the gate structure layer;

[0029] forming a third electrode layer on a side of the semiconductor substrate away from the epitaxial layer.

[0030] In one of the embodiments, the forming of the first electrode layer electrically connected with the first shielding region and the second electrode layer electrically connected with the gate structure layer comprises:

[0031] forming an interlayer dielectric layer on a side of the epitaxial layer away from the semiconductor substrate;

[0032] forming a first contact hole and a second contact hole in the interlayer dielectric layer in sequence, wherein a bottom of the first contact hole exposes the first shielding region and a bottom of the second contact hole exposes the gate structure layer;

[0033] forming an electrode material layer filling the first contact hole, the second contact hole and located on a side of the interlayer dielectric layer away from the semiconductor substrate;

[0034] performing etching treatment on the electrode material layer located on a side of the interlayer dielectric layer away from the semiconductor substrate, so as to separate the electrode material layer electrically connected with the first shielding region and the electrode material layer electrically connected with the gate structure layer, wherein the electrode material layer electrically connected with the first shielding region after etching treatment serves as the first electrode layer and the electrode material layer electrically connected with the gate structure layer after etching treatment serves as the second electrode layer.

[0035] In one of the embodiments, the forming of the third electrode layer on a side of the semiconductor substrate away from the epitaxial layer comprises:

[0036] performing thinning treatment on a side of the semiconductor substrate away from the epitaxial layer;

[0037] forming the third electrode layer on a surface of the thinned semiconductor substrate.

[0038] In one of the embodiments, before the forming of the plurality of first trenches arranged at intervals in the epitaxial layer, the method further comprises:

[0039] performing ion implantation on an upper layer of the epitaxial layer to obtain a well region, the well region having a conductive type opposite to that of the epitaxial layer, and the first trenches penetrating through the well region;

[0040] performing ion implantation on an upper layer of the well region to obtain a source region, the source region having a conductive type opposite to that of the well region, and the first electrode layer being electrically connected with the source region.

[0041] The application further provides a trench type power device prepared by the method for preparing a trench type power device according to any one of the above embodiments.

[0042] The trench type power device and the preparation method thereof form a filling structure layer in the first trench, the filling structure layer comprises a first dielectric layer and a second dielectric layer arranged in a stack, the first dielectric layer covers the inner wall of the first trench, the second dielectric layer covers the first dielectric layer and fills the first trench, the second dielectric layer is a semiconductor material, and the band gap of the second dielectric layer is not less than the band gap of the epitaxial layer. This structure can realize more fine and efficient modulation of the electric field in the trench area, especially the corner of the bottom of the gate trench. With the potential regulation characteristics of the wide band gap semiconductor material, the internal electric field of the device can present more uniform and flat distribution in the transverse and longitudinal directions, effectively suppressing the local electric field peak at the bottom of the trench, thereby significantly reducing the maximum electric field stress borne by the gate oxide layer, improving the long-term reliability and overall withstand voltage level of the gate oxide layer. At the same time, the filling structure layer has high thermal conductivity and structural stability, which can effectively reduce the thermal resistance of the trench area, improve the heat dissipation capacity of the device, increase the power density, reduce the accumulation of thermal stress during operation, and make the device have higher mechanical robustness and service life under harsh working conditions such as high temperature and high power cycling. In addition, by forming the first shielding area in the sidewall and the bottom of the first trench and the epitaxial layer, and then forming the second shielding area connected with the bottom of the first shielding area, not only the connection process of the two is simpler, but also the connection of the two is more closely connected, which can significantly improve the electric field modulation capability of the bottom of the trench, strengthen the synergistic effect between the shielding areas, and effectively reduce the interface transition and defects between different doped areas, improve the local electric field homogenization level and the stability of the conduction path. This structure can further improve the withstand voltage capability of the device, reduce the leakage current, and enhance the overall working stability. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creating any inventive labor.

[0044] Figure 1 The flow chart of the preparation method of the trench type power device provided in an embodiment;

[0045] Figure 2 The cross-sectional structure schematic diagram after forming the source region in the preparation method of the trench type power device provided in an embodiment;

[0046] Figure 3 The cross-sectional structure schematic diagram after forming the first trench in the preparation method of the trench type power device provided in an embodiment;

[0047] Figure 4A cross-sectional view of a trench power device after forming a first shielding region in a method of fabricating a trench power device according to an embodiment;

[0048] Figure 5 A cross-sectional view of a trench power device after forming a second shielding region in a method of fabricating a trench power device according to an embodiment;

[0049] Figure 6 A cross-sectional view of a trench power device after removing a first hard mask layer in a method of fabricating a trench power device according to an embodiment;

[0050] Figure 7 A cross-sectional view of a trench power device after forming a first dielectric material layer in a method of fabricating a trench power device according to an embodiment;

[0051] Figure 8 A cross-sectional view of a trench power device after forming a second dielectric material layer in a method of fabricating a trench power device according to an embodiment;

[0052] Figure 9 A cross-sectional view of a trench power device after forming a filling structure layer in a method of fabricating a trench power device according to an embodiment;

[0053] Figure 10 A cross-sectional view of a trench power device after forming a patterned first photoresist layer in a method of fabricating a trench power device according to an embodiment;

[0054] Figure 11 A cross-sectional view of a trench power device after forming a second trench in a method of fabricating a trench power device according to an embodiment;

[0055] Figure 12 A cross-sectional view of a trench power device after forming a gate oxide layer in a method of fabricating a trench power device according to an embodiment;

[0056] Figure 13 A cross-sectional view of a trench power device after forming a gate layer in a method of fabricating a trench power device according to an embodiment;

[0057] Figure 14 A cross-sectional view of a trench power device after forming an interlayer dielectric layer and a first contact hole in a method of fabricating a trench power device according to an embodiment;

[0058] Figure 15 A cross-sectional view of a trench power device after forming a first ohmic contact layer in a method of fabricating a trench power device according to an embodiment;

[0059] Figure 16 A cross-sectional view of a trench power device after forming a first electrode layer in a method of fabricating a trench power device according to an embodiment.

[0060] Reference Signs List:

[0061] 1-semiconductor substrate, 2-epitaxial layer, 21-well region, 22-source region, 23-first hard mask layer, 24-first photoresist layer, 25-interlayer dielectric layer, 251-first contact hole, 26-first ohmic contact layer, 3-first trench, 4-first shielding region, 5-second shielding region, 6-filling structure layer, 61-first dielectric layer, 611-first dielectric material layer, 62-second dielectric layer, 621-second dielectric material layer, 7-second trench, 8-gate structure layer, 81-gate oxide layer, 82-gate layer, 9-first electrode layer. DETAILED DESCRIPTION

[0062] For the purpose of facilitating the understanding of the present application, the present application will be described in greater detail below with reference to the related drawings. The embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0064] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application, and, similarly, a first aspect, concept or object discussed below could be termed a second aspect, concept or object without departing from the teachings of the present application. For example, a first dopant type can be a second dopant type, and similarly, a second dopant type can be a first dopant type, where the first and second dopant types are different dopant types, e.g., the first dopant type can be P-type and the second dopant type can be N-type, or the first dopant type can be N-type and the second dopant type can be P-type.

[0065] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0066] The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, as used herein, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0067] Referring to Figure 1 The application provides a trench power device manufacturing method, comprising the following steps:

[0068] Step S1: providing a semiconductor substrate 1, and forming an epitaxial layer 2 on one side of the semiconductor substrate 1;

[0069] Step S2: forming a plurality of first trenches 3 arranged at intervals in the epitaxial layer 2;

[0070] Step S3: performing ion implantation on the epitaxial layer 2 located at the side wall and bottom of the first trench 3 to form a first shielding region 4, wherein the conductive type of the first shielding region 4 is opposite to that of the epitaxial layer 2;

[0071] Step S4: performing ion implantation on the epitaxial layer 2 located at the bottom of the first shielding region 4 to form a second shielding region 5, wherein the top of the second shielding region 5 is connected with the bottom of the first shielding region 4, the implantation depth of the second shielding region 5 is greater than that of the first shielding region 4, the doping concentration of the first shielding region 4 is greater than that of the second shielding region 5, the conductive type of the first shielding region 4 and the second shielding region 5 is the same, and the bottom of the second shielding region 5 is arranged at intervals with the bottom of the epitaxial layer 2;

[0072] Step S5: forming a filling structure layer 6 in the first trench 3, wherein the filling structure layer 6 comprises a first dielectric layer 61 and a second dielectric layer 62 arranged in layers, the first dielectric layer 61 covers the inner wall of the first trench 3, the second dielectric layer 62 covers the first dielectric layer 61 and fills the first trench 3, the second dielectric layer 62 is a semiconductor material, and the band gap of the second dielectric layer 62 is not less than that of the epitaxial layer 2;

[0073] Step S6: forming a second trench 7 between two adjacent first trenches 3;

[0074] Step S7: forming a gate structure layer 8 in the second trench 7.

[0075] In the above example, by forming the filling structure layer 6 in the first trench 3, the filling structure layer 6 includes a first dielectric layer 61 and a second dielectric layer 62 arranged in a stack, the first dielectric layer 61 covers the inner wall of the first trench 3, and the second dielectric layer 62 covers the first dielectric layer 61 and fills the first trench 3, the second dielectric layer 62 is a semiconductor material, and the band gap width of the second dielectric layer 62 is not less than the band gap width of the epitaxial layer 2. This structure can achieve more fine and efficient modulation of the electric field in the trench area, especially the corner of the bottom of the gate trench. With the potential regulation characteristics of wide-bandgap semiconductor materials, the internal electric field of the device can be more uniform and flat in the lateral and longitudinal directions, effectively suppressing the local electric field peak at the bottom of the trench, thereby significantly reducing the maximum electric field stress on the gate oxide layer 81, improving the long-term reliability and overall withstand voltage level of the gate oxide layer 81. At the same time, the filling structure has high thermal conductivity and structural stability, which can effectively reduce the thermal resistance of the trench area, improve the heat dissipation capability of the device, increase the power density, and reduce the accumulation of thermal stress during operation. The device has higher mechanical robustness and service life under harsh working conditions such as high temperature and high power cycling. In addition, by forming the first shielding region 4 and the second shielding region 5 which is in contact with the bottom of the first shielding region 4 in the sidewall and bottom epitaxial layer 2 of the first trench 3 in sequence, the two are structurally continuous and connected. Not only does it significantly improve the electric field modulation capability of the trench bottom and strengthen the synergistic effect between the shielding regions, but it also effectively reduces the interface transition and defects between different doped regions, improves the local electric field homogenization level and the stability of the conduction path. This structure can further improve the withstand voltage capability of the device, reduce the leakage current, and enhance the overall working stability.

[0076] Specifically, referring to Figures 2-3 , steps S1 to S2 are performed to provide a semiconductor substrate 1, and an epitaxial layer 2 is formed on one side of the semiconductor substrate 1.

[0077] In one embodiment, the semiconductor substrate 1 is a silicon carbide material, such as a 4H-SiC single crystal substrate. Compared with traditional silicon substrates, silicon carbide materials have higher breakdown field strength, higher thermal conductivity, wider band gap, and superior radiation resistance, and can maintain stable electrical properties in high-temperature, high-pressure, and high-frequency environments. Therefore, using SiC as the substrate material of the device can significantly improve the withstand voltage capability, switching speed, and power density of the power device, and is particularly suitable for the preparation and application of medium and high voltage power devices.

[0078] In one embodiment, the epitaxial layer 2 is formed on the surface of the semiconductor substrate 1 by an epitaxial growth process. The epitaxial layer can be prepared by chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), or thermal plasma enhanced epitaxy, etc. suitable for silicon carbide material, and the specific process can be selected according to the equipment conditions, device performance index and cost requirements.

[0079] To ensure the stability of the device structure and the consistency of the electrical performance, the material of the epitaxial layer 2 is consistent with the semiconductor substrate 1, both of which are silicon carbide material. By matching the lattice constant through the same material system, the interface stress between the substrate and the epitaxial layer can be significantly reduced, and the interface defect density can be reduced, thereby improving the long-term reliability and performance stability of the device.

[0080] Further, the epitaxial layer 2 and the semiconductor substrate 1 have the same conductivity type, both of which have the first conductivity type, and the doping element is selected to be nitrogen (N) element, and the doping concentration is controlled in the range of 1 × 10 16 cm -3 ~1 × 10 17 cm -3 The design of the doping concentration can accurately match the structure requirements of the super junction device, and provide a basis for the formation of the super junction structure and the realization of the low on-resistance characteristics of the device.

[0081] In addition, the thickness of the epitaxial layer 2 can be designed according to the target breakdown voltage. By adjusting the thickness of the epitaxial layer, the device can withstand the required high voltage load under actual working conditions, thereby meeting the withstand voltage performance requirements in different application scenarios.

[0082] In one embodiment, as shown in FIG. 2, before forming a plurality of first trenches 3 spaced apart in the epitaxial layer 2, the method further comprises: Figure 2

[0083] The upper surface layer of the epitaxial layer 2 is ion implanted to form a well region 21. The conductivity type of the well region 21 is opposite to that of the epitaxial layer 2, the epitaxial layer 2 is of the first conductivity type, and the well region 21 has the second conductivity type. The doping element of the well region 21 is selected to be aluminum (Al), and the doping concentration is controlled in the range of 1 × 10 16 cm -3 ~1 × 10 17 cm -3 The well region 21 is a key channel forming region of the device. When a suitable bias voltage is applied to the gate, a conductive channel can be induced in the well region to provide a stable and low resistance channel for the carriers, which is an important structural unit for realizing the switching function of the device.

[0084] The upper surface layer of the well region 21 is further ion implanted to form a source region 22. The source region 22 has the same first conductivity type as the epitaxial layer 2, and the doping element is nitrogen, and the doping concentration is controlled in the range of 1 × 10​19 cm -3 ~1 21 cm -3 Highly doped source region 22 can establish low-resistance ohmic contact with the subsequently formed electrode layer, thereby effectively reducing the series resistance of the source region, improving the on-state performance of the device and reducing the conduction loss.

[0085] In one embodiment, before the ion implantation on the upper surface layer of epitaxial layer 2 to form well region 21, further comprising:

[0086] A patterned second hard mask layer (not shown) is formed on the side of epitaxial layer 2 away from semiconductor substrate 1, and the ion implantation steps for forming well region 21 and source region 22 are both masked by the second hard mask layer as a mask reference to achieve accurate definition of the implantation area.

[0087] Wherein, the patterned second hard mask layer is formed by:

[0088] A second hard mask material layer (not shown) is deposited on the side of epitaxial layer 2 away from semiconductor substrate 1, which can be silicon nitride, silicon dioxide or other mask materials with high etching resistance and high selectivity;

[0089] A patterned second photoresist layer (not shown) is formed on the second hard mask material layer. Through the photoexposure and development process, the second photoresist layer forms a pattern structure corresponding to the distribution and size of the device cell region;

[0090] The second hard mask material layer is etched with the patterned second photoresist layer as a mask to obtain a patterned second hard mask layer. The etching method of the second hard mask material layer can use dry etching or other suitable etching process to ensure accurate transfer of the mask pattern;

[0091] The patterned second photoresist layer is removed. The removal of the photoresist can be achieved by dry etching, wet etching or other appropriate methods. It should be noted that the patterned first hard mask layer only covers the terminal region of the device, while the cell region for subsequent ion implantation is completely exposed to ensure accurate control of the implantation position, size and depth of well region 21 and source region 22.

[0092] In one embodiment, after the ion implantation on the upper surface layer of well region 21 to form source region 22, further comprising:

[0093] The second hard mask layer is removed. The removal of the second hard mask layer can be performed by wet etching or other etching methods suitable for the mask material to avoid affecting the subsequent etching process of the first trench 3. During the removal process, the hard mask material should be completely removed to avoid any mask residue, and the etching damage or surface defects to the surface of the source region 22 should be prevented to ensure the interface quality and device reliability of the subsequent process.

[0094] It should be noted that the first conductivity type and the second conductivity type in the embodiment are opposite conductivity types, i.e., when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type is N-type. In the embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0095] In one embodiment, as shown in FIG. 2, a plurality of first trenches 3 are formed in the epitaxial layer 2, including: Figure 3

[0096] A patterned first hard mask layer 23 is formed on one side of the epitaxial layer 2. The first hard mask layer 23 is used to define the position and size of the first trench 3 and provide high selectivity etching protection in the subsequent deep trench etching process.

[0097] The formation of the patterned first hard mask layer 23 includes:

[0098] A first hard mask material layer is deposited on one side of the epitaxial layer 2. The material of the first hard mask material layer includes silicon nitride, silicon dioxide or other materials with high etching selectivity and good etching resistance to ensure that the pattern of the first trench 3 can be accurately transferred to the epitaxial layer 2 during the etching process.

[0099] A third photoresist layer (not shown) is formed on the first hard mask material layer, and is patterned by photolithography exposure and development process. The obtained pattern is consistent with the layout and size of the first trench 3 to be formed.

[0100] The first hard mask material layer is etched to form a patterned first hard mask layer 23 using the patterned third photoresist layer as a mask. The etching method can be dry etching or other suitable etching process to ensure accurate transfer of the mask pattern.

[0101] The patterned second photoresist layer is removed by dry etching, wet etching or a combination of both to avoid the influence of photoresist residue on the subsequent etching process.

[0102] ​Based on the first patterned hard mask layer 23, the epitaxial layer 2 is etched to form the first trench 3. The epitaxial layer 2 can be etched by dry etching or other appropriate methods. The first trench 3 formed by etching does not penetrate the epitaxial layer 2 in depth, but at least penetrates the well region 21, so that the bottom of the trench is spaced apart from the bottom of the epitaxial layer 2. It should be noted that the depth of the first trench 3 can be flexibly determined according to the device structure design and the electric field regulation requirement, which is not specifically limited in the embodiment.

[0103] Specifically, referring to Figure 4 , step S3 is performed to perform ion implantation in the epitaxial layer 2 located on the sidewall and bottom of the first trench 3 to form the first shielding region 4. The conductive type of the first shielding region 4 is the same as that of the epitaxial layer 2.

[0104] In one embodiment, as shown in Figure 4 , the ion implantation in the epitaxial layer 2 located on the sidewall and bottom of the first trench 3 to form the first shielding region 4 includes:

[0105] The semiconductor substrate 1 is tilted to perform high-temperature ion implantation in the epitaxial layer 2 located on the sidewall and bottom of the first trench 3. The tilt angle of the semiconductor substrate 1 is determined according to the opening depth, opening size of the first trench 3 and the thickness of the second hard mask layer, to ensure that the ion implantation can accurately reach the sidewall and bottom region of the first trench 3. The specific value of the tilt angle can be flexibly adjusted according to the actual structure parameters, which is not limited herein, and the tilting of the semiconductor substrate 1 is realized by adjusting the carrying table carrying the semiconductor substrate 1. The first shielding region 4 has a second conductive type, the doping element of the first shielding region 4 is aluminum element, and the doping concentration ranges from 1x10 20 cm -3 ~1x10 21 cm -3 , which is opposite to the conductive type of the epitaxial layer 2, and has a very high doping concentration, which can be used as a connection area for forming ohmic contact with the source metal layer in the subsequent process, to ensure low-resistance conduction between the electrode and the source region 22. The temperature range for high-temperature ion implantation is 450°C-550°C, which can be determined according to the actual process conditions such as implantation depth requirement and lattice damage control target.

[0106] Specifically, referring to Figures 5-6 , step S4 is performed to perform ion implantation in the epitaxial layer located at the bottom of the first shielding region 4 to form the second shielding region 5. The top of the second shielding region 5 is connected to the bottom of the first shielding region 4, the implantation depth of the second shielding region 5 is greater than that of the first shielding region, the doping concentration of the first shielding region 4 is less than that of the second shielding region 5, and the conductive types of the first shielding region 4 and the second shielding region 5 are the same. The bottom of the second shielding region 5 is spaced apart from the bottom of the epitaxial layer 2.

[0107] In one embodiment, as shown in Fig. 1, ion implantation is performed in the epitaxial layer 2 at the bottom of the first shielding region 4 to form the second shielding region 5, including: Figure 5

[0108] The semiconductor substrate 1 is adjusted to be inclined at a preset angle, wherein the preset angle is set according to the crystal direction of the epitaxial layer 2.

[0109] Based on the preset angle, the second shielding region 5 is formed in the epitaxial layer 2 at the bottom of the first trench 3 by using a preset implantation temperature, the preset implantation temperature ranges from 20℃ to 30℃, and the preset angle ranges from 4 degrees to 8 degrees.

[0110] Specifically, the ion implantation direction is aligned with the lattice channel of the crystal direction of the epitaxial layer 2, for example, the (0001) surface of 4H-SiC is selected to be cut at a specific direction by 4 degrees, which can trigger significant channeling effect, the scattering resistance of ions moving along the channel between lattice atoms is greatly reduced, so that deeper penetration depth can be achieved at lower implantation energy. This angle design can not only ensure the effective triggering of channeling effect, but also reduce the increase of lattice defects caused by excessive crystal direction deviation. Both implantation depth and lattice integrity are considered, and the semiconductor substrate 1 is adjusted to be inclined at a preset angle by adjusting the carrier table carrying the semiconductor substrate 1, so that the semiconductor substrate 1 placed on the carrier table is inclined at a preset angle.

[0111] The second shielding region 5 has a second conductivity type, and the doping element of the second shielding region 5 is aluminum element, and the doping concentration ranges from 1×10 17 cm -3 ~1×10 19 cm -3 By high concentration of doping with opposite conductivity type to the epitaxial layer 2, the electric field at the bottom of the first trench 3 can be effectively compensated to play a shielding role. The preset implantation temperature ranges from 20℃ to 30℃, i.e. the preset implantation temperature is room temperature. Therefore, by adjusting the semiconductor substrate 1 to be inclined at a preset angle to trigger channeling effect, a deeper second shielding region 5 can be formed without relying on high-energy implanters, which significantly reduces the requirements and manufacturing costs of the implantation equipment.

[0112] The implantation depth of the second shielding region 5 needs to be controlled within a certain range, and the bottom of the second shielding region 5 is kept apart from the bottom of the epitaxial layer 2 (i.e. not penetrating through the epitaxial layer 2) to avoid damaging the voltage-resistant structure at the bottom of the epitaxial layer 2, while ensuring effective shielding of the electric field at the corner region of the bottom of the first trench 3 to protect the gate oxide layer 81 from excessive electric field stress.

[0113] ​By first forming a first shielding region 4 and then a second shielding region 5, and by connecting the bottom of the first shielding region 4 with the top of the second shielding region 5, the connection process between the two is simplified, and a better structural continuity can be achieved. On the one hand, this can significantly improve the electric field modulation capability at the bottom of the trench and strengthen the synergistic effect of the shielding regions. On the other hand, it can effectively reduce the interface transition and defects of different doped regions, improve the local electric field homogenization level and the stability of the conductive path, so that the structure can further improve the device's withstand voltage capability, reduce leakage current, and enhance the overall working stability.

[0114] It should be noted that the ion implantation process of both the first shielding region 4 and the second shielding region 5 uses the previously formed patterned first hard mask layer 23 as a mask, without the need to prepare a new mask structure, which can simplify the process and reduce manufacturing costs.

[0115] In one embodiment, such as Figure 6 As shown, after ion implantation is performed in the epitaxial layer 2 located at the bottom of the first shielding region 4 to form the second shielding region 5, the process further includes:

[0116] The first hard mask layer 23 is removed. The first hard mask layer 23 can be removed by wet etching or other etching methods suitable for the mask material, so as to avoid affecting the subsequent etching process of the first trench 3.

[0117] In one embodiment, after ion implantation is performed on the epitaxial layer 2 located at the bottom of the first shielding region 4 to form the second shielding region 5, the method further includes:

[0118] High-temperature ion activation is performed. This mainly involves high-temperature ion activation of the epitaxial layer 2, the first shielding region 4, the second shielding region 5, the well region 21, and the source region 22, which are doped with ions, to activate the doped ions therein.

[0119] The high-temperature ion activation includes forming a protective layer (not shown) covering the exposed surface of the epitaxial layer 2. The protective layer includes a carbon film, which has excellent high-temperature resistance and chemical stability. It can effectively protect the surface of the epitaxial layer 2 and the trench structure from atmospheric corrosion or physical damage during the high-temperature activation process, while inhibiting the sublimation and decomposition of the silicon carbide material surface.

[0120] Under the protective layer, a high-temperature annealing process is performed to activate the doped ions. The high-temperature annealing temperature is 1750℃ and the time is 30 minutes. This allows the implanted ions to gain sufficient energy to escape from the interstitial positions of the crystal lattice and enter the substitutional positions of the silicon carbide crystal lattice, thereby achieving electroactive activation. This ensures that each doped region has the designed conductivity and carrier concentration. The annealing process is carried out in an argon atmosphere, which serves as an inert protective gas to prevent the device surface from reacting with oxygen, water vapor, etc. at high temperatures, and to reduce impurity contamination.

[0121] Through the high-temperature activation process, the doped region formed by the previous ion implantation is converted from a non-active state to an electrically active state, ensuring that the well region 21 can effectively form a channel, the source region 22 can achieve a low-resistance ohmic contact, and the first shielding region 4 and the second shielding region 5 can play an electric field compensation function, thereby laying a foundation for the subsequent electrical performance of the device.

[0122] In one embodiment, after the high-temperature ion activation, a sacrificial oxide layer (not shown) is formed on the exposed surface of the epitaxial layer 2 away from the semiconductor substrate 1. The method for forming the sacrificial oxide layer includes thermal oxidation or other suitable methods. The thickness of the sacrificial oxide layer can be controlled within a range of tens to hundreds of angstroms according to the degree of surface damage. The sacrificial oxide layer serves to adsorb and wrap surface defects generated during the high-temperature activation and trench etching processes, thereby reducing the interface state density and providing a high-quality substrate surface for the subsequent formation of the filling structure layer 6.

[0123] The sacrificial oxide layer is removed. The method for removing the sacrificial oxide layer includes wet etching or other suitable methods.

[0124] Specifically, referring to Figures 7-9 , step S5 is performed to form the filling structure layer 6 in the first trench 3. The filling structure layer 6 includes a first dielectric layer 61 and a second dielectric layer 62 stacked together. The first dielectric layer 61 covers the inner wall of the first trench 3, and the second dielectric layer 62 covers the first dielectric layer 61 and fills the first trench 3. The second dielectric layer 62 is a semiconductor material, and the band gap width of the second dielectric layer 62 is not less than the band gap width of the epitaxial layer 2.

[0125] In one embodiment, as shown in Figures 7-9 , the filling structure layer 6 is formed in the first trench 3, including:

[0126] forming a first dielectric material layer 611 covering the inner wall of the first trench 3 and located on the side of the epitaxial layer 2 away from the semiconductor substrate 1. The method for forming the first dielectric material layer 611 includes chemical vapor deposition, thermal oxidation, or other suitable methods.

[0127] forming a second dielectric material layer 621 filling the first trench 3 and covering the first dielectric material layer 611. The method for forming the second dielectric material layer 621 includes chemical vapor deposition, thermal oxidation, or other suitable methods.

[0128] The first dielectric material layer 611 and the second dielectric material layer 621 located on the side of the epitaxial layer 2 away from the semiconductor substrate 1 are removed to obtain a first dielectric layer 61 and a second dielectric layer 62, the first dielectric layer 61 covers the side wall of the first trench 3, the second dielectric layer 62 covers the first dielectric layer 61 and fills the first trench 3, and the first dielectric layer 61 and the second dielectric layer 62 form a filling structure layer 6. The method for removing the first dielectric material layer 611 and the second dielectric material layer 621 located on the side of the epitaxial layer 2 away from the semiconductor substrate 1 includes chemical mechanical polishing, wet etching, dry etching or other suitable methods.

[0129] In one embodiment, the material of the first dielectric layer 61 includes silicon dioxide, silicon nitride or other suitable materials; and the material of the second dielectric layer 62 includes silicon carbide, gallium nitride, gallium oxide, diamond or other suitable semiconductor materials with a wide band gap.

[0130] By forming the filling structure layer 6 in the first trench 3, the filling structure layer 6 includes the first dielectric layer 61 and the second dielectric layer 62 stacked, the first dielectric layer 61 covers the inner wall of the first trench 3, the second dielectric layer 62 covers the first dielectric layer 61 and fills the first trench 3, the second dielectric layer 62 is a semiconductor material and the band gap of the second dielectric layer 62 is not less than the band gap of the epitaxial layer 2. This structure can achieve more fine and efficient modulation of the electric field in the trench area, especially the corner of the bottom of the second trench 7. With the potential regulation characteristics of the wide-bandgap semiconductor material, the internal electric field of the device can present more uniform and flat distribution in the transverse and longitudinal directions, effectively suppressing the local electric field peak at the bottom of the trench, thereby significantly reducing the maximum electric field stress borne by the gate oxide layer, improving the long-term reliability and overall withstand voltage level of the gate oxide layer. At the same time, the filling structure layer 6 has high thermal conductivity and structural stability, which can effectively reduce the thermal resistance of the trench area, improve the heat dissipation capacity of the device, increase the power density, reduce the accumulation of thermal stress during operation, and make the device have higher mechanical robustness and service life under harsh working conditions such as high temperature and high power cycling.

[0131] Specifically, when the material of the second medium layer 62 is silicon carbide, the material of the epitaxial layer 2 is consistent, which can maximize the reduction of the lattice mismatch and the interface energy between the two, reduce the interface defect density, and further improve the thermal shock resistance and structural integrity of the filling structure layer 6 by virtue of the excellent thermal stability and mechanical strength of silicon carbide, thereby avoiding the problem of interlayer peeling or cracking under high temperature working conditions; when the material of the second medium layer 62 is gallium nitride, its wider band gap and higher breakdown field strength can further strengthen the electric field shielding effect of the trench area, especially suitable for high-voltage and high-frequency application scenarios, and the good carrier mobility of gallium nitride can assist in optimizing the charge transport efficiency of the device conduction path, balancing the switching speed and on-state loss of the device while improving the withstand voltage performance; when the second medium layer 62 is gallium oxide, its band gap is much wider than that of the epitaxial layer 2, which can form a strong electric field constraint and shielding effect on the trench area, greatly weakening the electric field concentration phenomenon at the corners of the trench, especially suitable for extra-high voltage power transmission and distribution, high-voltage distribution, and other high-voltage scenarios; when the material of the second medium layer 62 is diamond, it can achieve the ultimate shielding of the electric field in the trench area, completely solve the problem of electric field distortion and leakage current in high-voltage scenarios, and meet the requirements of extra-high voltage and extreme high-frequency devices. At the same time, diamond has super-high thermal conductivity, which is several times that of silicon carbide, can quickly conduct the heat generated in the trench area due to charge transport, avoid device performance degradation caused by local overheating, greatly improve the heat attenuation resistance of the filling structure layer 6, and the strong mechanical strength of diamond can significantly enhance the wear resistance and impact resistance of the filling structure layer 6, effectively resist mechanical stress during device preparation and working process, and prevent microcracks between layers.

[0132] Specifically, please refer to Figures 10-11 , execute step S6 to form a second trench 7 between the adjacent two first trenches 3.

[0133] In one embodiment, as shown in Figures 10-11 , forming a second trench 7 between the adjacent two first trenches 3 includes:

[0134] forming a patterned first photoresist layer 24, wherein the first photoresist layer 24 covers the filling structure layer 6 and exposes the epitaxial layer 2 between the adjacent two first trenches 3; the patterned first photoresist layer 24 is formed by photolithography exposure and development process, and its pattern is consistent with the distribution and size of the second trench 7 to be formed;

[0135] based on the patterned first photoresist layer 24, etching the exposed epitaxial layer 2 between the adjacent two first trenches 3 to obtain the second trench 7, wherein the method of etching the epitaxial layer 2 includes dry etching or other suitable methods;

[0136] The patterned first photoresist layer 24 is removed, and the method for removing the first photoresist layer 24 includes dry etching, wet etching or other suitable method or a combination of both, so as to avoid the residual photoresist affecting the subsequent process.

[0137] Specifically, referring to Figures 12-16 , step S7 is performed to form a gate structure layer 8 in the second trench 7.

[0138] In one embodiment, as shown in Figures 12-13 , the formation of the gate structure layer 8 in the second trench 7 includes the following steps:

[0139] A gate oxide layer 81 covering the sidewall of the second trench 7 and the side of the epitaxial layer 2 away from the semiconductor substrate 1 is formed; the material of the gate oxide layer 81 includes silicon dioxide or other suitable material; the method for forming the gate oxide layer 81 includes thermal oxidation, chemical vapor deposition or other suitable method, so as to ensure that the gate oxide layer 81 is uniform in thickness and defect-free.

[0140] A gate layer 82 covering the gate oxide layer 81 located on the sidewall of the second trench 7 and filling the second trench 7 is formed; the material of the gate layer 82 includes polysilicon or other suitable material, and the method for forming the gate layer 82 includes low-pressure chemical vapor deposition or other suitable method, wherein the deposition temperature for forming the gate layer 82 by low-pressure chemical vapor deposition is 620°C, the reaction gas is silane, and after the deposition is completed, the gate pattern is defined by the photoexposure and development process, and then the dry etching is used to remove the excess gate material to obtain the target gate layer 82.

[0141] The gate oxide layer 81 located on the side of the epitaxial layer 2 away from the semiconductor substrate 1 is removed.

[0142] In one embodiment, as shown in Figures 14-16 , after the formation of the gate structure layer 8 in the second trench 7, the following steps are further included:

[0143] A first electrode layer 9 electrically connected to the first shielding area 4 and a second electrode layer electrically connected to the gate structure layer 8 are formed.

[0144] A third electrode layer is formed on the side of the semiconductor substrate 1 away from the epitaxial layer 2.

[0145] In one embodiment, the formation of the first electrode layer 9 electrically connected to the first shielding area 4 and the second electrode layer electrically connected to the gate structure layer 8 includes the following steps:

[0146] An interlayer dielectric layer 25 is formed on the side of the epitaxial layer 2 away from the semiconductor substrate 1; the method for forming the interlayer dielectric layer 25 includes chemical vapor deposition or other suitable method, wherein the interlayer dielectric layer 25 has a double-layer structure, the lower layer is silicon dioxide, and the upper layer is phosphorus-doped silicon dioxide or boron- and phosphorus-doped silicon dioxide.

[0147] forming a first contact hole 251 and a second contact hole (not shown) in the interlayer dielectric layer 25 in sequence, wherein the bottom of the first contact hole 251 exposes the first shielding region 4, and the bottom of the second contact hole exposes the gate structure layer 8;

[0148] forming a first contact hole 251 and a second contact hole in the interlayer dielectric layer 25 in sequence, comprising:

[0149] reflowing the interlayer dielectric layer 25; wherein the temperature of the reflowing is 950°C, the time is 60 minutes, and the reflowing is performed in a nitrogen atmosphere; the high-temperature reflowing can eliminate surface unevenness, and provide a flat process surface for subsequent contact hole etching and metal wiring;

[0150] forming a patterned fourth photoresist layer (not shown) on the side of the interlayer dielectric layer 25 away from the semiconductor substrate 1;

[0151] based on the patterned fourth photoresist layer, sequentially etching the interlayer dielectric layer 25 to obtain the first contact hole 251 and the second contact hole, wherein the method of etching the interlayer dielectric layer 25 includes dry etching or other suitable methods;

[0152] In addition, before forming the first contact hole 251 in the interlayer dielectric layer 25, further comprising: forming a first ohmic contact layer 26 on the side of the first shielding region 4 and the source region 22 away from the semiconductor substrate 1;

[0153] forming a first ohmic contact layer 26 on the side of the first shielding region 4 and the source region 22 away from the semiconductor substrate 1, comprising:

[0154] forming a first metal layer on the side of the first shielding region 4 and the source region 22 away from the semiconductor substrate 1; the material of the first metal layer includes nickel or other suitable metal materials, and the method of forming the first metal layer includes physical vapor deposition or other suitable methods;

[0155] performing a first annealing treatment on the metal layer, the silicon element in the epitaxial layer 2 reacts with the first metal layer at high temperature to form a metal silicide, the temperature of the first annealing treatment is 750°C, the annealing time is 5 minutes, and the first annealing treatment is performed in a nitrogen atmosphere;

[0156] removing the unreacted first metal layer by wet etching;

[0157] performing a second annealing treatment on the metal silicide to form the first ohmic contact layer 26, the temperature of the second annealing treatment is 950°C, the annealing time is 3 minutes, and the second annealing treatment is performed in a nitrogen atmosphere;

[0158] forming an electrode material layer on the side of the interlayer dielectric layer 25 away from the semiconductor substrate 1, the electrode material layer comprising at least one of titanium, titanium nitride, and aluminum, and the electrode material layer being formed by physical vapor deposition or other suitable method;

[0159] performing etching on the electrode material layer on the side of the interlayer dielectric layer 25 away from the semiconductor substrate 1 to separate the electrode material layer electrically connected to the second shielding region 5 from the electrode material layer electrically connected to the gate structure layer 8, wherein the electrode material layer electrically connected to the first shielding region 4 after the etching is the first electrode layer 9, and the electrode material layer electrically connected to the gate structure layer 8 after the etching is the second electrode layer;

[0160] performing etching on the electrode material layer on the side of the interlayer dielectric layer 25 away from the semiconductor substrate 1, including:

[0161] forming a patterned fifth photoresist layer (not shown) on the side of the electrode material layer away from the semiconductor substrate 1;

[0162] performing etching on the electrode material layer based on the patterned fifth photoresist layer, wherein the etching on the electrode material layer is performed by dry etching or other suitable method;

[0163] It should be noted that at this time, the first electrode layer 9 is also electrically connected to the source region 22, i.e., the first electrode layer 9 is electrically connected to both the source region 22 and the first shielding region 4, which simplifies the process, realizes the equipotential of the source region 22 and the first shielding region 4, strengthens the electric field modulation synergy effect, further reduces the leakage current and improves the voltage stability, and also reduces the number of contact holes and metal wires, shortens the process cycle, reduces the process cost and device failure risk.

[0164] In one embodiment, after forming the first electrode layer 9 electrically connected to the first shielding region 4 and the second electrode layer electrically connected to the gate structure layer 8, the method further includes:

[0165] A passivation layer (not shown) is formed to cover the first electrode layer 9 and the second electrode layer, and the passivation layer is a multi-layer structure to avoid oxidation of the electrode layers. For example, the passivation layer includes an insulating passivation layer and a flexible passivation layer which are sequentially stacked. The material of the insulating passivation layer includes silicon nitride or other suitable material, and the method of forming the insulating passivation layer includes plasma chemical vapor deposition or other suitable method. It should be noted that, in order to avoid affecting the functions of other areas of the trench power device, the insulating passivation layer only covers the areas of the first electrode layer 9 and the second electrode layer. Therefore, the step of dry etching the insulating passivation layer based on a patterned photoresist layer is further included. The material of the flexible passivation layer includes polyimide or other suitable material, and the flexible passivation layer is formed by processes such as gluing, exposure, development, and curing.

[0166] In one embodiment, a third electrode layer is formed on the side of the semiconductor substrate 1 away from the epitaxial layer 2, including:

[0167] The side of the semiconductor substrate 1 away from the epitaxial layer 2 is thinned. The method of thinning the semiconductor substrate 1 includes mechanical grinding, chemical mechanical polishing, dry etching, or other suitable method, to reduce the on-resistance, improve the device heat dissipation performance and power density.

[0168] A third electrode layer (not shown) is formed on the surface of the thinned semiconductor substrate 1, wherein the material of the third electrode layer includes at least one of titanium, titanium nitride, aluminum, gold, and silver, and the method of forming the third electrode layer includes metal evaporation or other suitable method.

[0169] Before forming the third electrode layer on the surface of the thinned semiconductor substrate 1, further including:

[0170] A second ohmic contact layer is formed on the surface of the thinned semiconductor substrate 1, and the method of forming the second ohmic contact layer includes:

[0171] A second metal layer is formed on the surface of the thinned semiconductor substrate 1, and the material of the second metal layer includes nickel or other suitable metal material, and the method of forming the second metal layer includes physical vapor deposition or other suitable method.

[0172] The second metal layer is subjected to laser annealing.

[0173] In one embodiment, the application also provides a trench power device prepared by the method for preparing a trench power device as described above, comprising: a semiconductor substrate 1, an epitaxial layer 2, a first trench 3, a first shielding region 4, a second shielding region 5, a filling structure layer 6, a second trench 7, and a gate structure layer 8, wherein the epitaxial layer 2 is located on one side of the semiconductor substrate 1; the first trench 3 comprises a plurality of trenches and is arranged at intervals, and the first trench 3 is located in the epitaxial layer 2; the first shielding region 4 is located in the epitaxial layer 2 on the side wall and the bottom of the first trench 3, and the conductivity type of the first shielding region 4 is opposite to that of the epitaxial layer 2; the second shielding region 5 is located in the epitaxial layer 2 on the bottom of the first shielding region 4, the top of the second shielding region 5 is connected with the bottom of the first shielding region 4, the implantation depth of the second shielding region 5 is greater than that of the first shielding region 4, the doping concentration of the first shielding region 4 is greater than that of the second shielding region 5, and the conductivity types of the first shielding region 4 and the second shielding region 5 are the same, and the bottom of the second shielding region 5 is arranged at intervals with the bottom of the epitaxial layer 2; the filling structure layer 6 is located in the first trench 3, the filling structure layer 6 comprises a first dielectric layer 61 and a second dielectric layer 62 which are arranged in layers, the first dielectric layer 61 covers the inner wall of the first trench 3, the second dielectric layer 62 covers the first dielectric layer 61 and fills the first trench 3, the second dielectric layer 62 is a semiconductor material, and the band gap of the second dielectric layer 62 is not less than that of the epitaxial layer 2; the second trench 7 is located between two adjacent first trenches 3; and the gate structure layer 8 is located in the second trench 7.

[0174] In one embodiment, the trench power device further comprises a well region 21 and a source region 22, wherein the well region 21 is located on the upper layer of the epitaxial layer 2, and the source region 22 is located on the upper layer of the well region 21.

[0175] In one embodiment, the trench power device further comprises a first electrode layer 9, a second electrode layer, an interlayer dielectric layer 25, a first ohmic contact layer 26, a passivation layer, a second ohmic contact layer, and a third electrode layer, wherein the first electrode layer 9 is electrically connected with the first shielding region 4, the second electrode layer is electrically connected with the gate structure layer 8, the interlayer dielectric layer 25 is located on the side of the epitaxial layer 2 away from the semiconductor substrate 1, the interlayer dielectric layer 25 has a first contact hole 251 and a second contact hole therein, the bottom of the first contact hole 251 exposes the second shielding region 5, the bottom of the second contact hole exposes the gate structure layer 8, the first electrode layer 9 is filled in the first contact hole 251, the second electrode layer is filled in the second contact hole, the first ohmic contact layer 26 is located on the side of the first shielding region 4 and the source region 22 away from the semiconductor substrate 1 and in the first contact hole 251, the passivation layer covers the first electrode layer 9 and the second electrode layer, and the second ohmic contact layer and the third electrode layer are arranged in layers on the side of the semiconductor substrate 1 away from the epitaxial layer 2.

[0176] It should be understood that, although Figure 1The steps in the flowcharts of the above embodiments are displayed in sequence according to the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of the steps is not strictly limited in sequence, and the steps can be executed in other sequences. Moreover, Figure 1 At least a part of the steps in the flowcharts of the above embodiments can include a plurality of steps or a plurality of stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of the steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least a part of other steps or steps or stages in other steps.

[0177] In the description of the present specification, the description referring to the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0178] The technical features of the above embodiments can be combined in any manner. In order to make the description concise, not all possible combinations of the technical features of the above embodiments are described, but as long as the combinations of the technical features do not contradict, they should be considered within the scope of the present application.

[0179] The above embodiments only express several implementation manners of the present application, and the description is specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be noted that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A method for fabricating a trench-type power device, characterized in that, Includes the following steps: A semiconductor substrate is provided, and an epitaxial layer is formed on one side of the semiconductor substrate; Multiple spaced first trenches are formed within the epitaxial layer; Ion implantation is performed on the epitaxial layer located on the sidewalls and bottom of the first trench to form a first shielding region, the conductivity type of the first shielding region being opposite to that of the epitaxial layer; Ion implantation is performed in the epitaxial layer located at the bottom of the first shielding region to form a second shielding region, wherein the top of the second shielding region is connected to the bottom of the first shielding region, the implantation depth of the second shielding region is greater than the implantation depth of the first shielding region, the doping concentration of the first shielding region is greater than the doping concentration of the second shielding region, and the first shielding region and the second shielding region have the same conductivity type, and the bottom of the second shielding region is spaced apart from the bottom of the epitaxial layer. A filling structure layer is formed in the first trench. The filling structure layer includes a first dielectric layer and a second dielectric layer stacked together. The first dielectric layer covers the inner wall of the first trench, and the second dielectric layer covers the first dielectric layer and fills the first trench. The second dielectric layer is a semiconductor material and the band gap of the second dielectric layer is not less than the band gap of the epitaxial layer. A second trench is formed between two adjacent first trenches; A gate structure layer is formed within the second trench.

2. The method for fabricating a trench-type power device according to claim 1, characterized in that, The formation of a filling structure layer within the first trench includes: A first dielectric material layer is formed to cover the inner wall of the first trench and to be located on the side of the epitaxial layer away from the semiconductor substrate; A second dielectric material layer is formed to fill the first trench and cover the first dielectric material layer; The first dielectric material layer and the second dielectric material layer located on the side of the epitaxial layer away from the semiconductor substrate are removed to obtain the first dielectric layer and the second dielectric layer. The first dielectric layer covers the sidewall of the first trench, and the second dielectric layer covers the first dielectric layer and fills the first trench. The first dielectric layer and the second dielectric layer form the filling structure layer.

3. The method for fabricating a trench-type power device according to claim 2, characterized in that, The epitaxial layer is made of silicon carbide; the first dielectric layer is made of silicon dioxide and silicon nitride; the second dielectric layer is made of silicon carbide, gallium nitride, gallium oxide, and diamond.

4. The method for fabricating a trench-type power device according to claim 1, characterized in that, The process of forming a second trench between two adjacent first trenches includes: A patterned first photoresist layer is formed, wherein the first photoresist layer masks the filling structure layer and exposes the epitaxial layer located between two adjacent first trenches; Based on the patterned first photoresist layer, the epitaxial layer exposed between two adjacent first trenches is etched to obtain the second trench; Remove the patterned first photoresist layer.

5. The method for fabricating a trench-type power device according to claim 1, characterized in that, The step of performing ion implantation in the epitaxial layer located at the bottom of the first shielding region to form a second shielding region includes: The semiconductor substrate is adjusted to tilt at a preset angle, wherein the preset angle is set according to the crystal orientation of the epitaxial layer; Based on the preset angle and using a preset injection temperature, a second shielding area is formed in the epitaxial layer at the bottom of the first trench. The preset injection temperature ranges from 20°C to 30°C, and the preset angle ranges from 4°C to 8°C.

6. The method for fabricating a trench-type power device according to claim 1, characterized in that, After forming the gate structure layer in the second trench, the method further includes: A first electrode layer electrically connected to the first shielding region and a second electrode layer electrically connected to the gate structure layer are formed; A third electrode layer is formed on the side of the semiconductor substrate away from the epitaxial layer.

7. The method for fabricating a trench-type power device according to claim 6, characterized in that, The formation of a first electrode layer electrically connected to the first shielding region and a second electrode layer electrically connected to the gate structure layer includes: An interlayer dielectric layer is formed on the side of the epitaxial layer away from the semiconductor substrate; A first contact hole and a second contact hole are sequentially formed in the interlayer dielectric layer, wherein the bottom of the first contact hole exposes the first shielding area, and the bottom of the second contact hole exposes the gate structure layer; An electrode material layer is formed that fills the first contact hole and the second contact hole and is located on the side of the interlayer dielectric layer away from the semiconductor substrate; The electrode material layer located on the side of the interlayer dielectric layer away from the semiconductor substrate is etched to separate the electrode material layer electrically connected to the first shielding region and the electrode material layer electrically connected to the gate structure layer. The etched electrode material layer electrically connected to the first shielding region serves as the first electrode layer, and the electrode material layer electrically connected to the gate structure layer serves as the second electrode layer.

8. The method for fabricating a trench-type power device according to claim 6, characterized in that, The formation of a third electrode layer on the side of the semiconductor substrate away from the epitaxial layer includes: The side of the semiconductor substrate away from the epitaxial layer is thinned. The third electrode layer is formed on the surface of the thinned semiconductor substrate.

9. The method for fabricating a trench-type power device according to claim 6, characterized in that, Before forming a plurality of spaced-apart first trenches within the epitaxial layer, the method further includes: Ion implantation is performed on the upper surface of the epitaxial layer to obtain a well region, wherein the conductivity type of the well region is opposite to that of the epitaxial layer, and the first trench penetrates the well region. Ion implantation is performed on the upper surface layer of the well region to obtain a source region, the source region having the opposite conductivity type to the well region, and the first electrode layer is electrically connected to the source region.

10. A trench-type power device, characterized in that, The trench-type power device is prepared by the method for preparing a trench-type power device as described in any one of claims 1 to 9.

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