Display panel, preparation method thereof and display device

Abstract

The invention discloses a display panel and a preparation method thereof and a display device, the display panel comprises a substrate, a plurality of sub-pixels, a cathode layer and a first inhibition layer, the plurality of sub-pixels are located on the substrate, and the plurality of sub-pixels comprise a first sub-pixel and a second sub-pixel. The cathode layer is located on the side, away from the substrate, of the multiple sub-pixels, the cathode layer comprises a first cathode part and a second cathode part, the first cathode part is located on the light-emitting face of the first sub-pixel, the second cathode part is located on the light-emitting face of the second sub-pixel, and the thickness of the second cathode part is larger than that of the first cathode part. The first suppression layer is located on the side, away from the first sub-pixel, of the first cathode part. The first inhibition layer can inhibit continuous evaporation of the cathode material on the first cathode part in the process of continuous evaporation of the cathode material, and can control the thickness difference of the first cathode part and the second cathode part, so that the microcavity structure difference of the first sub-pixel and the second sub-pixel is realized, and the luminescence spectrum of the first sub-pixel and the luminescence spectrum of the second sub-pixel are independently adjusted.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] Organic Light-Emitting Diode (OLED) technology inherently possesses advantages such as infinite contrast ratio, pixel-level light control, and fast response time, far exceeding the image quality potential of traditional Liquid Crystal Display (LCD) / Micro-Light Emitting Diode (Micro-LED) screens. With the widespread adoption of high-quality content such as 4K / 8K ultra-high-definition video, High Dynamic Range (HDR) movies, and games, the color information carried by the source files themselves is becoming increasingly rich. If display devices cannot keep up, users will be unable to enjoy the full experience of this high-quality content, resulting in wasted resources.

[0003] Therefore, improving the color gamut of OLED screens is imperative. The core idea behind improving the color gamut of OLEDs is to make the spectra of the three primary colors of light—red, green, and blue—as pure as possible and as close as possible to the limits of human visual perception.

[0004] Currently, improving color gamut mainly revolves around adjusting the microcavity of luminescent materials and devices. Luminescent materials can be developed independently according to RGB requirements, but OLED screens are limited by the vapor deposition process, which prevents the microcavity structure from being adjusted in a differentiated manner. Summary of the Invention

[0005] This application provides a display panel, a method for manufacturing the same, and a display device. The first inhibition layer can inhibit the formation of cathode material on the first cathode portion during the formation of the second cathode portion, thereby controlling the thickness difference between the first cathode portion and the second cathode portion and achieving differential adjustment of the microcavity structure.

[0006] This application provides a display panel, comprising: a substrate; a plurality of sub-pixels located on the substrate, the plurality of sub-pixels including a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel emitting different colors; a cathode layer located on the side of the plurality of sub-pixels away from the substrate, the cathode layer including a first cathode portion and a second cathode portion, the first cathode portion being located on the light-emitting surface of the first sub-pixel, the second cathode portion being located on the light-emitting surface of the second sub-pixel, and the thickness of the second cathode portion being greater than the thickness of the first cathode portion; and a first suppression layer located on the side of the first cathode portion away from the first sub-pixel.

[0007] In some embodiments, the orthographic projection of the first sub-pixel on the substrate lies within the orthographic projection of the first suppression layer on the substrate.

[0008] In some embodiments, the pattern of the orthographic projection of the first suppression layer onto the substrate is the same as the pattern of the orthographic projection of the first sub-pixel onto the substrate.

[0009] In some embodiments, the first suppression layer includes a main body portion and an edge portion located around the main body portion, the main body portion having a uniform thickness and the sidewalls of the edge portion being sloped; the orthographic projection of the first sub-pixel on the substrate is located within the orthographic projection of the main body portion on the substrate.

[0010] In some embodiments, the thickness of the first suppression layer is uniform, and the thickness of the first suppression layer is greater than or equal to 10 nm.

[0011] In some embodiments, the plurality of sub-pixels further includes a third sub-pixel, the emission color of which is different from the emission colors of the first sub-pixel and the second sub-pixel; the cathode layer further includes a third cathode portion located on the light-emitting surface of the third sub-pixel, the thickness of which is greater than the thickness of the second cathode portion; the display panel further includes a second suppression layer located on the side of the second cathode portion opposite to the second sub-pixel.

[0012] In some embodiments, the thickness of the second inhibition layer is greater than or equal to 10 nm, and the second inhibition layer also extends to the surface of the first inhibition layer.

[0013] In some embodiments, the display panel further includes: a light-emitting area and a non-light-emitting area, wherein a sub-pixel is located within a light-emitting area, the non-light-emitting area is located between two adjacent sub-pixels, and the cathode layer extends continuously between the light-emitting area and the non-light-emitting area; wherein the first suppression layer extends from the light-emitting area where the first sub-pixel is located to the surrounding non-light-emitting area, and the second suppression layer extends from the light-emitting area where the second sub-pixel is located to the surrounding non-light-emitting area.

[0014] This application also provides a method for manufacturing a display panel, comprising: providing a substrate; forming a plurality of sub-pixels on the substrate, the plurality of sub-pixels including a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel emitting different colors; forming a first sub-cathode layer on the first sub-pixel and the second sub-pixel, the first sub-cathode layer including a first cathode portion located on the first sub-pixel; forming a first suppression layer on the first cathode portion; and forming a second sub-cathode layer on a portion of the first sub-cathode layer corresponding to the second sub-pixel.

[0015] This application also provides a display device, including the display panel in any of the above embodiments.

[0016] In the display panel and its manufacturing method according to the embodiments of this application, in order to make the thickness of the second cathode portion greater than that of the first cathode portion, it is necessary to continue evaporating or depositing cathode material after the first cathode portion is formed. This application, by setting a first suppression layer located on the side of the first cathode portion away from the first sub-pixel, can suppress the continued evaporation of cathode material on the first cathode portion during the continued evaporation process. This allows control over the thickness difference between the first and second cathode portions, thereby achieving a difference in the microcavity structure of the first and second sub-pixels, enabling individual adjustment of the emission spectra of the first and second sub-pixels and improving the color gamut.

[0017] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0019] Figure 1 This is a cross-sectional structural diagram of a display panel provided in some embodiments of this application; Figure 2 This is a cross-sectional structural diagram of a display panel provided in some embodiments of this application; Figure 3 yes Figure 2 A schematic diagram showing the arrangement of neutron pixels, the first suppression layer, and the second suppression layer; Figure 4 This is another cross-sectional schematic diagram of a display panel provided in some embodiments of this application; Figure 5 yes Figure 4 Enlarged structural diagram at point A; Figure 6 This is another cross-sectional structural schematic diagram of the display panel provided in some embodiments of this application; Figure 7 This is a schematic flowchart of a method for manufacturing a display panel according to some embodiments of this application; Figures 8 to 10 This is a cross-sectional structural diagram of the display panel provided in some embodiments of this application during the manufacturing process; Figure 11 This is a schematic cross-sectional view of the display panel after the formation of the second inhibition layer, provided in some embodiments of this application; Figure 12 This is a schematic diagram of the structure of a display device provided in some embodiments of this application.

[0020] Explanation of reference numerals in the attached figures: 100. Display panel; 101. Illuminated area; 102. Non-illuminated area; 10. Substrate; 11. Base; 12. Active layer; 13. Gate insulating layer; 14. Gate layer; 15. Interlayer dielectric layer; 16. Source; 17. Drain; 18. First planarization layer; 19. Second planarization layer; 20. Subpixel; 20a. First subpixel; 20b. Second subpixel; 20c. Third subpixel 30. Cathode layer; 31. First cathode section; 32. Second cathode section; 33. Third cathode section; 301. First sub-cathode layer; 302. Second sub-cathode layer; 303. Third sub-cathode layer; 41. First suppression layer; 411. Main body; 412. Edge portion; 42. Second suppression layer; 50. Anode layer; 60. Pixel definition layer; 200. Display device. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0022] In Organic Light-Emitting Diode (OLED) display technology, microcavities are formed between the anode and cathode layers. Light emitted from sub-pixels has its spectrum modulated within these microcavities through light interference. As light reflects back and forth within the microcavities, different wavelengths of light interfere. Some wavelengths are amplified, while others are suppressed. Therefore, the microcavities for the RGB primary colors need to be optimized according to the target wavelength of each color to achieve optimal spectral characteristics and color performance, thereby improving the color gamut.

[0023] In one embodiment, deposition, optical, and etching processes can be repeatedly performed on each of the sub-pixels of different colors to provide cathode portions of different thicknesses in each red, green, and blue pixel. That is, when applying a microcavity structure, nine additional manufacturing processes are required, increasing manufacturing complexity and cost. Currently, the commonly used vapor deposition process is a full-surface vapor deposition process, which does not require the use of fine metal masks to define the pattern, and is simple and low-cost.

[0024] However, if only a whole-surface evaporation or deposition process is used without etching, the microcavity structure of each sub-pixel cannot be differentiated, thus making it impossible to individually adjust the emission spectrum of different sub-pixels.

[0025] Based on this, this application provides a display panel, including: a substrate; a plurality of sub-pixels located on the substrate, the plurality of sub-pixels including a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel emitting different colors; a cathode layer located on the side of the plurality of sub-pixels away from the substrate, the cathode layer including a first cathode portion and a second cathode portion, the first cathode portion being located on the light-emitting surface of the first sub-pixel, the second cathode portion being located on the light-emitting surface of the second sub-pixel, and the thickness of the second cathode portion being greater than the thickness of the first cathode portion; and a first suppression layer located on the side of the first cathode portion away from the first sub-pixel.

[0026] In the display panel of this application embodiment, in order to make the thickness of the second cathode portion greater than the thickness of the first cathode portion, it is necessary to continue evaporating or depositing cathode material after the first cathode portion is formed. This application, by setting a first suppression layer located on the side of the first cathode portion away from the first sub-pixel, can suppress the continued evaporation of cathode material on the first cathode portion during the continued evaporation process. This allows control over the thickness difference between the first and second cathode portions, thereby achieving a difference in the microcavity structure of the first and second sub-pixels, enabling individual adjustment of the emission spectrum of the first and second sub-pixels, and improving the color gamut.

[0027] The structure of the display panel provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0028] Please see Figure 1 , Figure 1 This is a cross-sectional structural diagram of a display panel provided in some embodiments of this application.

[0029] The display panel 100 includes a substrate 10, a plurality of sub-pixels 20, a cathode layer 30, and a first suppression layer 41. The plurality of sub-pixels 20 are located on the substrate 10, and the plurality of sub-pixels 20 include a first sub-pixel 20a and a second sub-pixel 20b, wherein the first sub-pixel 20a and the second sub-pixel 20b emit different colors. The cathode layer 30 is located on the side of the plurality of sub-pixels 20 away from the substrate 10. The cathode layer 30 includes a first cathode portion 31 and a second cathode portion 32. The first cathode portion 31 is located on the light-emitting surface of the first sub-pixel 20a, and the second cathode portion 32 is located on the light-emitting surface of the second sub-pixel 20b, wherein the thickness H2 of the second cathode portion 32 is greater than the thickness H1 of the first cathode portion 31. The first suppression layer 41 is located on the side of the first cathode portion 31 away from the first sub-pixel 20a.

[0030] The display panel 100 may further include an anode layer (shown in the embodiments below) located between the substrate 10 and each sub-pixel 20. A microcavity is formed between the anode layer and the cathode layer 30, and the physical distance between the anode layer and the cathode layer 30 corresponding to the sub-pixel 20 is the physical cavity length of the microcavity.

[0031] The first sub-pixel 20a can be a blue sub-pixel, and the second sub-pixel 20b can be a green sub-pixel. Since the emission wavelength of the green sub-pixel is greater than that of the blue sub-pixel, the physical cavity length of the microcavity of the green sub-pixel should be relatively long to match the wavelength of green light, while the physical cavity length of the blue microcavity needs to be relatively short to accommodate the shorter wavelength, thereby achieving optimal light output.

[0032] In some embodiments, the thickness W2 of the second sub-pixel 20b can be greater than the thickness W1 of the first sub-pixel 20a, thereby making the physical cavity length of the microcavity of the second sub-pixel 20b greater than the physical cavity length of the microcavity of the first sub-pixel 20a. The differentiated microcavity structure can enhance light of different emission wavelengths respectively, so as to adjust the emission spectrum of the first sub-pixel 20a and the second sub-pixel 20b separately.

[0033] The thickness of the cathode affects its reflectivity, a key parameter in microcavity design as it determines the number of reflections and interference effects of light within the microcavity. Therefore, a thicker cathode typically has higher reflectivity, which enhances the output of light at specific wavelengths. Adjusting the cathode thickness can also, to some extent, regulate the effective cavity length of the microcavity. This adjustment can be used to optimize the spectral characteristics of the RGB primary colors for better color performance.

[0034] Therefore, by setting the thickness H2 of the second cathode portion 32 on the second sub-pixel 20b to be greater than the thickness H1 of the first cathode portion 31 on the first sub-pixel 20a, the microcavity effect of the second sub-pixel 20b can be enhanced, while optimizing the spectral characteristics of the first sub-pixel 20a and the second sub-pixel 20b and improving the color gamut.

[0035] In other embodiments, the first sub-pixel 20a can be a blue sub-pixel, and the second sub-pixel 20b can be a red sub-pixel. That is, the emission wavelength of the first sub-pixel 20a is shorter than the emission wavelength of the second sub-pixel 20b, so the thickness requirement of the second sub-pixel 20b for the second cathode portion 32 is greater than the thickness requirement of the first sub-pixel 20a for the first cathode portion 31.

[0036] In some embodiments, the cathode layer 30 may be made of a metal such as magnesium, and the first inhibition layer 41 may be made of at least one of BAlq (bis(2-methyl-8-hydroxyquinoline)-4-(p-phenylphenol)aluminum), TAZ (3-(biphenyl-4-yl)-5-(4-tert-butylphenyl)-4-phenyl-4H-1,2,4-triazole), and OTI (indium oxide). Magnesium metal has poor adhesion to BAlq, TAZ, and OTI materials. When magnesium metal is vapor-deposited to form the cathode layer 30, the first inhibition layer 41 can inhibit the formation of a magnesium film on the first inhibition layer 41.

[0037] It should be noted that the materials of the first suppression layer 41 that can suppress the adhesion of the cathode layer 30 to the first suppression layer 41 are all within the protection scope of this application.

[0038] like Figure 1 As shown, the thickness L1 of the first suppression layer 41 is uniform (i.e., basically equal) at each position, and the thickness L1 of the first suppression layer 41 is greater than or equal to 10 nm.

[0039] Research revealed that a thickness L1 of 10 nm or greater for the first inhibition layer 41 resulted in better inhibition. When the thickness of the first inhibition layer 41 was less than 10 nm, discontinuities occurred on the first cathode portion 31, making it easier for subsequently deposited cathode material to nucleate on it. However, when the thickness of the first inhibition layer 41 was greater than or equal to 10 nm, the film density was higher, making it less likely for cathode material to form on it, thus resulting in better inhibition.

[0040] In some embodiments, the orthographic projection of the first sub-pixel 20a onto the substrate 10 lies within the orthographic projection of the first suppression layer 41 onto the substrate 10. This ensures that the area directly above the first sub-pixel 20a is completely covered by the first suppression layer 41, minimizing the presence of cathode material on the first suppression layer 41. This, in turn, ensures that the microcavity structure of the first sub-pixel 20a is formed between the anode layer and the first cathode portion 31, optimizing the emission spectrum of the first sub-pixel 20a. Furthermore, it prevents residual cathode material on the first suppression layer 41 from affecting the emission of the first sub-pixel 20a.

[0041] It is understandable that, since the orthographic projection of the first sub-pixel 20a onto the substrate 10 lies within the orthographic projection of the first suppression layer 41 onto the substrate 10, the area of ​​the first suppression layer 41 is greater than or equal to the area of ​​the first sub-pixel 20a. When the area of ​​the first suppression layer 41 is greater than the area of ​​the first sub-pixel 20a, it can be ensured that there is no cathode material residue on the first suppression layer 41 corresponding to the area surrounding the first sub-pixel 20a. This ensures that the lateral light from the first sub-pixel 20a is reflected and interfered only within the microcavity between the anode layer and the first cathode portion 31, thus achieving a spectral optimization effect on the lateral light.

[0042] In some embodiments, the pattern of the orthographic projection of the first suppression layer 41 onto the substrate 10 is the same as the pattern of the orthographic projection of the first sub-pixel 20a onto the substrate 10, thereby effectively covering the first sub-pixel 20a.

[0043] For example, when the orthographic projection pattern of the first sub-pixel 20a is circular, the orthographic projection pattern of the first suppression layer 41 is also circular; when the orthographic projection pattern of the first sub-pixel 20a is rhomboid, the orthographic projection pattern of the first suppression layer 41 is also rhomboid. It should be noted that the embodiments of this application do not limit the orthographic projection pattern of the sub-pixel 20.

[0044] Please see Figure 2 and Figure 3 , Figure 2 This is a cross-sectional structural diagram of a display panel provided in some embodiments of this application. Figure 3 yes Figure 2 A schematic diagram showing the arrangement of the neutron pixels, the first suppression layer, and the second suppression layer. This embodiment is similar to... Figure 1 The embodiment differs in that the plurality of sub-pixels 20 also includes a third sub-pixel 20c.

[0045] The plurality of sub-pixels 20 further includes a third sub-pixel 20c, the emission color of which is different from the emission colors of the first sub-pixel 20a and the second sub-pixel 20b. For example, when the first sub-pixel 20a is a green sub-pixel and the second sub-pixel 20b is a blue sub-pixel, the third sub-pixel 20c is a red sub-pixel.

[0046] In some embodiments, the thickness W3 of the third sub-pixel 20c is greater than the thickness W2 of the second sub-pixel 20b to differentially adjust the physical cavity length of the microcavity.

[0047] The cathode layer 30 further includes a third cathode portion 33, which is located on the light-emitting surface of the third sub-pixel 20c. The thickness H3 of the third cathode portion 33 is greater than the thickness H2 of the second cathode portion 32.

[0048] It is understandable that different emission colors indicate different emission wavelengths, and different emission wavelengths indicate different effective cavity lengths required for the microcavity. The longer the wavelength, the longer the effective cavity length required, and the greater the thickness of the corresponding cathode portion. In other words, the thickness H3 of the third cathode portion 33 is greater than the thickness H2 of the second cathode portion 32, which means that the emission wavelength of the third sub-pixel 20c is greater than the emission wavelength of the second sub-pixel 20b.

[0049] By differentiating the cathode thickness of sub-pixels 20 corresponding to different emitting colors, the spectra of the first sub-pixel 20a, the second sub-pixel 20b, and the third sub-pixel 20c can be optimized individually to improve the color gamut of the display panel.

[0050] The display panel also includes a second suppression layer 42, which is located on the side of the second cathode portion 32 opposite to the second sub-pixel 20b. To simplify the process and reduce costs by using a full-surface vapor deposition process to form cathode portions of different thicknesses, cathode material can be deposited on the third sub-pixel 20c after the second cathode portion 32 is formed. The second suppression layer 42 can suppress the formation of the continuously deposited cathode material on the third sub-pixel 20c, thereby controlling the thickness difference between the second cathode portion 32 and the third cathode portion 33. Furthermore, since the first suppression layer 41 has already been formed above the first sub-pixel 20a, the cathode material will not form on the first suppression layer 41 when the cathode material is continuously deposited on the third sub-pixel 20c.

[0051] In some embodiments, the thickness L2 of the second suppression layer 42 is greater than or equal to 10 nm, thereby achieving a better suppression effect on the cathode material.

[0052] In some embodiments, the thickness L1 of the first suppression layer 41 may be greater than or equal to the thickness L2 of the second suppression layer 42. The fact that the thickness L1 of the first suppression layer 41 is greater than the thickness L2 of the second suppression layer 42 can compensate for the height difference between the first sub-pixel 20a and the second sub-pixel 20b, reducing the structural height difference between the positions of the first sub-pixel 20a and the second sub-pixel 20b, thus improving the flatness of the structure.

[0053] See Figure 3 , Figure 3 Taking the orthographic projection pattern of sub-pixel 20 as an example, the orthographic projection pattern of the first sub-pixel 20a is the same as the orthographic projection pattern of the first suppression layer 41, that is, the orthographic projection pattern of the first suppression layer 41 is also rectangular. The orthographic projection pattern of the second sub-pixel 20b is the same as the orthographic projection pattern of the second suppression layer 42, that is, the orthographic projection pattern of the second suppression layer 42 is also rectangular.

[0054] The orthographic projection of the first sub-pixel 20a on the substrate 10 lies within the orthographic projection of the first suppression layer 41 on the substrate 10, and the orthographic projection of the second sub-pixel 20b on the substrate 10 lies within the orthographic projection of the second suppression layer 42 on the substrate 10. The area of ​​the first suppression layer 41 is larger than the area of ​​the first sub-pixel 20a, and the area of ​​the second suppression layer 42 is larger than the area of ​​the second sub-pixel 20b.

[0055] Please see Figure 4 and Figure 5 , Figure 4 This is another cross-sectional schematic diagram of the display panel provided in some embodiments of this application. Figure 5 yes Figure 4 A magnified structural diagram at point A. The main difference between this embodiment and the above embodiment lies in the edge shape of the suppression layer, that is, the sidewall of the suppression layer is sloped.

[0056] See Figure 4 The substrate 10 can be an array substrate, which, from bottom to top, may include a base 11, an active layer 12, a gate insulating layer 13, a gate layer 14, an interlayer dielectric layer 15, a source 16 and a drain 17, a first planarization layer 18, and a second planarization layer 19. The active layer 12 is located on the base 11, and the gate insulating layer 13 is located on the base 11 and covers the active layer 12. The gate layer 14 is located on the gate insulating layer 13, and the interlayer dielectric layer 15 is located on the gate insulating layer 13 and covers the gate layer 14. The source 16 and drain 17 are located on the interlayer dielectric layer 15 and are respectively connected to both sides of the active layer 12 through vias. The first planarization layer 18 is located on the interlayer dielectric layer 15 and covers the source 16 and drain 17. The second planarization layer 19 is located on the first planarization layer 18, and the anode layer 50 is located on the second planarization layer 19, and the anode layer 50 is connected to the drain 17 through a via.

[0057] The display panel also includes a pixel definition layer 60 located on the second planarization layer 19 and having an opening that exposes the anode layer 50. The sub-pixels 20 are located within the opening. Since a portion of the first cathode portion 31 is located within the opening, i.e., the surface of the first cathode portion 31 is not flat, the first suppression layer 41 is conformally formed on the surface of the first cathode portion 31.

[0058] It should be noted that the thickness of the first cathode portion 31 is uniform at all positions, the thickness of the second cathode portion 32 is uniform at all positions, and the thickness of the third cathode portion 33 is uniform at all positions.

[0059] In some embodiments, the cathode layer 30 includes a first sub-cathode layer 301, a second sub-cathode layer 302, and a third sub-cathode layer 303 stacked sequentially from bottom to top. The first sub-cathode layer 301 extends continuously over the first sub-pixel 20a, the second sub-pixel 20b, and the third sub-pixel 20c. The second sub-cathode layer 302 is located in the area of ​​the first sub-cathode layer 301 other than the first suppression layer 41, and the third sub-cathode layer 303 is located in the area of ​​the second sub-cathode layer 302 other than the first suppression layer 41 and the second suppression layer 42.

[0060] The first cathode portion 31 is the first sub-cathode layer 301 on the first sub-pixel 20a, the second cathode portion 32 is composed of the first sub-cathode layer 301 and the second sub-cathode layer 302 on the second sub-pixel 20b, and the third cathode portion 33 is composed of the first sub-cathode layer 301, the second sub-cathode layer 302 and the third sub-cathode layer 303 on the third sub-pixel 20c.

[0061] See Figure 5 The first inhibition layer 41 includes a main body 411 and an edge portion 412 located around the main body 411. The main body 411 has a uniform thickness at all locations, and the sidewalls of the edge portion 412 are sloped. Therefore, the thickness of the edge portion 412 gradually decreases away from the main body 411, so the main body 411 is more effective than the edge portion 412 in inhibiting the adhesion of cathode material.

[0062] To ensure that no cathode material is formed on the first suppression layer 41 corresponding to the area directly above the first sub-pixel 20a, the orthographic projection of the first sub-pixel 20a on the substrate 10 can be positioned within the orthographic projection of the main body portion 411 on the substrate 10. In this way, the first suppression layer 41 corresponding to the area directly above the first sub-pixel 20a is entirely the main body portion 411, resulting in a better suppression effect.

[0063] In some embodiments, the orthographic projection of the main body 411 on the substrate 10 coincides with the orthographic projection of the first sub-pixel 20a on the substrate 10. Figure 5 The boundary of the main body 411 of the first suppression layer 41 is shown in dashed lines to be flush with the boundary of the first sub-pixel 20a.

[0064] See Figure 4 The display panel further includes a light-emitting area 101 and a non-light-emitting area 102. A sub-pixel 20 is located within a light-emitting area 101, and the non-light-emitting area 102 is located between two adjacent sub-pixels 20. The cathode layer 30 extends continuously between the light-emitting area 101 and the non-light-emitting area 102. That is, the first cathode portion 31, the second cathode portion 32, and the third cathode portion 33 are interconnected to form a single surface, except that the thicknesses of the first cathode portion 31, the second cathode portion 32, and the third cathode portion 33 are different.

[0065] It should be noted that the light-emitting area 101 can be defined by the opening range of the pixel definition layer 60, while the area between the openings is defined as the non-light-emitting area 102.

[0066] In some embodiments, the first suppression layer 41 may be located only in the light-emitting area 101 where the first sub-pixel 20a is located, that is, it does not extend to the non-light-emitting area 102 surrounding the first sub-pixel 20a, and is sufficient to suppress the formation of cathode material above the first cathode portion 31. The second suppression layer 42 may be located only in the light-emitting area 101 where the second sub-pixel 20b is located, that is, it does not extend to the non-light-emitting area 102 surrounding the second sub-pixel 20b, and is sufficient to suppress the formation of cathode material above the second cathode portion 32.

[0067] In other embodiments, the first suppression layer 41 can extend from the light-emitting area 101 where the first sub-pixel 20a is located to the non-light-emitting area 102 surrounding the first sub-pixel 20a, but cannot extend to the light-emitting area 101 of the second sub-pixel 20b. Similarly, the second suppression layer 42 can also extend from the light-emitting area 101 where the second sub-pixel 20b is located to the non-light-emitting area 102 surrounding the second sub-pixel 20b, but cannot extend to the light-emitting area 101 of the second sub-pixel 20b. This increases the area of ​​the first suppression layer 41 and the second suppression layer 42, which is beneficial for the formation process of the first suppression layer 41 and the second suppression layer 42.

[0068] The display panel may also include a first auxiliary layer and a second auxiliary layer (not shown), which may extend continuously between different light-emitting areas 101. The first auxiliary layer is located between the sub-pixel 20 and the anode layer 50, and the second auxiliary layer is located between the sub-pixel 20 and the cathode layer 30.

[0069] The first auxiliary layer may include a hole injection layer and a hole transport layer stacked sequentially along a direction away from the substrate 11, wherein the hole injection layer covers the anode layer 50. The second auxiliary layer may include an electron transport layer and an electron injection layer stacked sequentially along a direction away from the substrate 11, wherein the electron transport layer covers the sub-pixel 20. The cathode layer 30 is located on the side of the second auxiliary layer away from the substrate 11.

[0070] Please see Figure 6 , Figure 6 This is another cross-sectional structural schematic diagram of a display panel provided in some embodiments of this application. This embodiment is similar to... Figure 4 The difference in the embodiment lies in the position of the second suppression layer 42.

[0071] The second suppression layer 42 is not only located in the light-emitting area 101 of the second sub-pixel 20b, but also extends to the surface of the first suppression layer 41. That is, the second suppression layer 42 extends from the light-emitting area 101 of the second sub-pixel 20b, through the non-light-emitting area 102, to the light-emitting area 101 of the first sub-pixel 20a. In this way, the area of ​​the second suppression layer 42 is increased, so the mask opening for forming the second suppression layer 42 can be increased, thereby reducing the manufacturing difficulty of the second suppression layer 42.

[0072] and Figure 4 Compared to the previous example, due to Figure 4 In this embodiment, the area of ​​the second suppression layer 42 is small (only corresponding to the second sub-pixel 20b), so the thickness of the cathode layer 30 of each non-light-emitting area 102 is the same as the thickness of the third cathode portion 33, which is equivalent to increasing the thickness of the cathode layer 30 of the non-light-emitting area 102, thereby reducing the impedance of the cathode layer 30.

[0073] Accordingly, this application also provides a method for manufacturing a display panel; please refer to [link to relevant documentation]. Figure 7 , Figure 7 This is a schematic flowchart illustrating a method for fabricating a display panel according to some embodiments of this application. The method for fabricating the display panel includes: Step S1: Provide a substrate; Step S2: A plurality of sub-pixels are formed on the substrate, the plurality of sub-pixels including a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel emitting different colors; Step S3: A first sub-cathode layer is formed on the first sub-pixel and the second sub-pixel, the first sub-cathode layer including a first cathode portion located on the first sub-pixel; Step S4: Form a first suppression layer on the first cathode portion; Step S5: Form a second sub-cathode layer on the portion of the first sub-cathode layer corresponding to the second sub-pixel.

[0074] In the display panel fabrication method provided in this application embodiment, the first sub-cathode layer is formed simultaneously on the first sub-pixel and the second sub-pixel. Therefore, a full-area evaporation process can be used to form the first sub-cathode layer, simplifying the process. Since a first suppression layer is formed on the first cathode portion, the first suppression layer can suppress the formation of the second sub-cathode layer above the first cathode portion. Therefore, a full-area evaporation process can also be used to form the second sub-cathode layer. Because the first and second sub-cathode layers are formed above the second sub-pixel, while only the first sub-cathode layer is formed above the first sub-pixel, this application achieves thickness differences of the cathode layers above different sub-pixels through a simple full-area evaporation process, thereby individually adjusting the emission spectrum of the first and second sub-pixels and improving the color gamut.

[0075] The following is in conjunction with the appendix Figures 8 to 10 , Figures 8 to 10 This is a cross-sectional structural diagram of the display panel provided in some embodiments of this application during the manufacturing process.

[0076] Step S1: Provide substrate 10. See [link / reference] Figure 8 .

[0077] The substrate 10 can be an array substrate, which, from bottom to top, may include a base 11, an active layer 12, a gate insulating layer 13, a gate layer 14, an interlayer dielectric layer 15, a source 16 and a drain 17, a first planarization layer 18, and a second planarization layer 19. The active layer 12 is located on the base 11, and the gate insulating layer 13 is located on the base 11 and covers the active layer 12. The gate layer 14 is located on the gate insulating layer 13, and the interlayer dielectric layer 15 is located on the gate insulating layer 13 and covers the gate layer 14. The source 16 and drain 17 are located on the interlayer dielectric layer 15 and are respectively connected to both sides of the active layer 12 through vias. The first planarization layer 18 is located on the interlayer dielectric layer 15 and covers the source 16 and drain 17. The second planarization layer 19 is located on the first planarization layer 18.

[0078] The method for fabricating the display panel may further include: forming an anode layer 50 on the second planarization layer 19, the anode layer 50 being connected to the drain electrode 17 through a via; and forming a pixel definition layer 60 on the second planarization layer 19, the pixel definition layer 60 having an opening that exposes the anode layer 50.

[0079] Step S2: A plurality of sub-pixels 20 are formed on the substrate 10. The plurality of sub-pixels 20 includes a first sub-pixel 20a and a second sub-pixel 20b, wherein the first sub-pixel 20a and the second sub-pixel 20b emit different colors. See also... Figure 8 .

[0080] Multiple sub-pixels 20 can be formed within the opening using inkjet printing technology, and the multiple sub-pixels 20 may also include a third sub-pixel 20c.

[0081] Step S3: A first sub-cathode layer 301 is formed on the first sub-pixel 20a and the second sub-pixel 20b. The first sub-cathode layer 301 includes a first cathode portion 31 located on the first sub-pixel 20a. See also Figure 8 .

[0082] The first sub-cathode layer 301 can be formed on all sub-pixels 20 using a full-surface vapor deposition process or other full-surface deposition process, which simplifies the process. The material of the first sub-cathode layer 301 may include metals such as magnesium. It is understood that the thickness of the first sub-cathode layer 301 is based on the required thickness of the first cathode portion 31 of the first sub-pixel 20a.

[0083] Step S4: A first suppression layer 41 is formed on the first cathode portion 31. See also Figure 9 .

[0084] The portion of the first sub-cathode layer 301 corresponding to the first sub-pixel 20a can be called the first cathode portion 31, and the microcavity of the first sub-pixel 20a is formed between the anode layer 50 and the first cathode portion 31.

[0085] The material of the first inhibition layer 41 may include at least one of BAlq (bis(2-methyl-8-hydroxyquinoline)-4-(p-phenylphenol)aluminum), TAZ (3-(biphenyl-4-yl)-5-(4-tert-butylphenyl)-4-phenyl-4H-1,2,4-triazole) and OTI (indium oxide).

[0086] In some embodiments, the formation process of the first inhibition layer 41 may include a deposition process and a patterning etching process.

[0087] In other embodiments, the formation process of the first inhibition layer 41 may include a fine metal mask (FFM) process.

[0088] The first suppression layer 41 may be formed only on the first cathode portion 31 (e.g., Figure 9 As shown), it can also extend to the non-light-emitting area 102 around the first sub-pixel 20a.

[0089] Step S5: A second sub-cathode layer 302 is formed on the portion of the first sub-cathode layer 301 corresponding to the second sub-pixel 20b. See also Figure 9 .

[0090] The formation process and materials of the second sub-cathode layer 302 can be the same as those of the first sub-cathode layer 301. That is, the second sub-cathode layer 302 can be prepared on all sub-pixels 20 using a full-surface evaporation process or other full-surface deposition process, which simplifies the process. The material of the first sub-cathode layer 301 may include metals such as magnesium.

[0091] However, since the first suppression layer 41 can suppress the formation of the second sub-cathode layer 302 on the surface of the first suppression layer 41, when the second sub-cathode layer 302 is prepared using a full-surface vapor deposition process, only the surface of the first suppression layer 41 is not formed with the second sub-cathode layer 302. The first sub-cathode layer 301 and the second sub-cathode layer 302 on the second sub-pixel 20b constitute the second cathode portion 32, and the thickness of the second cathode portion 32 is greater than the thickness of the first cathode portion 31.

[0092] It is understandable that the sum of the thickness of the second sub-cathode layer 302 and the thickness of the first sub-cathode layer 301 is based on the thickness of the second cathode portion 32 required for the second sub-pixel 20b.

[0093] Please see next. Figure 10 and Figure 4 The method for manufacturing the display panel further includes: forming a second suppression layer 42 on the side of the second cathode portion 32 opposite to the second sub-pixel 20b; and forming a third sub-cathode layer 303 on the portion of the second sub-cathode layer 302 corresponding to the third sub-pixel 20c.

[0094] See Figure 10 The second inhibition layer 42 can be formed using the same process as the first inhibition layer 41.

[0095] See Figure 4 The third sub-cathode layer 303 can be formed using a full-surface evaporation or deposition process. Since the first suppression layer 41 and the second suppression layer 42 are formed on the first cathode portion 31 and the second cathode portion 32, the third sub-cathode layer 303 is formed at locations other than the first suppression layer 41 and the second suppression layer 42. Specifically, the first sub-cathode layer 301, the second sub-cathode layer 302, and the third sub-cathode layer 303 on the third sub-pixel 20c constitute the third cathode portion 33, and the third cathode portion 33 has the greatest thickness.

[0096] It is understandable that the sum of the thicknesses of the first sub-cathode layer 301, the second sub-cathode layer 302, and the third sub-cathode layer 303 is based on the thickness of the third cathode portion 33 required for the third sub-pixel 20c.

[0097] Please see Figure 11 , Figure 11 This is a cross-sectional structural diagram of the display panel after the formation of the second inhibition layer, provided in some embodiments of this application. Figure 11 The corresponding preparation process is used to form Figure 6 The display panel shown. This embodiment is similar to... Figure 10 The difference in the embodiments lies in the formation location of the second suppression layer 42.

[0098] In the process of forming the second suppression layer 42, the second suppression layer 42 is not only located in the light-emitting area 101 of the second sub-pixel 20b, but also extends to the surface of the first suppression layer 41. That is, the second suppression layer 42 extends from the light-emitting area 101 of the second sub-pixel 20b, through the non-light-emitting area 102, to the light-emitting area 101 of the first sub-pixel 20a. In this way, the area of ​​the second suppression layer 42 is increased, so the mask opening for forming the second suppression layer 42 can be increased, thereby reducing the process difficulty of the second suppression layer 42.

[0099] The display panel manufacturing method provided in this application embodiment achieves the differentiation of the thickness of the cathode layer 30 by evaporating two suppression layers (first suppression layer 41 and second suppression layer 42) and three sub-cathode layers (first sub-cathode layer 301, second sub-cathode layer 302 and third sub-cathode layer 303).

[0100] This application also provides a display device, which includes the display panel in any of the above embodiments.

[0101] Please see Figure 12 , Figure 12 This is a schematic diagram of the structure of a display device provided in some embodiments of this application.

[0102] The display device 200 includes a device body and a display panel 100, which can be the display panel 100 in any of the above embodiments. In addition, the device body may include a frame, driving components, power supply, etc., and the display device 200 can be a display terminal such as a mobile phone, tablet, or television, without limitation.

[0103] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0104] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0105] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0106] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel (100), characterized in that, include: substrate(10); Multiple sub-pixels (20) are located on the substrate (10). The multiple sub-pixels (20) include a first sub-pixel (20a) and a second sub-pixel (20b). The first sub-pixel (20a) and the second sub-pixel (20b) emit different colors. A cathode layer (30) is located on the side of the plurality of sub-pixels (20) away from the substrate (10). The cathode layer (30) includes a first cathode portion (31) and a second cathode portion (32). The first cathode portion (31) is located on the light-emitting surface of the first sub-pixel (20a), and the second cathode portion (32) is located on the light-emitting surface of the second sub-pixel (20b). The thickness of the second cathode portion (32) is greater than the thickness of the first cathode portion (31). The first suppression layer (41) is located on the side of the first cathode portion (31) away from the first sub-pixel (20a).

2. The display panel (100) according to claim 1, characterized in that, The orthographic projection of the first sub-pixel (20a) on the substrate (10) lies within the orthographic projection of the first suppression layer (41) on the substrate (10).

3. The display panel (100) according to claim 2, characterized in that, The pattern of the orthographic projection of the first suppression layer (41) onto the substrate (10) is the same as the pattern of the orthographic projection of the first sub-pixel (20a) onto the substrate (10).

4. The display panel (100) according to claim 2, characterized in that, The first suppression layer (41) includes a main body (411) and an edge portion (412) located around the main body (411). The main body (411) has a uniform thickness, and the sidewall of the edge portion (412) is sloped. The orthographic projection of the first sub-pixel (20a) on the substrate (10) is located within the orthographic projection of the main body portion (411) on the substrate (10).

5. The display panel (100) according to claim 1, characterized in that, The thickness of the first suppression layer (41) is uniform, and the thickness of the first suppression layer (41) is greater than or equal to 10 nm.

6. The display panel (100) according to claim 1, characterized in that, The plurality of sub-pixels (20) further include a third sub-pixel (20c), the emission color of which is different from the emission colors of the first sub-pixel (20a) and the second sub-pixel (20b); The cathode layer (30) further includes a third cathode portion (33), which is located on the light-emitting surface of the third sub-pixel (20c), and the thickness of the third cathode portion (33) is greater than the thickness of the second cathode portion (32). The display panel (100) further includes a second suppression layer (42), which is located on the side of the second cathode portion (32) away from the second sub-pixel (20b).

7. The display panel (100) according to claim 6, characterized in that, The thickness of the second inhibition layer (42) is greater than or equal to 10 nm, and the second inhibition layer (42) also extends to the surface of the first inhibition layer (41).

8. The display panel (100) according to claim 6, characterized in that, The display panel (100) also includes: The light-emitting area (101) and the non-light-emitting area (102) are respectively, one of the sub-pixels (20) is located in one of the light-emitting areas (101), the non-light-emitting area (102) is located between two adjacent sub-pixels (20), and the cathode layer (30) extends continuously between the light-emitting area (101) and the non-light-emitting area (102); The first suppression layer (41) extends from the light-emitting area (101) where the first sub-pixel (20a) is located to the surrounding non-light-emitting area (102), and the second suppression layer (42) extends from the light-emitting area (101) where the second sub-pixel (20b) is located to the surrounding non-light-emitting area (102).

9. A method for preparing a display panel (100), characterized in that, include: Provide substrate (10); A plurality of sub-pixels (20) are formed on the substrate (10), the plurality of sub-pixels (20) including a first sub-pixel (20a) and a second sub-pixel (20b), the first sub-pixel (20a) and the second sub-pixel (20b) having different light emission colors; A first sub-cathode layer (301) is formed on the first sub-pixel (20a) and the second sub-pixel (20b), the first sub-cathode layer (301) including a first cathode portion (31) located on the first sub-pixel (20a); A first suppression layer (41) is formed on the first cathode portion (31); A second sub-cathode layer (302) is formed on the portion of the first sub-cathode layer (301) corresponding to the second sub-pixel (20b).

10. A display device (200), characterized in that, Includes the display panel (100) as described in any one of claims 1 to 8.

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