Display panel and manufacturing method thereof

Abstract

Provided are a display panel and a method of manufacturing the same, the display panel including: a display area including a first pixel area in which a plurality of pixels are disposed; and a sensing region including a second pixel region in which a plurality of pixel groups are disposed, and a light transmitting portion disposed between the pixel groups. At least the second pixel region includes a light shielding layer, and the light shielding layer includes an opening corresponding to the light transmitting portion.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 202110733831.X, filed on June 30, 2021, entitled "Display Panel and Manufacturing Method Thereof".

[0002] Cross-references to related applications

[0003] This application claims priority and benefit to Korean patent applications filed on July 2, 2020, No. 2020-0081557, and July 12, 2020, No. 2020-0085531, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0004] This disclosure relates to a display panel and a method of manufacturing the same, the display panel including a sensing area having pixels disposed thereon for reproducing images. Background Technology

[0005] Based on the material of the light-emitting layer, electroluminescent display devices are broadly classified into inorganic light-emitting display devices and organic light-emitting display devices. Active-matrix organic light-emitting display devices include self-emissive organic light-emitting diodes (hereinafter referred to as "OLEDs"), and possess advantages such as fast response time, high luminous efficiency and brightness, and wide viewing angle. In organic light-emitting display devices, OLEDs are formed on each pixel. Because organic light-emitting display devices not only have fast response time, excellent luminous efficiency, brightness, and viewing angle, but also can represent black levels (grayscale) in complete black, and have excellent contrast and color gamut.

[0006] Multimedia capabilities on mobile devices are improving. For example, smartphones now come with a built-in camera by default, and camera resolution is gradually increasing to the level of traditional digital camcorders. However, the front-facing camera on smartphones limits screen design, making screen design difficult. To reduce the space occupied by the camera, screen designs including notches or punch holes have been adopted in smartphones, but full-screen display is still not possible because the screen size is still limited by the camera. Summary of the Invention

[0007] To achieve full-screen display, a method has been proposed as follows: An image capture area containing low-resolution pixels is provided within the screen of the display panel, and a camera is positioned below the display panel, opposite to the image capture area. The image capture area on the screen serves as a transparent display for showing the image. However, this image capture area suffers from reduced transmittance and low brightness due to the number of pixels.

[0008] This disclosure aims to address all the aforementioned necessities and problems.

[0009] This disclosure aims to provide a display panel capable of increasing the transmittance of the sensing area in a screen and a method for manufacturing the same.

[0010] It should be noted that the purpose of this disclosure is not limited to the above-described purposes, and other purposes of this disclosure will be apparent to those skilled in the art from the following description.

[0011] According to one aspect of this disclosure, a display panel is provided, comprising: a display area including a first pixel area having a plurality of pixels disposed therein; and a sensing area including a second pixel area having a plurality of pixel groups disposed therein and a light-transmitting portion disposed between the pixel groups, wherein at least the sensing area includes a light-shielding layer, and the light-shielding layer includes an opening corresponding to the light-transmitting portion.

[0012] According to another aspect of this disclosure, a method for manufacturing a display panel is provided, the display panel comprising: a display area including a first pixel area having a plurality of pixels disposed therein; and a sensing area including a second pixel area having a plurality of pixel groups disposed therein and a light-transmitting portion disposed between the pixel groups, the method comprising: forming a light-shielding layer at least in the sensing area, wherein the light-shielding layer includes an opening corresponding to the light-transmitting portion and is configured to expose the light-transmitting portion to a laser beam through the opening; forming a metal layer having an absorption coefficient higher than that of the light-shielding layer for a specific wavelength of the laser beam in the first pixel area of ​​the display area and the sensing area; and irradiating the laser beam onto at least the sensing area to remove the metal layer from the light-transmitting portion. Attached Figure Description

[0013] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0014] Figure 1 This is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0015] Figure 2 This is a view illustrating an example of pixel settings in a display area according to an embodiment of the present disclosure;

[0016] Figure 3A This is a view showing the pixels and light-transmitting portion of a sensing area according to an embodiment of the present disclosure;

[0017] Figure 3BThis is a view showing the pixels and light-transmitting portion of a sensing area according to another embodiment of the present disclosure;

[0018] Figure 4 This is a view showing the spotting of a laser beam during a laser ablation process to partially remove the cathode layer in the sensing area;

[0019] Figure 5 It is shown as follows Figure 4 The photographic image shown is a spot shot of a laser beam illuminating a metal layer;

[0020] Figure 6A This is a view showing a schematic cross-sectional structure of a display panel according to an embodiment of the present disclosure and a laser beam irradiated in a laser ablation process;

[0021] Figure 6B This is a view showing a schematic cross-sectional structure of a display panel according to another embodiment of the present disclosure and a laser beam irradiated in a laser ablation process;

[0022] Figures 7 to 9 This is a view illustrating various laser beam patterns according to an embodiment of the present disclosure;

[0023] Figure 10 These are photographic images showing experimental results of removing a metal layer from a light-transmitting region after performing a laser ablation process according to an embodiment of the present disclosure;

[0024] Figure 11 This is a block diagram illustrating a display panel and a display panel driving portion according to an embodiment of the present disclosure;

[0025] Figure 12 This is a block diagram schematically illustrating the configuration of the driver IC;

[0026] Figure 13 This is a circuit diagram showing an example of a pixel circuit;

[0027] Figure 14 This is a circuit diagram showing another example of a pixel circuit;

[0028] Figure 15 It shows the driver Figure 13 and Figure 14 A view of the pixel circuit method shown;

[0029] Figure 16 This is a cross-sectional view showing in detail the cross-sectional structure of a pixel region in a display panel according to an embodiment of the present disclosure;

[0030] Figure 17 and Figure 18This is a cross-sectional view showing the light-shielding layer of the pixel region and the light-transmitting portion of the sensing region in the cross-sectional structure of a display panel according to various embodiments of the present disclosure;

[0031] Figure 19 This is a cross-sectional view showing an example of an insulating layer that can be removed from the light-transmitting portion of the sensing area;

[0032] Figure 20A and Figure 20B This is a view showing the metal layer of the display panel and the light-shielding layer overlapping the metal layer;

[0033] Figure 21 This is a view illustrating the laser crystallization process of amorphous silicon used as a semiconductor layer; and

[0034] Figure 22A This is a view showing an example of multiple sensor modules set in a sensing area;

[0035] Figure 22B This is another view showing an example where only one sensor module is set up in the sensing area. Detailed Implementation

[0036] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed herein and can be implemented in various different forms. The embodiments are provided to make the preventative disclosure thorough and to fully convey the scope of this disclosure to those skilled in the art. It should be noted that the scope of this disclosure is defined by the claims.

[0037] The figures, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings for describing embodiments of the present disclosure are merely exemplary and are not limited to the content shown in the present disclosure. Throughout the text, similar reference numerals refer to similar elements. Furthermore, in describing the present disclosure, detailed descriptions of prior art will be omitted where it is determined that such detailed descriptions may unnecessarily obscure the essential points of the present disclosure.

[0038] Terms such as “including” and “having” as used herein are intended to allow for the inclusion of other elements unless the term is used in conjunction with the term “only”. Unless otherwise expressly stated, any reference to the singular may include the plural.

[0039] Even if not explicitly stated, components are interpreted as including the usual tolerance range.

[0040] To describe positional relationships, such as when describing the positional relationship between two parts as "on," "above," "below," "next to," etc., one or more parts may be inserted between them unless the terms "immediately" or "directly" are used in the expression.

[0041] Although terms such as "first" and "second" can be used to describe various components, these components are not necessarily limited to these terms. The terms are only used to distinguish one component from another.

[0042] To describe temporal relationships, such as when describing them as “after,” “following,” “next,” “before,” etc., non-continuous cases may be included unless the terms “immediately after” or “directly” are used in the expression.

[0043] Throughout the specification, the same reference numerals refer to the same components.

[0044] Features of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole. The embodiments may interact and be performed in various technical ways and may be performed independently or in connection with each other.

[0045] Various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0046] refer to Figure 1 and Figure 2 The display panel 100 screen includes at least a display area DA and a sensing area CA. Each of the display area DA and the sensing area CA includes a pixel array, in which pixels are arranged and pixel data is written. The number of pixels per unit area (i.e., pixels per inch (PPI)) of the sensing area CA is lower than the number of pixels per unit area of ​​the display area DA to ensure the transmittance of the sensing area CA.

[0047] The pixel array of the display area DA includes a pixel region (first pixel region) in which a plurality of pixels with high PPI are disposed. The pixel array of the sensing area CA includes a pixel region (second pixel region) in which a plurality of pixel groups are disposed, the plurality of pixel groups being spaced apart from each other by light-transmitting portions and thus having relatively low PPI. In the sensing area CA, external light can pass through the display panel 100 through the light-transmitting portions with high light transmittance and can be received by the sensing element module below the display panel 100.

[0048] Since the display area DA and the sensing area CA both include pixels, the input image can be reproduced on the display area DA and the sensing area CA.

[0049] Each pixel in the display area DA and the sensing area CA includes sub-pixels of different colors to achieve the color of the image. The sub-pixels include red sub-pixels (hereinafter referred to as "R sub-pixels"), green sub-pixels (hereinafter referred to as "G sub-pixels"), and blue sub-pixels (hereinafter referred to as "B sub-pixels"). Although not shown, each pixel P may also include a white sub-pixel (hereinafter referred to as "W sub-pixels"). Each sub-pixel may include pixel circuitry and a light-emitting element (OLED).

[0050] As an example, the sensing area CA includes, but is not limited to, a light sensing area and / or an image capture area, and the sensing element module includes, but is not limited to, a light sensor module and / or an imaging element module. When the light sensing area CA is an image capture area and the sensing element module is an imaging element module, the image capture area includes pixels and an imaging element module disposed below the screen of the display panel 100. When pixel data of an input image is written to the pixels of the image capture area in display mode, the input image is displayed through the lens 30 of the imaging element module. The imaging element module images an external image in imaging mode and outputs photographic or video image data. The lens of the imaging element module faces the image capture area. External light is incident on the lens of the imaging element module through the image capture area, and the lens 30 converges the light to an image sensor (not shown in the figure). The imaging element module images an external image in the imaging mode and outputs the photographic or video image data.

[0051] To ensure transmittance, since pixels are removed from the sensing region CA, an image quality compensation algorithm can be applied to compensate for the brightness and color coordinates of the pixels in the sensing region CA.

[0052] In this disclosure, since low-resolution pixels are set in the sensing area CA, the display area of ​​the screen is not limited by the sensing element module, thus enabling full-screen display.

[0053] The display panel 100 has a width in the X-axis direction, a length in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a circuit layer 12 disposed on a substrate 10 and a light-emitting element layer 14 disposed on the circuit layer 12. A polarizer 18 may be disposed on the light-emitting element layer 14, and a cover glass 20 may be disposed on the polarizer 18.

[0054] Circuit layer 12 may include pixel circuitry connected to lines such as data lines, gate lines, power lines, etc., and gate drive portions connected to the gate lines. Circuit layer 12 may include circuit elements such as transistors implemented as thin-film transistors (TFTs), capacitors, etc. The lines and circuit elements of circuit layer 12 may be implemented as multiple insulating layers, two or more metal layers spaced apart from each other by the insulating layers between them, and an active layer comprising semiconductor material.

[0055] The light-emitting element layer 14 may include light-emitting elements driven by pixel circuitry. The light-emitting elements may be implemented as organic light-emitting diodes (OLEDs). OLEDs include an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL), but this disclosure is not limited thereto. When a voltage is applied to the anode and cathode of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emission layer (EML) and then form excitons, thus visible light is emitted from the emission layer (EML). The light-emitting element layer 14 may be disposed on pixels that selectively transmit red, green, and blue wavelengths, and may also include a color filter array.

[0056] The light-emitting element layer 14 can be covered by a protective layer, and the protective layer can be covered by an encapsulation layer. The protective layer and encapsulation layer can have a structure in which organic and inorganic films are alternately stacked. The inorganic film blocks the permeation of moisture or oxygen. The organic film flattens the surface of the inorganic film. When the organic and inorganic films are stacked in a multilayer manner, the channels for moisture or oxygen are longer than those in a single layer, effectively blocking the permeation of moisture or oxygen that could affect the light-emitting element layer 14.

[0057] Polarizer 18 can be attached to the encapsulation layer. Polarizer 18 improves the outdoor visibility of the display device. Polarizer 18 reduces light reflected from the surface of the display panel 100 and blocks light reflected from the metal of the circuit layer 12 to improve pixel brightness. Polarizer 18 can be implemented as a linear polarizer or a circular polarizer in which a linear polarizer and a phase retardation (delay) film are combined.

[0058] In the display panel of this disclosure, each of the pixel regions of the display area DA and the sensing area CA may include a light-shielding layer. The light-shielding layer is removed from the light-transmitting portion of the sensing area to define the light-transmitting portion. The light-shielding layer includes an opening corresponding to the light-transmitting portion region. The light-shielding layer is removed from the opening. The light-shielding layer is formed of a metal or inorganic film that has a lower absorption coefficient than the metal layer removed from the light-transmitting portion for the wavelength of the laser beam used in the laser ablation process for removing the metal layer present in the light-transmitting portion.

[0059] Figure 2 This is a view that shows an example of the pixel configuration in the display area DA. Figure 3A This is a view showing an example of the pixels and light-transmitting portion of the sensing area CA. Figure 3B This is another example view showing the pixels and light-transmitting portion of the sensing area CA. Figure 2 , Figure 3A and Figure 3B The lines connecting to the pixels are omitted.

[0060] refer to Figure 2 The display area DA comprises pixels PIX1 and PIX2 arranged in a matrix. Each of pixels PIX1 and PIX2 can be implemented as a real-type pixel where the R, G, and B sub-pixels of the three primary colors are configured as one pixel. Each of pixels PIX1 and PIX2 may also include W sub-pixels (omitted in the diagram). Furthermore, a sub-pixel rendering algorithm can be used to configure two sub-pixels as one pixel. For example, the first pixel PIX1 can consist of R and G sub-pixels, and the second pixel PIX2 can consist of B and G sub-pixels. Insufficient color representation in each of pixels PIX1 and PIX2 can be compensated for by averaging the corresponding color data between adjacent pixels.

[0061] refer to Figure 3A The sensing area CA includes pixel groups PG spaced apart from each other at a predetermined pitch, and a light-transmitting portion AG disposed between adjacent pixel groups PG. External light is received by a lens of the sensing element module (in this case, the imaging element module) through the light-transmitting portion AG. The light-transmitting portion AG may comprise a transparent medium with high transmittance without metal, allowing light to enter with minimal light loss. In other words, the light-transmitting portion AG may be formed of a transparent insulating material, without including metal lines or pixels. As the amount of light-transmitting portion AG increases, the transmittance of the sensing area CA increases.

[0062] A pixel group PG can include one or two pixels. Each pixel in a pixel group can include two to four sub-pixels. For example, a pixel in a pixel group can include R, G, and B sub-pixels, or it can include two sub-pixels and may also include a W sub-pixel. Figure 3A In the example, the first pixel PIX1 is composed of R and G sub-pixels, and the second pixel PIX2 is composed of B and G sub-pixels, but this disclosure is not limited thereto.

[0063] The distance D3 between the light-transmitting portions AG is less than the spacing D1 between pixel groups PG. The spacing D2 between sub-pixels is less than the spacing D1 between pixel groups PG.

[0064] Figure 3BAnother example of the pixels and light-transmitting portion of the sensing area CA is shown. Besides the size of the light-transmitting portion AG, such as... Figure 3B The structure of the other example shown can be similar to Figure 3A The structure of the example shown.

[0065] In particular, with Figure 3A Compared to the examples shown, such as Figure 3B Each light-transmitting portion AG shown is enlarged, and from... Figure 3B As can be seen, the distance D3 between the light-transmitting portions AG is smaller than the spacing D2 between sub-pixels (i.e., D3 < D2). As a result, the light-transmitting portion AG can be maximized, and the transmittance in the sensing area CA can be improved.

[0066] The shape of each element in the translucent AG portion is in Figure 3A and Figure 3B The translucent portion AG is exemplified as a circle, but is not limited to this. For example, each of the translucent portions AG can be designed into various shapes such as circles, ellipses, polygons, etc. The translucent portion AG can be defined as the area in the screen where all metal layers have been removed.

[0067] All metal electrode material is removed from the light-transmitting portion AG. In the method of manufacturing a display panel, the metal used as the cathode can be uniformly deposited across the entire screen, and then the cathode layer can be removed only in the light-transmitting portion of the sensing area CA in a laser ablation process. In the laser ablation process, the cathode layer can be melted and removed while the laser beam is irradiated with spot beams and moved along the X and Y axes. The wavelength of the laser beam used in the laser ablation process is selected to have a high absorption coefficient for the cathode material. When the laser beam is irradiated with spot beams into the light-transmitting area, the diameter of the beam spot (BSPOT) formed on the cathode layer should be smaller than that of the light-transmitting portion AG, such as... Figure 4 As shown. When the cathode layer of the transparent portion of the AG is removed by a laser beam that is irradiated in a point (e.g.) Figure 4 and Figure 5 As shown, the processing time increases, and unwanted residual metal CR from the cathode layer not exposed to the beam spot may remain on the light-transmitting portion AG. When irradiating with a laser beam, sufficient margin (or tolerance) should be ensured between the display area DA and the sensing area CA so that the cathode of the pixel is not removed at the boundary between the display area DA and the sensing area CA.

[0068] In laser ablation processes, when the laser beam is only applied to the light-transmitting area in a point-like manner, the processing time increases, and the margin between the display area (DA) and the sensing area (CA) increases. Furthermore, since unwanted residual metal remains in the light-transmitting area, the transmittance in the image may decrease, and noise may increase. In this disclosure, to address the problems of using such a point-like laser ablation process, such as... Figure 6A and Figure 6B As shown, a light-shielding layer is formed in the screen of the display panel 100 to expose the light-transmitting area, and in the laser ablation process, a laser beam is irradiated in the shape of a line beam or a block beam.

[0069] Figure 6A This is a view showing a schematic cross-sectional structure of a display panel 100 according to an embodiment of the present disclosure and a laser beam irradiated in a laser ablation process. Figure 6B This is a schematic cross-sectional view showing a display panel according to another embodiment of the present disclosure and a laser beam irradiated in a laser ablation process.

[0070] refer to Figure 6A and Figure 6B The display panel 100 includes a light-shielding layer LS that blocks the laser beam and a metal layer ML that is exposed to the laser beam through an opening OP, wherein the light-shielding layer LS is removed from the opening OP.

[0071] According to one embodiment, such as Figure 6A As shown, the light-shielding layer LS can be deposited throughout the entire display area DA and the entire sensing area CA, and then patterned in a photolithography process. Specifically, the light-shielding layer LS can be formed throughout the entire display area DA and the entire sensing area CA, or at least formed in the pixel regions of the display area DA and the sensing area CA, and is removed from the aperture region that exposes the light-transmitting portion AG of the sensing area CA to define the aperture OP. On the other hand, according to another embodiment, such as... Figure 6B As shown, the light-shielding layer LS can be formed only in the sensing area CA and can be removed from the opening area, which exposes the light-transmitting portion AG of the sensing area CA to define the opening OP. The pixel area refers to the area in each of the display area DA and the sensing area CA where pixels PIX1 and PIX2 are disposed.

[0072] The metal layer ML is one of the metal layers required to drive the pixels of the display panel 100, and is a metal layer that should be removed from the light-transmitting portion AG of the sensing area CA. For example, the metal layer ML may be a cathode material layer or a metal layer formed on a layer other than a cathode material layer. When the metal layer ML is a metal that should be partially removed in a laser ablation process, the wavelength of the laser beam LB is determined in the wavelength band where the absorption coefficient of the metal is high.

[0073] In laser processing, the light-shielding layer LS should protect the metal layer ML in the screen, except for the light-transmitting portion AG of the sensing area CA, from the laser beam LB generated during the laser ablation process. Therefore, the light-shielding layer LS should be selected from a material with a low absorption coefficient at a certain wavelength of the laser beam LB.

[0074] When the metal layer ML is a Mg / Ag alloy thin film layer used as a cathode material, Mg has a high absorption coefficient at a wavelength of 1,064 nm. On the other hand, amorphous silicon (a-Si) or molybdenum (Mo) has a low absorption coefficient at a wavelength of 1,064 nm. Therefore, when the Mg / Ag alloy thin film layer is removed using a laser beam LB with a wavelength of 1,064 nm, the light-shielding layer LS used to protect the Mg / Ag thin film alloy layer from the laser beam in areas other than the light-transmitting portion includes materials such as amorphous silicon (a-Si) and molybdenum (Mo) that have a low absorption coefficient at a wavelength of 1,064 nm.

[0075] Due to the light-shielding layer LS formed on the display panel 100, the laser beam LB can irradiate in a linear or block shape during the laser ablation process. The length of the linear or block shape can be greater than the length of the sensing area CA. The length of the beam spot BSPOT of the laser beam LB irradiating the display panel 100 in a linear or block shape can be greater than or equal to the length of the sensing area CA in at least one direction (X-axis or Y-axis direction). When the beam spot BSPOT irradiates with a length greater than the sensing area CA, only a portion of the metal layer ML in the light-transmitting area exposed from the opening OP without the light-shielding layer LS can be exposed to the laser beam, while the metal layer ML in another area shielded by the light-shielding layer LS can be protected from the laser beam.

[0076] Laser ablation equipment can use a beam shaper or homogenizer (BSH) to generate linear or block beams with uniform laser beam intensity. Linear or block beams can be generated depending on the structure of the beam shaper (BSH), and the size of the laser beam (LB) can be adjusted according to the distance between the beam shaper (BSH) and the substrate of the display panel 100.

[0077] When a light-shielding layer LS formed on the display panel 100 is used to irradiate the entire sensing area CA with a laser beam LB during a laser ablation process, the metal layer ML can be completely removed from the light-transmitting portion AG of the sensing area CA simultaneously. In this case, the metal layer ML existing in the pixel array outside the light-transmitting portion AG is protected by the light-shielding layer LS and is not affected by the laser beam LB, so it is not removed during the laser ablation process. By irradiating the sensor area CA with only one laser beam, the metal layer ML can be removed only from the light-transmitting portion of the sensing area CA within the screen. Therefore, in this disclosure, the laser ablation processing time can be minimized, and the margin between the display area DA and the sensing area CA can be minimized. Furthermore, in this disclosure, by completely removing the metal layer ML from the light-transmitting portion AG without any residual metal, the transmittance of the sensing area CA can be increased, and the noise of the image data can be reduced.

[0078] Figures 7 to 9 This is a view illustrating various laser beams according to an embodiment of the present disclosure, which are particularly suitable for manufacturing Figure 6A The laser ablation process is shown in the display panel.

[0079] refer to Figure 7 In the laser ablation process, the laser beam LB is irradiated in a beam shape that spans the sensing area CA. Since the metal layer ML exposed to the laser beam LB is removed only through the opening OP without the light-shielding layer LS, the length of the laser beam LB can be sufficiently long. The width Wb of the laser beam LB can be greater than the diameter R or maximum length of the light-transmitting portion AG, and further can be greater than or equal to the diameter or maximum length of the sensing area CA.

[0080] The length L of the laser beam LB can be greater than or equal to the maximum length of the sensing area CA. The laser beam LB, irradiating the display panel 100 in a beam shape, scans the display panel 100 while moving along a first direction (X or Y axis). The laser beam LB has a large beam spot, thus irradiating not only the sensing area CA, but also a portion of the display area DA adjacent to the sensing area CA, or the entire surface of the display area DA. At least a portion of the laser beam can overlap (interlace) between previous and current beams, such that no residual metal is retained in the light-transmitting portion AG of the sensing area CA as the laser beam LB moves along the first direction.

[0081] The laser beam LB can scan the display panel 100 along a first direction (X or Y axis direction) and then along a second direction (X or Y axis direction) to ensure the removal of residual metal by removing the metal layer ML only in the light-transmitting area. Since the metal layer ML is a thin film, it can usually be removed without residual metal by performing a laser scan in only one direction.

[0082] refer to Figure 8 In laser ablation processes, a laser beam LB can be used as a bulk beam with a size greater than or equal to the light-transmitting portion AG and further greater than or equal to the sensing region CA. Therefore, due to the large beam spot of the laser beam LB irradiating in a bulk beam shape, the laser beam LB irradiates the entire surface of the light-transmitting portion AG in a single irradiation, and further, the entire surface of the sensing region CA in a single irradiation. Since the beam spot of the bulk beam covers the entire surface of the sensing region CA, a metal layer (e.g., a cathode) selected from all light-transmitting portions AG of the sensing region CA can be removed by a single laser beam irradiation.

[0083] The shape and size of the beam are determined by the beam shaper (BSH), and the intensity of the laser beam is constant within the block. The block beam can be a circular beam or a quadrilateral beam, but the shape is not limited to a specific shape.

[0084] Since only the metal layer ML exposed to the laser beam LB through the opening OP is removed, the size of the laser beam LB can be large enough. For example, a block-shaped laser beam formed on the display panel 100 can not only irradiate the sensing area CA at once, but also a portion or the entire surface of the display area DA adjacent to the sensing area CA at once. Therefore, the metal layer ML of all the light-transmitting portions AG can be removed from the screen simultaneously with a single irradiation by the laser beam LB, without any residual metal.

[0085] refer to Figure 9 It is possible to manufacture many display panels 100 simultaneously through a multi-faceted process.

[0086] The process of forming thin films on multiple cell units on the mother substrate MSUBS is performed simultaneously. Here, a cell unit is a single unit of the display panel 100. The circuit layer 12 of the cell unit is simultaneously formed on the mother substrate MSUBS. The circuit layer 12 includes a light-shielding layer LS that exposes the light-transmitting portion. When the metal layer formed in the light-transmitting portion of the circuit layer 12 is removed from the circuit layer 12, a laser ablation process can be performed.

[0087] In the manufacturing process of circuit layer 12, after forming the anode of the light-emitting element (OLED), an organic compound layer of light-emitting element layer 14 is deposited, and the light-emitting element layer 14 of the cell is simultaneously formed on the mother substrate MSUBS. After coating a protective layer and an encapsulation layer covering the light-emitting element layer 14, the mother substrate MSUBS is separated into cells by cutting along the scribing lines using a scribing wheel in a scribing process. After the scribing process, the contour of each display panel 100 is trimmed using a laser cutting device in a finishing process.

[0088] In the laser ablation process, a laser beam LB in the shape of a wire or a block beam can be irradiated onto the mother substrate MSUBS. In this case, the size of the beam spot can be larger than the size of the light-transmitting portion AG of the sensing area CA, and can have a size that can completely cover the sensing area CA or a larger size that can cover the unit cell CELL.

[0089] Figure 10 These are photographic images illustrating experimental results of removing a metal layer from a light-transmitting region after performing a laser ablation process according to an embodiment of this disclosure. Figure 10 It can be seen that a laser beam can be directed onto it (such as...). Figures 6A to 9 The light-transmitting portion AG of the sensing area CA (as shown) cleanly removes the metal layer ML without leaving any metal residue.

[0090] Figure 11 This is a block diagram illustrating a display panel and a display panel driving portion according to an embodiment of the present disclosure. Figure 12 This is a block diagram that schematically illustrates the configuration of the driver IC.

[0091] refer to Figure 11 and Figure 12 The display device includes a display panel 100 in which a pixel array is disposed on a screen, a display panel driving part, etc.

[0092] The pixel array of the display panel 100 includes data lines DL, gate lines GL intersecting the data lines DL, and pixels P arranged in a matrix form defined by the data lines DL and the gate lines GL. The pixel array also includes, for example,... Figure 13 and Figure 14 The power lines shown are VDD line PL1, Vini line PL2, and VSS line PL3.

[0093] like Figure 1 As shown, the pixel array can be divided into a circuit layer 12 and a light-emitting element layer 14. A touch sensor array can be disposed on the light-emitting element layer 14. As described above, each pixel in the pixel array can include two to four sub-pixels. Each of the sub-pixels includes pixel circuitry disposed on the circuit layer 12.

[0094] The screen that reproduces the input image on the display panel 100 includes a display area DA and a sensing area CA.

[0095] Each sub-pixel in the display area DA and the sensing area CA includes a pixel circuit. The pixel circuit may include a driving element, multiple switching elements, capacitors, etc., wherein the driving element supplies current to the light-emitting element (OLED), the multiple switching elements sample the threshold voltage of the driving element and switch the current path of the pixel circuit, and the capacitor maintains the gate voltage of the driving element. The pixel circuit is disposed below the light-emitting element.

[0096] As an example, the sensing area CA includes a light-transmitting portion AG disposed between pixel groups and an imaging element module (e.g., a camera) 400 disposed below the sensing area CA. The imaging element module 400 uses an image sensor to photoelectrically convert the light incident through the sensing area CA in imaging mode, converts pixel data of the image output from the image sensor into digital data, and then outputs the image data of the image.

[0097] The display panel driver writes the pixel data of the input image to pixel P. Pixel P can be interpreted as a group of pixels comprising multiple sub-pixels.

[0098] The display panel driving section includes: a data driving section 306 that supplies data voltages of pixel data to data lines DL; and a gate driving section 120 that sequentially supplies gate pulses to gate lines GL. The data driving section 306 can be integrated into a driver integrated circuit (IC) 300. The display panel driving section may also include a touch sensor driving section (not shown in the figure).

[0099] The driver IC 300 can be attached to the display panel 100. The driver IC 300 receives pixel data and timing signals of the input image from the host system 200 to supply the data voltage of the pixel data to the pixels and synchronize the data driving section 306 and the gate driving section 120.

[0100] The driver IC 300 is connected to the data line DL via a data output channel to supply the data voltage of the pixel data to the data line DL. The driver IC 300 can also output gate timing signals for controlling the gate drive section 120 via a gate timing signal output channel. The gate timing signals generated from the timing controller 303 may include a gate start pulse VST, a gate shift clock CLK, etc. The gate start pulse VST and the gate shift clock CLK oscillate between the gate on-voltage VGL and the gate off-voltage VGH. The gate timing signals VST and CLK output from the level shifter 307 are applied to the gate drive section 120 to control the shift operation of the gate drive section 120.

[0101] The gate driving section 120 may include a shift register formed on the circuit layer of the display panel 100 together with the pixel array. Under the control of the timing controller 303, the shift register of the gate driving section 120 sequentially supplies gate signals to the gate lines GL. The gate signals may include scan pulses and EM pulses of the light emission signal. The shift register may include a scan driving section that outputs scan pulses and an EM driving section that outputs EM pulses. Figure 12 In this context, GVST and GCLK are the gate timing signals input to the scan drive section. EVST and ECLK are the gate timing signals input to the EM drive section.

[0102] The driver IC 300 can be connected to the host system 200, the first memory (RAM) 301, and the display panel 100. The driver IC 300 may include a data receiving and calculation section 308, a timing controller 303, a data driving section 306, a gamma-compensated voltage generator 305, a power supply section 304, a second memory 302, etc.

[0103] The data receiving and processing section 308 includes: a receiving section that receives pixel data as a digital signal input from the host system 200; and a data processing section that processes the pixel data input through the receiving section to improve image quality. The data processing section may include: a data recovery section that decodes and recovers compressed pixel data; and an optical compensation section that adds a predetermined optical compensation value to the pixel data. The optical compensation value can be set as a value used to correct the brightness of each pixel data based on the brightness of the screen, which is based on camera image measurements acquired during the manufacturing process.

[0104] The timing controller 303 provides pixel data of the input image received from the host system 200 to the data driving section 306. The timing controller 303 generates gate timing signals for controlling the gate driving section 120 and source timing signals for controlling the data driving section 306, so as to control the operating timing of the gate driving section 120 and the data driving section 306.

[0105] The data driver section 306 converts the digital data, including pixel data, received from the timing controller 303 into a gamma-compensated voltage via a digital-to-analog converter (DAC) to output a data voltage. The data voltage output from the data driver section 306 is supplied to the data lines DL of the pixel array through an output buffer connected to the data channel of the driver IC 300.

[0106] The gamma compensation voltage generator 305 divides the gamma reference voltage from the power supply section 304 using a voltage divider circuit to generate a gamma compensation voltage for each grayscale level. The gamma compensation voltage is an analog voltage that sets the voltage for each grayscale level of the pixel data. The gamma compensation voltage output from the gamma compensation voltage generator 305 is provided to the data drive section 306.

[0107] Power supply section 304 uses a DC-DC converter to generate the power required to drive the pixel array, gate drive section 120, and driver IC 300 of display panel 100. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Power supply section 304 can regulate the DC input voltage from host system 200 to generate DC power (such as gamma reference voltage, gate on-state voltage VGL, gate off-state voltage VGH, pixel drive voltage VDD, low potential power supply voltage VSS, and initialization voltage Vini). The gamma reference voltage is supplied to gamma compensation voltage generator 305. Gate on-state voltage VGL and gate off-state voltage VGH are supplied to level shifter 307 and gate drive section 120. Pixel power, such as pixel drive voltage VDD, low potential power supply voltage VSS, and initialization voltage Vini, is collectively supplied to pixel P. The initialization voltage Vini is set to a DC voltage lower than pixel drive voltage VDD and lower than the threshold voltage of the light-emitting element (OLED) to initialize the main node of the pixel circuit and suppress the light emission of the light-emitting element (OLED).

[0108] When power is supplied to the driver IC 300, the second memory 302 stores compensation values, register setting data, etc., received from the first memory 301. These compensation values ​​can be applied to various algorithms to improve image quality. The compensation values ​​may include optical compensation values. The register setting data defines the operation of the data driver section 306, the timing controller 303, the gamma compensation voltage generator 305, etc. The first memory 301 may include flash memory. The second memory 302 may include static random access memory (SRAM).

[0109] The host system 200 can be implemented as an application processor (AP). The host system 200 can transmit pixel data of the input image to the driver IC 300 via a Mobile Industrial Processor Interface (MIPI). The host system 200 can be connected to the driver IC 300 via printed circuitry, such as a flexible printed circuit (FPC).

[0110] Meanwhile, the display panel 100 can be implemented as a flexible panel suitable for flexible displays. The screen size of the flexible display can be changed by rolling, folding, and bending the flexible panel, and flexible displays can be easily manufactured in various designs. Flexible displays can be implemented as rollable displays, foldable displays, bendable displays, sliding displays, etc. The flexible panel can be manufactured as a so-called "plastic OLED panel." A plastic OLED panel may include a backplane and a pixel array on an organic thin film bonded to the backplane. A touch sensor array can be formed on the pixel array.

[0111] The backsheet can be a polyethylene terephthalate (PET) substrate. The pixel array and touch sensor array can be formed on the organic thin film. The backsheet can prevent moisture from penetrating into the organic thin film, thus preventing the pixel array from being exposed to moisture. The organic thin film can be a polyimide (PI) substrate. A multilayer buffer film (not shown) made of insulating material can be formed on the organic thin film. The circuit layer 12 and the light-emitting element layer 14 can be stacked on the organic thin film.

[0112] In the display device of this disclosure, the pixel circuit, gate driving portion, etc., disposed on the circuit layer 12 may include a plurality of transistors. The transistors may be implemented as oxide thin-film transistors (TFTs) including oxide semiconductors, LTPS TFTs including low-temperature polycrystalline silicon (LTPS), etc. Each of the transistors may be implemented as a p-channel TFT or an n-channel TFT. In this embodiment, an example in which the transistors of the pixel circuit are implemented as p-channel TFTs is described, but this disclosure is not limited thereto.

[0113] A transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers begin to flow from the source. The drain is the electrode through which charge carriers flow out of the transistor. In a transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. In the case of an n-channel transistor, current flows from the drain to the source. In the case of a p-channel transistor (PMOS), since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In the case of a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, this disclosure is not limited to the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0114] The gate pulse oscillates between the gate on-voltage and the gate off-voltage. The gate on-voltage is set to a voltage higher than the transistor's threshold voltage, and the gate off-voltage is set to a voltage lower than the transistor's threshold voltage. The transistor turns on in response to the gate on-voltage but turns off in response to the gate off-voltage. In the case of an n-channel transistor, the gate on-voltage can be the gate high voltage VGH, and the gate off-voltage can be the gate low voltage VGL. In the case of a p-channel transistor, the gate on-voltage can be the gate low voltage VGL, and the gate off-voltage can be the gate high voltage VGH.

[0115] The driving element of a pixel circuit can be implemented as a transistor. The driving element should have uniform electrical characteristics across all pixels; however, due to variations in process technology and element characteristics, differences may exist between pixels, and the electrical characteristics may change over time as the display drives the image. To compensate for these variations in the driving element's electrical characteristics, the display device may include internal and external compensation circuits. The internal compensation circuit samples the threshold voltage (Vth) and / or mobility (μ) of the driving element, which is added to the pixel circuit in each sub-pixel and varies according to the driving element's electrical characteristics, compensating for these changes in real time. The external compensation circuit transmits the threshold voltage and / or mobility of the driving element, sensed via a sensing line connected to each sub-pixel, to an external compensation section. The compensation section of the external compensation circuit compensates for the variations in the driving element's electrical characteristics by reflecting the sensing results and modulating the pixel data of the input image. Because the pixel voltage, which changes according to the external compensation driving element's electrical characteristics, is sensed, and the external circuit modulates the input image data based on the sensed voltage, the variations in the driving element's electrical characteristics between pixels are compensated.

[0116] Figure 13 and Figure 14 This is a circuit diagram illustrating an example of a pixel circuit that incorporates internal compensation circuitry. Figure 15 It shows the driver Figure 13 and Figure 14 A view of the pixel circuit method shown. It should be noted that the pixel circuit of this disclosure is not limited to... Figure 13 and Figure 14 . Figure 13 and Figure 14 The pixel circuit shown can be equivalently applied to the pixel circuits of the display area DA and the sensing area CA. The pixel circuit suitable for this disclosure can be implemented as follows: Figure 13 and Figure 14 The circuit shown is not limited to this.

[0117] refer to Figures 13 to 15The pixel circuit includes: an OLED light-emitting element; a driving element DT that supplies current to the OLED; and an internal compensation circuit that compensates the gate voltage of the driving element DT to be as large as the threshold voltage Vth of the driving element DT by sampling the threshold voltage Vth of the driving element DT using multiple switching elements M1 to M6. Each of the driving element DT and the switching elements M1 to M6 can be implemented as a p-type channel TFT.

[0118] like Figure 15 As shown, the driving period of the pixel circuit using the internal compensation circuit can be divided into the initialization period Tini, the sampling period Tsam, the data writing period Twr, and the emission period Tem.

[0119] During the initialization period Tini, the (N-1)th scan signal SCAN(N-1) is generated as a pulse of the gate on-state voltage VGL, and the voltage of each of the Nth scan signal SCAN(N) and the light-emitting signal EM(N) is the gate off-state voltage VGH. During the sampling period (Tsam), the Nth scan signal SCAN(N) is generated as a pulse of the gate on-state voltage VGL, and the voltage of each of the (N-1)th scan signal SCAN(N-1) and the light-emitting signal EM(N) is the gate off-state voltage VGH. During the data writing period Twr, the voltage of each of the (N-1)th scan signal SCAN(N-1), the Nth scan signal SCAN(N), and the light-emitting signal EM(N) is the gate off-state voltage VGH. During at least a portion of the light-emitting period Tem, the light-emitting signal EM(N) is generated as the gate on-state voltage VGL, and the voltage of each of the (N-1)th scan signal SCAN(N-1) and the Nth scan signal SCAN(N) is generated as the gate off-state voltage VGH.

[0120] During the initialization period Tini, the fifth switching element M5 is turned on according to the gate on-state voltage VGL of the (N-1)th scan signal SCAN(N-1) to initialize the pixel circuit. During the sampling period Tsam, the threshold voltage of the driving element DT is sampled and stored in the capacitor Cst1 because the first switching element M1 and the second switching element M2 are turned on according to the gate on-state voltage VGL of the Nth scan signal SCAN(N). Simultaneously, the sixth switching element M6 is turned on during the sampling period Tsam to reduce the voltage of the fourth node n4 to the reference voltage Vref, thereby suppressing the emission of the light-emitting element OLED. During the data writing period Twr, the first to sixth switching elements M1 to M6 remain in the off state. During the emission period Tem, the third switching element M3 and the fourth switching element M4 are turned on, causing the light-emitting element OLED to emit light. During the light emission period Tem, in order to accurately represent the brightness of the low gray level using the duty cycle of the light emission signal EM(N), the light emission signal EM(N) oscillates between the gate turn-on low voltage VGL and the gate turn-off voltage VGH with a predetermined duty cycle, so the third and fourth switching elements M3 and M4 can be repeatedly turned on / off.

[0121] The light-emitting element OLED can be implemented as an organic light-emitting diode or an inorganic light-emitting diode. An example of implementing the light-emitting element OLED as an organic light-emitting diode will be described below.

[0122] An OLED (Light Emitting Diode) may include an organic compound layer formed between an anode and a cathode. This organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode and cathode of the OLED, visible light is emitted from the emissive layer (EML) as holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emissive layer (EML) and excitons are formed.

[0123] The anode of the OLED is connected to a fourth node n4 between the fourth and sixth switching elements M4 and M6. The fourth node n4 is connected to the anode of the OLED, the second electrode of the fourth switching element M4, and the second electrode of the sixth switching element M6. The cathode of the OLED is connected to the VSS line PL3, to which a low-potential power supply voltage VSS is applied. The OLED emits light using a current Ids flowing according to the gate-source voltage Vgs of the driving element DT. The current path of the OLED is switched by the third and fourth switching elements M3 and M4.

[0124] Storage capacitor Cst1 is connected between VDD line PL1 and the first node n1. Data voltage Vdata, compensated by the threshold voltage Vth of the driving element DT, is charged into storage capacitor Cst1. Since the data voltage Vdata in each sub-pixel is compensated to be as large as the threshold voltage Vth of the driving element DT, the characteristic variation of the driving element DT is compensated in the sub-pixel.

[0125] The first switching element M1 is turned on in response to the gate turn-on voltage VGL of the Nth scan pulse SCAN(N) to connect the second node n2 and the third node n3. The second node n2 is connected to the gate of the driving element DT, the first electrode of the storage capacitor Cst1, and the first electrode of the first switching element M1. The third node n3 is connected to the second electrode of the driving element DT, the second electrode of the first switching element M1, and the first electrode of the fourth switching element M4. The gate of the first switching element M1 is connected to the first gate line GL1 to receive the Nth scan pulse SCAN(N). The first electrode of the first switching element M1 is connected to the second node n2, and the second electrode of the first switching element M1 is connected to the third node n3.

[0126] Since the first switching element M1 is turned on only for a very short horizontal period (1H) during which the Nth scan signal SCAN(N) is generated as the gate on-state voltage VGL in a frame cycle, and therefore remains in the off state for approximately one frame cycle, leakage current may occur in the off state of the first switching element M1. To suppress the leakage current of the first switching element M1, the first switching element M1 can be implemented as a transistor with a dual-gate structure, wherein the two transistors M1a and M1b are as follows: Figure 14 The series connection is shown.

[0127] The second switching element M2 is turned on in response to the gate turn-on voltage VGL of the Nth scan pulse SCAN(N) to supply the data voltage Vdata to the first node n1. The gate of the second switching element M2 is connected to the first gate line GL1 to receive the Nth scan pulse SCAN(N). The first electrode of the second switching element M2 is connected to the first node n1. The second electrode of the second switching element M2 is connected to the data line DL to which the data voltage Vdata is applied. The first node n1 is connected to the first electrode of the second switching element M2, the second electrode of the third switching element M3, and the first electrode of the driving element DT.

[0128] The third switching element M3 is turned on in response to the gate turn-on voltage VGL of the light-emitting signal EM(N) to connect the VDD line PL1 to the first node n1. The gate of the third switching element M3 is connected to the third gate line GL3 to receive the light-emitting signal EM(N). The first electrode of the third switching element M3 is connected to the VDD line PL1. The second electrode of the third switching element M3 is connected to the first node n1.

[0129] The fourth switching element M4 is turned on in response to the gate turn-on voltage VGL of the light-emitting signal EM(N) to connect the third node n3 to the anode of the light-emitting element OLED. The gate of the fourth switching element M4 is connected to the third gate line GL3 to receive the light-emitting signal EM(N). The first electrode of the fourth switching element M4 is connected to the third node n3, and the second electrode of the fourth switching element M4 is connected to the fourth node n4.

[0130] The fifth switching element M5 is turned on in response to the gate turn-on voltage VGL of the (N-1)th scan pulse SCAN(N-1), connecting the second node n2 to the Vini line PL2. The gate of the fifth switching element M5 is connected to the second gate line GL2 to receive the (N-1)th scan pulse SCAN(N-1). The first electrode of the fifth switching element M5 is connected to the second node n2, and the second electrode of the fifth switching element M5 is connected to the Vini line PL2. To suppress the leakage current of the fifth switching element M5, the fifth switching element M5 is implemented as a transistor with a dual-gate structure, wherein the two transistors M5a and M5b are as follows: Figure 14 The series connection is shown.

[0131] The sixth switching element M6 is turned on in response to the gate turn-on voltage VGL of the Nth scan pulse SCAN(N) to connect the Vini line PL2 to the fourth node n4. The gate of the sixth switching element M6 is connected to the first gate line GL1 to receive the Nth scan pulse SCAN(N). The first electrode of the sixth switching element M6 is connected to the Vini line PL2, and the second electrode of the sixth switching element M6 is connected to the fourth node n4.

[0132] The driving element DT drives the OLED by controlling the current Ids flowing through the OLED according to the gate-source voltage Vgs. The driving element DT includes a gate connected to the second node n2, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0133] like Figure 15As shown, during the initialization period Tini, the (N-1)th scan pulse SCAN(N-1) is generated as the gate on-state voltage VGL. During the initialization period Tini, the Nth scan pulse SCAN(N) and the emission signal EM(N) maintain the gate off-state voltage VGH. Therefore, since the fifth switching element M5 is turned on during the initialization period Tini, the second node n2 and the fourth node n4 are initialized to the initialization voltage Vini. A hold period Th can be set between the initialization period Tini and the sampling period Tsam. During the hold period Th, the gate pulses SCAN(N-1), SCAN(N), and EM(N) maintain their previous states.

[0134] During the sampling period Tsam, the Nth scan pulse SCAN(N) is generated as the gate on-state voltage VGL. The pulse of the Nth scan pulse SCAN(N) is synchronized with the data voltage Vdata of the Nth pixel line. During the sampling period Tsam, the (N-1)th scan pulse SCAN(N-1) and the light emission signal EM(N) maintain the gate off-state voltage VGH. Therefore, during the sampling period Tsam, the first switching element M1 and the second switching element M2 are turned on.

[0135] During the sampling period Tsam, the gate voltage DTG of the driving element DT increases due to the current flowing through the first switching element M1 and the second switching element M2. When the driving element DT is turned off, the gate node voltage DTG is Vdata - |Vth|. In this case, the voltage of the first node n is also Vdata - |Vth|. During the sampling period Tsam, the gate-source voltage Vgs of the driving element DT is |Vgs| = Vdata - (Vdata - |Vth|) = |Vth|.

[0136] During the data write period Twr, the Nth scan pulse SCAN(N) is inverted to the gate cutoff voltage VGH. During the data write period Twr, the (N-1)th scan pulse SCAN(N-1) and the light emission signal EM(N) maintain the gate cutoff voltage VGH. Therefore, all switching elements M1 to M6 remain in the off state during the data write period Twr.

[0137] During the emission period Tem, the emission signal EM(N) can be generated as a gate on-state voltage VGL. During the emission period Tem, the emission signal EM(N) is turned on and off with a predetermined duty cycle to improve the representation of low gray levels, and therefore can swing between the gate on-state voltage VGL and the gate off-state voltage VGH. Thus, the emission signal EM(N) can be generated as a gate on-state voltage VGL during at least a portion of the emission period Tem.

[0138] When the emission signal EM(N) is the gate on-state voltage VGL, the OLED emits light as current flows from VDD to the OLED. During the emission period Temp, the (N-1)th and Nth scan pulses SCAN(N-1) and SCAN(N) maintain the gate off-state voltage VGH. During the emission period Temp, the third and fourth switching elements M3 and M4 repeatedly turn on and off according to the voltage of the emission signal EM. When the emission signal EM(N) is the gate on-state voltage VGL, current flows through the OLED as the third switching element M3 and the fourth switching element M4 are turned on. In this case, the gate-source voltage Vgs of the driving element DT is |Vgs| = VDD - (Vdata - |Vth|), and the current flowing through the OLED is K(VDD - Vdata)². K is a constant value determined by charge mobility, parasitic capacitance, and channel capacitance of the driving element DT.

[0139] Figure 16 This is a cross-sectional view showing in detail the cross-sectional structure of a display panel according to an embodiment of the present disclosure. It should be noted that the cross-sectional structure of the display panel 100 is not limited to... Figure 16 .exist Figure 16 In this context, TFT represents the driving element DT of the pixel circuit.

[0140] refer to Figure 16 Circuit layer 12, light-emitting element layer 14, etc., can be stacked on substrates PI1 and PI2. Substrates PI1 and PI2 can include a first PI substrate PI1 and a second PI substrate PI2. An inorganic film IPD can be formed between the first PI substrate PI1 and the second PI substrate PI2. The inorganic film IPD blocks moisture penetration.

[0141] The first buffer layer BUF1 can be formed on the second PI substrate PI2. For example... Figure 21 As shown, the first buffer layer BUF1 can be composed of two or more oxide films SiO2 and nitride films SiN stacked therein. x A multilayer insulating film is formed. A first metal layer can be formed on the first buffer layer BUF1, and a second buffer layer BUF2 can be formed on the first metal layer. The first metal layer is patterned in a photolithography process. The first metal layer may include a bottom masking metal pattern BSM. The bottom masking metal pattern BSM blocks external light so that light does not shine on the active layer of the TFT, thereby preventing photocurrent of the TFT formed in the pixel area. When the bottom masking metal pattern BSM is formed of a metal with a lower absorption coefficient for the laser wavelength used in the laser ablation process compared to the metal layer ML that should be removed from the sensing area CA, the bottom masking metal pattern BSM can also be used as a light-shielding layer LS, which blocks the laser beam LB in the laser ablation process.

[0142] Each of the first buffer layer BUF1 and the second buffer layer BUF2 may be formed of an inorganic insulating material and may be formed of one or more insulating layers.

[0143] The active layer ACT is formed from semiconductor material deposited on the second buffer layer BUF2 and can be patterned using photolithography. The active layer ACT includes active patterns for each of the TFTs in the pixel circuit and the TFTs in the gate driving portion. A portion of the active layer ACT can be metallized by ion doping. The metallized portion can be used as a bridging pattern that connects the metal layers at some nodes of the pixel circuit to connect components of the pixel circuit.

[0144] A gate insulating layer GI can be formed on the second buffer layer BUF2 to cover the active layer ACT. The gate insulating layer GI can be formed of an inorganic insulating material. A second metal layer can be formed on the gate insulating layer GI. The second metal layer can be patterned using a photolithography process. The second metal layer may include gate lines and gate patterns GATE, the lower electrode of the storage capacitor Cst1, and bridging patterns connecting the patterns of the first and third metal layers, etc.

[0145] A first interlayer insulating layer (ILD1) can be formed on the gate insulating layer (GI) to cover the second metal layer. A third metal layer can be formed on the first interlayer insulating layer (ILD1), and a second interlayer insulating layer (ILD2) can cover the third metal layer. The third metal layer can be patterned using a photolithography process. The third metal layer may include a metal pattern TM such as the upper electrode of a storage capacitor (Cst1). The first interlayer insulating layer (ILD1) and the second interlayer insulating layer (ILD2) may include inorganic insulating materials.

[0146] A fourth metal layer can be formed on the second interlayer insulating layer ILD2, and an inorganic insulating layer PAS1 and a first planarization layer PLN1 can be stacked on it. A fifth metal layer can be formed on the first planarization layer PLN1.

[0147] Some patterns of the fourth metal layer can be connected to the third metal layer through contact holes passing through the first planarization layer PLN1 and the inorganic insulating layer PAS1. The first planarization layer PLN1 and the second planarization layer PLN2 can be formed of an organic insulating material that planarizes the surface.

[0148] The fourth metal layer may include the first and second electrodes of the TFT connected to the active pattern of the TFT through contact holes passing through the second interlayer insulating layer ILD2. Data lines DL and power lines PL1, PL2, and PL3 may be implemented as either the fourth metal layer pattern SD1 or the fifth metal layer pattern SD2.

[0149] The anode AND of the OLED light-emitting element can be formed on the second planarization layer PLN2. The anode AND can be connected to the electrode of the TFT used as a switching element or driving element through the contact hole of the second planarization layer PLN2. The anode AND can be formed of a transparent or translucent electrode material.

[0150] Pixel-defining films (BNKs) can cover the anode and AND of an OLED light-emitting element. The BNK is formed in a pattern defining a light-emitting region (or opening region) from which light travels from each pixel to the outside. Spacers (SPCs) can be formed on the BNK. The BNK and SPC can be integrated together using the same organic insulating material. The SPC ensures a gap between the fine metal mask (FMM) and the anode and AND, preventing the FMM from contacting the anode and AND during the deposition of the organic compound (EL).

[0151] Organic compound EL is formed in the light-emitting region of each pixel defined by the pixel defining film BNK. The cathode CAT of the OLED is formed on the entire surface of the display panel 100 to cover the pixel defining film BNK, spacer SPC, and organic compound EL. The cathode CAT may be connected to a VSS line PL3 formed by any of the underlying metal layers. A capping layer CPL may cover the cathode CAT. The capping layer CPL protects the cathode CAT by forming an inorganic insulating material on it, thus blocking the venting of the organic insulating material applied to the capping layer CPL and the permeation of air. An inorganic insulating layer PAS2 may cover the capping layer CPL, and a planarization layer PCL may be formed on the inorganic insulating layer PAS2. The planarization layer PCL may include an organic insulating material. An inorganic insulating layer PAS3, which forms an encapsulation layer, may be formed on the planarization layer PCL.

[0152] Figure 17 and Figure 18 This is a cross-sectional view showing the light-shielding layer LS of the pixel region and the light-transmitting portion AG of the sensing region CA in the cross-sectional structure of a display panel according to various embodiments of the present disclosure. Figure 17 and Figure 18 In, with Figure 16 Components that are substantially the same as those shown are indicated by the same reference numerals, and their detailed descriptions will be omitted.

[0153] refer to Figure 17 The light-shielding layer LS protects the pixel areas PIX of the display area DA and the sensing area CA from the laser beam LB that irradiates the display panel 100 during the laser ablation process.

[0154] A light-shielding layer LS is removed from the area of ​​the light-transmitting portion AG to define an opening OP that exposes the light-transmitting portion AG to the laser beam. The laser beam LB, generated in the laser ablation process, passes through the opening OP of the light-shielding layer LS to remove the metal layer to be removed (e.g., cathode metal in the light-transmitting portion). Each of the pixel areas (second pixel areas) of the display area DA and the sensing area CA includes a light-shielding layer and a metal layer having a higher absorption coefficient than the light-shielding layer for a specific wavelength of the laser beam. The metal layer of the cathode CAT may include magnesium (Mg).

[0155] A light-shielding layer LS can be disposed below the TFT in the pixel area to prevent photocurrent in the TFT. In this case, the light-shielding layer LS can be formed of a metal whose absorption coefficient to the wavelength of the laser beam is lower than that of the metal layer to be removed. When the metal layer to be removed is a cathode material formed of Mg / Ag alloy, the light-shielding layer LS can be formed of Mo, which has a lower absorption coefficient to a laser beam LB with a wavelength of 1,064 nm than Mg. Mo is a metal with high light reflectivity, and therefore can prevent photocurrent in the TFT by reflecting external light.

[0156] Figure 17 The light-shielding layer LS shown is disposed between the inorganic insulating layers BUF1 and BUF2 below the TFT in the pixel region PIX.

[0157] Figure 18 The example shown is formed from amorphous silicon (a-Si). Since amorphous silicon has a lower absorption coefficient for a laser beam LB with a wavelength of 1,064 nm than Mg, the upper metal layer can be protected from the laser beam used to remove Mg and Ag during the laser ablation process. In this case, since the light-shielding layer LS may not be able to block external light affecting the TFTs of the pixel region PIX, a separate bottom-shielding metal pattern BSM can be added to the pixel region PIX. Figure 18 The bottom-masking metal pattern (BSM) shown is positioned between the inorganic insulating layers BUF2 and BUF3 below the TFT in the pixel region (PIX). Figure 18 In the process, the second buffer layer BUF2 is an inorganic insulating layer formed between the light-shielding layer LS and the bottom masking metal pattern BSM in the pixel region PIX. The third buffer layer BUF3 is an inorganic insulating layer formed between the light-shielding layer LS and the active layer ACT in the pixel region PIX.

[0158] All metal layers in the pixel region (PIX) are removed from the light-transmitting portion (AG). Therefore, only a transparent insulating layer may exist in the light-transmitting portion (AG).

[0159] like Figure 19As shown, one of the PI substrates PI1 and PI2 can be removed from the light-transmitting portion AG. One or more of the inorganic insulating layers BUF1, BUF2, GI, ILD1, ILD2, and PAS1 can be removed from the light-transmitting portion AG, and one or more of the active layer ACT, pixel-defining film BNK, and spacer SPC can also be removed. Since the insulating layers are removed from the light-transmitting portion AG, the recessed portion can be filled with the organic insulating layers PLN1 and PLN2.

[0160] In the photolithography process for patterning the metal layer of a display panel, a difference in etch rate may occur when there is a large density difference between the metal pattern in the display area DA and the metal pattern in the sensing area CA. This difference in etch rate can lead to dimensional differences in gaps and overlapping areas between the patterned metal patterns, potentially resulting in critical size (CD) defects. In this disclosure, to minimize the density difference between the metal pattern in the display area DA and the metal pattern in the sensing area CA, such as... Figure 20A As shown, a dummy pattern DPIX with the same pattern shape as the pixel area PIX can be formed on the metal layer of the light-transmitting portion AG, and then it can be... Figure 20B The process illustrated involves using a light-shielding layer LS to remove at least a portion of the metal layer ML in the light-transmitting portion AG during laser ablation. The metal layer ML, excluding the opening OP of the light-shielding layer LS, remains on the sensing area CA, and the dummy pattern DP facing the opening OP of the light-shielding layer LS can be removed. Here, the metal layer ML can be one or more of the first to fifth metal layers of the circuit layer 12. The light-shielding layer LS can be selected from a material whose absorption coefficient at the wavelength of the laser beam removing the metal layer is lower than that of the metal layer.

[0161] In the above embodiments, the semiconductor layer ACT can be disposed above the light-shielding layer LS. The semiconductor layer ACT can be formed of amorphous silicon (a-Si). To increase the electron mobility of the semiconductor layer ACT, the amorphous silicon (a-Si) can be crystallized. For this purpose, the amorphous silicon (a-Si) of the semiconductor layer ACT can be crystallized in a laser crystallization (excimer laser annealing (ELA)) process, such as... Figure 21 As shown, amorphous silicon (a-Si) is transformed into polycrystalline silicon with a polycrystalline structure through laser crystallization. During laser crystallization, interlayer separation or film delamination may occur between the light-shielding layer LS and its adjacent layer.

[0162] For example, when the light-shielding layer LS is formed of amorphous silicon (a-Si), hydrogen (H2) atoms can bond to dangling bonds (or unsaturated bonds) in the amorphous silicon (a-Si). In laser crystallization processes, the amorphous silicon film used as the semiconductor layer ACT is scanned by a laser beam (line beam) with a wavelength of 308 nm at a high temperature (e.g., 1,400°C or higher) above or equal to the melting temperature of amorphous silicon (a-Si). In this case, film delamination of the light-shielding layer LS may occur because hydrogen atoms penetrating into the amorphous silicon (a-Si) used as the light-shielding layer may explode at a temperature of approximately 450°C. To prevent this, the light-shielding layer LS can be sandwiched between materials that do not contain hydrogen or have a very low hydrogen content. Figure 21 In the example, the second oxide film OX2 is disposed between the semiconductor layer ACT and the light-shielding layer LS. The first oxide film OX1 may be disposed between the light-shielding layer LS and the first buffer layer BUF1 below the light-shielding layer LS.

[0163] exist Figure 21 In this structure, a light-shielding layer LS is formed between the first and second oxide films OX1 and OX2, which do not contain hydrogen atoms. Because hydrogen atoms are not bonded to the amorphous silicon (a-Si) used as the light-shielding layer LS, film delamination of the light-shielding layer LS during laser crystallization is prevented.

[0164] exist Figure 21 In this design, the first and second oxide films OX1 and OX2 are exemplified as silicon oxide films (SiO2), but are not limited thereto. For example, each of the oxide films OX1 and OX2 can be formed as a single-layer or multi-layer film selected from silicon oxide (SiO2), zirconium oxide (ZrO2), and hafnium oxide (HfO2). The first and second oxide films OX1 and OX2 can be formed from oxide films of the same material and can have the same thickness. Moreover, the first and second oxide films OX1 and OX2 can be formed from oxide films of different materials, or can be formed with different thicknesses.

[0165] like Figure 22AAs shown, according to an example of this disclosure, multiple sensor modules can be disposed in a sensing region CA. For example, an infrared sensor module (not shown) can be further disposed in the sensing region CA together with the imaging element module 400. Another sensor, such as an illuminance sensor or a proximity sensor, can be additionally disposed in the sensing region CA. Low PPI pixels and light-transmitting portions AG can be disposed above the light-receiving surfaces 401 and 402 of the imaging element module 400 and the infrared sensor module, respectively. Since the transmittance of infrared wavelengths in the thin film of the sensing region CA is higher than that of visible light wavelengths, the number and / or size of the light-transmitting portions AG in the light-receiving surface 402 of the infrared sensor module can be smaller than, or the light-transmitting portions AG may be absent, compared to the light-receiving surface 401 of the imaging element module. Meanwhile, the infrared sensor module can sense infrared light and can be used for facial recognition.

[0166] By dividing the sensing area CA into regions, the light-shielding layer LS can be formed from a variety of different materials. For example, such as Figure 22A As shown, when the infrared sensor module and the imaging element module are disposed on the sensing area CA, the transparency of the light-shielding layer LS in the area where the infrared sensor module is located can be higher than the transparency of the light-shielding layer LS in the area where the imaging element module 400 is located. The transparency of the light-shielding layer LS can vary depending on any electronic module located in the area where the light-shielding layer LS is located. For example, amorphous silicon (a-Si) can be used as the light-shielding layer LS on the light-receiving surface 402 of the infrared sensor module, and molybdenum (Mo) can be used as the light-shielding layer LS on the light-receiving surface 401 of the imaging element module.

[0167] As Figure 22A Variations or alternatives to the example shown Figure 22B Another example of this disclosure is shown, in which only one sensor module (e.g., a light sensor module other than the imaging element module) is disposed in the sensing area CA. As an example, the single sensor module includes, but is not limited to, an infrared sensor module.

[0168] In this disclosure, since a light-shielding layer with a low absorption coefficient for a specific laser wavelength is disposed in the pixel area other than the metal layer to be removed, the light-transmitting portion of the sensing area can be removed simultaneously by a large laser beam in the shape of a linear or block beam. Therefore, in this disclosure, the metal layer can be removed cleanly and quickly from the light-transmitting portion without residual metal, and the manufacturing cost of the display panel can be reduced by minimizing laser ablation processing time and defect rate.

[0169] In this disclosure, the transmittance of the sensing area can be increased by completely removing the metal layer from the light-transmitting portion without any residual metal, and the margin between the display area and the sensing area can be minimized.

[0170] Furthermore, in this disclosure, since the metal layer is removed from the light-transmitting portion without any residual metal, the transmittance of the sensing area can be increased, and the noise of the image data can be reduced.

[0171] The effects achievable through this disclosure are not limited to those described above. In other words, those skilled in the art to which this disclosure pertains will clearly understand from the following description other purposes not mentioned.

[0172] Although embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the present disclosure is not limited to these embodiments, and various changes and modifications can be made without departing from the technical spirit of the present disclosure. Therefore, the embodiments disclosed herein should be considered descriptive rather than restrictive of the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by the embodiments. Thus, it should be understood that the above embodiments are illustrative in all respects and not restrictive. The scope of the present disclosure should be interpreted by the appended claims, and all technical spirit within the scope of its equivalents should be interpreted as included within the scope of this disclosure.

Claims

1. A display panel comprising: The display area includes a first pixel area in which a plurality of pixels are disposed; as well as The sensing area includes a second pixel area in which a plurality of pixel groups are disposed and a light-transmitting portion disposed between the plurality of pixel groups; The sensing area includes: Light-shielding layer; and A metal layer disposed above the light-shielding layer, The light-shielding layer in the sensing area includes a first hole corresponding to the light-transmitting portion, and the metal layer in the sensing area includes a second hole that overlaps with the first hole in the light-shielding layer.

2. The display panel according to claim 1, wherein, The first pixel region includes: The light-shielding layer extends from the sensing area; The cathode layer on the light-shielding layer; The capping layer on the cathode layer; and The encapsulation layer on the capping layer.

3. The display panel according to claim 2, wherein, The light-shielding layer comprises a material whose absorption coefficient at a specific wavelength of the laser beam is lower than that of the cathode.

4. The display panel according to claim 2, wherein, The first pixel region includes: A semiconductor layer disposed between the cathode layer and the light-shielding layer; A first oxide film disposed beneath the light-shielding layer; and A second oxide film is disposed between the semiconductor layer and the light-shielding layer.

5. The display panel according to claim 4, wherein: Each of the semiconductor layer and the light-shielding layer comprises amorphous silicon; and The first oxide film and the second oxide film are formed from a single layer or a multilayer film selected from silicon oxide film (SiO2), zirconium oxide film (ZrO2) and hafnium oxide film (HfO2).

6. The display panel according to claim 1, further comprising a circuit layer disposed in the first pixel region and the second pixel region. in, The circuit layer includes multiple transistors.

7. The display panel according to claim 1, further comprising a third hole in the light-emitting element in the second pixel region of the sensing area. in, The third hole overlaps with the first hole in the light-shielding layer and the second hole in the metal layer.

8. The display panel according to claim 1, wherein, The light-transmitting portion includes: A cathode layer extending from the first pixel region; The capping layer on the cathode layer; and The encapsulation layer on the capping layer.

9. The display panel according to claim 8, wherein, The light-shielding layer comprises a material whose absorption coefficient at a specific wavelength of the laser beam is lower than that of the cathode.

10. The display panel according to claim 6, wherein, Each of the display area and the sensing area further includes another light-shielding pattern disposed between the light-shielding layer and the transistor; and The other light-shielding pattern includes metal.

11. A display device comprising: A substrate having a display area and a sensing area; The light-shielding layer on the sensing area; The transistor is disposed above the light-shielding layer; as well as The cathode layer on the transistor; The display area includes a plurality of first pixels; The sensing area includes a plurality of second pixels and a light-transmitting portion disposed between at least two of the plurality of second pixels; Both the light-shielding layer and the cathode layer have openings in the light-transmitting portion.

12. The display device according to claim 11, wherein, The display area includes: A light-shielding layer extending from the sensing area; The cathode layer on the light-shielding layer; The capping layer on the cathode layer; and The encapsulation layer on the capping layer.

13. The display device according to claim 12, wherein, The light-shielding layer comprises a material whose absorption coefficient at a specific wavelength of the laser beam is lower than that of the cathode.

14. The display device according to claim 12, wherein, The display area includes: The semiconductor layer of the transistor disposed between the cathode layer and the light-shielding layer; A first oxide film disposed beneath the light-shielding layer; and A second oxide film is disposed between the semiconductor layer and the light-shielding layer.

15. The display device according to claim 14, wherein: Each of the semiconductor layer and the light-shielding layer comprises amorphous silicon; and The first oxide film and the second oxide film are formed from a single layer or a multilayer film selected from silicon oxide film (SiO2), zirconium oxide film (ZrO2) and hafnium oxide film (HfO2).

16. The display device of claim 11, further comprising another opening in the light-emitting element layer in the sensing region. in, The other opening overlaps with the openings of the light-shielding layer and the cathode layer.

17. The display device according to claim 11, wherein, The light-transmitting portion includes: A cathode layer extending from the display area; The capping layer on the cathode layer; and The encapsulation layer on the capping layer.

18. The display device according to claim 17, wherein, The light-shielding layer comprises a material whose absorption coefficient at a specific wavelength of the laser beam is lower than that of the cathode.

19. The display device according to claim 11, wherein, The number of pixels per unit area of ​​the sensing area is lower than the number of pixels per unit area of ​​the display area.

20. The display device according to claim 11, wherein, Each of the display area and the sensing area further includes another light-shielding pattern disposed between the light-shielding layer and the transistor; and The other light-shielding pattern includes metal.

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