Chip heat dissipation structure and preparation method thereof

Abstract

The invention provides a chip heat dissipation structure and a preparation method thereof. The chip heat dissipation structure comprises a substrate; the first chip and the second chip are arranged on the same side of the substrate, and the active surface of the first chip and the active surface of the second chip are arranged towards the substrate; a first heat dissipation channel is formed in the surface of one side, deviating from the substrate, of the first chip, and a second heat dissipation channel is formed in the surface of one side, deviating from the substrate, of the second chip; the first heat dissipation structure is arranged on the side, away from the substrate, of the first chip, and the first heat dissipation channel is filled with the first heat dissipation structure; the second heat dissipation structure is arranged on the side, away from the substrate, of the second chip, and the second heat dissipation channel is filled with the second heat dissipation structure; wherein the surface of one side, deviating from the substrate, of the first heat dissipation structure and the surface of one side, deviating from the substrate, of the second heat dissipation structure are coplanar. Through the coplanar design, the arrangement of a thin thermal interface layer is facilitated, the thermal resistance is reduced, and the overall heat dissipation efficiency and reliability of multi-chip integrated packaging are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, and in particular to a chip heat dissipation structure and a preparation method thereof. BACKGROUND

[0002] As a core component of electronic devices, the basic working principle of a chip is to convert electrical signals into various functional signals to realize functions such as data processing, storage and transmission. However, in the process of completing these functions, a large amount of heat will be generated because the transmission of electrical signals will be accompanied by energy loss such as resistance, capacitance and inductance, which will be converted into heat energy.

[0003] Excessive temperature will affect the working performance of electronic devices, and even cause damage to electronic devices, affecting the service life. With the increasing integration of chips and the increasing complexity of chip structures, the heat problem is becoming more and more serious, and timely heat dissipation is needed. SUMMARY

[0004] Therefore, the purpose of the present application is to provide a chip heat dissipation structure and a preparation method thereof to improve the heat dissipation efficiency.

[0005] To achieve the above purpose, the present application provides a chip heat dissipation structure, comprising: a substrate; a first chip and a second chip arranged on the same side of the substrate, the active surface of the first chip and the active surface of the second chip are arranged towards the substrate; a first heat dissipation channel is formed on the side surface of the first chip away from the substrate, and a second heat dissipation channel is formed on the side surface of the second chip away from the substrate; a first heat dissipation structure arranged on the side of the first chip away from the substrate, the first heat dissipation structure filling the first heat dissipation channel; a second heat dissipation structure arranged on the side of the second chip away from the substrate, the second heat dissipation structure filling the second heat dissipation channel; wherein the surface of the first heat dissipation structure away from the substrate is coplanar with the surface of the second heat dissipation structure away from the substrate.

[0006] Optionally, the size of the first chip in the direction perpendicular to the substrate is different from the size of the second chip in the direction perpendicular to the substrate.

[0007] Optionally, the first heat dissipation channel comprises a first blind hole formed on the surface of the first chip away from the substrate, and the size of the first blind hole in the direction perpendicular to the substrate is smaller than the size of the first chip in the direction perpendicular to the substrate. The second heat dissipation channel comprises a second blind hole formed on the surface of the second chip away from the substrate, and the size of the second blind hole in the direction perpendicular to the substrate is smaller than the size of the second chip in the direction perpendicular to the substrate.

[0008] Optionally, the first heat dissipation structure comprises a first filling portion and a first covering portion, the first filling portion fills the first heat dissipation channel, and the first covering portion covers the side surface of the first chip away from the substrate. The second heat dissipation structure comprises a second filling portion and a second covering portion, the second filling portion fills the second heat dissipation channel, and the second covering portion covers the side surface of the second chip away from the substrate.

[0009] Optionally, the size of the first chip in the direction perpendicular to the substrate is greater than the size of the second chip in the direction perpendicular to the substrate, and the size of the first covering portion in the direction perpendicular to the substrate is less than the size of the second covering portion in the direction perpendicular to the substrate.

[0010] Optionally, the material of the first heat dissipation structure and the second heat dissipation structure comprises at least one of copper, aluminum and silver.

[0011] Optionally, the chip heat dissipation structure further comprises: The first thermal interface layer and the second thermal interface layer are arranged at intervals, the first thermal interface layer covers the first heat dissipation structure, and the second thermal interface layer covers the second heat dissipation structure; wherein the size of the first thermal interface layer in the direction perpendicular to the substrate is the same as the size of the second thermal interface layer in the direction perpendicular to the substrate. The heat sink is arranged on the side of the first thermal interface layer and the second thermal interface layer away from the substrate.

[0012] Based on the same inventive concept, the application further provides a preparation method of a chip heat dissipation structure, the method comprising: providing a substrate; arranging the first chip and the second chip on the same side of the substrate, and making the active surfaces of the first chip and the second chip face the substrate; forming a first heat dissipation channel on the side surface of the first chip away from the substrate, and forming a second heat dissipation channel on the side surface of the second chip away from the substrate; forming a first heat dissipation structure and a second heat dissipation structure, the first heat dissipation structure fills the first heat dissipation channel, and the second heat dissipation structure fills the second heat dissipation channel; performing a planarization treatment on the first heat dissipation structure and the second heat dissipation structure, so that the surface of the first heat dissipation structure away from the substrate is coplanar with the surface of the second heat dissipation structure away from the substrate.

[0013] Optionally, when the first heat dissipation structure and the second heat dissipation structure are formed, different sizes of the first heat dissipation structure and the second heat dissipation structure are formed according to the size difference of the first chip and the second chip in the direction perpendicular to the substrate. Optionally, forming the first heat dissipation structure and the second heat dissipation structure of different sizes comprises: forming a first filling part filling the first heat dissipation channel; forming a first covering part covering the first chip on the side surface away from the substrate; forming a second filling part filling the second heat dissipation channel; and forming a second covering part covering the second chip on the side surface away from the substrate. Optionally, the thickness of the first chip is greater than the thickness of the second chip, and the thickness of the first covering part is less than the thickness of the second covering part.

[0014] Optionally, after the planarization treatment, the method further comprises: disposing a first thermal interface layer on the side surface of the first heat dissipation structure away from the substrate and disposing a second thermal interface layer on the side surface of the second heat dissipation structure away from the substrate; disposing a heat sink on the side surface of the first thermal interface layer and the second thermal interface layer away from the substrate, so that the first heat dissipation structure and the second heat dissipation structure are thermally coupled with the heat sink through the first thermal interface layer and the second thermal interface layer.

[0015] The chip heat dissipation structure provided by the present application comprises: a first chip and a second chip, a first heat dissipation structure and a second heat dissipation structure, and a substrate, wherein the first heat dissipation structure and the second heat dissipation structure are disposed on the side surface of the first chip and the second chip away from the substrate respectively, and the first heat dissipation structure and the second heat dissipation structure are filled in the first heat dissipation channel and the second heat dissipation channel respectively.

[0016] Meanwhile, the side surface of the first heat dissipation structure and the second heat dissipation structure away from the substrate is coplanar, which provides a flat and consistent base for the installation of the subsequent thermal interface layer and the heat sink, helps to set a relatively thin thermal interface layer, reduces the thermal resistance, ensures the uniformity and stability of the heat dissipation path, and further improves the overall heat dissipation efficiency and reliability of the multi-chip integrated package. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present application or related art, the following will briefly introduce the drawings needed to be used in the embodiments or related art descriptions. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0018] Figure 1 is a structural schematic diagram of a chip heat dissipation structure provided by an embodiment of the present application; Figure 2 is a structural schematic diagram of a chip heat dissipation structure provided by another embodiment of the present application; Figure 3 This is a schematic flowchart of a method for fabricating a chip heat dissipation structure according to an embodiment of this application; Figure 4 This is a flowchart of the process steps for fabricating a chip heat dissipation structure according to an embodiment of this application.

[0019] Marker explanation: 100. Chip heat dissipation structure; 10. Substrate; 20. First chip; 21. First heat dissipation channel; 30. Second chip; 31. Second heat dissipation channel; 41. First heat dissipation structure; 411. First filling portion; 412. First covering portion; 42. Second heat dissipation structure; 421. Second filling portion; 422. Second covering portion; 51. First thermal interface layer; 52. Second thermal interface layer; 60. Heat sink. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0021] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0022] As the core component of electronic devices, chips work by converting electrical signals into various functional signals to perform data processing, storage, and transmission. During this process, chips generate a significant amount of heat. This heat is due to energy losses during signal transmission caused by resistance, capacitance, and inductance, which are ultimately dissipated as heat.

[0023] When a chip's temperature exceeds its designed operating range, a series of problems arise: the carrier mobility of the semiconductor material decreases, leading to slower transistor switching speeds; thermal noise increases, causing signal integrity degradation; more seriously, electromigration effects intensify, where metal atoms in the metal interconnects are displaced under the impact of high-speed electron flow, ultimately causing open or short circuits and permanently damaging the chip. Therefore, efficient heat dissipation is not only a prerequisite for ensuring stable chip performance but also crucial for ensuring the long-term reliable operation of electronic devices.

[0024] Traditional chip packaging heat dissipation solutions primarily rely on directly contacting the back side of the chip (i.e., the passive side) with the heat sink via a thermal interface material (TIM) to conduct heat to the heat sink and dissipate it into the environment. However, the inventors discovered that the chip itself is relatively thin (typically on the order of tens to hundreds of micrometers), limiting the effective heat dissipation area on its back side that can be used for contact with the heat sink—it's only the chip's projected area. This limited contact area restricts the heat flux density from the chip to the heat sink, resulting in a bottleneck in heat dissipation efficiency and limiting further improvements, posing a challenge in the application of high-performance chips.

[0025] In addition, traditional heat dissipation solutions face challenges in further improving heat dissipation efficiency when dealing with advanced packaging scenarios involving multiple chips and high power consumption, especially when there are differences in the thickness of integrated chips, which increases the difficulty of ensuring uniform thermal management.

[0026] Based on this, this application provides a solution for a chip heat dissipation structure and fabrication method to increase the heat dissipation area and improve heat dissipation efficiency.

[0027] like Figure 1 As shown, an embodiment of this application provides a chip heat dissipation structure 100, which includes a substrate 10, a first chip 20, a second chip 30, a first heat dissipation structure 41, and a second heat dissipation structure 42.

[0028] The first chip 20 and the second chip 30 are disposed on the same side of the substrate 10, with the active surfaces of both the first chip 20 and the second chip 30 facing the substrate 10. A first heat dissipation channel 21 is formed on the surface of the first chip 20 facing away from the substrate 10, and a second heat dissipation channel 31 is formed on the surface of the second chip 30 facing away from the substrate 10. A first heat dissipation structure 41 is disposed on the side of the first chip 20 facing away from the substrate 10, and the first heat dissipation structure 41 fills the first heat dissipation channel 21. A second heat dissipation structure 42 is disposed on the side of the second chip 30 facing away from the substrate 10, and the second heat dissipation structure 42 fills the second heat dissipation channel 31. The surfaces of the first heat dissipation structure 41 and the second heat dissipation structure 42 facing away from the substrate 10 are coplanar.

[0029] In this embodiment, substrate 10 serves as the core carrier for packaging and can be either an adapter plate or a packaging substrate. In a specific example, substrate 10 is a glass adapter plate with a thickness of 200 μm, and it has a TGV (Through Glass Via) interconnect structure formed inside. Glass material has excellent high-frequency electrical properties and a coefficient of thermal expansion similar to silicon, which can effectively reduce thermal stress. The TGV structure facilitates three-dimensional interconnection between the upper and lower surfaces of the substrate, providing a foundation for high-density packaging.

[0030] The first chip 20 and the second chip 30 are flip-chip soldered to the substrate 10 via copper pillar bumps. During installation, the active surfaces of both the first chip 20 and the second chip 30 face the substrate 10 to achieve electrical interconnection. Copper pillar bumps offer higher conductivity and better thermal conductivity compared to traditional solder bumps. The underfill uses epoxy resin filled with nano-silica, which not only provides mechanical protection but also facilitates heat conduction downwards to the substrate due to its optimized thermal conductivity.

[0031] The active side is the side of the chip that integrates transistors and a front-end interconnect layer. The first chip 20 can be a logic chip, such as a central processing unit (CPU) or a graphics processing unit (GPU), and the second chip 30 can be a memory chip, such as a high-bandwidth memory (HBM) chip.

[0032] On the back side of the first chip 20 away from the substrate 10, a plurality of first heat dissipation channels 21 are formed by dry etching. Similarly, a plurality of second heat dissipation channels 31 are formed on the back side of the second chip 30. A first heat dissipation structure 41 is disposed on the back side of the first chip 20 and fills the first heat dissipation channels 21. A second heat dissipation structure 42 is disposed on the back side of the second chip 30 and fills the second heat dissipation channels 31. In this embodiment, the first heat dissipation structure 41 and the second heat dissipation structure 42 are formed by copper electroplating.

[0033] The first heat dissipation structure 41 completely fills the first heat dissipation channel 21. The second heat dissipation structure 42 completely fills the second heat dissipation channel 31, and the resulting heat conduction path can effectively improve heat dissipation efficiency. The surface of the first heat dissipation structure 41 facing away from the substrate 10 and the surface of the second heat dissipation structure 42 facing away from the substrate 10 can be made coplanar after being treated by chemical mechanical polishing (CMP) process.

[0034] It should be noted that, in the embodiments of this application, "coplanar" means that, after planarization, the height difference between the surfaces of the first heat dissipation structure 41 and the second heat dissipation structure 42 that are away from the substrate 10 is less than 1 μm, preferably less than 0.5 μm. Coplanarity provides a flat and consistent base for the subsequent installation of the thermal interface layer and the heat sink, which helps to set a thinner thermal interface layer, reduces thermal resistance, and helps to ensure overall heat dissipation performance.

[0035] The chip heat dissipation structure 100 provided in this application increases the contact area between the chip and the heat dissipation structure by opening heat dissipation channels on the back of the chip, expanding the original two-dimensional planar heat dissipation into three-dimensional heat dissipation and improving heat conduction efficiency. The surfaces of the first heat dissipation structure 41 and the second heat dissipation structure 42 are highly coplanar, ensuring that the thickness of the subsequently applied thermal interface layer is uniform and can be reduced as much as possible, and providing a flat mounting base for the heat sink. It also avoids poor contact between the heat sink and the chip and increased local thermal resistance caused by height differences.

[0036] The chip heat dissipation structure 100 of this application overcomes the inconvenience of the traditional solution where each chip needs to manage its heat dissipation path independently, and provides a new heat dissipation solution suitable for advanced packaging.

[0037] In some embodiments, the dimension of the first chip 20 in the direction perpendicular to the substrate 10 is different from the dimension of the second chip 30 in the direction perpendicular to the substrate 10.

[0038] By adjusting the thickness of the heat dissipation structure, the coplanarity issue caused by inconsistent chip heights was compensated for, ensuring a flat installation of the thermal interface layer and the heat sink. This also improved the flexibility of the packaging design, reduced limitations on chip thickness specifications, and allowed for the integration of chips with different functions and from different sources, expanding application scenarios.

[0039] In the embodiments of this application, "thickness", "height" and "depth" of blind holes refer to dimensions in a direction perpendicular to the substrate 10.

[0040] This application achieves coplanarity of the heat dissipation surfaces of multiple chips and simultaneously reduces the overall thickness of the thermal interface layer by actively adjusting the thickness of the covering portions of the first heat dissipation structure 41 and the second heat dissipation structure 42. Since the thermal conductivity of metals (such as copper) is much higher than that of typical thermal interface materials (such as thermal grease), according to Fourier's law of thermal conductivity, under the same heat flux density, the smaller the thickness of the thermally conductive medium, the lower its thermal resistance. Therefore, reducing the thickness of the thermal interface layer can reduce its overall thermal resistance in the heat dissipation path. Furthermore, coplanarity ensures that the thermal interface layer can be coated uniformly and extremely thinly, avoiding thermal bottlenecks caused by excessively thick local thermal interface material due to height differences. This design allows heat to pass more efficiently through the highly thermally conductive metal structure and through the thin thermal interface material with lower resistance to reach the heat sink, thereby comprehensively improving the heat dissipation efficiency from the chip to the environment.

[0041] In some embodiments, the first heat dissipation channel 21 includes a first blind hole formed on the surface of the first chip 20 facing away from the substrate 10, and the dimension of the first blind hole in the direction perpendicular to the substrate 10 is smaller than the dimension of the first chip 20 in the direction perpendicular to the substrate 10. The second heat dissipation channel 31 includes a second blind hole formed on the surface of the second chip 30 facing away from the substrate 10, and the dimension of the second blind hole in the direction perpendicular to the substrate 10 is smaller than the dimension of the second chip 30 in the direction perpendicular to the substrate 10.

[0042] For example, in the process of forming the heat dissipation channels, an inductively coupled plasma dry etching technology based on CF4 / Ar is employed. Anisotropic etching can be achieved by precisely controlling the chamber pressure (50 mTorr), source power (500 W), and gas ratio, resulting in blind via structures with steep sidewalls and consistent depth. In the electroplating filling stage, a pulsed reverse electroplating process is used. By optimizing the parameter configuration of the forward pulse (10 ms, 20 ASD) and reverse pulse (1 ms, 5 ASD), preferential deposition is achieved at the bottom of the blind vias, ensuring complete filling without voids. This process combination guarantees filling quality while avoiding the sealing effect that may occur with traditional DC electroplating, providing process assurance for the performance reliability of the heat dissipation structure.

[0043] Specifically, the process of forming heat dissipation channels involves creating an array of blind vias on the back of the chip using dry etching. These blind vias can be optimally arranged according to the heat source distribution of the chip. In high-power areas (such as the CPU core area), the density of blind vias can be increased to 70%, while in low-power areas it is reduced to 30%. This gradient density design ensures heat dissipation while avoiding the impact of excessive processing on the integrity of the chip structure.

[0044] It is understood that the above blind via density ratio is only an example, and those skilled in the art can make adaptive adjustments according to the thermal design power (TDP) distribution of a specific chip.

[0045] In this design, the depth of the blind via is less than the chip thickness, ensuring that the etching process does not penetrate to the active surface of the chip. This avoids the risk of damaging the internal circuitry and maintains the electrical integrity and functionality of the chip. The blind via structure creates numerous vertical heat conduction paths within the chip.

[0046] Filling blind vias with highly thermally conductive metal is equivalent to creating numerous highly thermally conductive vertical heat conduction paths on the silicon chip, optimizing the efficiency of heat conduction from the inside of the chip to the back side.

[0047] Furthermore, the first heat dissipation structure 41 includes a first filling portion 411 and a first covering portion 412. The first filling portion 411 fills the first heat dissipation channel 21, and the first covering portion 412 covers the surface of the first chip 20 facing away from the substrate 10. The second heat dissipation structure 42 includes a second filling portion 421 and a second covering portion 422. The second filling portion 421 fills the second heat dissipation channel 31, and the second covering portion 422 covers the surface of the second chip 30 facing away from the substrate 10.

[0048] Specifically, the first heat dissipation structure 41 includes an integrally formed first filling portion 411 and a first covering portion 412. The first filling portion 411 fills the first heat dissipation channel 21, and the first covering portion 412 covers the entire surface of the first chip 20 facing away from the substrate 10. Similarly, the second heat dissipation structure 42 includes an integrally formed second filling portion 421 and a second covering portion 422. The second filling portion 421 fills the second heat dissipation channel 31, and the second covering portion 422 covers the entire surface of the second chip 30 facing away from the substrate 10. The first heat dissipation structure 41 and the second heat dissipation structure 42 are each completed by a single copper electroplating process.

[0049] The unibody structure eliminates potential physical interfaces (such as seams and holes) between the filler and cover portions. This creates a continuous, seamless metal body along the heat conduction path, effectively reducing additional thermal resistance caused by poor interface contact and improving heat conduction efficiency. Simultaneously, the unibody metal structure, lacking potential physical interfaces, exhibits higher mechanical strength and better adhesion to the chip substrate. Under stress conditions such as temperature cycling and mechanical vibration, this unibody structure effectively prevents crack initiation and delamination at the interface, thereby improving the long-term reliability of the package.

[0050] Furthermore, the dimension of the first chip 20 in the direction perpendicular to the substrate 10 is larger than the dimension of the second chip 30 in the direction perpendicular to the substrate 10, and the dimension of the first covering portion 412 in the direction perpendicular to the substrate 10 is smaller than the dimension of the second covering portion 422 in the direction perpendicular to the substrate 10.

[0051] For example, in the direction perpendicular to the substrate 10, the thickness of the first chip 20 is 100 μm, and the thickness of the second chip 30 is 50 μm. Due to the initial thickness difference of 50 μm, if heat dissipation structures of the same thickness are directly deposited, their surfaces will inevitably not be coplanar. This application differentiates the thickness of the heat dissipation structures, for example, adjusting the thickness of the first cover portion 412 of the first heat dissipation structure 41 to 70 μm and the thickness of the second cover portion 422 of the second heat dissipation structure 42 to 20 μm, thereby actively compensating for the thickness difference between the chips and ultimately achieving coplanarity through planarization. This allows chips of different thicknesses to be integrated into the same package and achieve equivalent heat dissipation performance.

[0052] In some embodiments, the materials of the first heat dissipation structure 41 and the second heat dissipation structure 42 include at least one of copper, aluminum and silver.

[0053] The first heat dissipation structure 41 and the second heat dissipation structure 42 preferably use pure copper as the thermal conductive material.

[0054] In other embodiments, the materials of the first heat dissipation structure 41 and the second heat dissipation structure 42 can also be: high-purity aluminum, formed by a combination of sputtering and electroplating, which has a low cost; or silver, formed by silver electroplating, which provides excellent thermal conductivity; or other high thermal conductivity metals or alloys such as copper-silver alloys. Copper, aluminum, and silver are all high thermal conductivity metals, with thermal conductivity much higher than that of the silicon chip itself, enabling rapid lateral diffusion and upward conduction of heat generated by the chip, thus improving heat dissipation efficiency. Copper and aluminum are relatively mature and commonly used metal interconnect materials in semiconductor manufacturing, and their deposition, electroplating, etching, and polishing processes are relatively well-established, ensuring the feasibility and high yield of this heat dissipation structure fabrication.

[0055] Specifically, the first heat dissipation structure 41 and the second heat dissipation structure 42 are formed by copper electroplating. The electroplating process can achieve the deposition of high-purity copper under relatively low temperature conditions, avoiding the impact of high-temperature processes on chip performance.

[0056] like Figure 2 As shown, in some embodiments, the chip heat dissipation structure 100 further includes a first thermal interface layer 51 and a second thermal interface layer 52 spaced apart, as well as a heat sink 60. The first thermal interface layer 51 covers the first heat dissipation structure 41, and the second thermal interface layer 52 covers the second heat dissipation structure 42. The dimensions of the first thermal interface layer 51 in the direction perpendicular to the substrate 10 are the same as the dimensions of the second thermal interface layer 52 in the direction perpendicular to the substrate 10.

[0057] The heat sink 60 is disposed on the side of the first thermal interface layer 51 and the second thermal interface layer 52 opposite to the substrate 10. The heat sink 60 may be an aluminum finned heat sink.

[0058] The first thermal interface layer 51 and the second thermal interface layer 52 fill the microscopic unevenness and gaps between the coplanar metal surface and the substrate of the heat sink 60, eliminate air with extremely poor thermal conductivity, and reduce the contact thermal resistance between the heat dissipation structure and the heat sink.

[0059] Even after CMP treatment, metal surfaces still exhibit microscopic irregularities. A uniformly thick thermal interface layer effectively compensates for these microscopic unevenness, ensuring that heat is evenly transferred upwards to the heat sink and preventing localized overheating. The heat sink 60 provides a large surface area pathway for ultimately dissipating heat into the environment.

[0060] The first thermal interface layer 51 and the second thermal interface layer 52 are spaced apart to accommodate scenarios requiring thermal isolation between different chips. For example, the first chip 20 (power device) operates at a high temperature, while the second chip 30 (sensitive sensor) needs to operate at a low temperature. The spaced thermal interface layers interrupt the lateral heat conduction path through the thermal interface material itself, effectively reducing thermal crosstalk and ensuring the thermal environment independence of each chip.

[0061] In some applications, continuous thermal interface layers can act as thermal bridges for lateral heat conduction between chips, causing heat transfer from high-temperature chips to low-temperature chips. Spacing, on the other hand, physically cuts off the lateral heat conduction path through the thermal interface material itself, helping to achieve effective thermal isolation and ensuring an independent thermal environment for each chip.

[0062] In another embodiment, the first thermal interface layer 51 and the second thermal interface layer 52 can also form a single, continuously arranged structural layer, simultaneously covering the first heat dissipation structure 41 and the second heat dissipation structure 42. This arrangement is simpler to manufacture (e.g., it can be completed in a single screen printing process), provides better overall sealing to prevent moisture intrusion, and ensures a uniform heat conduction path between the heat sink and all the heat dissipation structures below, making it suitable for general scenarios where there are no strict thermal isolation requirements between chips.

[0063] This application enhances the heat dissipation area through a micro-nano scale heat dissipation channel network on the back of the chip. This is primarily achieved on two levels: at the geometric level, by optimizing the depth, diameter, and distribution density of blind vias, the heat dissipation surface area is maximized while maintaining the integrity of the chip structure; at the material level, a continuous heat conduction path from the chip's interior to its exterior is constructed using a high thermal conductivity metal material. This design overcomes the physical limitations of traditional two-dimensional planar heat dissipation and, through a precise thickness compensation mechanism, addresses the coplanarity challenge in multi-chip heterogeneous integration, providing a complete heat dissipation solution for advanced packaging.

[0064] The height compensation mechanism in this application not only solves the coplanarity problem but also optimizes material utilization efficiency. By accurately calculating the required compensation thickness, waste of metallic materials is avoided.

[0065] Based on the same inventive concept, embodiments of this application also provide a method for preparing a chip heat dissipation structure, used to prepare the chip heat dissipation structure 100 in any of the above embodiments.

[0066] like Figure 3 , Figure 4 As shown, the fabrication method of the chip heat dissipation structure 100 includes the following steps: Step S10: Provide substrate 10; Step S20: Place the first chip 20 and the second chip 30 on the same side of the substrate 10, and make the active surfaces of the first chip 20 and the second chip 30 face the substrate 10. Step S30: A first heat dissipation channel 21 is formed on the side surface of the first chip 20 away from the substrate, and a second heat dissipation channel 31 is formed on the side surface of the second chip 30 away from the substrate. Step S40: Form a first heat dissipation structure 41 and a second heat dissipation structure 42. The first heat dissipation structure 41 fills the first heat dissipation channel 21, and the second heat dissipation structure 42 fills the second heat dissipation channel 31. Step S50: The first heat dissipation structure 41 and the second heat dissipation structure 42 are planarized so that the surface of the first heat dissipation structure 41 facing away from the substrate 10 is coplanar with the surface of the second heat dissipation structure 42 facing away from the substrate 10.

[0067] Specifically, a glass adapter plate is provided as substrate 10. The first chip 20 and the second chip 30 are mounted on the same side of substrate 10 via thermo-press bonding, with their active surfaces facing substrate 10, followed by underfilling and curing. A first heat dissipation channel 21 is formed on the back side of the first chip 20 using dry etching, and a second heat dissipation channel 31 is formed on the back side of the second chip 30. A Ti / Cu seed layer is deposited by PVD, followed by copper electroplating to form a first heat dissipation structure 41 and a second heat dissipation structure 42, which respectively fill the first heat dissipation channel 21 and the second heat dissipation channel 31. The first heat dissipation structure 41 and the second heat dissipation structure 42 are chemically and mechanically polished to make the surfaces facing away from substrate 10 highly coplanar.

[0068] The chip heat dissipation structure 100 fabrication method provided in this application increases the contact area between the chip and the heat dissipation structure by creating heat dissipation channels on the back of the chip, expanding the original two-dimensional planar heat dissipation into three-dimensional heat dissipation and improving heat conduction efficiency. The coplanarity of the surfaces of the first and second heat dissipation structures ensures that the thickness of the subsequently applied thermal interface layer is uniform and can be minimized, providing a flat mounting base for the heat sink. This avoids poor contact between the heat sink and the chip and increased local thermal resistance caused by height differences, thereby improving overall heat dissipation stability and reliability.

[0069] In addition, the chip mounting, dry etching, PVD, electroplating, CMP and other processes involved in the preparation method are all standard processes in the semiconductor manufacturing and advanced packaging fields, which are easy to integrate into existing production lines and have good mass production feasibility.

[0070] In step S40, the first heat dissipation structure 41 and the second heat dissipation structure 42 are formed, specifically including: The first heat dissipation channel 21 is filled with electroplated copper in one step and covers the back of the first chip 20, thereby forming a first heat dissipation structure 41 integrally. The second heat dissipation channel 31 is filled with electroplated copper and covers the back of the second chip 30, thereby forming a second heat dissipation structure 42 integrally.

[0071] By combining the filling of blind vias and the formation of the cover portion into a single electroplating step, the process flow is simplified, alignment errors and interface problems that may arise from multiple patterning and deposition processes are reduced, and production efficiency is improved. This one-step molding directly creates a seamless, integrated heat dissipation structure, ensuring the continuity and efficiency of the heat conduction path from the chip's interior (through the filling portion) to the chip's exterior (through the cover portion).

[0072] Furthermore, in step S40, when forming the first heat dissipation structure 41 and the second heat dissipation structure 42, the metal coverings of different thicknesses are actively formed by controlling the electroplating time according to the thickness difference between the first chip 20 and the second chip 30. This adaptive height compensation strategy aims to ensure that, even after integrating chips of different thicknesses, the surfaces of the heat dissipation structures remain coplanar after subsequent planarization processing.

[0073] By precisely controlling the thickness of metal deposition, it is possible to avoid depositing excessive amounts of useless metal in certain areas while ensuring coplanarity, thereby reducing the amount of metal material used.

[0074] Furthermore, the first heat dissipation structure 41 includes a first filling portion 411 and a first covering portion 412. The first filling portion 411 fills the first heat dissipation channel 21, and the first covering portion 412 covers the surface of the first chip 20 facing away from the substrate 10. The second heat dissipation structure 42 includes a second filling portion 421 and a second covering portion 422. The second filling portion 421 fills the second heat dissipation channel 31, and the second covering portion 422 covers the surface of the second chip 30 facing away from the substrate 10.

[0075] The thickness of the first chip 20 is greater than the thickness of the second chip 30, and the thickness of the first covering portion 412 is less than the thickness of the second covering portion 422.

[0076] After the planarization process in step S50, the method for fabricating the chip heat dissipation structure 100 further includes the following steps: Step S61: A first thermal interface layer 51 and a second thermal interface layer 52 are respectively provided on the side surface of the first heat dissipation structure 41 and the second heat dissipation structure 42 away from the substrate 10. Step S62: A heat sink 60 is disposed on the side surface of the first thermal interface layer 51 and the second thermal interface layer 52 facing away from the substrate 10, so that the first heat dissipation structure 41 and the second heat dissipation structure 42 are thermally coupled to the heat sink 60 through the first thermal interface layer 51 and the second thermal interface layer 52.

[0077] It should be noted that thermal coupling refers to the efficient thermal conduction state established between the first heat dissipation structure 41, the second heat dissipation structure 42 and the heat sink 60 through the conduction of the first thermal interface layer 51 and the second thermal interface layer 52.

[0078] By setting a thermal interface layer on the surface of the coplanar heat dissipation structure formed by the preceding process and installing a heat sink, a complete connection between chip-level heat dissipation and system-level heat dissipation is achieved: the coplanar surface ensures that the thermal interface layer can be coated uniformly and thinly, reducing the thermal resistance of the thermal interface layer; subsequently, by applying pressure to install the heat sink, the thermal interface layer fully fills the microscopic gaps between the heat sink substrate and the metal heat dissipation structure, effectively eliminating air and reducing the interface contact thermal resistance, thereby constructing a complete, efficient and low-thermal-resistance thermal management path from the core of chip heat generation to the external environment, ultimately transforming the structural advantages into system-level heat dissipation performance improvement.

[0079] The chip heat dissipation structure and fabrication method provided in this application effectively address the low heat dissipation efficiency caused by the limited back surface area of ​​traditional heat dissipation solutions, as well as the coplanarity challenges caused by thickness differences in multi-chip integration. The chip heat dissipation structure constructs a three-dimensional heat dissipation path by opening heat dissipation channels on the back of the chip and filling them with highly thermally conductive metal, increasing the heat dissipation area and improving heat conduction efficiency. Simultaneously, through thickness compensation of the heat dissipation structure, a high degree of coplanarity is achieved on the heat dissipation surfaces of chips with different thicknesses, ensuring uniform contact between the thermal interface layer and the heat sink and reducing interface thermal resistance. The fabrication method achieves integrated molding of the heat dissipation structure through a one-step electroplating process, simplifying the process and ensuring the continuity of the thermal path. The overall solution improves heat dissipation performance while also considering the reliability and process feasibility of multi-chip packaging.

[0080] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0081] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A chip heat dissipation structure, characterized in that, include: substrate; A first chip and a second chip are disposed on the same side of the substrate, with the active surfaces of the first chip and the second chip both facing the substrate; a first heat dissipation channel is formed on the surface of the first chip facing away from the substrate, and a second heat dissipation channel is formed on the surface of the second chip facing away from the substrate. A first heat dissipation structure is disposed on the side of the first chip away from the substrate, and the first heat dissipation structure fills the first heat dissipation channel. The second heat dissipation structure is disposed on the side of the second chip away from the substrate, and the second heat dissipation structure fills the second heat dissipation channel; The surface of the first heat dissipation structure facing away from the substrate is coplanar with the surface of the second heat dissipation structure facing away from the substrate.

2. The chip heat dissipation structure according to claim 1, characterized in that, The dimension of the first chip in the direction perpendicular to the substrate is different from the dimension of the second chip in the direction perpendicular to the substrate.

3. The chip heat dissipation structure according to claim 1, characterized in that, The first heat dissipation channel includes a first blind hole formed on the surface of the first chip facing away from the substrate, and the dimension of the first blind hole in the direction perpendicular to the substrate is smaller than the dimension of the first chip in the direction perpendicular to the substrate. The second heat dissipation channel includes a second blind hole formed on the surface of the second chip facing away from the substrate, and the dimension of the second blind hole in the direction perpendicular to the substrate is smaller than the dimension of the second chip in the direction perpendicular to the substrate.

4. The chip heat dissipation structure according to claim 1, characterized in that, The first heat dissipation structure includes a first filling portion and a first covering portion. The first filling portion fills the first heat dissipation channel, and the first covering portion covers the surface of the first chip facing away from the substrate. The second heat dissipation structure includes a second filling portion and a second covering portion. The second filling portion fills the second heat dissipation channel, and the second covering portion covers the surface of the second chip facing away from the substrate.

5. The chip heat dissipation structure according to claim 4, characterized in that, The dimension of the first chip in the direction perpendicular to the substrate is greater than the dimension of the second chip in the direction perpendicular to the substrate, and the dimension of the first cover portion in the direction perpendicular to the substrate is smaller than the dimension of the second cover portion in the direction perpendicular to the substrate.

6. The chip heat dissipation structure according to claim 1, characterized in that, The materials of the first heat dissipation structure and the second heat dissipation structure include at least one of copper, aluminum and silver.

7. The chip heat dissipation structure according to claim 1, characterized in that, The chip heat dissipation structure also includes: A first thermal interface layer and a second thermal interface layer are spaced apart, the first thermal interface layer covering the first heat dissipation structure and the second thermal interface layer covering the second heat dissipation structure; wherein, the dimension of the first thermal interface layer in the direction perpendicular to the substrate is the same as the dimension of the second thermal interface layer in the direction perpendicular to the substrate. A heat sink is disposed on the side of the first thermal interface layer and the second thermal interface layer away from the substrate.

8. A method for fabricating a chip heat dissipation structure, characterized in that, The method includes: Provide substrate; The first chip and the second chip are disposed on the same side of the substrate, and the active surfaces of the first chip and the second chip face the substrate. A first heat dissipation channel is formed on the surface of the first chip facing away from the substrate, and a second heat dissipation channel is formed on the surface of the second chip facing away from the substrate. A first heat dissipation structure and a second heat dissipation structure are formed, wherein the first heat dissipation structure fills the first heat dissipation channel and the second heat dissipation structure fills the second heat dissipation channel; The first heat dissipation structure and the second heat dissipation structure are flattened so that the surface of the first heat dissipation structure facing away from the substrate is coplanar with the surface of the second heat dissipation structure facing away from the substrate.

9. The method for preparing the chip heat dissipation structure according to claim 8, characterized in that, When forming the first heat dissipation structure and the second heat dissipation structure, the first heat dissipation structure and the second heat dissipation structure of different sizes are formed according to the size difference between the first chip and the second chip in the direction perpendicular to the substrate. Preferably, forming the first heat dissipation structure and the second heat dissipation structure of different sizes includes: forming a first filling portion, the first filling portion filling the first heat dissipation channel; forming a first covering portion, the first covering portion covering the surface of the first chip facing away from the substrate; forming a second filling portion, the second filling portion filling the second heat dissipation channel; and forming a second covering portion, the second covering portion covering the surface of the second chip facing away from the substrate. Preferably, the thickness of the first chip is greater than the thickness of the second chip, and the thickness of the first covering portion is less than the thickness of the second covering portion.

10. The method for preparing the chip heat dissipation structure according to claim 8, characterized in that, After the leveling process, the method further includes: A first thermal interface layer is provided on the surface of the first heat dissipation structure facing away from the substrate, and a second thermal interface layer is provided on the surface of the second heat dissipation structure facing away from the substrate. A heat sink is disposed on the side surface of the first thermal interface layer and the second thermal interface layer opposite to the substrate, such that the first heat dissipation structure and the second heat dissipation structure are thermally coupled to the heat sink through the first thermal interface layer and the second thermal interface layer.

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