Chip packaging structure, preparation method thereof and display device

Abstract

The invention provides a chip packaging structure, a preparation method thereof and a display device. The chip packaging structure comprises a substrate which comprises a supporting structure and a plurality of substrate subunits, the supporting structure comprises a plurality of containing spaces, and at least part of the substrate subunits are located in the containing spaces; the first wiring layer is located on the first side of the substrate subunit; the second wiring layer is located on the second side of the substrate subunit, and the first side and the second side are oppositely arranged in the direction perpendicular to the plane where the substrate is located; a plurality of connecting lines located between the substrate subunit and the support structure and electrically connected with the first wiring layer and the second wiring layer; the chip is located on the side, away from the substrate, of the first wiring layer and / or the second wiring layer. The chip packaging structure is high in mechanical strength and reliability, and the failure risk in subsequent use can be reduced. Moreover, the wiring widths of the first wiring layer, the second wiring layer and the connecting line are relatively wide, so that the packaging structure is suitable for packaging a high-power chip.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to chip packaging structures and their fabrication methods, and display devices. Background Technology

[0002] An IC package substrate serves as a carrier for signals between a chip (die) and a printed circuit board (PCB). It provides electrical connections between the chip and the PCB; offers support, heat dissipation, and protection for the chip; and can embed passive and active components to achieve specific system functions. However, due to limitations in related technologies, current IC package substrates still cannot meet all requirements. Summary of the Invention

[0003] In view of this, embodiments of this application provide a chip packaging structure, a method for fabricating the same, and a display device.

[0004] The first aspect of this application provides a chip packaging structure, including: The base includes a supporting structure and multiple base sub-units. The supporting structure includes multiple receiving spaces, and at least some of the base sub-units are located within the receiving spaces. The first wiring layer is located on the first side of the base sub-unit; The second wiring layer is located on the second side of the substrate sub-unit, and is arranged opposite to the first side along a direction perpendicular to the plane of the substrate; Multiple connecting lines are located between the base subunit and the support structure, and are electrically connected to the first wiring layer and the second wiring layer; The chip is located on the side of the first wiring layer and / or the second wiring layer away from the substrate sub-cell.

[0005] In one embodiment, in the first direction, the size of the connecting line is greater than or equal to 5 micrometers and less than or equal to 8 centimeters; And / or, in the second direction, the size of the connecting line is greater than or equal to 20 μm and less than or equal to 500 μm, and the first direction intersects the second direction; And / or, the surface of the chip with pins faces the substrate subcell; Preferably, the connecting line is located on both sides of the substrate sub-unit, parallel to the plane of the substrate; Preferably, along a direction parallel to the plane of the substrate, the number of connecting lines on each side of the substrate sub-unit is greater than or equal to one.

[0006] In one embodiment, in a first direction, the size of the first wiring layer is less than or equal to the width of the connecting line; and / or, in a first direction, the size of the second wiring layer is less than or equal to the width of the connecting line.

[0007] In one embodiment, the dimensions of the support structure are equal to the dimensions of the base sub-unit in the direction perpendicular to the plane of the base; Preferably, the surface of the support structure on the first side is flush with the surface of the base subunit, and the surface of the support structure on the second side is flush with the surface of the base subunit. Preferably, the chip package structure further includes: a first protective layer located on a first side, the first protective layer covering at least a portion of the first wiring layer; and / or, a second protective layer located on a second side, the second protective layer covering at least a portion of the second wiring layer; Preferably, the material of the first protective layer and / or the second protective layer includes at least one of polyimide, Ajinomoto stacking film, and bismaleimide triazine resin.

[0008] In one embodiment, the chip packaging structure further includes: A first dielectric layer is located on the side of the first protective layer closest to the substrate; and / or, a second dielectric layer is located on the side of the second protective layer closest to the substrate; Preferably, the first wiring layer includes a plurality of first portions, a plurality of second portions, and a plurality of third portions. The plurality of first portions are located on a first side, the plurality of third portions are located on the side of the first dielectric layer away from the substrate sub-unit, and the plurality of second portions are located between the plurality of first portions and the plurality of third portions, and the plurality of second portions connect the plurality of first portions and the plurality of third portions; the first dielectric layer covers the plurality of first portions, and the plurality of second portions penetrate the first dielectric layer; a first protective layer covers the plurality of third portions; and / or, the second wiring layer includes a plurality of fourth portions, a plurality of fifth portions, and a plurality of sixth portions. The plurality of fourth portions are located on a second side, the plurality of sixth portions are located on the side of the second dielectric layer away from the substrate sub-unit, the plurality of fifth portions are located between the plurality of fourth portions and the plurality of sixth portions, and the plurality of fifth portions connect the plurality of fourth portions and the plurality of sixth portions; the second dielectric layer covers the plurality of fourth portions, the plurality of fifth portions penetrate the second dielectric layer; and a second protective layer covers the plurality of sixth portions; Preferably, the material of the first dielectric layer and / or the second dielectric layer includes at least one of polyimide, Ajinomoto stacked film, and bismaleimide triazine resin.

[0009] In one embodiment, the size of the support structure is larger than the size of the base subunit in the direction perpendicular to the plane of the base. Preferably, the surface of the support structure on the first side is flush with the surface of the base subunit; The chip packaging structure further includes: a first protective layer located on the first side, the first protective layer covering at least a portion of the first wiring layer; The first dielectric layer is located on the side of the first protective layer closest to the substrate; Alternatively, the surface of the support structure on the second side is flush with the surface of the base subunit; The chip package structure also includes: a second protective layer located on the second side, the second protective layer covering at least a portion of the second wiring layer; The second dielectric layer is located on the side of the second protective layer closest to the substrate; Preferably, the first wiring layer includes a plurality of first portions, a plurality of second portions, and a plurality of third portions. The plurality of first portions are located on a first side of the substrate sub-unit, the plurality of third portions are located on a side of the first dielectric layer away from the substrate sub-unit, and the plurality of second portions are located between the plurality of first portions and the plurality of third portions, and the plurality of second portions connect the plurality of first portions and the plurality of third portions; the first dielectric layer covers the plurality of first portions, and the plurality of second portions penetrate the first dielectric layer; a first protective layer is located on a side of the first dielectric layer away from the substrate, and the first protective layer covers the plurality of third portions; and / or, the second wiring layer includes a plurality of fourth portions, a plurality of fifth portions, and a plurality of sixth portions. The plurality of fourth portions are located on a second side, the plurality of sixth portions are located on a side of the second dielectric layer away from the substrate sub-unit, the plurality of fifth portions are located between the plurality of fourth portions and the plurality of sixth portions, and the plurality of fifth portions connect the plurality of fourth portions and the plurality of sixth portions; the second dielectric layer covers the plurality of fourth portions, the plurality of fifth portions penetrate the second dielectric layer; a second protective layer is located on a side of the second dielectric layer away from the substrate, and the second protective layer covers the plurality of sixth portions; Alternatively, the surface of the support structure located on the first side is located on the side of the first wiring layer away from the substrate subunit, and the surface of the support structure located on the second side is located on the side of the second wiring layer away from the substrate subunit.

[0010] In one embodiment, the chip includes: The chip body and the first conductive part are located between the chip body and the first wiring layer. The first conductive part is used to connect the chip body and the first wiring layer. And / or, the chip package structure also includes: The second conductive part is located on the side of the second wiring layer away from the substrate sub-unit and is connected to the second wiring layer; Preferably, the chip is located on the side of the first wiring layer opposite to the substrate sub-unit; Preferably, the material of the support structure includes epoxy molding compound and / or polyimide; and / or, the material of the substrate subunit includes glass and / or silicon.

[0011] A second aspect of this application provides a method for fabricating a chip packaging structure, comprising: Multiple through-holes are formed in the substrate body, and multiple connecting lines are fabricated in the through-holes. A first wiring layer is fabricated on a first side of the substrate body, and a second wiring layer is fabricated on a second side of the substrate body. The first side and the second side are arranged opposite to each other along a direction perpendicular to the plane of the substrate body. The first wiring layer and the second wiring layer are electrically connected by multiple connecting lines. The base body is segmented to obtain multiple base sub-units; Multiple base sub-units are embedded in the receiving space of the supporting structure; The chip is fixed on the side of the first wiring layer and / or the second wiring layer away from the substrate to obtain a chip package structure.

[0012] In one embodiment, multiple interconnecting lines are fabricated in the via, a first wiring layer is fabricated on a first side of the substrate, and a second wiring layer is fabricated on a second side of the substrate through the same fabrication process. Preferably, an electroplating process is used to prepare multiple connecting lines in the through-hole, prepare a first wiring layer on a first side of the substrate, and prepare a second wiring layer on a second side of the substrate. And / or, the step of embedding multiple base sub-units within the receiving space of the support structure includes: Multiple substrate subunits are fixed on the substrate; Multiple base sub-units are placed in a liquid supporting structural material; After the supporting structure material has cured, the substrate is removed.

[0013] A third aspect of this application provides a display device, including the aforementioned chip packaging structure, or including a chip packaging structure prepared by the aforementioned preparation method.

[0014] According to the chip packaging structure provided in the embodiments of this application, a first wiring layer and a second wiring layer are respectively provided on the first and second sides of the substrate subunit. After providing multiple connecting lines connecting the first wiring layer and the second wiring layer, the above structure is at least partially embedded in the receiving space of the support structure. This is beneficial to improving the mechanical strength and reliability of the chip packaging structure and can reduce the risk of failure in subsequent use. Moreover, the wiring width of the first wiring layer, the second wiring layer, and the connecting lines is relatively wide, which is suitable for packaging high-power chips. Attached Figure Description

[0015] Figure 1 This is a cross-sectional schematic diagram of the chip packaging structure in one embodiment of this application.

[0016] Figure 2 This is a top view of the chip packaging structure in one embodiment of this application.

[0017] Figure 3 This is a side view of the base sub-unit, the first wiring layer, and the second wiring layer in one embodiment of this application.

[0018] Figure 4 This is a cross-sectional schematic diagram of the chip packaging structure in another embodiment of this application.

[0019] Figure 5This is a cross-sectional schematic diagram of the chip packaging structure in another embodiment of this application.

[0020] Figure 6 This is a cross-sectional schematic diagram of the chip packaging structure in another embodiment of this application.

[0021] Figure 7 This is a cross-sectional schematic diagram of the chip packaging structure in another embodiment of this application.

[0022] Figure 8 This is a cross-sectional schematic diagram of the chip packaging structure in another embodiment of this application.

[0023] Figure 9 This is a schematic diagram of the fabrication process of a chip packaging structure in one embodiment of this application.

[0024] Figures 10 to 14 This is a schematic diagram of the fabrication process of the chip packaging structure in one embodiment of this application. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented even without certain specific details. In some instances, methods and means well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0027] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0028] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0029] The first aspect of this application provides a chip packaging structure, with reference to... Figure 1 The diagram shows a cross-sectional view of the chip packaging structure. Figure 2 The diagram shows a top view of the chip packaging structure and Figure 3The side view of the substrate sub-unit, first wiring layer, and second wiring layer shown indicates that the chip package structure includes: a substrate 100, including a support structure 120 and a plurality of substrate sub-units 110, the support structure 120 including a plurality of receiving spaces 121, at least some of the substrate sub-units 110 being located within the receiving spaces 121; a first wiring layer 210, located on a first side A of the substrate sub-units 110; a second wiring layer 220, located on a second side B of the substrate sub-units 110, along a direction perpendicular to the plane of the substrate 100 (direction z), with the first side A and the second side B being opposite to each other; a plurality of connecting lines 230, located between the substrate sub-units 110 and the support structure 120, and electrically connected to the first wiring layer 210 and the second wiring layer 220; and a chip 300, located on the side of the first wiring layer 210 and / or the second wiring layer 220 facing away from the substrate sub-units 110.

[0030] According to the chip packaging structure provided in the embodiments of this application, a first wiring layer 210 and a second wiring layer 220 are respectively provided on the first side A and the second side B of the substrate subunit 110. After providing a connecting line 230 connecting the first wiring layer 210 and the second wiring layer 220, the above structure is at least partially embedded in the receiving space 121 of the support structure 120. This is beneficial to improving the mechanical strength and reliability of the chip packaging structure and can reduce the risk of failure in subsequent use. Moreover, the wiring widths of the first wiring layer 210, the second wiring layer 220 and the connecting line 230 are relatively wide, which is suitable for packaging high-power chips.

[0031] Optionally, the first wiring layer 210, the second wiring layer 220 and the connecting line 230 can be prepared by electroplating the first wiring layer 210, the second wiring layer 220 and the connecting line 230 on the surface of the substrate subunit 110.

[0032] Optionally, the preparation method of the first wiring layer 210, the second wiring layer 220 and the connecting line 230 can also be as follows: a through hole is opened in a whole substrate body, the first wiring layer 210, the second wiring layer 220 and the connecting line 230 are obtained by electroplating on the surface of the substrate body, and then the substrate body is cut to obtain a plurality of substrate sub-units 110.

[0033] For example, the connecting line 230 extends in a direction parallel to the first side A and pointing to the second side B.

[0034] In one embodiment, in the first direction x, the width L of the connecting line 230 is greater than or equal to 5 micrometers and less than or equal to 8 centimeters, for example, it can be 5 micrometers, 50 micrometers, 100 micrometers, 500 micrometers, 1 millimeter, 5 millimeters, 1 centimeter, 4 centimeters, or 8 centimeters, etc. Therefore, the larger width L of the connecting line 230 results in lower resistance, enabling the chip packaging structure to operate at a faster speed and making it more suitable for high-power chip packaging.

[0035] In one embodiment, in the second direction y, the thickness H of the connecting line 230 is greater than or equal to 20 μm and less than or equal to 500 μm, for example, it can be 20 μm, 50 μm, 100 μm, 200 μm, 300 μm, 400 μm, or 500 μm, etc., and the first direction x intersects the second direction y. For example, the first direction x and the second direction y are perpendicular to each other. Therefore, the connecting line 230 has a relatively thick thickness H, resulting in a lower resistance, which allows the chip packaging structure to operate at a faster speed and is more suitable for high-power chip packaging.

[0036] Optionally, the connecting lines 230 are located on opposite sides of the base sub-unit 110 along a direction parallel to the plane of the base 100. Optionally, along a direction parallel to the plane of the base 100, the number of connecting lines 230 on each side of the base sub-unit 110 is greater than or equal to one, for example, one, two, three, etc.

[0037] In one embodiment, the surface of chip 300 with pins faces the substrate sub-cell 110.

[0038] In one embodiment, refer to Figure 3 In the first direction x, the width of the first wiring layer 210 is less than or equal to the width of the connection line 230; and / or, the width of the second wiring layer 220 is less than or equal to the width of the connection line 230. Therefore, the wider widths of the first wiring layer 210 and the second wiring layer 220 are more suitable for high-power chip packaging. It can be understood that when the width of the first wiring layer 210 is less than the width of the connection line 230, the wider connection line 230 results in lower resistance. Similarly, when the width of the second wiring layer 220 is less than the width of the connection line 230, the wider connection line 230 results in lower resistance.

[0039] In one embodiment, refer to Figure 4 The schematic diagram of the cross-sectional structure of the chip packaging structure shown indicates that the thickness of the support structure 120 is equal to the thickness of the substrate sub-unit 110. For example, the support structure 120 on the first side A is flush with the surface of the substrate sub-unit 110, and the support structure 120 on the second side B is also flush with the surface of the substrate sub-unit 110. Therefore, the support structure 120 provides better support, resulting in higher mechanical strength of the chip packaging structure.

[0040] In one embodiment, refer to Figure 4The chip packaging structure further includes a first protective layer 410 and a second protective layer 420. The first protective layer 410 is located on a first side A and covers at least a portion of the first wiring layer 210. The second protective layer 420 is located on a second side B and covers at least a portion of the second wiring layer 220. Therefore, the first protective layer 410 and the second protective layer 420 can effectively protect the substrate 100 and the wiring layer, which helps improve the reliability of the chip packaging structure and reduces the risk of failure during subsequent use.

[0041] For example, the material of the first protective layer 410 includes at least one of polyimide (PI), Ajinomoto stacked film (ABF), and bismaleimide triazine resin (BT); the material of the second protective layer 420 includes at least one of polyimide, Ajinomoto stacked film, and bismaleimide triazine resin.

[0042] In one embodiment, refer to Figure 5 The schematic diagram of the cross-sectional structure of the chip packaging structure shown includes: a first dielectric layer 610 located on the side of the first protective layer 410 close to the substrate 100; and a second dielectric layer 620 located on the side of the second protective layer 420 close to the substrate 100.

[0043] For example, the first wiring layer 210 includes a plurality of first portions 211, a plurality of second portions 212, and a plurality of third portions 213. The plurality of first portions 211 are located on a first side A, the plurality of third portions 213 are located on the side of the first dielectric layer 610 opposite to the substrate sub-unit 110, and the plurality of second portions 212 are located between the plurality of first portions 211 and the plurality of third portions 213, and the plurality of second portions 212 connect the plurality of first portions 211 and the plurality of third portions 213. The first dielectric layer 610 covers the plurality of first portions 211, and the plurality of second portions 212 penetrate the first dielectric layer 610. The first protective layer 410 covers the plurality of third portions 213. For example, the second wiring layer 220 includes a plurality of fourth portions 221, a plurality of fifth portions 222, and a plurality of sixth portions 223. The plurality of fourth portions 221 are located on the second side B, the plurality of sixth portions 223 are located on the side of the second dielectric layer 620 opposite to the substrate sub-unit 110, and the plurality of fifth portions 222 are located between the plurality of fourth portions 221 and the plurality of sixth portions 223, and the plurality of fifth portions 222 connect the plurality of fourth portions 221 and the plurality of sixth portions 223. The second dielectric layer 620 covers the plurality of fourth portions 221, and the plurality of fifth portions 222 penetrate the second dielectric layer 620. The second protective layer 420 covers the plurality of sixth portions 223. Thus, the number of wiring layers can be increased, allowing for more flexible placement of the chip 300. For example, if the size of the chip 300 is large, a first dielectric layer 610 or a second dielectric layer 620 can be provided. By controlling the structure of the wiring layer, the spacing between adjacent chips 300 can be increased by shortening the length of multiple third parts 213 in the second direction y or adjusting the spacing between multiple third parts 213 to be relatively large, or by shortening the length of multiple sixth parts 223 in the second direction y or adjusting the spacing between multiple sixth parts 223 to be relatively large, thereby achieving the encapsulation of the chip 300.

[0044] For example, chip 300 may include, but is not limited to, logic chips or memory chips.

[0045] In one embodiment, refer to Figures 6 to 8 The schematic diagram of the chip packaging structure shown shows that the thickness of the support structure 120 is greater than the thickness of the substrate subunit 110.

[0046] For example, refer to Figure 6 The surfaces of the support structure 120 and the base subunit 110 on the first side A are flush; optionally, the surface of the support structure 120 on the second side B is located on the side of the second wiring layer 220 away from the base subunit 110.

[0047] In one embodiment, refer to Figure 6The chip packaging structure further includes a first protective layer 410 located on the first side A, which covers at least a portion of the first wiring layer 210. The support structure 120 provides excellent support, resulting in high mechanical strength for the chip packaging structure. Furthermore, the chip packaging structure of this embodiment eliminates the need for a protective layer on the second side B, resulting in a simpler structure and lower cost.

[0048] Optionally, the chip packaging structure further includes a first dielectric layer 610 located on the side of the first protective layer 410 near the substrate 100.

[0049] For example, the first wiring layer 201 includes a plurality of first portions 211, a plurality of second portions 212, and a plurality of third portions 213. The plurality of first portions 211 are located on a first side A of the substrate sub-unit 110, the plurality of third portions 213 are located on a side of the first dielectric layer 610 opposite to the substrate sub-unit 110, and the plurality of second portions 212 are located between the plurality of first portions 211 and the plurality of third portions 213, and the plurality of second portions 212 connect the plurality of first portions 211 and the plurality of third portions 213. The first dielectric layer 610 covers the plurality of first portions 211, and the plurality of second portions 212 penetrate the first dielectric layer 610. The first protective layer 410 covers the plurality of third portions 213.

[0050] For example, refer to Figure 7 The surfaces of the support structure 120 on the second side B and the base subunit 110 are flush; optionally, the surface of the support structure 120 on the second side A is located on the side of the first wiring layer 210 away from the base subunit 110.

[0051] In one embodiment, refer to Figure 7 The chip packaging structure further includes a second protective layer 420 located on the second side B, which covers at least a portion of the second wiring layer 220. The support structure 120 provides excellent support, resulting in high mechanical strength for the chip packaging structure. Furthermore, the chip packaging structure of this embodiment eliminates the need for the protective layer on the first side A, resulting in a simpler structure and lower cost.

[0052] In one embodiment, refer to Figure 7 The chip packaging structure also includes a second dielectric layer 620, located on the side of the second protective layer 420 near the substrate 100.

[0053] For example, refer to Figure 7The second wiring layer 220 includes a plurality of fourth portions 221, a plurality of fifth portions 222, and a plurality of sixth portions 223. The plurality of fourth portions 221 are located on the second side B of the substrate sub-unit 110, the plurality of sixth portions 223 are located on the side of the second dielectric layer 620 opposite to the substrate sub-unit 110, and the plurality of fifth portions 222 are located between the plurality of fourth portions 221 and the plurality of sixth portions 223, and the plurality of fifth portions 222 connect the plurality of fourth portions 221 and the plurality of sixth portions 223. The second dielectric layer 620 covers the plurality of fourth portions 221, and the plurality of fifth portions 222 penetrate the second dielectric layer 620. The second protective layer 420 covers the plurality of sixth portions 223.

[0054] For example, the material of the first dielectric layer 610 includes at least one of polyimide, Ajinomoto stacked film, and bismaleimide triazine resin; the material of the second dielectric layer 620 includes at least one of polyimide, Ajinomoto stacked film, and bismaleimide triazine resin.

[0055] In one embodiment, refer to Figure 8 The surface of the support structure 120 on the first side A is located on the side of the first wiring layer 210 facing away from the substrate sub-unit 110, and the surface of the support structure 120 on the second side B is located on the side of the second wiring layer 220 facing away from the substrate sub-unit 110. Thus, the support structure completely encloses the substrate sub-unit 110, the first wiring layer 210, the second wiring layer 220, and the connecting lines 230, providing excellent support and giving the chip packaging structure high mechanical strength. Furthermore, the chip packaging structure of this embodiment does not require a protective layer, resulting in a simple structure and low cost.

[0056] For example, the chip 300 is located on the side of the first wiring layer 210 away from the substrate sub-unit 110 and is electrically connected to the first wiring layer 210, which facilitates wiring and facilitates the electrical connection of the second wiring layer 220 located on the second side B with subsequent structures, such as the printed circuit board (PCB).

[0057] In one embodiment, refer to Figure 4 , Figure 5 , Figure 6 , Figure 7 or Figure 8 The chip 300 includes a chip body 310 and a first conductive part 320. The first conductive part 320 is located between the chip body 310 and the first wiring layer 210 and is used to connect the chip body 310 and the first wiring layer 210.

[0058] For example, the first conductive portion 320 can be a solder ball. Alternatively, the first conductive portion 320 can have any other shape, as long as it satisfies the electrical connection between the chip body 310 and the first wiring layer 210.

[0059] In one embodiment, the chip package structure further includes a second conductive portion 500 located on the side of the second wiring layer 220 opposite to the substrate sub-unit 110 and connected to the second wiring layer 220. Thus, the second conductive portion 500 is electrically connected to subsequent structures, such as a printed circuit board (PCB).

[0060] For example, the second conductive part 500 can be a solder ball. Alternatively, the second conductive part 500 can have any other shape, as long as it allows for electrical connection between the second conductive part 500 and subsequent structures.

[0061] In one embodiment, the material of the support structure 120 includes epoxy molding compound (EMC) and / or polyimide. Therefore, the support structure 120 provides excellent support, low cost, and excellent encapsulation performance.

[0062] In one embodiment, the material of the substrate subunit 110 includes glass and / or silicon. For example, the material of the substrate subunit 110 is glass, or the material of the substrate subunit 110 is monocrystalline silicon, or the material of the substrate subunit 110 is polycrystalline silicon.

[0063] The second aspect of this application provides a method for fabricating a chip packaging structure, referring to... Figure 9 The schematic diagram shown illustrates the fabrication process of the chip packaging structure, which includes the following steps.

[0064] S100: Multiple through holes are formed in the substrate body, multiple connecting lines 230 are formed in the through holes, a first wiring layer 210 is formed on the first side A of the substrate body, and a second wiring layer 220 is formed on the second side B of the substrate body.

[0065] Along a direction perpendicular to the plane of the base body, the first side A and the second side B are positioned opposite each other.

[0066] It should be noted that the first wiring layer 210, the second wiring layer 220 and the connecting line 230 are consistent with the previous description, and will not be repeated here.

[0067] The first wiring layer 210 and the second wiring layer 220 are electrically connected by a connecting line 230.

[0068] In one embodiment, multiple interconnecting lines 230 are fabricated in the through-hole, a first wiring layer 210 is fabricated on the first side A of the substrate, and a second wiring layer 220 is fabricated on the second side B of the substrate through the same fabrication process.

[0069] In one embodiment, an electroplating process is used to prepare multiple interconnecting lines 230 in the through-hole, a first wiring layer 210 is prepared on a first side A of the substrate, and a second wiring layer 220 is prepared on a second side B of the substrate.

[0070] It is understandable that the size of the vias in the substrate is the same as the size of the connector 230, and the connector 230, fabricated by the electroplating process, completely fills the vias. Therefore, the process of creating vias is relatively simple, which helps to reduce the difficulty of manufacturing the chip packaging structure and lower production costs.

[0071] For example, the first wiring layer, the second wiring layer, and the interconnects are fabricated simultaneously.

[0072] S200: The substrate body is segmented to obtain multiple substrate sub-units 110.

[0073] Optionally, the substrate body can be cut using a laser cutting method to obtain multiple substrate sub-units 110.

[0074] It is understood that the surface of the base sub-unit 110 obtained by the segmentation process has a first wiring layer 210, a second wiring layer 220 and a connecting line 230.

[0075] It should be noted that the base subunit 110 is consistent with the previous description, and will not be elaborated further here.

[0076] S300: Multiple base sub-units 110 are embedded in the receiving space 121 of the support structure 120.

[0077] In one embodiment, the step of embedding a plurality of substrate sub-units 110 into the receiving space 121 of the support structure 120 includes: fixing the plurality of substrate sub-units 110 onto a substrate; placing the plurality of substrate sub-units 110 in a liquid support structure 120 material; and removing the substrate after the support structure 120 material has solidified. It is understood that in the step of embedding the plurality of substrate sub-units 110 into the receiving space 121 of the support structure 120, the surface of the substrate sub-units 110 has a first wiring layer 210, a second wiring layer 220, and connecting lines 230.

[0078] It is understood that a baffle can be set on the substrate surface, and the baffle and the substrate can form a groove. Multiple base subunits 110 are fixed in the groove. Liquid support structure 120 material is poured into the groove. After the liquid support structure 120 material solidifies, the substrate and the baffle are removed to obtain the base subunits 110 embedded in the receiving space 121 of the support structure 120.

[0079] S400: The chip 300 is fixed on the side of the first wiring layer 210 and / or the second wiring layer 220 away from the substrate body to obtain a chip package structure.

[0080] It should be noted that chip 300 is consistent with the previous description, and will not be elaborated on further here.

[0081] In one specific embodiment, the method for fabricating a chip packaging structure includes the following steps: 1. Multiple through holes 11 are formed in the substrate body 10. Multiple connecting lines 230 are formed in the through holes 11 by electroplating. A first wiring layer 210 is formed on the first side A of the substrate body 10, and a second wiring layer 220 is formed on the second side B of the substrate body 10. See details below. Figure 10 .

[0082] 2. The substrate body 10 is segmented to obtain multiple substrate sub-units 110. The surface of the segmented substrate sub-units 110 has a first wiring layer 210, a second wiring layer 220, and connecting lines 230, as detailed below. Figure 11 .

[0083] 3. Embed multiple base sub-units 110 into the receiving space 121 of the support structure 120, as detailed in the following reference. Figure 12 .

[0084] 4. A first protective layer 410 is prepared on the side of the first wiring layer 210 facing away from the substrate sub-unit 110, and a second protective layer 420 is prepared on the side of the second wiring layer 220 facing away from the substrate sub-unit 110. Through holes are formed in the first protective layer 410 and the second protective layer 420. A second conductive part 500 is fixed on the side of the second protective layer 420 facing away from the substrate sub-unit 110. The second conductive part 500 is electrically connected to the second wiring layer 220 through the through holes in the second protective layer 420. See the following for details. Figure 13 .

[0085] 5. A chip 300 is fixed on the side of the first protective layer 410 away from the substrate subunit 110. The chip 300 is electrically connected to the first wiring layer 210 through a through-hole in the first protective layer 410 to obtain the chip packaging structure. See the following for details. Figure 14 .

[0086] For example, fixing the second conductive portion 500 to the side of the second protective layer 420 away from the base subunit 110 includes soldering the second wiring layer 220 to the second conductive portion 500.

[0087] For example, the chip 300 includes a chip body 310 and a first conductive part 320. The first conductive part 320 is connected to the first wiring layer 210 by soldering. The chip 300 is fixed on the side of the first protective layer 410 away from the substrate subunit 110.

[0088] It should be noted that the chip packaging structure prepared by the method of this embodiment can be combined with the chip packaging structure described above in whole or in part, which will not be elaborated further here.

[0089] A third aspect of this application provides a display device, including the aforementioned chip packaging structure, or including a chip packaging structure prepared by the aforementioned preparation method.

[0090] It should be noted that the aforementioned display device can be a desktop computer, tablet computer, high-performance calculator, etc. It should also be noted that, in addition to the chip packaging structure described above, the display device may also include the structures that conventional display devices should possess, such as a display panel, touch panel, and casing, which will not be elaborated upon further here.

[0091] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0092] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A chip packaging structure, characterized in that, include: A substrate includes a support structure and multiple substrate sub-units, the support structure including multiple receiving spaces, at least some of the substrate sub-units being located within the receiving spaces; The first wiring layer is located on the first side of the substrate subunit; The second wiring layer is located on the second side of the substrate subunit, along a direction perpendicular to the plane of the substrate, with the first side and the second side disposed opposite to each other; Multiple connecting lines are located between the base subunit and the support structure, and are electrically connected to the first wiring layer and the second wiring layer; The chip is located on the side of the first wiring layer and / or the second wiring layer opposite to the substrate sub-unit.

2. The chip packaging structure according to claim 1, characterized in that, In the first direction, the dimension of the connecting line is greater than or equal to 5 micrometers and less than or equal to 8 centimeters; And / or, in the second direction, the size of the connecting line is greater than or equal to 20 μm and less than or equal to 500 μm, and the first direction intersects the second direction; And / or, the surface of the chip having pins faces the substrate subcell; Preferably, the connecting line is located on two opposite sides of the substrate subunit along a direction parallel to the plane of the substrate; Preferably, along a direction parallel to the plane of the substrate, the number of connecting lines on each side of the substrate sub-unit is greater than or equal to one.

3. The chip packaging structure according to claim 1 or 2, characterized in that, In a first direction, the size of the first wiring layer is less than or equal to the size of the connecting line; and / or, in a first direction, the size of the second wiring layer is less than or equal to the size of the connecting line.

4. The chip packaging structure according to claim 1, characterized in that, In a direction perpendicular to the plane of the base, the dimension of the support structure is equal to the dimension of the base sub-unit; Preferably, the support structure located on the first side is flush with the surface of the base subunit, and the support structure located on the second side is flush with the surface of the base subunit; Preferably, the chip packaging structure further includes: a first protective layer located on the first side, the first protective layer covering at least a portion of the first wiring layer; and / or, a second protective layer located on the second side, the second protective layer covering at least a portion of the second wiring layer.

5. The chip packaging structure according to claim 4, characterized in that, The chip packaging structure also includes: A first dielectric layer is located on the side of the first protective layer near the substrate; and / or, a second dielectric layer is located on the side of the second protective layer near the substrate; Preferably, the first wiring layer includes a plurality of first portions, a plurality of second portions, and a plurality of third portions. The plurality of first portions are located on the first side, the plurality of third portions are located on the side of the first dielectric layer opposite to the substrate sub-unit, and the plurality of second portions are located between the plurality of first portions and the plurality of third portions, and the plurality of second portions connect the plurality of first portions and the plurality of third portions; the first dielectric layer covers the plurality of first portions, and the plurality of second portions penetrate the first dielectric layer; the first protective layer covers the plurality of third portions; and / or, the second wiring layer includes a plurality of fourth portions, a plurality of fifth portions, and a plurality of sixth portions. The plurality of fourth portions are located on the second side, the plurality of sixth portions are located on the side of the second dielectric layer opposite to the substrate sub-unit, the plurality of fifth portions are located between the plurality of fourth portions and the plurality of sixth portions, and the plurality of fifth portions connect the plurality of fourth portions and the plurality of sixth portions; the second dielectric layer covers the plurality of fourth portions, the plurality of fifth portions penetrate the second dielectric layer; the second protective layer covers the plurality of sixth portions; Preferably, the material of the first dielectric layer and / or the second dielectric layer includes at least one of polyimide, Ajinomoto stacked film, and bismaleimide triazine resin.

6. The chip packaging structure according to claim 1, characterized in that, In a direction perpendicular to the plane of the base, the dimension of the support structure is larger than the dimension of the base sub-unit; Preferably, the surface of the support structure located on the first side is flush with the surface of the base subunit; The chip packaging structure further includes: a first protective layer located on the first side, the first protective layer covering at least a portion of the first wiring layer; The first dielectric layer is located on the side of the first protective layer closest to the substrate; Alternatively, the support structure located on the second side is flush with the surface of the base subunit; The chip packaging structure further includes: a second protective layer located on the second side, the second protective layer covering at least a portion of the second wiring layer; The second dielectric layer is located on the side of the second protective layer closer to the substrate; Preferably, the first wiring layer includes a plurality of first portions, a plurality of second portions, and a plurality of third portions. The plurality of first portions are located on a first side of the substrate sub-unit, the plurality of third portions are located on a side of the first dielectric layer opposite to the substrate sub-unit, and the plurality of second portions are located between the plurality of first portions and the plurality of third portions, and the plurality of second portions connect the plurality of first portions and the plurality of third portions. The first dielectric layer covers the plurality of first portions, and the plurality of second portions penetrate the first dielectric layer. The first protective layer is located on the side of the first dielectric layer opposite to the substrate, and the first protective layer covers the plurality of first portions. Three parts; and / or, the second wiring layer includes a plurality of fourth parts, a plurality of fifth parts, and a plurality of sixth parts, the plurality of fourth parts being located on the second side, the plurality of sixth parts being located on the side of the second dielectric layer opposite to the substrate sub-unit, the plurality of fifth parts being located between the plurality of fourth parts and the plurality of sixth parts, and the plurality of fifth parts connecting the plurality of fourth parts and the plurality of sixth parts; the second dielectric layer covers the plurality of fourth parts, and the plurality of fifth parts penetrate the second dielectric layer; the second protective layer is located on the side of the second dielectric layer opposite to the substrate, and the second protective layer covers the plurality of sixth parts; Alternatively, the surface of the support structure located on the first side is located on the side of the first wiring layer away from the substrate subunit, and the surface of the support structure located on the second side is located on the side of the second wiring layer away from the substrate subunit.

7. The chip packaging structure according to claim 1, characterized in that, The chip includes: A chip body and a first conductive portion, wherein the first conductive portion is located between the chip body and the first wiring layer, and the first conductive portion is used to connect the chip body and the first wiring layer; And / or, the chip packaging structure further includes: The second conductive part is located on the side of the second wiring layer away from the substrate sub-unit and is connected to the second wiring layer; Preferably, the chip is located on the side of the first wiring layer opposite to the substrate sub-unit; Preferably, the material of the support structure includes epoxy molding compound and / or polyimide; and / or, the material of the substrate subunit includes glass and / or silicon.

8. A method for fabricating a chip packaging structure, characterized in that, include: Multiple through holes are formed in the substrate body, and multiple connecting lines are formed in the through holes. A first wiring layer is formed on a first side of the substrate body, and a second wiring layer is formed on a second side of the substrate body. The first side and the second side are arranged opposite to each other along a direction perpendicular to the plane of the substrate body. The first wiring layer and the second wiring layer are electrically connected through the multiple connecting lines. The substrate body is segmented to obtain multiple substrate sub-units; Multiple base sub-units are embedded in the receiving space of the support structure; A chip is fixed on the side of the first wiring layer and / or the second wiring layer away from the substrate body to obtain the chip packaging structure.

9. The preparation method according to claim 8, characterized in that, The plurality of connecting lines are fabricated in the through-hole, the first wiring layer is fabricated on the first side, and the second wiring layer is fabricated on the second side through the same fabrication process; Preferably, the plurality of connecting lines are prepared in the through-hole using an electroplating process, the first wiring layer is prepared on the first side, and the second wiring layer is prepared on the second side; The step of embedding the plurality of said base sub-units into the receiving space of the support structure includes: Multiple substrate subunits are fixed on the substrate; Multiple of the aforementioned substrate sub-units are placed in a liquid supporting structural material; After the supporting structure material is cured, the substrate is removed.

10. A display device, characterized in that, Includes the chip packaging structure according to any one of claims 1 to 7, or includes the chip packaging structure prepared by the preparation method according to claim 8 or 9.

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